pub struct W<U, REG> { /* fields omitted */ }
Expand description
Register writer
Used as an argument to the closures in the write
and modify
methods of the register
pub unsafe fn bits(&mut self, bits: U) -> &mut Self
Writes raw bits to the register
impl W<u32, Reg<u32, _IFCR>>
Bit 27 - Channel x transfer error clear (x = 1 ..7)
Bit 26 - Channel x half transfer clear (x = 1 ..7)
Bit 25 - Channel x transfer complete clear (x = 1 ..7)
Bit 24 - Channel x global interrupt clear (x = 1 ..7)
Bit 23 - Channel x transfer error clear (x = 1 ..7)
Bit 22 - Channel x half transfer clear (x = 1 ..7)
Bit 21 - Channel x transfer complete clear (x = 1 ..7)
Bit 20 - Channel x global interrupt clear (x = 1 ..7)
Bit 19 - Channel x transfer error clear (x = 1 ..7)
Bit 18 - Channel x half transfer clear (x = 1 ..7)
Bit 17 - Channel x transfer complete clear (x = 1 ..7)
Bit 16 - Channel x global interrupt clear (x = 1 ..7)
Bit 15 - Channel x transfer error clear (x = 1 ..7)
Bit 14 - Channel x half transfer clear (x = 1 ..7)
Bit 13 - Channel x transfer complete clear (x = 1 ..7)
Bit 12 - Channel x global interrupt clear (x = 1 ..7)
Bit 11 - Channel x transfer error clear (x = 1 ..7)
Bit 10 - Channel x half transfer clear (x = 1 ..7)
Bit 9 - Channel x transfer complete clear (x = 1 ..7)
Bit 8 - Channel x global interrupt clear (x = 1 ..7)
Bit 7 - Channel x transfer error clear (x = 1 ..7)
Bit 6 - Channel x half transfer clear (x = 1 ..7)
Bit 5 - Channel x transfer complete clear (x = 1 ..7)
Bit 4 - Channel x global interrupt clear (x = 1 ..7)
Bit 3 - Channel x transfer error clear (x = 1 ..7)
Bit 2 - Channel x half transfer clear (x = 1 ..7)
Bit 1 - Channel x transfer complete clear (x = 1 ..7)
Bit 0 - Channel x global interrupt clear (x = 1 ..7)
impl W<u32, Reg<u32, _CCR1>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR1>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR1>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR1>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR2>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR2>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR2>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR2>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR3>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR3>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR3>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR3>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR4>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR4>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR4>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR4>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR5>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR5>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR5>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR5>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR6>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR6>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR6>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR6>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR7>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR7>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR7>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR7>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _IFCR>>
Bit 27 - Channel x transfer error clear (x = 1 ..7)
Bit 26 - Channel x half transfer clear (x = 1 ..7)
Bit 25 - Channel x transfer complete clear (x = 1 ..7)
Bit 24 - Channel x global interrupt clear (x = 1 ..7)
Bit 23 - Channel x transfer error clear (x = 1 ..7)
Bit 22 - Channel x half transfer clear (x = 1 ..7)
Bit 21 - Channel x transfer complete clear (x = 1 ..7)
Bit 20 - Channel x global interrupt clear (x = 1 ..7)
Bit 19 - Channel x transfer error clear (x = 1 ..7)
Bit 18 - Channel x half transfer clear (x = 1 ..7)
Bit 17 - Channel x transfer complete clear (x = 1 ..7)
Bit 16 - Channel x global interrupt clear (x = 1 ..7)
Bit 15 - Channel x transfer error clear (x = 1 ..7)
Bit 14 - Channel x half transfer clear (x = 1 ..7)
Bit 13 - Channel x transfer complete clear (x = 1 ..7)
Bit 12 - Channel x global interrupt clear (x = 1 ..7)
Bit 11 - Channel x transfer error clear (x = 1 ..7)
Bit 10 - Channel x half transfer clear (x = 1 ..7)
Bit 9 - Channel x transfer complete clear (x = 1 ..7)
Bit 8 - Channel x global interrupt clear (x = 1 ..7)
Bit 7 - Channel x transfer error clear (x = 1 ..7)
Bit 6 - Channel x half transfer clear (x = 1 ..7)
Bit 5 - Channel x transfer complete clear (x = 1 ..7)
Bit 4 - Channel x global interrupt clear (x = 1 ..7)
Bit 3 - Channel x transfer error clear (x = 1 ..7)
Bit 2 - Channel x half transfer clear (x = 1 ..7)
Bit 1 - Channel x transfer complete clear (x = 1 ..7)
Bit 0 - Channel x global interrupt clear (x = 1 ..7)
impl W<u32, Reg<u32, _CCR1>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR1>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR1>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR1>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR2>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR2>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR2>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR2>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR3>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR3>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR3>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR3>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR4>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR4>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR4>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR4>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR5>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR5>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR5>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR5>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR6>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR6>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR6>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR6>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR7>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR7>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR7>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR7>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CSELR>>
Bits 24:27 - DMA channel 7 selection
Bits 20:23 - DMA channel 6 selection
Bits 16:19 - DMA channel 5 selection
Bits 12:15 - DMA channel 4 selection
Bits 8:11 - DMA channel 3 selection
Bits 4:7 - DMA channel 2 selection
Bits 0:3 - DMA channel 1 selection
impl W<u32, Reg<u32, _C0CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C1CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C2CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C3CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C4CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C5CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C6CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C7CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C8CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C9CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C10CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C11CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C12CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _C13CR>>
Bits 17:18 - Sync polarity
pub fn se(&mut self) -> SE_W<'_>
Bit 16 - Synchronization enable
Bit 9 - Event Generation Enable
Bit 8 - Synchronization Overrun Interrupt Enable
Bits 0:7 - DMA Request ID
impl W<u32, Reg<u32, _CFR>>
Bit 0 - Synchronization Clear Overrun Flag 0
Bit 1 - Synchronization Clear Overrun Flag 1
Bit 2 - Synchronization Clear Overrun Flag 2
Bit 3 - Synchronization Clear Overrun Flag 3
Bit 4 - Synchronization Clear Overrun Flag 4
Bit 5 - Synchronization Clear Overrun Flag 5
Bit 6 - Synchronization Clear Overrun Flag 6
Bit 7 - Synchronization Clear Overrun Flag 7
Bit 8 - Synchronization Clear Overrun Flag 8
Bit 9 - Synchronization Clear Overrun Flag 9
Bit 10 - Synchronization Clear Overrun Flag 10
Bit 11 - Synchronization Clear Overrun Flag 11
Bit 12 - Synchronization Clear Overrun Flag 12
Bit 13 - Synchronization Clear Overrun Flag 13
impl W<u32, Reg<u32, _RG0CR>>
Bits 19:23 - Number of Request
Bits 17:18 - Generation Polarity
pub fn ge(&mut self) -> GE_W<'_>
Bit 16 - Generation Enable
Bit 8 - Overrun Interrupt Enable
impl W<u32, Reg<u32, _RG1CR>>
Bits 19:23 - Number of Request
Bits 17:18 - Generation Polarity
pub fn ge(&mut self) -> GE_W<'_>
Bit 16 - Generation Enable
Bit 8 - Overrun Interrupt Enable
impl W<u32, Reg<u32, _RG2CR>>
Bits 19:23 - Number of Request
Bits 17:18 - Generation Polarity
pub fn ge(&mut self) -> GE_W<'_>
Bit 16 - Generation Enable
Bit 8 - Overrun Interrupt Enable
impl W<u32, Reg<u32, _RG3CR>>
Bits 19:23 - Number of Request
Bits 17:18 - Generation Polarity
pub fn ge(&mut self) -> GE_W<'_>
Bit 16 - Generation Enable
Bit 8 - Overrun Interrupt Enable
impl W<u32, Reg<u32, _DR>>
pub fn dr(&mut self) -> DR_W<'_>
Bits 0:31 - Data register bits
impl W<u32, Reg<u32, _IDR>>
Bits 0:31 - General-purpose 32-bit data register bits
impl W<u32, Reg<u32, _CR>>
Bit 7 - Reverse output data
Bits 5:6 - Reverse input data
Bits 3:4 - Polynomial size
impl W<u32, Reg<u32, _INIT>>
Bits 0:31 - Programmable initial CRC value
impl W<u32, Reg<u32, _POL>>
Bits 0:31 - Programmable polynomial
impl W<u32, Reg<u32, _CR>>
Bits 2:4 - Duty selection
Bit 1 - Voltage source selection
Bit 0 - LCD controller enable
Bit 7 - Mux segment enable
Bit 8 - Voltage output buffer enable
impl W<u32, Reg<u32, _FCR>>
pub fn ps(&mut self) -> PS_W<'_>
Bits 22:25 - PS 16-bit prescaler
Bits 18:21 - DIV clock divider
Bits 16:17 - Blink mode selection
Bits 13:15 - Blink frequency selection
pub fn cc(&mut self) -> CC_W<'_>
Bits 10:12 - Contrast control
Bits 7:9 - Dead time duration
Bits 4:6 - Pulse ON duration
Bit 3 - Update display done interrupt enable
Bit 1 - Start of frame interrupt enable
pub fn hd(&mut self) -> HD_W<'_>
Bit 0 - High drive enable
impl W<u32, Reg<u32, _SR>>
Bit 2 - Update display request
impl W<u32, Reg<u32, _CLR>>
Bit 3 - Update display done clear
Bit 1 - Start of frame flag clear
impl W<u32, Reg<u32, _RAM_COM0>>
impl W<u32, Reg<u32, _RAM_COM1>>
impl W<u32, Reg<u32, _RAM_COM2>>
impl W<u32, Reg<u32, _RAM_COM3>>
impl W<u32, Reg<u32, _RAM_COM4>>
impl W<u32, Reg<u32, _RAM_COM5>>
impl W<u32, Reg<u32, _RAM_COM6>>
impl W<u32, Reg<u32, _RAM_COM7>>
impl W<u32, Reg<u32, _CR>>
Bits 28:31 - Charge transfer pulse high
Bits 24:27 - Charge transfer pulse low
Bits 17:23 - Spread spectrum deviation
Bit 16 - Spread spectrum enable
Bit 15 - Spread spectrum prescaler
Bits 12:14 - pulse generator prescaler
Bits 5:7 - Max count value
Bit 3 - Synchronization pin polarity
pub fn am(&mut self) -> AM_W<'_>
Bit 1 - Start a new acquisition
Bit 0 - Touch sensing controller enable
impl W<u32, Reg<u32, _IER>>
Bit 1 - Max count error interrupt enable
Bit 0 - End of acquisition interrupt enable
impl W<u32, Reg<u32, _ICR>>
Bit 1 - Max count error interrupt clear
Bit 0 - End of acquisition interrupt clear
impl W<u32, Reg<u32, _ISR>>
Bit 1 - Max count error flag
Bit 0 - End of acquisition flag
impl W<u32, Reg<u32, _IOHCR>>
impl W<u32, Reg<u32, _IOASCR>>
impl W<u32, Reg<u32, _IOSCR>>
impl W<u32, Reg<u32, _IOCCR>>
impl W<u32, Reg<u32, _IOGCSR>>
Bit 6 - Analog I/O group x enable
Bit 5 - Analog I/O group x enable
Bit 4 - Analog I/O group x enable
Bit 3 - Analog I/O group x enable
Bit 2 - Analog I/O group x enable
Bit 1 - Analog I/O group x enable
Bit 0 - Analog I/O group x enable
impl W<u32, Reg<u32, _KR>>
Bits 0:15 - Key value (write only, read 0x0000)
impl W<u32, Reg<u32, _PR>>
pub fn pr(&mut self) -> PR_W<'_>
Bits 0:2 - Prescaler divider
impl W<u32, Reg<u32, _RLR>>
pub fn rl(&mut self) -> RL_W<'_>
Bits 0:11 - Watchdog counter reload value
impl W<u32, Reg<u32, _WINR>>
Bits 0:11 - Watchdog counter window value
impl W<u32, Reg<u32, _CR>>
pub fn t(&mut self) -> T_W<'_>
Bits 0:6 - 7-bit counter (MSB to LSB)
impl W<u32, Reg<u32, _CFR>>
Bit 9 - Early wakeup interrupt
pub fn w(&mut self) -> W_W<'_>
Bits 0:6 - 7-bit window value
impl W<u32, Reg<u32, _SR>>
Bit 0 - Early wakeup interrupt flag
impl W<u32, Reg<u32, _COMP1_CSR>>
Bit 0 - Comparator enable
Bits 2:3 - Comparator power mode
Bits 4:6 - Comparator input minus selection
Bits 7:8 - Comparator input plus selection
Bit 15 - Comparator output polarity
Bits 16:17 - Comparator hysteresis
Bits 18:20 - Comparator blanking source
Bit 22 - Comparator voltage scaler enable
Bit 23 - Comparator scaler bridge enable
Bits 25:26 - Comparator input minus extended selection
impl W<u32, Reg<u32, _COMP2_CSR>>
Bit 0 - Comparator 2 enable bit
Bits 2:3 - Power Mode of the comparator 2
Bits 4:5 - Comparator 2 input minus selection bits
Bits 7:8 - Comparator 1 input plus selection bit
Bit 9 - Windows mode selection bit
Bit 15 - Comparator 2 polarity selection bit
Bits 16:17 - Comparator 2 hysteresis selection bits
Bits 18:20 - Comparator 2 blanking source selection bits
Bit 22 - Scaler bridge enable
Bit 23 - Voltage scaler enable bit
Bits 25:26 - comparator 2 input minus extended selection bits.
Bit 31 - CSR register lock bit
impl W<u32, Reg<u32, _CR1>>
pub fn pe(&mut self) -> PE_W<'_>
Bit 0 - Peripheral enable
Bit 1 - TX Interrupt enable
Bit 2 - RX Interrupt enable
Bit 3 - Address match interrupt enable (slave only)
Bit 4 - Not acknowledge received interrupt enable
Bit 5 - STOP detection Interrupt enable
Bit 6 - Transfer Complete interrupt enable
Bit 7 - Error interrupts enable
Bits 8:11 - Digital noise filter
Bit 12 - Analog noise filter OFF
Bit 14 - DMA transmission requests enable
Bit 15 - DMA reception requests enable
Bit 16 - Slave byte control
Bit 17 - Clock stretching disable
Bit 18 - Wakeup from STOP enable
Bit 19 - General call enable
Bit 20 - SMBus Host address enable
Bit 21 - SMBus Device Default address enable
Bit 22 - SMBUS alert enable
impl W<u32, Reg<u32, _CR2>>
Bit 26 - Packet error checking byte
Bit 25 - Automatic end mode (master mode)
Bit 24 - NBYTES reload mode
Bits 16:23 - Number of bytes
Bit 15 - NACK generation (slave mode)
Bit 14 - Stop generation (master mode)
Bit 13 - Start generation
Bit 12 - 10-bit address header only read direction (master receiver mode)
Bit 11 - 10-bit addressing mode (master mode)
Bit 10 - Transfer direction (master mode)
Bits 0:9 - Slave address bit (master mode)
impl W<u32, Reg<u32, _OAR1>>
Bits 0:9 - Interface address
Bit 10 - Own Address 1 10-bit mode
Bit 15 - Own Address 1 enable
impl W<u32, Reg<u32, _OAR2>>
Bits 1:7 - Interface address
Bits 8:10 - Own Address 2 masks
Bit 15 - Own Address 2 enable
impl W<u32, Reg<u32, _TIMINGR>>
Bits 0:7 - SCL low period (master mode)
Bits 8:15 - SCL high period (master mode)
Bits 16:19 - Data hold time
Bits 20:23 - Data setup time
Bits 28:31 - Timing prescaler
impl W<u32, Reg<u32, _TIMEOUTR>>
Bits 0:11 - Bus timeout A
Bit 12 - Idle clock timeout detection
Bit 15 - Clock timeout enable
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
Bit 31 - Extended clock timeout enable
impl W<u32, Reg<u32, _ISR>>
Bit 1 - Transmit interrupt status (transmitters)
Bit 0 - Transmit data register empty (transmitters)
impl W<u32, Reg<u32, _ICR>>
Bit 13 - Alert flag clear
Bit 12 - Timeout detection flag clear
Bit 11 - PEC Error flag clear
Bit 10 - Overrun/Underrun flag clear
Bit 9 - Arbitration lost flag clear
Bit 8 - Bus error flag clear
Bit 5 - Stop detection flag clear
Bit 4 - Not Acknowledge flag clear
Bit 3 - Address Matched flag clear
impl W<u32, Reg<u32, _TXDR>>
Bits 0:7 - 8-bit transmit data
impl W<u32, Reg<u32, _ACR>>
Bit 9 - Instruction cache enable
Bit 10 - Data cache enable
Bit 11 - Instruction cache reset
Bit 12 - Data cache reset
Bit 15 - CPU1 CortexM4 program erase suspend request
Bit 16 - Flash User area empty
impl W<u32, Reg<u32, _KEYR>>
impl W<u32, Reg<u32, _OPTKEYR>>
Bits 0:31 - Option byte key
impl W<u32, Reg<u32, _SR>>
Bit 3 - Programming error
Bit 4 - Write protected error
Bit 5 - Programming alignment error
Bit 7 - Programming sequence error
Bit 8 - Fast programming data miss error
Bit 9 - Fast programming error
Bit 14 - PCROP read error
Bit 15 - Option validity error
impl W<u32, Reg<u32, _CR>>
pub fn pg(&mut self) -> PG_W<'_>
Bit 2 - This bit triggers the mass erase (all user pages) when set
Bits 3:10 - Page number selection
Bit 17 - Options modification start
Bit 18 - Fast programming
Bit 24 - End of operation interrupt enable
Bit 25 - Error interrupt enable
Bit 26 - PCROP read error interrupt enable
Bit 27 - Force the option byte loading
impl W<u32, Reg<u32, _ECCR>>
Bit 24 - ECC correction interrupt enable
impl W<u32, Reg<u32, _OPTR>>
Bits 0:7 - Read protection level
Bits 9:11 - BOR reset Level
Bit 16 - Independent watchdog selection
Bit 17 - Independent watchdog counter freeze in Stop mode
Bit 18 - Independent watchdog counter freeze in Standby mode
Bit 19 - Window watchdog selection
Bit 23 - Boot configuration
Bit 24 - SRAM2 parity check enable
Bit 25 - SRAM2 Erase when system reset
Bit 27 - nBoot0 option bit
Bits 29:31 - Radio Automatic Gain Control Trimming
impl W<u32, Reg<u32, _PCROP1ASR>>
Bits 0:8 - Bank 1 PCROPQ area start offset
impl W<u32, Reg<u32, _PCROP1AER>>
Bits 0:8 - Bank 1 PCROP area end offset
Bit 31 - PCROP area preserved when RDP level decreased
impl W<u32, Reg<u32, _WRP1AR>>
Bits 0:7 - Bank 1 WRP first area A start offset
Bits 16:23 - Bank 1 WRP first area A end offset
impl W<u32, Reg<u32, _WRP1BR>>
Bits 16:23 - Bank 1 WRP second area B end offset
Bits 0:7 - Bank 1 WRP second area B start offset
impl W<u32, Reg<u32, _PCROP1BSR>>
Bits 0:8 - Bank 1 PCROP area B start offset
impl W<u32, Reg<u32, _PCROP1BER>>
Bits 0:8 - Bank 1 PCROP area end area B offset
impl W<u32, Reg<u32, _IPCCBR>>
Bits 0:13 - PCC mailbox data buffer base address
impl W<u32, Reg<u32, _C2ACR>>
Bit 8 - CPU2 cortex M0 prefetch enable
Bit 9 - CPU2 cortex M0 instruction cache enable
Bit 11 - CPU2 cortex M0 instruction cache reset
Bit 15 - CPU2 cortex M0 program erase suspend request
impl W<u32, Reg<u32, _C2SR>>
Bit 3 - Programming error
Bit 4 - write protection error
Bit 5 - Programming alignment error
Bit 7 - Programming sequence error
Bit 8 - Fast programming data miss error
Bit 9 - Fast programming error
Bit 14 - PCROP read error
Bit 18 - Programming or erase configuration busy
Bit 19 - Programming or erase operation suspended
impl W<u32, Reg<u32, _C2CR>>
pub fn pg(&mut self) -> PG_W<'_>
Bits 3:10 - Page Number selection
Bit 18 - Fast programming
Bit 24 - End of operation interrupt enable
Bit 25 - Error interrupt enable
Bit 26 - PCROP read error interrupt enable
impl W<u32, Reg<u32, _SFR>>
Bits 0:7 - Secure flash start address
Bit 12 - Disable Cortex M0 debug access
Bit 8 - Flash security disable
impl W<u32, Reg<u32, _SRRVR>>
Bits 0:17 - cortex M0 access control register
Bits 18:22 - Secure backup SRAM2a start address
Bit 23 - backup SRAM2a security disable
Bits 25:29 - Secure non backup SRAM2a start address
Bit 31 - CPU2 cortex M0 boot reset vector memory selection
Bit 30 - non-backup SRAM2b security disable
impl W<u32, Reg<u32, _CR>>
Bits 24:31 - Clock prescaler
Bit 23 - Polling match mode
Bit 22 - Automatic poll mode stop
Bit 20 - TimeOut interrupt enable
Bit 19 - Status match interrupt enable
Bit 18 - FIFO threshold interrupt enable
Bit 17 - Transfer complete interrupt enable
Bit 16 - Transfer error interrupt enable
Bits 8:11 - FIFO threshold level
Bit 3 - Timeout counter enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _DCR>>
Bits 16:20 - FLASH memory size
Bits 8:10 - Chip select high time
impl W<u32, Reg<u32, _FCR>>
Bit 4 - Clear timeout flag
Bit 3 - Clear status match flag
Bit 1 - Clear transfer complete flag
Bit 0 - Clear transfer error flag
impl W<u32, Reg<u32, _DLR>>
pub fn dl(&mut self) -> DL_W<'_>
impl W<u32, Reg<u32, _CCR>>
Bit 31 - Double data rate mode
Bit 28 - Send instruction only once mode
Bits 26:27 - Functional mode
Bits 18:22 - Number of dummy cycles
Bits 16:17 - Alternate bytes size
Bits 14:15 - Alternate bytes mode
Bits 12:13 - Address size
Bits 10:11 - Address mode
Bits 8:9 - Instruction mode
impl W<u32, Reg<u32, _AR>>
impl W<u32, Reg<u32, _ABR>>
impl W<u32, Reg<u32, _DR>>
impl W<u32, Reg<u32, _PSMKR>>
impl W<u32, Reg<u32, _PSMAR>>
impl W<u32, Reg<u32, _PIR>>
Bits 0:15 - Polling interval
impl W<u32, Reg<u32, _LPTR>>
Bits 0:15 - Timeout period
impl W<u32, Reg<u32, _CR>>
Bit 20 - HSE sysclk and PLL M divider prescaler
Bit 19 - HSE Clock security system enable
Bit 18 - HSE crystal oscillator bypass
Bit 16 - HSE clock enabled
Bit 11 - HSI automatic start from Stop
Bit 9 - HSI always enable for peripheral kernels
Bit 8 - HSI clock enabled
Bits 4:7 - MSI clock ranges
Bit 2 - MSI clock PLL enable
impl W<u32, Reg<u32, _ICSCR>>
Bits 24:30 - HSI clock trimming
Bits 8:15 - MSI clock trimming
impl W<u32, Reg<u32, _CFGR>>
Bits 28:30 - Microcontroller clock output prescaler
Bits 24:27 - Microcontroller clock output
Bit 15 - Wakeup from Stop and CSS backup clock selection
Bits 11:13 - APB high-speed prescaler (APB2)
Bits 8:10 - PB low-speed prescaler (APB1)
pub fn sw(&mut self) -> SW_W<'_>
Bits 0:1 - System clock switch
impl W<u32, Reg<u32, _PLLCFGR>>
Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)
Bit 28 - Main PLLSYSR PLLCLK output enable
Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK
Bit 24 - Main PLLSYSQ output enable
Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK
Bit 16 - Main PLLSYSP output enable
Bits 8:14 - Main PLLSYS multiplication factor N
Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source
impl W<u32, Reg<u32, _PLLSAI1CFGR>>
Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)
Bit 28 - PLLSAI PLLADC1CLK output enable
Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
Bit 24 - SAIPLL PLLSAIUSBCLK output enable
Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)
Bit 16 - SAIPLL PLLSAI1CLK output enable
Bits 8:14 - SAIPLL multiplication factor for VCO
impl W<u32, Reg<u32, _CIER>>
Bit 11 - LSI2 ready interrupt enable
Bit 10 - HSI48 ready interrupt enable
Bit 9 - LSE clock security system interrupt enable
Bit 6 - PLLSAI1 ready interrupt enable
Bit 5 - PLLSYS ready interrupt enable
Bit 4 - HSE ready interrupt enable
Bit 3 - HSI ready interrupt enable
Bit 2 - MSI ready interrupt enable
Bit 1 - LSE ready interrupt enable
Bit 0 - LSI1 ready interrupt enable
impl W<u32, Reg<u32, _CICR>>
Bit 11 - LSI2 ready interrupt clear
Bit 10 - HSI48 ready interrupt clear
Bit 9 - LSE Clock security system interrupt clear
Bit 8 - HSE Clock security system interrupt clear
Bit 6 - PLLSAI1 ready interrupt clear
Bit 5 - PLL ready interrupt clear
Bit 4 - HSE ready interrupt clear
Bit 3 - HSI ready interrupt clear
Bit 2 - MSI ready interrupt clear
Bit 1 - LSE ready interrupt clear
Bit 0 - LSI1 ready interrupt clear
impl W<u32, Reg<u32, _SMPSCR>>
Bits 4:5 - Step Down converter clock prescaler
Bits 0:1 - Step Down converter clock selection
impl W<u32, Reg<u32, _AHB1RSTR>>
Bit 16 - Touch Sensing Controller reset
impl W<u32, Reg<u32, _AHB2RSTR>>
Bit 16 - AES1 hardware accelerator reset
impl W<u32, Reg<u32, _AHB3RSTR>>
Bit 25 - Flash interface reset
Bit 20 - IPCC interface reset
Bit 19 - HSEM interface reset
Bit 18 - RNG interface reset
Bit 17 - AES2 interface reset
Bit 16 - PKA interface reset
Bit 8 - Quad SPI memory interface reset
impl W<u32, Reg<u32, _APB1RSTR1>>
Bit 31 - Low Power Timer 1 reset
Bit 9 - LCD interface reset
impl W<u32, Reg<u32, _APB1RSTR2>>
Bit 5 - Low-power timer 2 reset
Bit 0 - Low-power UART 1 reset
impl W<u32, Reg<u32, _APB2RSTR>>
Bit 21 - Serial audio interface 1 (SAI1) reset
Bit 18 - TIM17 timer reset
Bit 17 - TIM16 timer reset
Bit 11 - TIM1 timer reset
impl W<u32, Reg<u32, _APB3RSTR>>
Bit 0 - Radio system BLE reset
impl W<u32, Reg<u32, _AHB1ENR>>
Bit 16 - Touch Sensing Controller clock enable
Bit 12 - CPU1 CRC clock enable
Bit 2 - DMAMUX clock enable
Bit 1 - DMA2 clock enable
Bit 0 - DMA1 clock enable
impl W<u32, Reg<u32, _AHB2ENR>>
Bit 16 - AES1 accelerator clock enable
Bit 13 - ADC clock enable
Bit 7 - IO port H clock enable
Bit 4 - IO port E clock enable
Bit 3 - IO port D clock enable
Bit 2 - IO port C clock enable
Bit 1 - IO port B clock enable
Bit 0 - IO port A clock enable
impl W<u32, Reg<u32, _AHB3ENR>>
impl W<u32, Reg<u32, _APB1ENR1>>
Bit 31 - CPU1 Low power timer 1 clock enable
Bit 26 - CPU1 USB clock enable
Bit 24 - CPU1 CRS clock enable
Bit 23 - CPU1 I2C3 clock enable
Bit 21 - CPU1 I2C1 clock enable
Bit 14 - CPU1 SPI2 clock enable
Bit 11 - CPU1 Window watchdog clock enable
Bit 10 - CPU1 RTC APB clock enable
Bit 9 - CPU1 LCD clock enable
Bit 0 - CPU1 TIM2 timer clock enable
impl W<u32, Reg<u32, _APB1ENR2>>
Bit 0 - CPU1 Low power UART 1 clock enable
impl W<u32, Reg<u32, _APB2ENR>>
Bit 21 - CPU1 SAI1 clock enable
Bit 18 - CPU1 TIM17 timer clock enable
Bit 17 - CPU1 TIM16 timer clock enable
Bit 14 - CPU1 USART1clock enable
Bit 12 - CPU1 SPI1 clock enable
Bit 11 - CPU1 TIM1 timer clock enable
impl W<u32, Reg<u32, _AHB1SMENR>>
Bit 16 - CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
Bit 9 - CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
Bit 2 - CPU1 DMAMUX clocks enable during Sleep and Stop modes
Bit 1 - CPU1 DMA2 clocks enable during Sleep and Stop modes
Bit 0 - CPU1 DMA1 clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _AHB2SMENR>>
Bit 16 - CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
Bit 13 - CPU1 ADC clocks enable during Sleep and Stop modes
Bit 7 - CPU1 IO port H clocks enable during Sleep and Stop modes
Bit 4 - CPU1 IO port E clocks enable during Sleep and Stop modes
Bit 3 - CPU1 IO port D clocks enable during Sleep and Stop modes
Bit 2 - CPU1 IO port C clocks enable during Sleep and Stop modes
Bit 1 - CPU1 IO port B clocks enable during Sleep and Stop modes
Bit 0 - CPU1 IO port A clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _AHB3SMENR>>
Bit 25 - Flash interface clocks enable during CPU1 sleep mode
Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
Bit 18 - True RNG clocks enable during CPU1 sleep mode
Bit 17 - AES2 accelerator clocks enable during CPU1 sleep mode
Bit 16 - PKA accelerator clocks enable during CPU1 sleep mode
impl W<u32, Reg<u32, _APB1SMENR1>>
Bit 31 - Low power timer 1 clocks enable during CPU1 Sleep mode
Bit 26 - USB FS clocks enable during CPU1 Sleep mode
Bit 24 - CRS clocks enable during CPU1 Sleep mode
Bit 23 - I2C3 clocks enable during CPU1 Sleep mode
Bit 21 - I2C1 clocks enable during CPU1 Sleep mode
Bit 14 - SPI2 clocks enable during CPU1 Sleep mode
Bit 11 - Window watchdog clocks enable during CPU1 Sleep mode
Bit 10 - RTC APB clocks enable during CPU1 Sleep mode
Bit 9 - LCD clocks enable during CPU1 Sleep mode
Bit 0 - TIM2 timer clocks enable during CPU1 Sleep mode
impl W<u32, Reg<u32, _APB1SMENR2>>
Bit 5 - Low power timer 2 clocks enable during CPU1 Sleep mode
Bit 0 - Low power UART 1 clocks enable during CPU1 Sleep mode
impl W<u32, Reg<u32, _APB2SMENR>>
Bit 21 - SAI1 clocks enable during CPU1 Sleep mode
Bit 18 - TIM17 timer clocks enable during CPU1 Sleep mode
Bit 17 - TIM16 timer clocks enable during CPU1 Sleep mode
Bit 14 - USART1clocks enable during CPU1 Sleep mode
Bit 12 - SPI1 clocks enable during CPU1 Sleep mode
Bit 11 - TIM1 timer clocks enable during CPU1 Sleep mode
impl W<u32, Reg<u32, _CCIPR>>
Bits 30:31 - RNG clock source selection
Bits 28:29 - ADCs clock source selection
Bits 26:27 - 48 MHz clock source selection
Bits 22:23 - SAI1 clock source selection
Bits 20:21 - Low power timer 2 clock source selection
Bits 18:19 - Low power timer 1 clock source selection
Bits 16:17 - I2C3 clock source selection
Bits 12:13 - I2C1 clock source selection
Bits 10:11 - LPUART1 clock source selection
Bits 0:1 - USART1 clock source selection
impl W<u32, Reg<u32, _BDCR>>
Bits 25:26 - Low speed clock output selection
Bit 24 - Low speed clock output enable
Bit 16 - Backup domain software reset
Bit 15 - RTC clock enable
Bits 8:9 - RTC clock source selection
Bits 3:4 - SE oscillator drive capability
Bit 2 - LSE oscillator bypass
Bit 0 - LSE oscillator enable
impl W<u32, Reg<u32, _CSR>>
Bit 23 - Remove reset flag
Bits 14:15 - RF system wakeup clock source selection
Bits 8:11 - LSI2 oscillator bias configuration
Bit 4 - LSI2 oscillator trimming enable
Bit 2 - LSI2 oscillator enabled
Bit 0 - LSI1 oscillator enabled
impl W<u32, Reg<u32, _CRRCR>>
Bit 0 - HSI48 oscillator enabled
impl W<u32, Reg<u32, _HSECR>>
Bits 4:6 - HSE current control
Bit 3 - HSE Sense amplifier threshold
Bit 0 - Register lock system
impl W<u32, Reg<u32, _EXTCFGR>>
Bits 4:7 - CPU2 AHB prescaler
Bits 0:3 - Shared AHB prescaler
impl W<u32, Reg<u32, _C2AHB1ENR>>
Bit 16 - CPU2 Touch Sensing Controller clock enable
Bit 12 - CPU2 CRC clock enable
Bit 9 - CPU2 SRAM1 clock enable
Bit 2 - CPU2 DMAMUX clock enable
Bit 1 - CPU2 DMA2 clock enable
Bit 0 - CPU2 DMA1 clock enable
impl W<u32, Reg<u32, _C2AHB2ENR>>
Bit 16 - CPU2 AES1 accelerator clock enable
Bit 13 - CPU2 ADC clock enable
Bit 7 - CPU2 IO port H clock enable
Bit 4 - CPU2 IO port E clock enable
Bit 3 - CPU2 IO port D clock enable
Bit 2 - CPU2 IO port C clock enable
Bit 1 - CPU2 IO port B clock enable
Bit 0 - CPU2 IO port A clock enable
impl W<u32, Reg<u32, _C2AHB3ENR>>
impl W<u32, Reg<u32, _C2APB1ENR1>>
Bit 31 - CPU2 Low power timer 1 clock enable
Bit 26 - CPU2 USB clock enable
Bit 24 - CPU2 CRS clock enable
Bit 23 - CPU2 I2C3 clock enable
Bit 21 - CPU2 I2C1 clock enable
Bit 14 - CPU2 SPI2 clock enable
Bit 10 - CPU2 RTC APB clock enable
Bit 9 - CPU2 LCD clock enable
Bit 0 - CPU2 TIM2 timer clock enable
impl W<u32, Reg<u32, _C2APB1ENR2>>
Bit 0 - CPU2 Low power UART 1 clock enable
impl W<u32, Reg<u32, _C2APB2ENR>>
Bit 21 - CPU2 SAI1 clock enable
Bit 18 - CPU2 TIM17 timer clock enable
Bit 17 - CPU2 TIM16 timer clock enable
Bit 14 - CPU2 USART1clock enable
Bit 12 - CPU2 SPI1 clock enable
Bit 11 - CPU2 TIM1 timer clock enable
impl W<u32, Reg<u32, _C2APB3ENR>>
Bit 1 - CPU2 802.15.4 interface clock enable
Bit 0 - CPU2 BLE interface clock enable
impl W<u32, Reg<u32, _C2AHB1SMENR>>
Bit 16 - CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes
Bit 9 - SRAM1 interface clock enable during CPU1 CSleep mode
Bit 2 - CPU2 DMAMUX clocks enable during Sleep and Stop modes
Bit 1 - CPU2 DMA2 clocks enable during Sleep and Stop modes
Bit 0 - CPU2 DMA1 clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _C2AHB2SMENR>>
Bit 16 - CPU2 AES1 accelerator clocks enable during Sleep and Stop modes
Bit 13 - CPU2 ADC clocks enable during Sleep and Stop modes
Bit 7 - CPU2 IO port H clocks enable during Sleep and Stop modes
Bit 4 - CPU2 IO port E clocks enable during Sleep and Stop modes
Bit 3 - CPU2 IO port D clocks enable during Sleep and Stop modes
Bit 2 - CPU2 IO port C clocks enable during Sleep and Stop modes
Bit 1 - CPU2 IO port B clocks enable during Sleep and Stop modes
Bit 0 - CPU2 IO port A clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _C2AHB3SMENR>>
Bit 25 - Flash interface clocks enable during CPU2 sleep modes
Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
Bit 18 - True RNG clocks enable during CPU2 sleep modes
Bit 17 - AES2 accelerator clocks enable during CPU2 sleep modes
Bit 16 - PKA accelerator clocks enable during CPU2 sleep modes
impl W<u32, Reg<u32, _C2APB1SMENR1>>
Bit 31 - Low power timer 1 clocks enable during CPU2 Sleep mode
Bit 26 - USB FS clocks enable during CPU2 Sleep mode
Bit 24 - CRS clocks enable during CPU2 Sleep mode
Bit 23 - I2C3 clocks enable during CPU2 Sleep mode
Bit 21 - I2C1 clocks enable during CPU2 Sleep mode
Bit 14 - SPI2 clocks enable during CPU2 Sleep mode
Bit 10 - RTC APB clocks enable during CPU2 Sleep mode
Bit 9 - LCD clocks enable during CPU2 Sleep mode
Bit 0 - TIM2 timer clocks enable during CPU2 Sleep mode
impl W<u32, Reg<u32, _C2APB1SMENR2>>
Bit 5 - Low power timer 2 clocks enable during CPU2 Sleep mode
Bit 0 - Low power UART 1 clocks enable during CPU2 Sleep mode
impl W<u32, Reg<u32, _C2APB2SMENR>>
Bit 21 - SAI1 clocks enable during CPU2 Sleep mode
Bit 18 - TIM17 timer clocks enable during CPU2 Sleep mode
Bit 17 - TIM16 timer clocks enable during CPU2 Sleep mode
Bit 14 - USART1clocks enable during CPU2 Sleep mode
Bit 12 - SPI1 clocks enable during CPU2 Sleep mode
Bit 11 - TIM1 timer clocks enable during CPU2 Sleep mode
impl W<u32, Reg<u32, _C2APB3SMENR>>
Bit 1 - 802.15.4 interface clocks enable during CPU2 Sleep modes
Bit 0 - BLE interface clocks enable during CPU2 Sleep mode
impl W<u32, Reg<u32, _CR1>>
Bits 9:10 - Voltage scaling range selection
Bit 8 - Disable backup domain write protection
Bit 5 - Flash power down mode during LPsSleep for CPU1
Bit 4 - Flash power down mode during LPRun for CPU1
Bits 0:2 - Low-power mode selection for CPU1
impl W<u32, Reg<u32, _CR2>>
Bit 10 - VDDUSB USB supply valid
Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
Bits 1:3 - Power voltage detector level selection
Bit 0 - Power voltage detector enable
impl W<u32, Reg<u32, _CR3>>
Bit 15 - Enable internal wakeup line for CPU1
Bit 14 - Enable CPU2 Hold interrupt for CPU1
Bit 13 - Enable end of activity interrupt for CPU1
Bit 11 - Enable BLE end of activity interrupt for CPU1
Bit 12 - Enable critical radio phase end of activity interrupt for CPU1
Bit 10 - Apply pull-up and pull-down configuration
Bit 9 - SRAM2a retention in Standby mode
Bit 8 - Enable BORH and Step Down counverter forced in Bypass interrups for CPU1
Bit 4 - Enable Wakeup pin WKUP5
Bit 3 - Enable Wakeup pin WKUP4
Bit 2 - Enable Wakeup pin WKUP3
Bit 1 - Enable Wakeup pin WKUP2
Bit 0 - Enable Wakeup pin WKUP1
impl W<u32, Reg<u32, _CR4>>
Bit 15 - BOOT CPU2 after reset or wakeup from Stop or Standby modes
Bit 9 - VBAT battery charging resistor selection
Bit 8 - VBAT battery charging enable
Bit 4 - Wakeup pin WKUP5 polarity
Bit 3 - Wakeup pin WKUP4 polarity
Bit 2 - Wakeup pin WKUP3 polarity
Bit 1 - Wakeup pin WKUP2 polarity
Bit 0 - Wakeup pin WKUP1 polarity
impl W<u32, Reg<u32, _SCR>>
Bit 14 - Clear CPU2 Hold interrupt flag
Bit 13 - Clear 802.15.4 end of activity interrupt flag
Bit 12 - Clear BLE end of activity interrupt flag
Bit 11 - Clear critical radio phase end of activity interrupt flag
Bit 10 - Clear 802.15.4 wakeup interrupt flag
Bit 9 - Clear BLE wakeup interrupt flag
Bit 8 - Clear BORH interrupt flag
Bit 7 - Clear SMPS Step Down converter forced in Bypass interrupt flag
Bit 4 - Clear wakeup flag 5
Bit 3 - Clear wakeup flag 4
Bit 2 - Clear wakeup flag 3
Bit 1 - Clear wakeup flag 2
Bit 0 - Clear wakeup flag 1
impl W<u32, Reg<u32, _CR5>>
Bit 15 - Enable Step Down converter SMPS mode enabled
Bit 14 - Enable Step Down converter Bypass mode enabled
Bit 9 - VOS configuration selection (non user)
Bit 8 - BORH configuration selection
Bits 4:6 - Step Down converter supplt startup current selection
Bits 0:3 - Step Down converter voltage output scaling
impl W<u32, Reg<u32, _PUCRA>>
Bit 15 - Port A pull-up bit y (y=0..15)
Bit 13 - Port A pull-up bit y (y=0..15)
Bit 12 - Port A pull-up bit y (y=0..15)
Bit 11 - Port A pull-up bit y (y=0..15)
Bit 10 - Port A pull-up bit y (y=0..15)
Bit 9 - Port A pull-up bit y (y=0..15)
Bit 8 - Port A pull-up bit y (y=0..15)
Bit 7 - Port A pull-up bit y (y=0..15)
Bit 6 - Port A pull-up bit y (y=0..15)
Bit 5 - Port A pull-up bit y (y=0..15)
Bit 4 - Port A pull-up bit y (y=0..15)
Bit 3 - Port A pull-up bit y (y=0..15)
Bit 2 - Port A pull-up bit y (y=0..15)
Bit 1 - Port A pull-up bit y (y=0..15)
Bit 0 - Port A pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRA>>
Bit 14 - Port A pull-down bit y (y=0..15)
Bit 12 - Port A pull-down bit y (y=0..15)
Bit 11 - Port A pull-down bit y (y=0..15)
Bit 10 - Port A pull-down bit y (y=0..15)
Bit 9 - Port A pull-down bit y (y=0..15)
Bit 8 - Port A pull-down bit y (y=0..15)
Bit 7 - Port A pull-down bit y (y=0..15)
Bit 6 - Port A pull-down bit y (y=0..15)
Bit 5 - Port A pull-down bit y (y=0..15)
Bit 4 - Port A pull-down bit y (y=0..15)
Bit 3 - Port A pull-down bit y (y=0..15)
Bit 2 - Port A pull-down bit y (y=0..15)
Bit 1 - Port A pull-down bit y (y=0..15)
Bit 0 - Port A pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRB>>
Bit 15 - Port B pull-up bit y (y=0..15)
Bit 14 - Port B pull-up bit y (y=0..15)
Bit 13 - Port B pull-up bit y (y=0..15)
Bit 12 - Port B pull-up bit y (y=0..15)
Bit 11 - Port B pull-up bit y (y=0..15)
Bit 10 - Port B pull-up bit y (y=0..15)
Bit 9 - Port B pull-up bit y (y=0..15)
Bit 8 - Port B pull-up bit y (y=0..15)
Bit 7 - Port B pull-up bit y (y=0..15)
Bit 6 - Port B pull-up bit y (y=0..15)
Bit 5 - Port B pull-up bit y (y=0..15)
Bit 4 - Port B pull-up bit y (y=0..15)
Bit 3 - Port B pull-up bit y (y=0..15)
Bit 2 - Port B pull-up bit y (y=0..15)
Bit 1 - Port B pull-up bit y (y=0..15)
Bit 0 - Port B pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRB>>
Bit 15 - Port B pull-down bit y (y=0..15)
Bit 14 - Port B pull-down bit y (y=0..15)
Bit 13 - Port B pull-down bit y (y=0..15)
Bit 12 - Port B pull-down bit y (y=0..15)
Bit 11 - Port B pull-down bit y (y=0..15)
Bit 10 - Port B pull-down bit y (y=0..15)
Bit 9 - Port B pull-down bit y (y=0..15)
Bit 8 - Port B pull-down bit y (y=0..15)
Bit 7 - Port B pull-down bit y (y=0..15)
Bit 6 - Port B pull-down bit y (y=0..15)
Bit 5 - Port B pull-down bit y (y=0..15)
Bit 3 - Port B pull-down bit y (y=0..15)
Bit 2 - Port B pull-down bit y (y=0..15)
Bit 1 - Port B pull-down bit y (y=0..15)
Bit 0 - Port B pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRC>>
Bit 15 - Port C pull-up bit y (y=0..15)
Bit 14 - Port C pull-up bit y (y=0..15)
Bit 13 - Port C pull-up bit y (y=0..15)
Bit 12 - Port C pull-up bit y (y=0..15)
Bit 11 - Port C pull-up bit y (y=0..15)
Bit 10 - Port C pull-up bit y (y=0..15)
Bit 9 - Port C pull-up bit y (y=0..15)
Bit 8 - Port C pull-up bit y (y=0..15)
Bit 7 - Port C pull-up bit y (y=0..15)
Bit 6 - Port C pull-up bit y (y=0..15)
Bit 5 - Port C pull-up bit y (y=0..15)
Bit 4 - Port C pull-up bit y (y=0..15)
Bit 3 - Port C pull-up bit y (y=0..15)
Bit 2 - Port C pull-up bit y (y=0..15)
Bit 1 - Port C pull-up bit y (y=0..15)
Bit 0 - Port C pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRC>>
Bit 15 - Port C pull-down bit y (y=0..15)
Bit 14 - Port C pull-down bit y (y=0..15)
Bit 13 - Port C pull-down bit y (y=0..15)
Bit 12 - Port C pull-down bit y (y=0..15)
Bit 11 - Port C pull-down bit y (y=0..15)
Bit 10 - Port C pull-down bit y (y=0..15)
Bit 9 - Port C pull-down bit y (y=0..15)
Bit 8 - Port C pull-down bit y (y=0..15)
Bit 7 - Port C pull-down bit y (y=0..15)
Bit 6 - Port C pull-down bit y (y=0..15)
Bit 5 - Port C pull-down bit y (y=0..15)
Bit 4 - Port C pull-down bit y (y=0..15)
Bit 3 - Port C pull-down bit y (y=0..15)
Bit 2 - Port C pull-down bit y (y=0..15)
Bit 1 - Port C pull-down bit y (y=0..15)
Bit 0 - Port C pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRD>>
Bit 15 - Port D pull-up bit y (y=0..15)
Bit 14 - Port D pull-up bit y (y=0..15)
Bit 13 - Port D pull-up bit y (y=0..15)
Bit 12 - Port D pull-up bit y (y=0..15)
Bit 11 - Port D pull-up bit y (y=0..15)
Bit 10 - Port D pull-up bit y (y=0..15)
Bit 9 - Port D pull-up bit y (y=0..15)
Bit 8 - Port D pull-up bit y (y=0..15)
Bit 7 - Port D pull-up bit y (y=0..15)
Bit 6 - Port D pull-up bit y (y=0..15)
Bit 5 - Port D pull-up bit y (y=0..15)
Bit 4 - Port D pull-up bit y (y=0..15)
Bit 3 - Port D pull-up bit y (y=0..15)
Bit 2 - Port D pull-up bit y (y=0..15)
Bit 1 - Port D pull-up bit y (y=0..15)
Bit 0 - Port D pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRD>>
Bit 15 - Port D pull-down bit y (y=0..15)
Bit 14 - Port D pull-down bit y (y=0..15)
Bit 13 - Port D pull-down bit y (y=0..15)
Bit 12 - Port D pull-down bit y (y=0..15)
Bit 11 - Port D pull-down bit y (y=0..15)
Bit 10 - Port D pull-down bit y (y=0..15)
Bit 9 - Port D pull-down bit y (y=0..15)
Bit 8 - Port D pull-down bit y (y=0..15)
Bit 7 - Port D pull-down bit y (y=0..15)
Bit 6 - Port D pull-down bit y (y=0..15)
Bit 5 - Port D pull-down bit y (y=0..15)
Bit 4 - Port D pull-down bit y (y=0..15)
Bit 3 - Port D pull-down bit y (y=0..15)
Bit 2 - Port D pull-down bit y (y=0..15)
Bit 1 - Port D pull-down bit y (y=0..15)
Bit 0 - Port D pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRE>>
Bit 4 - Port E pull-up bit y (y=0..15)
Bit 3 - Port E pull-up bit y (y=0..15)
Bit 2 - Port E pull-up bit y (y=0..15)
Bit 1 - Port E pull-up bit y (y=0..15)
Bit 0 - Port E pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRE>>
Bit 4 - Port E pull-down bit y (y=0..15)
Bit 3 - Port E pull-down bit y (y=0..15)
Bit 2 - Port E pull-down bit y (y=0..15)
Bit 1 - Port E pull-down bit y (y=0..15)
Bit 0 - Port E pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRH>>
Bit 3 - Port H pull-up bit y (y=0..1)
Bit 1 - Port H pull-up bit y (y=0..1)
Bit 0 - Port H pull-up bit y (y=0..1)
impl W<u32, Reg<u32, _PDCRH>>
Bit 3 - Port H pull-down bit y (y=0..1)
Bit 1 - Port H pull-down bit y (y=0..1)
Bit 0 - Port H pull-down bit y (y=0..1)
impl W<u32, Reg<u32, _C2CR1>>
Bit 15 - 802.15.4 external wakeup signal
Bit 14 - BLE external wakeup signal
Bit 5 - Flash power down mode during LPSleep for CPU2
Bit 4 - Flash power down mode during LPRun for CPU2
Bits 0:2 - Low-power mode selection for CPU2
impl W<u32, Reg<u32, _C2CR3>>
Bit 15 - Enable internal wakeup line for CPU2
Bit 12 - Apply pull-up and pull-down configuration for CPU2
Bit 10 - Enable 802.15.4 host wakeup interrupt for CPU2
Bit 9 - Enable BLE host wakeup interrupt for CPU2
Bit 4 - Enable Wakeup pin WKUP5 for CPU2
Bit 3 - Enable Wakeup pin WKUP4 for CPU2
Bit 2 - Enable Wakeup pin WKUP3 for CPU2
Bit 1 - Enable Wakeup pin WKUP2 for CPU2
Bit 0 - Enable Wakeup pin WKUP1 for CPU2
impl W<u32, Reg<u32, _EXTSCR>>
Bit 2 - Clear Critical Radio system phase
Bit 1 - Clear CPU2 Stop Standby flags
Bit 0 - Clear CPU1 Stop Standby flags
impl W<u32, Reg<u32, _MEMRMP>>
Bits 0:2 - Memory mapping selection
impl W<u32, Reg<u32, _CFGR1>>
Bits 26:31 - Floating Point Unit interrupts enable bits
Bit 22 - I2C3 Fast-mode Plus driving capability activation
Bit 20 - I2C1 Fast-mode Plus driving capability activation
Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9
Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8
Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7
Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6
Bit 8 - I/O analog switch voltage booster enable
impl W<u32, Reg<u32, _EXTICR1>>
Bits 12:14 - EXTI 3 configuration bits
Bits 8:10 - EXTI 2 configuration bits
Bits 4:6 - EXTI 1 configuration bits
Bits 0:2 - EXTI 0 configuration bits
impl W<u32, Reg<u32, _EXTICR2>>
Bits 12:14 - EXTI 7 configuration bits
Bits 8:10 - EXTI 6 configuration bits
Bits 4:6 - EXTI 5 configuration bits
Bits 0:2 - EXTI 4 configuration bits
impl W<u32, Reg<u32, _EXTICR3>>
Bits 12:14 - EXTI 11 configuration bits
Bits 8:10 - EXTI 10 configuration bits
Bits 4:6 - EXTI 9 configuration bits
Bits 0:2 - EXTI 8 configuration bits
impl W<u32, Reg<u32, _EXTICR4>>
Bits 12:14 - EXTI15 configuration bits
Bits 8:10 - EXTI14 configuration bits
Bits 4:6 - EXTI13 configuration bits
Bits 0:2 - EXTI12 configuration bits
impl W<u32, Reg<u32, _SCSR>>
Bit 31 - CPU2 SRAM fetch (execution) disable.
impl W<u32, Reg<u32, _CFGR2>>
Bit 8 - SRAM2 parity error flag
Bit 2 - PVD lock enable bit
Bit 1 - SRAM2 parity lock bit
Bit 0 - Cortex-M4 LOCKUP (Hardfault) output enable bit
impl W<u32, Reg<u32, _SWPR>>
Bit 31 - SRAM2 page 31 write protection
impl W<u32, Reg<u32, _SKR>>
Bits 0:7 - SRAM2 write protection key for software erase
impl W<u32, Reg<u32, _SWPR2>>
Bit 31 - SRAM2 page 63 write protection
impl W<u32, Reg<u32, _IMR1>>
Bit 13 - Peripheral TIM1 interrupt mask to CPU1
Bit 14 - Peripheral TIM16 interrupt mask to CPU1
Bit 15 - Peripheral TIM17 interrupt mask to CPU1
Bit 21 - Peripheral EXIT5 interrupt mask to CPU1
Bit 22 - Peripheral EXIT6 interrupt mask to CPU1
Bit 23 - Peripheral EXIT7 interrupt mask to CPU1
Bit 24 - Peripheral EXIT8 interrupt mask to CPU1
Bit 25 - Peripheral EXIT9 interrupt mask to CPU1
Bit 26 - Peripheral EXIT10 interrupt mask to CPU1
Bit 27 - Peripheral EXIT11 interrupt mask to CPU1
Bit 28 - Peripheral EXIT12 interrupt mask to CPU1
Bit 29 - Peripheral EXIT13 interrupt mask to CPU1
Bit 30 - Peripheral EXIT14 interrupt mask to CPU1
Bit 31 - Peripheral EXIT15 interrupt mask to CPU1
impl W<u32, Reg<u32, _IMR2>>
Bit 18 - Peripheral PVM3 interrupt mask to CPU1
Bit 16 - Peripheral PVM1 interrupt mask to CPU1
Bit 20 - Peripheral PVD interrupt mask to CPU1
impl W<u32, Reg<u32, _C2IMR1>>
Bit 0 - Peripheral RTCSTAMP interrupt mask to CPU2
Bit 3 - Peripheral RTCWKUP interrupt mask to CPU2
Bit 4 - Peripheral RTCALARM interrupt mask to CPU2
Bit 5 - Peripheral RCC interrupt mask to CPU2
Bit 6 - Peripheral FLASH interrupt mask to CPU2
Bit 8 - Peripheral PKA interrupt mask to CPU2
Bit 9 - Peripheral RNG interrupt mask to CPU2
Bit 10 - Peripheral AES1 interrupt mask to CPU2
Bit 11 - Peripheral COMP interrupt mask to CPU2
Bit 12 - Peripheral ADC interrupt mask to CPU2
impl W<u32, Reg<u32, _C2IMR2>>
Bit 0 - Peripheral DMA1 CH1 interrupt mask to CPU2
Bit 1 - Peripheral DMA1 CH2 interrupt mask to CPU2
Bit 2 - Peripheral DMA1 CH3 interrupt mask to CPU2
Bit 3 - Peripheral DMA1 CH4 interrupt mask to CPU2
Bit 4 - Peripheral DMA1 CH5 interrupt mask to CPU2
Bit 5 - Peripheral DMA1 CH6 interrupt mask to CPU2
Bit 6 - Peripheral DMA1 CH7 interrupt mask to CPU2
Bit 8 - Peripheral DMA2 CH1 interrupt mask to CPU1
Bit 9 - Peripheral DMA2 CH2 interrupt mask to CPU1
Bit 10 - Peripheral DMA2 CH3 interrupt mask to CPU1
Bit 11 - Peripheral DMA2 CH4 interrupt mask to CPU1
Bit 12 - Peripheral DMA2 CH5 interrupt mask to CPU1
Bit 13 - Peripheral DMA2 CH6 interrupt mask to CPU1
Bit 14 - Peripheral DMA2 CH7 interrupt mask to CPU1
Bit 15 - Peripheral DMAM UX1 interrupt mask to CPU1
Bit 16 - Peripheral PVM1IM interrupt mask to CPU1
Bit 18 - Peripheral PVM3IM interrupt mask to CPU1
Bit 20 - Peripheral PVDIM interrupt mask to CPU1
Bit 21 - Peripheral TSCIM interrupt mask to CPU1
Bit 22 - Peripheral LCDIM interrupt mask to CPU1
impl W<u32, Reg<u32, _SIPCR>>
Bit 0 - Enable AES1 KEY[7:0]
security.
Bit 1 - Enable AES2 security.
Bit 2 - Enable PKA security
Bit 3 - Enable True RNG security
impl W<u32, Reg<u32, _CR>>
Bit 2 - Random number generator enable
pub fn ie(&mut self) -> IE_W<'_>
Bit 6 - Bypass mode enable
impl W<u32, Reg<u32, _SR>>
Bit 6 - Seed error interrupt status
Bit 5 - Clock error interrupt status
impl W<u32, Reg<u32, _CR>>
Bits 20:23 - Number of padding bytes in last block of payload
Bit 18 - Key size selection
Bit 16 - AES chaining mode Bit2
Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
Bit 12 - Enable DMA management of data output phase
pub fn dmainen(&mut self) -> DMAINEN_W<'_>
Bit 11 - Enable DMA management of data input phase
Bit 10 - Error interrupt enable
Bit 9 - CCF flag interrupt enable
Bit 7 - Computation Complete Flag Clear
Bits 5:6 - AES chaining mode Bit1 Bit0
Bits 3:4 - AES operating mode
Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _DINR>>
Bits 0:31 - Data Input Register
impl W<u32, Reg<u32, _KEYR0>>
Bits 0:31 - Data Output Register (LSB key [31:0])
impl W<u32, Reg<u32, _KEYR1>>
Bits 0:31 - AES key register (key [63:32])
impl W<u32, Reg<u32, _KEYR2>>
Bits 0:31 - AES key register (key [95:64])
impl W<u32, Reg<u32, _KEYR3>>
Bits 0:31 - AES key register (MSB key [127:96])
impl W<u32, Reg<u32, _IVR0>>
Bits 0:31 - initialization vector register (LSB IVR [31:0])
impl W<u32, Reg<u32, _IVR1>>
Bits 0:31 - Initialization Vector Register (IVR [63:32])
impl W<u32, Reg<u32, _IVR2>>
Bits 0:31 - Initialization Vector Register (IVR [95:64])
impl W<u32, Reg<u32, _IVR3>>
Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])
impl W<u32, Reg<u32, _KEYR4>>
Bits 0:31 - AES key register (MSB key [159:128])
impl W<u32, Reg<u32, _KEYR5>>
Bits 0:31 - AES key register (MSB key [191:160])
impl W<u32, Reg<u32, _KEYR6>>
Bits 0:31 - AES key register (MSB key [223:192])
impl W<u32, Reg<u32, _KEYR7>>
Bits 0:31 - AES key register (MSB key [255:224])
impl W<u32, Reg<u32, _SUSP0R>>
Bits 0:31 - AES suspend register 0
impl W<u32, Reg<u32, _SUSP1R>>
Bits 0:31 - AES suspend register 1
impl W<u32, Reg<u32, _SUSP2R>>
Bits 0:31 - AES suspend register 2
impl W<u32, Reg<u32, _SUSP3R>>
Bits 0:31 - AES suspend register 3
impl W<u32, Reg<u32, _SUSP4R>>
Bits 0:31 - AES suspend register 4
impl W<u32, Reg<u32, _SUSP5R>>
Bits 0:31 - AES suspend register 5
impl W<u32, Reg<u32, _SUSP6R>>
Bits 0:31 - AES suspend register 6
impl W<u32, Reg<u32, _SUSP7R>>
Bits 0:31 - AES suspend register 7
impl W<u32, Reg<u32, _CR>>
Bits 20:23 - Number of padding bytes in last block of payload
Bit 18 - Key size selection
Bit 16 - AES chaining mode Bit2
Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
Bit 12 - Enable DMA management of data output phase
pub fn dmainen(&mut self) -> DMAINEN_W<'_>
Bit 11 - Enable DMA management of data input phase
Bit 10 - Error interrupt enable
Bit 9 - CCF flag interrupt enable
Bit 7 - Computation Complete Flag Clear
Bits 5:6 - AES chaining mode Bit1 Bit0
Bits 3:4 - AES operating mode
Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _DINR>>
Bits 0:31 - Data Input Register
impl W<u32, Reg<u32, _KEYR0>>
Bits 0:31 - Data Output Register (LSB key [31:0])
impl W<u32, Reg<u32, _KEYR1>>
Bits 0:31 - AES key register (key [63:32])
impl W<u32, Reg<u32, _KEYR2>>
Bits 0:31 - AES key register (key [95:64])
impl W<u32, Reg<u32, _KEYR3>>
Bits 0:31 - AES key register (MSB key [127:96])
impl W<u32, Reg<u32, _IVR0>>
Bits 0:31 - initialization vector register (LSB IVR [31:0])
impl W<u32, Reg<u32, _IVR1>>
Bits 0:31 - Initialization Vector Register (IVR [63:32])
impl W<u32, Reg<u32, _IVR2>>
Bits 0:31 - Initialization Vector Register (IVR [95:64])
impl W<u32, Reg<u32, _IVR3>>
Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])
impl W<u32, Reg<u32, _KEYR4>>
Bits 0:31 - AES key register (MSB key [159:128])
impl W<u32, Reg<u32, _KEYR5>>
Bits 0:31 - AES key register (MSB key [191:160])
impl W<u32, Reg<u32, _KEYR6>>
Bits 0:31 - AES key register (MSB key [223:192])
impl W<u32, Reg<u32, _KEYR7>>
Bits 0:31 - AES key register (MSB key [255:224])
impl W<u32, Reg<u32, _SUSP0R>>
Bits 0:31 - AES suspend register 0
impl W<u32, Reg<u32, _SUSP1R>>
Bits 0:31 - AES suspend register 1
impl W<u32, Reg<u32, _SUSP2R>>
Bits 0:31 - AES suspend register 2
impl W<u32, Reg<u32, _SUSP3R>>
Bits 0:31 - AES suspend register 3
impl W<u32, Reg<u32, _SUSP4R>>
Bits 0:31 - AES suspend register 4
impl W<u32, Reg<u32, _SUSP5R>>
Bits 0:31 - AES suspend register 5
impl W<u32, Reg<u32, _SUSP6R>>
Bits 0:31 - AES suspend register 6
impl W<u32, Reg<u32, _SUSP7R>>
Bits 0:31 - AES suspend register 7
impl W<u32, Reg<u32, _R0>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R1>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R2>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R3>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R4>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R5>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R6>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R7>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R8>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R9>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R10>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R11>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R12>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R13>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R14>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R15>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R16>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R17>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R18>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R19>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R20>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R21>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R22>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R23>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R24>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R25>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R26>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R27>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R28>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R29>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R30>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _R31>>
Bits 8:11 - Semaphore CoreID
Bits 0:7 - Semaphore ProcessID
impl W<u32, Reg<u32, _CR>>
Bits 16:31 - Semaphore clear Key
Bits 8:11 - CoreID of semaphore to be cleared
impl W<u32, Reg<u32, _KEYR>>
Bits 16:31 - Semaphore Clear Key
impl W<u32, Reg<u32, _C1IER>>
Bits 0:31 - CPU(n) semaphore m enable bit
impl W<u32, Reg<u32, _C1ICR>>
Bits 0:31 - CPU(n) semaphore m clear bit
impl W<u32, Reg<u32, _C2IER>>
Bits 0:31 - CPU(2) semaphore m enable bit.
impl W<u32, Reg<u32, _C2ICR>>
Bits 0:31 - CPU(2) semaphore m clear bit
impl W<u32, Reg<u32, _ISR>>
Bit 10 - ADC group injected contexts queue overflow flag
Bit 9 - ADC analog watchdog 3 flag
Bit 8 - ADC analog watchdog 2 flag
Bit 7 - ADC analog watchdog 1 flag
Bit 6 - ADC group injected end of sequence conversions flag
Bit 5 - ADC group injected end of unitary conversion flag
Bit 4 - ADC group regular overrun flag
Bit 3 - ADC group regular end of sequence conversions flag
Bit 2 - ADC group regular end of unitary conversion flag
Bit 1 - ADC group regular end of sampling flag
impl W<u32, Reg<u32, _IER>>
Bit 10 - ADC group injected contexts queue overflow interrupt
Bit 9 - ADC analog watchdog 3 interrupt
Bit 8 - ADC analog watchdog 2 interrupt
Bit 7 - ADC analog watchdog 1 interrupt
Bit 6 - ADC group injected end of sequence conversions interrupt
Bit 5 - ADC group injected end of unitary conversion interrupt
Bit 4 - ADC group regular overrun interrupt
Bit 3 - ADC group regular end of sequence conversions interrupt
Bit 2 - ADC group regular end of unitary conversion interrupt
Bit 1 - ADC group regular end of sampling interrupt
Bit 0 - ADC ready interrupt
impl W<u32, Reg<u32, _CR>>
Bit 30 - ADC differential mode for calibration
Bit 29 - ADC deep power down enable
Bit 28 - ADC voltage regulator enable
Bit 5 - ADC group injected conversion stop
Bit 4 - ADC group regular conversion stop
Bit 3 - ADC group injected conversion start
Bit 2 - ADC group regular conversion start
impl W<u32, Reg<u32, _CFGR>>
Bit 31 - ADC group injected contexts queue disable
Bits 26:30 - ADC analog watchdog 1 monitored channel selection
Bit 25 - ADC group injected automatic trigger mode
Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected
Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular
Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels
Bit 21 - ADC group injected contexts queue mode
Bit 20 - ADC group injected sequencer discontinuous mode
Bits 17:19 - ADC group regular sequencer discontinuous number of ranks
Bit 16 - ADC group regular sequencer discontinuous mode
Bit 14 - ADC low power auto wait
Bit 13 - ADC group regular continuous conversion mode
Bit 12 - ADC group regular overrun configuration
Bits 10:11 - ADC group regular external trigger polarity
Bits 6:9 - ADC group regular external trigger source
Bit 5 - ADC data alignement
Bits 3:4 - ADC data resolution
Bit 1 - ADC DMA transfer configuration
Bit 0 - ADC DMA transfer enable
impl W<u32, Reg<u32, _CFGR2>>
Bit 10 - ADC oversampling mode managing interlaced conversions of ADC group regular and group injected
Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular
Bits 5:8 - ADC oversampling shift
Bits 2:4 - ADC oversampling ratio
Bit 1 - ADC oversampler enable on scope ADC group injected
Bit 0 - ADC oversampler enable on scope ADC group regular
impl W<u32, Reg<u32, _SMPR1>>
Bits 27:29 - ADC channel 9 sampling time selection
Bits 24:26 - ADC channel 8 sampling time selection
Bits 21:23 - ADC channel 7 sampling time selection
Bits 18:20 - ADC channel 6 sampling time selection
Bits 15:17 - ADC channel 5 sampling time selection
Bits 12:14 - ADC channel 4 sampling time selection
Bits 9:11 - ADC channel 3 sampling time selection
Bits 6:8 - ADC channel 2 sampling time selection
Bits 3:5 - ADC channel 1 sampling time selection
impl W<u32, Reg<u32, _SMPR2>>
Bits 24:26 - ADC channel 18 sampling time selection
Bits 21:23 - ADC channel 17 sampling time selection
Bits 18:20 - ADC channel 16 sampling time selection
Bits 15:17 - ADC channel 15 sampling time selection
Bits 12:14 - ADC channel 14 sampling time selection
Bits 9:11 - ADC channel 13 sampling time selection
Bits 6:8 - ADC channel 12 sampling time selection
Bits 3:5 - ADC channel 11 sampling time selection
Bits 0:2 - ADC channel 10 sampling time selection
impl W<u32, Reg<u32, _TR1>>
Bits 16:27 - ADC analog watchdog 1 threshold high
Bits 0:11 - ADC analog watchdog 1 threshold low
impl W<u32, Reg<u32, _TR2>>
Bits 16:23 - ADC analog watchdog 2 threshold high
Bits 0:7 - ADC analog watchdog 2 threshold low
impl W<u32, Reg<u32, _TR3>>
Bits 16:23 - ADC analog watchdog 3 threshold high
Bits 0:7 - ADC analog watchdog 3 threshold low
impl W<u32, Reg<u32, _SQR1>>
Bits 24:28 - ADC group regular sequencer rank 4
Bits 18:22 - ADC group regular sequencer rank 3
Bits 12:16 - ADC group regular sequencer rank 2
Bits 6:10 - ADC group regular sequencer rank 1
pub fn l(&mut self) -> L_W<'_>
Bits 0:3 - Regular channel sequence length
impl W<u32, Reg<u32, _SQR2>>
Bits 24:28 - ADC group regular sequencer rank 9
Bits 18:22 - ADC group regular sequencer rank 8
Bits 12:16 - ADC group regular sequencer rank 7
Bits 6:10 - ADC group regular sequencer rank 6
Bits 0:4 - ADC group regular sequencer rank 5
impl W<u32, Reg<u32, _SQR3>>
Bits 24:28 - ADC group regular sequencer rank 14
Bits 18:22 - ADC group regular sequencer rank 13
Bits 12:16 - ADC group regular sequencer rank 12
Bits 6:10 - ADC group regular sequencer rank 11
Bits 0:4 - ADC group regular sequencer rank 10
impl W<u32, Reg<u32, _SQR4>>
Bits 6:10 - ADC group regular sequencer rank 16
Bits 0:4 - ADC group regular sequencer rank 15
impl W<u32, Reg<u32, _DR>>
Bits 0:5 - Regular Data converted 0_6
impl W<u32, Reg<u32, _JSQR>>
Bits 26:30 - ADC group injected sequencer rank 4
Bits 20:24 - ADC group injected sequencer rank 3
Bits 14:18 - ADC group injected sequencer rank 2
Bits 8:12 - ADC group injected sequencer rank 1
Bits 6:7 - ADC group injected external trigger polarity
Bits 2:5 - ADC group injected external trigger source
pub fn jl(&mut self) -> JL_W<'_>
Bits 0:1 - ADC group injected sequencer scan length
impl W<u32, Reg<u32, _OFR1>>
Bit 31 - ADC offset number 1 enable
Bits 26:30 - ADC offset number 1 channel selection
Bits 0:11 - ADC offset number 1 offset level
impl W<u32, Reg<u32, _OFR2>>
Bit 31 - ADC offset number 2 enable
Bits 26:30 - ADC offset number 2 channel selection
Bits 0:11 - ADC offset number 2 offset level
impl W<u32, Reg<u32, _OFR3>>
Bit 31 - ADC offset number 3 enable
Bits 26:30 - ADC offset number 3 channel selection
Bits 0:11 - ADC offset number 3 offset level
impl W<u32, Reg<u32, _OFR4>>
Bit 31 - ADC offset number 4 enable
Bits 26:30 - ADC offset number 4 channel selection
Bits 0:11 - ADC offset number 4 offset level
impl W<u32, Reg<u32, _AWD2CR>>
Bits 0:18 - ADC analog watchdog 2 monitored channel selection
impl W<u32, Reg<u32, _AWD3CR>>
Bits 0:18 - ADC analog watchdog 3 monitored channel selection
impl W<u32, Reg<u32, _DIFSEL>>
Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15
impl W<u32, Reg<u32, _CALFACT>>
Bits 16:22 - ADC calibration factor in differential mode
Bits 0:6 - ADC calibration factor in single-ended mode
impl W<u32, Reg<u32, _CCR>>
Bit 23 - Temperature sensor enable
Bits 18:21 - ADC prescaler
Bits 16:17 - ADC clock mode
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _MODER>>
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _MODER>>
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 3 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 3 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 19 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _CR1>>
Bit 27 - Master clock generation enable
Bit 26 - Oversampling ratio for master clock
Bits 20:25 - Master clock divider
Bit 16 - Audio block B enable
Bits 10:11 - Synchronization enable
Bit 9 - Clock strobing edge
Bit 8 - Least significant bit first
pub fn ds(&mut self) -> DS_W<'_>
Bits 2:3 - Protocol configuration
Bits 0:1 - Audio block mode
impl W<u32, Reg<u32, _CR2>>
Bits 14:15 - Companding mode
Bit 4 - Tristate management on data line
Bits 0:2 - FIFO threshold
impl W<u32, Reg<u32, _FRCR>>
Bit 18 - Frame synchronization offset
Bit 17 - Frame synchronization polarity
Bit 16 - Frame synchronization definition
Bits 8:14 - Frame synchronization active level length
impl W<u32, Reg<u32, _SLOTR>>
Bits 8:11 - Number of slots in an audio frame
Bits 0:4 - First bit offset
impl W<u32, Reg<u32, _IM>>
Bit 6 - Late frame synchronization detection interrupt enable
Bit 5 - Anticipated frame synchronization detection interrupt enable
Bit 4 - Codec not ready interrupt enable
Bit 3 - FIFO request interrupt enable
Bit 2 - Wrong clock configuration interrupt enable
Bit 1 - Mute detection interrupt enable
Bit 0 - Overrun/underrun interrupt enable
impl W<u32, Reg<u32, _CLRFR>>
Bit 6 - Clear late frame synchronization detection flag
Bit 5 - Clear anticipated frame synchronization detection flag
Bit 4 - Clear codec not ready flag
Bit 2 - Clear wrong clock configuration flag
Bit 1 - Mute detection flag
Bit 0 - Clear overrun / underrun
impl W<u32, Reg<u32, _DR>>
impl W<u32, Reg<u32, _GCR>>
Bits 4:5 - Synchronization outputs
Bits 0:1 - Synchronization inputs
impl W<u32, Reg<u32, _PDMCR>>
Bit 11 - Clock enable of bitstream clock number 4
Bit 10 - Clock enable of bitstream clock number 3
Bit 9 - Clock enable of bitstream clock number 2
Bit 8 - Clock enable of bitstream clock number 1
Bits 4:5 - Number of microphones
impl W<u32, Reg<u32, _PDMDLY>>
Bits 28:30 - Delay line for second microphone of pair 4
Bits 24:26 - Delay line for first microphone of pair 4
Bits 20:22 - Delay line for second microphone of pair 3
Bits 16:18 - Delay line for first microphone of pair 3
Bits 12:14 - Delay line for second microphone of pair 2
Bits 8:10 - Delay line for first microphone of pair 2
Bits 4:6 - Delay line for second microphone of pair 1
Bits 0:2 - Delay line for first microphone of pair 1
impl W<u32, Reg<u32, _CR1>>
Bit 11 - UIF status bit remapping
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
Bit 16 - Slave mode selection - bit 3
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bit 3 - OCREF clear selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 24 - Output Compare 2 mode - bit 3
Bit 16 - Output Compare 1 mode - bit 3
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 24 - Output Compare 4 mode - bit 3
Bit 16 - Output Compare 3 mode - bit 3
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 15 - Capture/Compare 4 output Polarity
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 16:30 - High counter value (TIM2 only)
Bits 0:15 - Low counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 16:31 - High Auto-reload value (TIM2 only)
Bits 0:15 - Low Auto-reload value
impl W<u32, Reg<u32, _CCR1>>
Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
Bits 0:15 - Low Capture/Compare 1 value
impl W<u32, Reg<u32, _CCR2>>
Bits 16:31 - High Capture/Compare 2 value (TIM2 only)
Bits 0:15 - Low Capture/Compare 2 value
impl W<u32, Reg<u32, _CCR3>>
Bits 16:31 - High Capture/Compare value (TIM2 only)
Bits 0:15 - Low Capture/Compare value
impl W<u32, Reg<u32, _CCR4>>
Bits 16:31 - High Capture/Compare value (TIM2 only)
Bits 0:15 - Low Capture/Compare value
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 2:3 - Input capture 4 remap
Bit 1 - External trigger remap
Bit 0 - Internal trigger remap
impl W<u32, Reg<u32, _AF>>
Bits 14:16 - External trigger source selection
impl W<u32, Reg<u32, _CR1>>
Bit 2 - Update request source.
Bit 7 - Auto-reload preload enable.
Bits 8:9 - Clock division.
Bit 11 - UIF status bit remapping.
impl W<u32, Reg<u32, _CR2>>
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
Bit 0 - Update interrupt enable.
Bit 1 - Capture/Compare 1 interrupt enable.
Bit 5 - COM interrupt enable.
Bit 8 - Break interrupt enable.
Bit 8 - Update DMA request enable.
Bits 9:10 - Capture/Compare 1 DMA request enable.
impl W<u32, Reg<u32, _SR>>
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 16 - Output Compare 1 mode
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR1>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:1 - Input capture 1 remap
impl W<u32, Reg<u32, _AF1>>
Bit 0 - BRK BKIN input enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarit
impl W<u32, Reg<u32, _CR1>>
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
impl W<u32, Reg<u32, _CR2>>
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
Bit 0 - Update interrupt enable.
Bit 1 - Capture/Compare 1 interrupt enable.
Bit 5 - COM interrupt enable.
Bit 8 - Break interrupt enable.
Bit 8 - Update DMA request enable.
Bits 9:10 - Capture/Compare 1 DMA request enable.
impl W<u32, Reg<u32, _SR>>
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 16 - Output Compare 1 mode
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR1>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:1 - Input capture 1 remap
impl W<u32, Reg<u32, _AF1>>
Bit 0 - BRK BKIN input enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarit
impl W<u32, Reg<u32, _CR1>>
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
impl W<u32, Reg<u32, _CR2>>
Bits 20:23 - Master mode selection 2
Bit 18 - Output Idle state 6 (OC6 output)
Bit 16 - Output Idle state 5 (OC5 output)
Bit 14 - Output Idle state 4
Bit 13 - Output Idle state 3
Bit 12 - Output Idle state 3
Bit 11 - Output Idle state 2
Bit 10 - Output Idle state 2
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection - bit 3
impl W<u32, Reg<u32, _DIER>>
Bit 0 - Update interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 5 - COM interrupt enable
Bit 6 - Trigger interrupt enable
Bit 7 - Break interrupt enable
Bit 8 - Update DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 13 - COM DMA request enable
Bit 14 - Trigger DMA request enable
impl W<u32, Reg<u32, _SR>>
Bit 0 - Update interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 5 - COM interrupt flag
Bit 6 - Trigger interrupt flag
Bit 7 - Break interrupt flag
Bit 8 - Break 2 interrupt flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 12 - Capture/Compare 4 overcapture flag
Bit 13 - System Break interrupt flag
Bit 16 - Compare 5 interrupt flag
Bit 17 - Compare 6 interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
Bit 1 - Capture/compare 1 generation
Bit 2 - Capture/compare 2 generation
Bit 3 - Capture/compare 3 generation
Bit 4 - Capture/compare 4 generation
Bit 5 - Capture/Compare control update generation
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
pub fn bg(&mut self) -> BG_W<'_>
Bit 8 - Break 2 generation
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 0:1 - Capture/Compare 1 selection
Bits 2:3 - Input capture 1 prescaler
Bits 4:7 - Input capture 1 filter
Bits 8:9 - capture/Compare 2 selection
Bits 10:11 - Input capture 2 prescaler
Bits 12:15 - Input capture 2 filter
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output Compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bit 7 - Output Compare 1 clear enable
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output Compare 2 fast enable
Bit 11 - Output Compare 2 preload enable
Bits 12:14 - Output Compare 2 mode
Bit 15 - Output Compare 2 clear enable
Bit 16 - Output Compare 1 mode - bit 3
Bit 24 - Output Compare 2 mode - bit 3
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bits 0:1 - Capture/Compare 3 selection
Bit 2 - Output compare 3 fast enable
Bit 3 - Output compare 3 preload enable
Bits 4:6 - Output compare 3 mode
Bit 7 - Output compare 3 clear enable
Bits 8:9 - Capture/Compare 4 selection
Bit 10 - Output compare 4 fast enable
Bit 11 - Output compare 4 preload enable
Bits 12:14 - Output compare 4 mode
Bit 15 - Output compare 4 clear enable
Bit 16 - Output Compare 3 mode - bit 3
Bit 24 - Output Compare 4 mode - bit 3
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 0:1 - Capture/Compare 3 selection
Bits 2:3 - Input capture 3 prescaler
Bits 4:7 - Input capture 3 filter
Bits 8:9 - Capture/Compare 4 selection
Bits 10:11 - Input capture 4 prescaler
Bits 12:15 - Input capture 4 filter
impl W<u32, Reg<u32, _CCER>>
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 4 complementary output polarity
Bit 16 - Capture/Compare 5 output enable
Bit 17 - Capture/Compare 5 output polarity
Bit 20 - Capture/Compare 6 output enable
Bit 21 - Capture/Compare 6 output polarity
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:15 - Repetition counter value
impl W<u32, Reg<u32, _CCR1>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _CCR2>>
Bits 0:15 - Capture/Compare 2 value
impl W<u32, Reg<u32, _CCR3>>
Bits 0:15 - Capture/Compare value
impl W<u32, Reg<u32, _CCR4>>
Bits 0:15 - Capture/Compare value
impl W<u32, Reg<u32, _BDTR>>
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 20:23 - Break 2 filter
Bit 25 - Break 2 polarity
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:1 - TIM1_ETR_ADC1 remapping capability
Bit 4 - Input Capture 1 remap
impl W<u32, Reg<u32, _CCMR3_OUTPUT>>
Bit 24 - Output Compare 6 mode bit 3
Bit 16 - Output Compare 5 mode bit 3
Bit 15 - Output compare 6 clear enable
Bits 12:14 - Output compare 6 mode
Bit 11 - Output compare 6 preload enable
Bit 10 - Output compare 6 fast enable
Bit 7 - Output compare 5 clear enable
Bits 4:6 - Output compare 5 mode
Bit 3 - Output compare 5 preload enable
Bit 2 - Output compare 5 fast enable
impl W<u32, Reg<u32, _CCR5>>
Bits 0:15 - Capture/Compare value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
impl W<u32, Reg<u32, _CCR6>>
Bits 0:15 - Capture/Compare value
impl W<u32, Reg<u32, _AF1>>
Bit 0 - BRK BKIN input enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarity
Bits 14:16 - ETR source selection
impl W<u32, Reg<u32, _AF2>>
Bit 0 - BRK2 BKIN input enable
Bit 1 - BRK2 COMP1 enable
Bit 2 - BRK2 COMP2 enable
Bit 8 - BRK2 DFSDM_BREAK0 enable
Bit 9 - BRK2 BKIN input polarity
Bit 10 - BRK2 COMP1 input polarity
Bit 11 - BRK2 COMP2 input polarity
impl W<u32, Reg<u32, _ICR>>
Bit 6 - Direction change to down Clear Flag
Bit 5 - Direction change to UP Clear Flag
Bit 4 - Autoreload register update OK Clear Flag
Bit 3 - Compare register update OK Clear Flag
Bit 2 - External trigger valid edge Clear Flag
Bit 1 - Autoreload match Clear Flag
Bit 0 - compare match Clear Flag
impl W<u32, Reg<u32, _IER>>
Bit 6 - Direction change to down Interrupt Enable
Bit 5 - Direction change to UP Interrupt Enable
Bit 4 - Autoreload register update OK Interrupt Enable
Bit 3 - Compare register update OK Interrupt Enable
Bit 2 - External trigger valid edge Interrupt Enable
Bit 1 - Autoreload match Interrupt Enable
Bit 0 - Compare match Interrupt Enable
impl W<u32, Reg<u32, _CFGR>>
Bit 24 - Encoder mode enable
Bit 23 - counter mode enabled
Bit 22 - Registers update mode
Bit 21 - Waveform shape polarity
Bits 17:18 - Trigger enable and polarity
Bits 13:15 - Trigger selector
Bits 9:11 - Clock prescaler
Bits 6:7 - Configurable digital filter for trigger
Bits 3:4 - Configurable digital filter for external clock
Bits 1:2 - Clock Polarity
impl W<u32, Reg<u32, _CR>>
Bit 4 - Reset after read enable
Bit 2 - Timer start in continuous mode
Bit 1 - LPTIM start in single mode
impl W<u32, Reg<u32, _CMP>>
Bits 0:15 - Compare value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto reload value
impl W<u32, Reg<u32, _OR>>
Bit 0 - Option register bit 1
Bit 1 - Option register bit 2
impl W<u32, Reg<u32, _CR1>>
Bit 31 - RXFIFO Full interrupt enable
Bit 30 - TXFIFO empty interrupt enable
Bit 29 - FIFO mode enable
pub fn m1(&mut self) -> M1_W<'_>
Bit 27 - End of Block interrupt enable
Bit 26 - Receiver timeout interrupt enable
Bit 25 - Driver Enable assertion time
Bit 20 - Driver Enable de-assertion time
Bit 15 - Oversampling mode
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
pub fn m0(&mut self) -> M0_W<'_>
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
pub fn ps(&mut self) -> PS_W<'_>
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
pub fn te(&mut self) -> TE_W<'_>
Bit 3 - Transmitter enable
pub fn re(&mut self) -> RE_W<'_>
Bit 1 - USART enable in Stop mode
pub fn ue(&mut self) -> UE_W<'_>
impl W<u32, Reg<u32, _CR2>>
Bits 28:31 - Address of the USART node
Bits 24:27 - Address of the USART node
Bit 23 - Receiver timeout enable
Bit 22 - Auto baud rate mode
Bit 20 - Auto baud rate enable
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 8 - Last bit clock pulse
Bit 6 - LIN break detection interrupt enable
Bit 5 - LIN break detection length
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored
Bit 0 - Synchronous Slave mode enable
impl W<u32, Reg<u32, _CR3>>
Bits 29:31 - TXFIFO threshold configuration
Bit 28 - RXFIFO threshold interrupt enable
Bits 25:27 - Receive FIFO threshold configuration
Bit 24 - Tr Complete before guard time, interrupt enable
Bit 23 - threshold interrupt enable
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bits 17:19 - Smartcard auto-retry count
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 11 - One sample bit method enable
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 5 - Smartcard mode enable
Bit 4 - Smartcard NACK enable
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _GTPR>>
pub fn gt(&mut self) -> GT_W<'_>
Bits 8:15 - Guard time value
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
Bits 24:31 - Block Length
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
Bit 4 - Transmit data flush request
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 13 - SPI slave underrun clear flag
Bit 12 - End of block clear flag
Bit 11 - Receiver timeout clear flag
Bit 8 - LIN break detection clear flag
Bit 7 - Transmission complete before Guard time clear flag
Bit 6 - Transmission complete clear flag
Bit 5 - TXFIFO empty clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
Bits 0:8 - Transmit data value
impl W<u32, Reg<u32, _PRESC>>
Bits 0:3 - Clock prescaler
impl W<u32, Reg<u32, _CR1>>
Bit 15 - Bidirectional data mode enable
Bit 14 - Output enable in bidirectional mode
Bit 13 - Hardware CRC calculation enable
Bit 12 - CRC transfer next
Bit 11 - Data frame format
Bit 9 - Software slave management
Bit 8 - Internal slave select
pub fn br(&mut self) -> BR_W<'_>
Bits 3:5 - Baud rate control
impl W<u32, Reg<u32, _CR2>>
Bit 0 - Rx buffer DMA enable
Bit 1 - Tx buffer DMA enable
Bit 3 - NSS pulse management
Bit 5 - Error interrupt enable
Bit 6 - RX buffer not empty interrupt enable
Bit 7 - Tx buffer empty interrupt enable
pub fn ds(&mut self) -> DS_W<'_>
Bit 12 - FIFO reception threshold
Bit 13 - Last DMA transfer for reception
Bit 14 - Last DMA transfer for transmission
impl W<u32, Reg<u32, _SR>>
impl W<u32, Reg<u32, _DR>>
pub fn dr(&mut self) -> DR_W<'_>
Bits 0:15 - Data register
impl W<u32, Reg<u32, _CRCPR>>
Bits 0:15 - CRC polynomial register
impl W<u32, Reg<u32, _CSR>>
Bit 0 - Voltage reference buffer enable
Bit 1 - High impedance mode
Bit 2 - Voltage reference scale
impl W<u32, Reg<u32, _CCR>>
impl W<u32, Reg<u32, _TR>>
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _DR>>
pub fn yt(&mut self) -> YT_W<'_>
Bits 20:23 - Year tens in BCD format
pub fn yu(&mut self) -> YU_W<'_>
Bits 16:19 - Year units in BCD format
Bits 13:15 - Week day units
pub fn mt(&mut self) -> MT_W<'_>
Bit 12 - Month tens in BCD format
pub fn mu(&mut self) -> MU_W<'_>
Bits 8:11 - Month units in BCD format
pub fn dt(&mut self) -> DT_W<'_>
Bits 4:5 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 0:3 - Date units in BCD format
impl W<u32, Reg<u32, _CR>>
Bits 0:2 - Wakeup clock selection
Bit 3 - Time-stamp event active edge
Bit 4 - Reference clock detection enable (50 or 60 Hz)
Bit 5 - Bypass the shadow registers
Bit 10 - Wakeup timer enable
Bit 11 - Time stamp enable
Bit 12 - Alarm A interrupt enable
Bit 13 - Alarm B interrupt enable
Bit 14 - Wakeup timer interrupt enable
Bit 15 - Time-stamp interrupt enable
Bit 16 - Add 1 hour (summer time change)
Bit 17 - Subtract 1 hour (winter time change)
Bit 19 - Calibration output selection
Bits 21:22 - Output selection
Bit 23 - Calibration output enable
Bit 24 - timestamp on internal event enable
impl W<u32, Reg<u32, _ISR>>
Bit 3 - Shift operation pending
Bit 5 - Registers synchronization flag
Bit 7 - Initialization mode
Bit 10 - Wakeup timer flag
Bit 12 - Time-stamp overflow flag
Bit 13 - Tamper detection flag
Bit 14 - RTC_TAMP2 detection flag
Bit 15 - RTC_TAMP3 detection flag
Bit 17 - INTERNAL TIME-STAMP FLAG
impl W<u32, Reg<u32, _PRER>>
Bits 16:22 - Asynchronous prescaler factor
Bits 0:14 - Synchronous prescaler factor
impl W<u32, Reg<u32, _WUTR>>
Bits 0:15 - Wakeup auto-reload value bits
impl W<u32, Reg<u32, _ALRMAR>>
Bit 31 - Alarm A date mask
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
Bits 28:29 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm A hours mask
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm A minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm A seconds mask
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _ALRMBR>>
Bit 31 - Alarm B date mask
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
Bits 28:29 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm B hours mask
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm B minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm B seconds mask
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _WPR>>
Bits 0:7 - Write protection key
impl W<u32, Reg<u32, _SHIFTR>>
Bits 0:14 - Subtract a fraction of a second
impl W<u32, Reg<u32, _CALR>>
Bit 15 - Increase frequency of RTC by 488.5 ppm
Bit 14 - Use an 8-second calibration cycle period
Bit 13 - Use a 16-second calibration cycle period
Bits 0:8 - Calibration minus
impl W<u32, Reg<u32, _TAMPCR>>
Bit 0 - Tamper 1 detection enable
Bit 1 - Active level for tamper 1
Bit 2 - Tamper interrupt enable
Bit 3 - Tamper 2 detection enable
Bit 4 - Active level for tamper 2
Bit 5 - Tamper 3 detection enable
Bit 6 - Active level for tamper 3
Bit 7 - Activate timestamp on tamper detection event
Bits 8:10 - Tamper sampling frequency
Bits 11:12 - Tamper filter count
Bits 13:14 - Tamper precharge duration
Bit 15 - TAMPER pull-up disable
Bit 16 - Tamper 1 interrupt enable
Bit 17 - Tamper 1 no erase
Bit 18 - Tamper 1 mask flag
Bit 19 - Tamper 2 interrupt enable
Bit 20 - Tamper 2 no erase
Bit 21 - Tamper 2 mask flag
Bit 22 - Tamper 3 interrupt enable
Bit 23 - Tamper 3 no erase
Bit 24 - Tamper 3 mask flag
impl W<u32, Reg<u32, _ALRMASSR>>
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _ALRMBSSR>>
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _OR>>
Bit 0 - RTC_ALARM on PC13 output type
impl W<u32, Reg<u32, _BKP0R>>
impl W<u32, Reg<u32, _BKP1R>>
impl W<u32, Reg<u32, _BKP2R>>
impl W<u32, Reg<u32, _BKP3R>>
impl W<u32, Reg<u32, _BKP4R>>
impl W<u32, Reg<u32, _BKP5R>>
impl W<u32, Reg<u32, _BKP6R>>
impl W<u32, Reg<u32, _BKP7R>>
impl W<u32, Reg<u32, _BKP8R>>
impl W<u32, Reg<u32, _BKP9R>>
impl W<u32, Reg<u32, _BKP10R>>
impl W<u32, Reg<u32, _BKP11R>>
impl W<u32, Reg<u32, _BKP12R>>
impl W<u32, Reg<u32, _BKP13R>>
impl W<u32, Reg<u32, _BKP14R>>
impl W<u32, Reg<u32, _BKP15R>>
impl W<u32, Reg<u32, _BKP16R>>
impl W<u32, Reg<u32, _BKP17R>>
impl W<u32, Reg<u32, _BKP18R>>
impl W<u32, Reg<u32, _BKP19R>>
impl W<u32, Reg<u32, _CR>>
Bit 2 - Debug Standby Mode
Bit 5 - Trace port and clock enable
Bit 28 - External trigger output enable
impl W<u32, Reg<u32, _APB1FZR1>>
Bit 0 - Debug Timer 2 stopped when Core is halted
Bit 10 - RTC counter stopped when core is halted
Bit 11 - WWDG counter stopped when core is halted
Bit 12 - IWDG counter stopped when core is halted
Bit 21 - Debug I2C1 SMBUS timeout stopped when Core is halted
Bit 23 - Debug I2C3 SMBUS timeout stopped when core is halted
Bit 31 - Debug LPTIM1 stopped when Core is halted
impl W<u32, Reg<u32, _C2AP_B1FZR1>>
Bit 0 - LPTIM2 counter stopped when core is halted
Bit 10 - RTC counter stopped when core is halted
Bit 12 - IWDG stopped when core is halted
Bit 21 - I2C1 SMBUS timeout stopped when core is halted
Bit 23 - I2C3 SMBUS timeout stopped when core is halted
Bit 31 - LPTIM1 counter stopped when core is halted
impl W<u32, Reg<u32, _APB1FZR2>>
Bit 5 - LPTIM2 counter stopped when core is halted
impl W<u32, Reg<u32, _C2APB1FZR2>>
Bit 5 - LPTIM2 counter stopped when core is halted
impl W<u32, Reg<u32, _APB2FZR>>
Bit 11 - TIM1 counter stopped when core is halted
Bit 17 - TIM16 counter stopped when core is halted
Bit 18 - TIM17 counter stopped when core is halted
impl W<u32, Reg<u32, _C2APB2FZR>>
Bit 11 - TIM1 counter stopped when core is halted
Bit 17 - TIM16 counter stopped when core is halted
Bit 18 - TIM17 counter stopped when core is halted
impl W<u32, Reg<u32, _CR>>
Bit 20 - Address error interrupt enable
Bit 19 - RAM error interrupt enable
Bit 17 - End of operation interrupt enable
Bits 8:13 - PKA Operation Mode
Bit 1 - Start the operation
pub fn en(&mut self) -> EN_W<'_>
Bit 0 - Peripheral Enable
impl W<u32, Reg<u32, _CLRFR>>
Bit 20 - Clear Address error flag
Bit 19 - Clear RAM error flag
Bit 17 - Clear PKA End of Operation flag
impl W<u32, Reg<u32, _C1CR>>
Bit 16 - processor 1 Transmit channel free interrupt enable
Bit 0 - processor 1 Receive channel occupied interrupt enable
impl W<u32, Reg<u32, _C1MR>>
Bit 21 - processor 1 Transmit channel 6 free interrupt mask
Bit 20 - processor 1 Transmit channel 5 free interrupt mask
Bit 19 - processor 1 Transmit channel 4 free interrupt mask
Bit 18 - processor 1 Transmit channel 3 free interrupt mask
Bit 17 - processor 1 Transmit channel 2 free interrupt mask
Bit 16 - processor 1 Transmit channel 1 free interrupt mask
Bit 5 - processor 1 Receive channel 6 occupied interrupt enable
Bit 4 - processor 1 Receive channel 5 occupied interrupt enable
Bit 3 - processor 1 Receive channel 4 occupied interrupt enable
Bit 2 - processor 1 Receive channel 3 occupied interrupt enable
Bit 1 - processor 1 Receive channel 2 occupied interrupt enable
Bit 0 - processor 1 Receive channel 1 occupied interrupt enable
impl W<u32, Reg<u32, _C1SCR>>
Bit 21 - processor 1 Transmit channel 6 status set
Bit 20 - processor 1 Transmit channel 5 status set
Bit 19 - processor 1 Transmit channel 4 status set
Bit 18 - processor 1 Transmit channel 3 status set
Bit 17 - processor 1 Transmit channel 2 status set
Bit 16 - processor 1 Transmit channel 1 status set
Bit 5 - processor 1 Receive channel 6 status clear
Bit 4 - processor 1 Receive channel 5 status clear
Bit 3 - processor 1 Receive channel 4 status clear
Bit 2 - processor 1 Receive channel 3 status clear
Bit 1 - processor 1 Receive channel 2 status clear
Bit 0 - processor 1 Receive channel 1 status clear
impl W<u32, Reg<u32, _C2CR>>
Bit 16 - processor 2 Transmit channel free interrupt enable
Bit 0 - processor 2 Receive channel occupied interrupt enable
impl W<u32, Reg<u32, _C2MR>>
Bit 21 - processor 2 Transmit channel 6 free interrupt mask
Bit 20 - processor 2 Transmit channel 5 free interrupt mask
Bit 19 - processor 2 Transmit channel 4 free interrupt mask
Bit 18 - processor 2 Transmit channel 3 free interrupt mask
Bit 17 - processor 2 Transmit channel 2 free interrupt mask
Bit 16 - processor 2 Transmit channel 1 free interrupt mask
Bit 5 - processor 2 Receive channel 6 occupied interrupt enable
Bit 4 - processor 2 Receive channel 5 occupied interrupt enable
Bit 3 - processor 2 Receive channel 4 occupied interrupt enable
Bit 2 - processor 2 Receive channel 3 occupied interrupt enable
Bit 1 - processor 2 Receive channel 2 occupied interrupt enable
Bit 0 - processor 2 Receive channel 1 occupied interrupt enable
impl W<u32, Reg<u32, _C2SCR>>
Bit 21 - processor 2 Transmit channel 6 status set
Bit 20 - processor 2 Transmit channel 5 status set
Bit 19 - processor 2 Transmit channel 4 status set
Bit 18 - processor 2 Transmit channel 3 status set
Bit 17 - processor 2 Transmit channel 2 status set
Bit 16 - processor 2 Transmit channel 1 status set
Bit 5 - processor 2 Receive channel 6 status clear
Bit 4 - processor 2 Receive channel 5 status clear
Bit 3 - processor 2 Receive channel 4 status clear
Bit 2 - processor 2 Receive channel 3 status clear
Bit 1 - processor 2 Receive channel 2 status clear
Bit 0 - processor 2 Receive channel 1 status clear
impl W<u32, Reg<u32, _RTSR1>>
pub fn rt(&mut self) -> RT_W<'_>
Bits 0:21 - Rising trigger event configuration bit of Configurable Event input
Bit 31 - Rising trigger event configuration bit of Configurable Event input
Bit 0 - Rising trigger event configuration bit of configurable Event input 0.
Bit 1 - Rising trigger event configuration bit of configurable Event input 1.
Bit 2 - Rising trigger event configuration bit of configurable Event input 2.
Bit 3 - Rising trigger event configuration bit of configurable Event input 3.
Bit 4 - Rising trigger event configuration bit of configurable Event input 4.
Bit 5 - Rising trigger event configuration bit of configurable Event input 5.
Bit 6 - Rising trigger event configuration bit of configurable Event input 6.
Bit 7 - Rising trigger event configuration bit of configurable Event input 7.
Bit 8 - Rising trigger event configuration bit of configurable Event input 8.
Bit 9 - Rising trigger event configuration bit of configurable Event input 9.
Bit 10 - Rising trigger event configuration bit of configurable Event input 10.
Bit 11 - Rising trigger event configuration bit of configurable Event input 11.
Bit 12 - Rising trigger event configuration bit of configurable Event input 12.
Bit 13 - Rising trigger event configuration bit of configurable Event input 13.
Bit 14 - Rising trigger event configuration bit of configurable Event input 14.
Bit 15 - Rising trigger event configuration bit of configurable Event input 15.
Bit 16 - Rising trigger event configuration bit of configurable Event input 16.
Bit 17 - Rising trigger event configuration bit of configurable Event input 17.
Bit 18 - Rising trigger event configuration bit of configurable Event input 18.
Bit 19 - Rising trigger event configuration bit of configurable Event input 19.
Bit 20 - Rising trigger event configuration bit of configurable Event input 20.
Bit 21 - Rising trigger event configuration bit of configurable Event input 21.
Bit 31 - Rising trigger event configuration bit of configurable Event input 31.
impl W<u32, Reg<u32, _FTSR1>>
pub fn ft(&mut self) -> FT_W<'_>
Bits 0:21 - Falling trigger event configuration bit of Configurable Event input
Bit 31 - Falling trigger event configuration bit of Configurable Event input
Bit 0 - Falling trigger event configuration bit of configurable Event input 0.
Bit 1 - Falling trigger event configuration bit of configurable Event input 1.
Bit 2 - Falling trigger event configuration bit of configurable Event input 2.
Bit 3 - Falling trigger event configuration bit of configurable Event input 3.
Bit 4 - Falling trigger event configuration bit of configurable Event input 4.
Bit 5 - Falling trigger event configuration bit of configurable Event input 5.
Bit 6 - Falling trigger event configuration bit of configurable Event input 6.
Bit 7 - Falling trigger event configuration bit of configurable Event input 7.
Bit 8 - Falling trigger event configuration bit of configurable Event input 8.
Bit 9 - Falling trigger event configuration bit of configurable Event input 9.
Bit 10 - Falling trigger event configuration bit of configurable Event input 10.
Bit 11 - Falling trigger event configuration bit of configurable Event input 11.
Bit 12 - Falling trigger event configuration bit of configurable Event input 12.
Bit 13 - Falling trigger event configuration bit of configurable Event input 13.
Bit 14 - Falling trigger event configuration bit of configurable Event input 14.
Bit 15 - Falling trigger event configuration bit of configurable Event input 15.
Bit 16 - Falling trigger event configuration bit of configurable Event input 16.
Bit 17 - Falling trigger event configuration bit of configurable Event input 17.
Bit 18 - Falling trigger event configuration bit of configurable Event input 18.
Bit 19 - Falling trigger event configuration bit of configurable Event input 19.
Bit 20 - Falling trigger event configuration bit of configurable Event input 20.
Bit 21 - Falling trigger event configuration bit of configurable Event input 21.
Bit 31 - Falling trigger event configuration bit of configurable Event input 31.
impl W<u32, Reg<u32, _SWIER1>>
Bits 0:21 - Software interrupt on event
Bit 31 - Software interrupt on event
impl W<u32, Reg<u32, _PR1>>
Bits 0:21 - Configurable event inputs Pending bit
Bit 31 - Configurable event inputs Pending bit
impl W<u32, Reg<u32, _RTSR2>>
Bit 1 - Rising trigger event configuration bit of Configurable Event input
Bits 8:9 - Rising trigger event configuration bit of Configurable Event input
impl W<u32, Reg<u32, _FTSR2>>
Bit 1 - Falling trigger event configuration bit of Configurable Event input
Bits 8:9 - Falling trigger event configuration bit of Configurable Event input
impl W<u32, Reg<u32, _SWIER2>>
Bit 1 - Software interrupt on event
Bits 8:9 - Software interrupt on event
impl W<u32, Reg<u32, _PR2>>
Bit 1 - Configurable event inputs x+32 Pending bit.
Bits 8:9 - Configurable event inputs x+32 Pending bit.
impl W<u32, Reg<u32, _IMR1>>
pub fn im(&mut self) -> IM_W<'_>
Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input
Bit 0 - CPU wakeup with interrupt mask on event input 0.
Bit 1 - CPU wakeup with interrupt mask on event input 1.
Bit 2 - CPU wakeup with interrupt mask on event input 2.
Bit 3 - CPU wakeup with interrupt mask on event input 3.
Bit 4 - CPU wakeup with interrupt mask on event input 4.
Bit 5 - CPU wakeup with interrupt mask on event input 5.
Bit 6 - CPU wakeup with interrupt mask on event input 6.
Bit 7 - CPU wakeup with interrupt mask on event input 7.
Bit 8 - CPU wakeup with interrupt mask on event input 8.
Bit 9 - CPU wakeup with interrupt mask on event input 9.
Bit 10 - CPU wakeup with interrupt mask on event input 10.
Bit 11 - CPU wakeup with interrupt mask on event input 11.
Bit 12 - CPU wakeup with interrupt mask on event input 12.
Bit 13 - CPU wakeup with interrupt mask on event input 13.
Bit 14 - CPU wakeup with interrupt mask on event input 14.
Bit 15 - CPU wakeup with interrupt mask on event input 15.
Bit 16 - CPU wakeup with interrupt mask on event input 16.
Bit 17 - CPU wakeup with interrupt mask on event input 17.
Bit 18 - CPU wakeup with interrupt mask on event input 18.
Bit 19 - CPU wakeup with interrupt mask on event input 19.
Bit 20 - CPU wakeup with interrupt mask on event input 20.
Bit 21 - CPU wakeup with interrupt mask on event input 21.
Bit 22 - CPU wakeup with interrupt mask on event input 22.
Bit 23 - CPU wakeup with interrupt mask on event input 23.
Bit 24 - CPU wakeup with interrupt mask on event input 24.
Bit 25 - CPU wakeup with interrupt mask on event input 25.
Bit 26 - CPU wakeup with interrupt mask on event input 26.
Bit 27 - CPU wakeup with interrupt mask on event input 27.
Bit 28 - CPU wakeup with interrupt mask on event input 28.
Bit 29 - CPU wakeup with interrupt mask on event input 29.
Bit 30 - CPU wakeup with interrupt mask on event input 30.
Bit 31 - CPU wakeup with interrupt mask on event input 31.
impl W<u32, Reg<u32, _C2IMR1>>
pub fn im(&mut self) -> IM_W<'_>
Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input
impl W<u32, Reg<u32, _C1EMR1>>
Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input
Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input
impl W<u32, Reg<u32, _C2EMR1>>
Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input
Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input
impl W<u32, Reg<u32, _C1IMR2>>
pub fn im(&mut self) -> IM_W<'_>
Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input
impl W<u32, Reg<u32, _C2IMR2>>
pub fn im(&mut self) -> IM_W<'_>
Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input
impl W<u32, Reg<u32, _C1EMR2>>
pub fn em(&mut self) -> EM_W<'_>
Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input
impl W<u32, Reg<u32, _C2EMR2>>
pub fn em(&mut self) -> EM_W<'_>
Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input
impl W<u32, Reg<u32, _CR>>
Bit 0 - SYNC event OK interrupt enable
Bit 1 - SYNC warning interrupt enable
Bit 2 - Synchronization or trimming error interrupt enable
Bit 3 - Expected SYNC interrupt enable
Bit 5 - Frequency error counter enable
Bit 6 - Automatic trimming enable
Bit 7 - Automatic trimming enable
Bits 8:13 - HSI48 oscillator smooth trimming
impl W<u32, Reg<u32, _CFGR>>
Bits 0:15 - Counter reload value
Bits 16:23 - Frequency error limit
Bits 28:29 - SYNC signal source selection
Bit 31 - SYNC polarity selection
impl W<u32, Reg<u32, _ICR>>
Bit 0 - SYNC event OK clear flag
Bit 1 - warning clear flag
Bit 3 - Expected SYNC clear flag
impl W<u16, Reg<u16, _EP0R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _EP1R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _EP2R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _EP3R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _EP4R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _EP5R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _EP6R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _EP7R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u16, Reg<u16, _CNTR>>
Bit 5 - LPM L1 Resume request
Bit 7 - LPM L1 state request interrupt mask
Bit 8 - Expected start of frame interrupt mask
Bit 9 - Start of frame interrupt mask
Bit 10 - USB reset interrupt mask
Bit 11 - Suspend mode interrupt mask
Bit 12 - Wakeup interrupt mask
Bit 13 - Error interrupt mask
Bit 14 - Packet memory area over / underrun interrupt mask
Bit 15 - Correct transfer interrupt mask
impl W<u16, Reg<u16, _ISTR>>
Bit 7 - LPM L1 state request
Bit 8 - Expected start frame
Bit 11 - Suspend mode request
Bit 14 - Packet memory area over / underrun
impl W<u16, Reg<u16, _DADDR>>
Bits 0:6 - Device address
pub fn ef(&mut self) -> EF_W<'_>
impl W<u16, Reg<u16, _BTABLE>>
impl W<u16, Reg<u16, _COUNT0_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _COUNT1_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _COUNT2_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _COUNT3_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _COUNT4_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _COUNT5_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _COUNT6_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _COUNT7_TX>>
Bits 0:9 - Transmission byte count
impl W<u16, Reg<u16, _ADDR0_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _ADDR1_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _ADDR2_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _ADDR3_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _ADDR4_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _ADDR5_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _ADDR6_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _ADDR7_RX>>
Bits 1:15 - Reception buffer address
impl W<u16, Reg<u16, _COUNT0_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _COUNT1_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _COUNT2_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _COUNT3_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _COUNT4_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _COUNT5_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _COUNT6_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _COUNT7_RX>>
Bits 10:14 - Number of blocks
impl W<u16, Reg<u16, _LPMCSR>>
Bit 0 - LPM support enable
Bit 1 - LPM Token acknowledge enable
impl W<u16, Reg<u16, _BCDR>>
Bit 0 - Battery charging detector (BCD) enable
Bit 1 - Data contact detection (DCD) mode enable
Bit 2 - Primary detection (PD) mode enable
Bit 3 - Secondary detection (SD) mode enable
Bit 15 - DP pull-up control
impl W<u32, Reg<u32, _CTRL>>
Bit 1 - SysTick exception request enable
Bit 2 - Clock source selection
impl W<u32, Reg<u32, _LOAD>>
impl W<u32, Reg<u32, _VAL>>
Bits 0:23 - Current counter value
impl W<u32, Reg<u32, _CALIB>>
Bits 0:23 - Calibration value
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
Bit 31 - NOREF flag. Reads as zero
impl W<u32, Reg<u32, _STIR>>
Bits 0:8 - Software generated interrupt ID
impl W<u32, Reg<u32, _ACTRL>>
impl W<u32, Reg<u32, _CPACR>>
pub fn cp(&mut self) -> CP_W<'_>
impl<T> Any for T where
T: 'static + ?Sized,
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more
impl<T, U> Into<U> for T where
U: From<T>,
The type returned in the event of a conversion error.
The type returned in the event of a conversion error.