stm32wb_stm32hal/stm32wb55/

mod.rs

#![deny(unused_allocation)]
#![deny(unused_comparisons)]
extern crate cortex_m;
#[cfg(feature = "rt")]
extern crate cortex_m_rt;
extern crate vcell;
use core::marker::PhantomData;
use core::ops::Deref;
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
extern "C" {
    fn WWDG();
    fn PVD();
    fn RTC_TAMP();
    fn RTC_WKUP();
    fn FLASH();
    fn RCC();
    fn EXTI0();
    fn EXTI1();
    fn EXTI2();
    fn EXTI3();
    fn EXTI4();
    fn DMA1_CHANNEL1();
    fn DMA1_CHANNEL2();
    fn DMA1_CHANNEL3();
    fn DMA1_CHANNEL4();
    fn DMA1_CHANNEL5();
    fn DMA1_CHANNEL6();
    fn DMA1_CHANNEL7();
    fn ADC1();
    fn USB_HP();
    fn USB_LP();
    fn C2SEV();
    fn COMP();
    fn EXTI5_9();
    fn TIM1_BRK();
    fn TIM1_UP();
    fn TIM1_TRG_COM_TIM17();
    fn TIM1_CC();
    fn TIM2();
    fn PKA();
    fn I2C1_EV();
    fn I2C1_ER();
    fn I2C3_EV();
    fn I2C3_ER();
    fn SPI1();
    fn SPI2();
    fn USART1();
    fn LPUART1();
    fn SAI1();
    fn TSC();
    fn EXTI10_15();
    fn RTC_ALARM();
    fn CRS_IT();
    fn PWR_SOTF();
    fn IPCC_C1_RX_IT();
    fn IPCC_C1_TX_IT();
    fn HSEM();
    fn LPTIM1();
    fn LPTIM2();
    fn LCD();
    fn QUADSPI();
    fn AES1();
    fn AES2();
    fn TRUE_RNG();
    fn FPU();
    fn DMA2_CH1();
    fn DMA2_CH2();
    fn DMA2_CH3();
    fn DMA2_CH4();
    fn DMA2_CH5();
    fn DMA2_CH6();
    fn DMA2_CH7();
    fn DMAMUX_OVR();
}
#[doc(hidden)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 63] = [
    Vector { _handler: WWDG },
    Vector { _handler: PVD },
    Vector { _handler: RTC_TAMP },
    Vector { _handler: RTC_WKUP },
    Vector { _handler: FLASH },
    Vector { _handler: RCC },
    Vector { _handler: EXTI0 },
    Vector { _handler: EXTI1 },
    Vector { _handler: EXTI2 },
    Vector { _handler: EXTI3 },
    Vector { _handler: EXTI4 },
    Vector {
        _handler: DMA1_CHANNEL1,
    },
    Vector {
        _handler: DMA1_CHANNEL2,
    },
    Vector {
        _handler: DMA1_CHANNEL3,
    },
    Vector {
        _handler: DMA1_CHANNEL4,
    },
    Vector {
        _handler: DMA1_CHANNEL5,
    },
    Vector {
        _handler: DMA1_CHANNEL6,
    },
    Vector {
        _handler: DMA1_CHANNEL7,
    },
    Vector { _handler: ADC1 },
    Vector { _handler: USB_HP },
    Vector { _handler: USB_LP },
    Vector { _handler: C2SEV },
    Vector { _handler: COMP },
    Vector { _handler: EXTI5_9 },
    Vector { _handler: TIM1_BRK },
    Vector { _handler: TIM1_UP },
    Vector {
        _handler: TIM1_TRG_COM_TIM17,
    },
    Vector { _handler: TIM1_CC },
    Vector { _handler: TIM2 },
    Vector { _handler: PKA },
    Vector { _handler: I2C1_EV },
    Vector { _handler: I2C1_ER },
    Vector { _handler: I2C3_EV },
    Vector { _handler: I2C3_ER },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector { _handler: USART1 },
    Vector { _handler: LPUART1 },
    Vector { _handler: SAI1 },
    Vector { _handler: TSC },
    Vector {
        _handler: EXTI10_15,
    },
    Vector {
        _handler: RTC_ALARM,
    },
    Vector { _handler: CRS_IT },
    Vector { _handler: PWR_SOTF },
    Vector {
        _handler: IPCC_C1_RX_IT,
    },
    Vector {
        _handler: IPCC_C1_TX_IT,
    },
    Vector { _handler: HSEM },
    Vector { _handler: LPTIM1 },
    Vector { _handler: LPTIM2 },
    Vector { _handler: LCD },
    Vector { _handler: QUADSPI },
    Vector { _handler: AES1 },
    Vector { _handler: AES2 },
    Vector { _handler: TRUE_RNG },
    Vector { _handler: FPU },
    Vector { _handler: DMA2_CH1 },
    Vector { _handler: DMA2_CH2 },
    Vector { _handler: DMA2_CH3 },
    Vector { _handler: DMA2_CH4 },
    Vector { _handler: DMA2_CH5 },
    Vector { _handler: DMA2_CH6 },
    Vector { _handler: DMA2_CH7 },
    Vector {
        _handler: DMAMUX_OVR,
    },
];
///Enumeration of all the interrupts
#[derive(Copy, Clone, Debug)]
#[repr(u8)]
pub enum Interrupt {
    ///0 - Window Watchdog interrupt
    WWDG = 0,
    ///1 - PVD through EXTI\[16\]
    ///(C1IMR2\[20\])
    PVD = 1,
    ///2 - RTC/TAMP/CSS on LSE through EXTI line 19 interrupt
    RTC_TAMP = 2,
    ///3 - RTC wakeup interrupt through EXTI\[19\]
    RTC_WKUP = 3,
    ///4 - Flash global interrupt
    FLASH = 4,
    ///5 - RCC global interrupt
    RCC = 5,
    ///6 - EXTI line 0 interrupt through EXTI\[0\]
    EXTI0 = 6,
    ///7 - EXTI line 0 interrupt through EXTI\[1\]
    EXTI1 = 7,
    ///8 - EXTI line 0 interrupt through EXTI\[2\]
    EXTI2 = 8,
    ///9 - EXTI line 0 interrupt through EXTI\[3\]
    EXTI3 = 9,
    ///10 - EXTI line 0 interrupt through EXTI\[4\]
    EXTI4 = 10,
    ///11 - DMA1 Channel1 global interrupt
    DMA1_CHANNEL1 = 11,
    ///12 - DMA1 Channel2 global interrupt
    DMA1_CHANNEL2 = 12,
    ///13 - DMA1 Channel3 interrupt
    DMA1_CHANNEL3 = 13,
    ///14 - DMA1 Channel4 interrupt
    DMA1_CHANNEL4 = 14,
    ///15 - DMA1 Channel5 interrupt
    DMA1_CHANNEL5 = 15,
    ///16 - DMA1 Channel6 interrupt
    DMA1_CHANNEL6 = 16,
    ///17 - DMA1 Channel 7 interrupt
    DMA1_CHANNEL7 = 17,
    ///18 - ADC1 global interrupt
    ADC1 = 18,
    ///19 - USB high priority interrupt
    USB_HP = 19,
    ///20 - USB low priority interrupt (including USB wakeup)
    USB_LP = 20,
    ///21 - CPU2 SEV through EXTI\[40\]
    C2SEV = 21,
    ///22 - COMP2 & COMP1 interrupt through AIEC\[21:20\]
    COMP = 22,
    ///23 - EXTI line \[9:5\]
    ///interrupt through EXTI\[9:5\]
    EXTI5_9 = 23,
    ///24 - Timer 1 break interrupt
    TIM1_BRK = 24,
    ///25 - Timer 1 Update
    TIM1_UP = 25,
    ///26 - TIM1 Trigger and Commutation interrupts and TIM17 global interrupt
    TIM1_TRG_COM_TIM17 = 26,
    ///27 - TIM1 Capture Compare interrupt
    TIM1_CC = 27,
    ///28 - TIM2 global interrupt
    TIM2 = 28,
    ///29 - Private key accelerator interrupt
    PKA = 29,
    ///30 - I2C1 event interrupt
    I2C1_EV = 30,
    ///31 - I2C1 error interrupt
    I2C1_ER = 31,
    ///32 - I2C3 event interrupt
    I2C3_EV = 32,
    ///33 - I2C3 error interrupt
    I2C3_ER = 33,
    ///34 - SPI 1 global interrupt
    SPI1 = 34,
    ///35 - SPI1 global interrupt
    SPI2 = 35,
    ///36 - USART1 global interrupt
    USART1 = 36,
    ///37 - LPUART1 global interrupt
    LPUART1 = 37,
    ///38 - SAI1 global interrupt
    SAI1 = 38,
    ///39 - TSC global interrupt
    TSC = 39,
    ///40 - EXTI line \[15:10\]
    ///interrupt through EXTI\[15:10\]
    EXTI10_15 = 40,
    ///41 - RTC Alarms (A and B) interrupt through AIEC
    RTC_ALARM = 41,
    ///42 - CRS interrupt
    CRS_IT = 42,
    ///43 - PWR switching on the fly interrupt
    PWR_SOTF = 43,
    ///44 - IPCC CPU1 RX occupied interrupt
    IPCC_C1_RX_IT = 44,
    ///45 - IPCC CPU1 TX free interrupt
    IPCC_C1_TX_IT = 45,
    ///46 - Semaphore interrupt 0 to CPU1
    HSEM = 46,
    ///47 - LPtimer 1 global interrupt
    LPTIM1 = 47,
    ///48 - LPtimer 2 global interrupt
    LPTIM2 = 48,
    ///49 - LCD global interrupt
    LCD = 49,
    ///50 - QSPI global interrupt
    QUADSPI = 50,
    ///51 - AES1 global interrupt
    AES1 = 51,
    ///52 - AES2 global interrupt
    AES2 = 52,
    ///53 - True random number generator interrupt
    TRUE_RNG = 53,
    ///54 - Floating point unit interrupt
    FPU = 54,
    ///55 - DMA2 channel 1 interrupt
    DMA2_CH1 = 55,
    ///56 - DMA2 channel 2 interrupt
    DMA2_CH2 = 56,
    ///57 - DMA2 channel 3 interrupt
    DMA2_CH3 = 57,
    ///58 - DMA2 channel 4 interrupt
    DMA2_CH4 = 58,
    ///59 - DMA2 channel 5 interrupt
    DMA2_CH5 = 59,
    ///60 - DMA2 channel 6 interrupt
    DMA2_CH6 = 60,
    ///61 - DMA2 channel 7 interrupt
    DMA2_CH7 = 61,
    ///62 - DMAMUX overrun interrupt
    DMAMUX_OVR = 62,
}
unsafe impl bare_metal::Nr for Interrupt {
    #[inline(always)]
    fn nr(&self) -> u8 {
        *self as u8
    }
}
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
///Direct memory access controller
pub struct DMA1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for DMA1 {}
impl DMA1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const dma1::RegisterBlock {
        0x4002_0000 as *const _
    }
}
impl Deref for DMA1 {
    type Target = dma1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*DMA1::ptr() }
    }
}
///Direct memory access controller
pub mod dma1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - interrupt status register
        pub isr: ISR,
        ///0x04 - interrupt flag clear register
        pub ifcr: IFCR,
        ///0x08 - channel x configuration register
        pub ccr1: CCR1,
        ///0x0c - channel x number of data register
        pub cndtr1: CNDTR1,
        ///0x10 - channel x peripheral address register
        pub cpar1: CPAR1,
        ///0x14 - channel x memory address register
        pub cmar1: CMAR1,
        _reserved6: [u8; 4usize],
        ///0x1c - channel x configuration register
        pub ccr2: CCR2,
        ///0x20 - channel x number of data register
        pub cndtr2: CNDTR2,
        ///0x24 - channel x peripheral address register
        pub cpar2: CPAR2,
        ///0x28 - channel x memory address register
        pub cmar2: CMAR2,
        _reserved10: [u8; 4usize],
        ///0x30 - channel x configuration register
        pub ccr3: CCR3,
        ///0x34 - channel x number of data register
        pub cndtr3: CNDTR3,
        ///0x38 - channel x peripheral address register
        pub cpar3: CPAR3,
        ///0x3c - channel x memory address register
        pub cmar3: CMAR3,
        _reserved14: [u8; 4usize],
        ///0x44 - channel x configuration register
        pub ccr4: CCR4,
        ///0x48 - channel x number of data register
        pub cndtr4: CNDTR4,
        ///0x4c - channel x peripheral address register
        pub cpar4: CPAR4,
        ///0x50 - channel x memory address register
        pub cmar4: CMAR4,
        _reserved18: [u8; 4usize],
        ///0x58 - channel x configuration register
        pub ccr5: CCR5,
        ///0x5c - channel x number of data register
        pub cndtr5: CNDTR5,
        ///0x60 - channel x peripheral address register
        pub cpar5: CPAR5,
        ///0x64 - channel x memory address register
        pub cmar5: CMAR5,
        _reserved22: [u8; 4usize],
        ///0x6c - channel x configuration register
        pub ccr6: CCR6,
        ///0x70 - channel x number of data register
        pub cndtr6: CNDTR6,
        ///0x74 - channel x peripheral address register
        pub cpar6: CPAR6,
        ///0x78 - channel x memory address register
        pub cmar6: CMAR6,
        _reserved26: [u8; 4usize],
        ///0x80 - channel x configuration register
        pub ccr7: CCR7,
        ///0x84 - channel x number of data register
        pub cndtr7: CNDTR7,
        ///0x88 - channel x peripheral address register
        pub cpar7: CPAR7,
        ///0x8c - channel x memory address register
        pub cmar7: CMAR7,
    }
    ///interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///interrupt status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Reader of field `TEIF7`
        pub type TEIF7_R = crate::R<bool, bool>;
        ///Reader of field `HTIF7`
        pub type HTIF7_R = crate::R<bool, bool>;
        ///Reader of field `TCIF7`
        pub type TCIF7_R = crate::R<bool, bool>;
        ///Reader of field `GIF7`
        pub type GIF7_R = crate::R<bool, bool>;
        ///Reader of field `TEIF6`
        pub type TEIF6_R = crate::R<bool, bool>;
        ///Reader of field `HTIF6`
        pub type HTIF6_R = crate::R<bool, bool>;
        ///Reader of field `TCIF6`
        pub type TCIF6_R = crate::R<bool, bool>;
        ///Reader of field `GIF6`
        pub type GIF6_R = crate::R<bool, bool>;
        ///Reader of field `TEIF5`
        pub type TEIF5_R = crate::R<bool, bool>;
        ///Reader of field `HTIF5`
        pub type HTIF5_R = crate::R<bool, bool>;
        ///Reader of field `TCIF5`
        pub type TCIF5_R = crate::R<bool, bool>;
        ///Reader of field `GIF5`
        pub type GIF5_R = crate::R<bool, bool>;
        ///Reader of field `TEIF4`
        pub type TEIF4_R = crate::R<bool, bool>;
        ///Reader of field `HTIF4`
        pub type HTIF4_R = crate::R<bool, bool>;
        ///Reader of field `TCIF4`
        pub type TCIF4_R = crate::R<bool, bool>;
        ///Reader of field `GIF4`
        pub type GIF4_R = crate::R<bool, bool>;
        ///Reader of field `TEIF3`
        pub type TEIF3_R = crate::R<bool, bool>;
        ///Reader of field `HTIF3`
        pub type HTIF3_R = crate::R<bool, bool>;
        ///Reader of field `TCIF3`
        pub type TCIF3_R = crate::R<bool, bool>;
        ///Reader of field `GIF3`
        pub type GIF3_R = crate::R<bool, bool>;
        ///Reader of field `TEIF2`
        pub type TEIF2_R = crate::R<bool, bool>;
        ///Reader of field `HTIF2`
        pub type HTIF2_R = crate::R<bool, bool>;
        ///Reader of field `TCIF2`
        pub type TCIF2_R = crate::R<bool, bool>;
        ///Reader of field `GIF2`
        pub type GIF2_R = crate::R<bool, bool>;
        ///Reader of field `TEIF1`
        pub type TEIF1_R = crate::R<bool, bool>;
        ///Reader of field `HTIF1`
        pub type HTIF1_R = crate::R<bool, bool>;
        ///Reader of field `TCIF1`
        pub type TCIF1_R = crate::R<bool, bool>;
        ///Reader of field `GIF1`
        pub type GIF1_R = crate::R<bool, bool>;
        impl R {
            ///Bit 27 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif7(&self) -> TEIF7_R {
                TEIF7_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif7(&self) -> HTIF7_R {
                HTIF7_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif7(&self) -> TCIF7_R {
                TCIF7_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif7(&self) -> GIF7_R {
                GIF7_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif6(&self) -> TEIF6_R {
                TEIF6_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif6(&self) -> HTIF6_R {
                HTIF6_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif6(&self) -> TCIF6_R {
                TCIF6_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif6(&self) -> GIF6_R {
                GIF6_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif5(&self) -> TEIF5_R {
                TEIF5_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif5(&self) -> HTIF5_R {
                HTIF5_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif5(&self) -> TCIF5_R {
                TCIF5_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif5(&self) -> GIF5_R {
                GIF5_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif4(&self) -> TEIF4_R {
                TEIF4_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif4(&self) -> HTIF4_R {
                HTIF4_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif4(&self) -> TCIF4_R {
                TCIF4_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif4(&self) -> GIF4_R {
                GIF4_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif3(&self) -> TEIF3_R {
                TEIF3_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif3(&self) -> HTIF3_R {
                HTIF3_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif3(&self) -> TCIF3_R {
                TCIF3_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif3(&self) -> GIF3_R {
                GIF3_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif2(&self) -> TEIF2_R {
                TEIF2_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif2(&self) -> HTIF2_R {
                HTIF2_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif2(&self) -> TCIF2_R {
                TCIF2_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif2(&self) -> GIF2_R {
                GIF2_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif1(&self) -> TEIF1_R {
                TEIF1_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif1(&self) -> HTIF1_R {
                HTIF1_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif1(&self) -> TCIF1_R {
                TCIF1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif1(&self) -> GIF1_R {
                GIF1_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///interrupt flag clear register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ifcr](ifcr) module
    pub type IFCR = crate::Reg<u32, _IFCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IFCR;
    ///`write(|w| ..)` method takes [ifcr::W](ifcr::W) writer structure
    impl crate::Writable for IFCR {}
    ///interrupt flag clear register
    pub mod ifcr {
        ///Writer for register IFCR
        pub type W = crate::W<u32, super::IFCR>;
        ///Register IFCR `reset()`'s with value 0
        impl crate::ResetValue for super::IFCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `CTEIF7`
        pub struct CTEIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Write proxy for field `CHTIF7`
        pub struct CHTIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Write proxy for field `CTCIF7`
        pub struct CTCIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Write proxy for field `CGIF7`
        pub struct CGIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Write proxy for field `CTEIF6`
        pub struct CTEIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Write proxy for field `CHTIF6`
        pub struct CHTIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Write proxy for field `CTCIF6`
        pub struct CTCIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `CGIF6`
        pub struct CGIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `CTEIF5`
        pub struct CTEIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `CHTIF5`
        pub struct CHTIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `CTCIF5`
        pub struct CTCIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `CGIF5`
        pub struct CGIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `CTEIF4`
        pub struct CTEIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Write proxy for field `CHTIF4`
        pub struct CHTIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `CTCIF4`
        pub struct CTCIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `CGIF4`
        pub struct CGIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `CTEIF3`
        pub struct CTEIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `CHTIF3`
        pub struct CHTIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `CTCIF3`
        pub struct CTCIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `CGIF3`
        pub struct CGIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `CTEIF2`
        pub struct CTEIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `CHTIF2`
        pub struct CHTIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `CTCIF2`
        pub struct CTCIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `CGIF2`
        pub struct CGIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CTEIF1`
        pub struct CTEIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CHTIF1`
        pub struct CHTIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CTCIF1`
        pub struct CTCIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CGIF1`
        pub struct CGIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 27 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif7(&mut self) -> CTEIF7_W {
                CTEIF7_W { w: self }
            }
            ///Bit 26 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif7(&mut self) -> CHTIF7_W {
                CHTIF7_W { w: self }
            }
            ///Bit 25 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif7(&mut self) -> CTCIF7_W {
                CTCIF7_W { w: self }
            }
            ///Bit 24 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif7(&mut self) -> CGIF7_W {
                CGIF7_W { w: self }
            }
            ///Bit 23 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif6(&mut self) -> CTEIF6_W {
                CTEIF6_W { w: self }
            }
            ///Bit 22 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif6(&mut self) -> CHTIF6_W {
                CHTIF6_W { w: self }
            }
            ///Bit 21 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif6(&mut self) -> CTCIF6_W {
                CTCIF6_W { w: self }
            }
            ///Bit 20 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif6(&mut self) -> CGIF6_W {
                CGIF6_W { w: self }
            }
            ///Bit 19 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif5(&mut self) -> CTEIF5_W {
                CTEIF5_W { w: self }
            }
            ///Bit 18 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif5(&mut self) -> CHTIF5_W {
                CHTIF5_W { w: self }
            }
            ///Bit 17 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif5(&mut self) -> CTCIF5_W {
                CTCIF5_W { w: self }
            }
            ///Bit 16 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif5(&mut self) -> CGIF5_W {
                CGIF5_W { w: self }
            }
            ///Bit 15 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif4(&mut self) -> CTEIF4_W {
                CTEIF4_W { w: self }
            }
            ///Bit 14 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif4(&mut self) -> CHTIF4_W {
                CHTIF4_W { w: self }
            }
            ///Bit 13 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif4(&mut self) -> CTCIF4_W {
                CTCIF4_W { w: self }
            }
            ///Bit 12 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif4(&mut self) -> CGIF4_W {
                CGIF4_W { w: self }
            }
            ///Bit 11 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif3(&mut self) -> CTEIF3_W {
                CTEIF3_W { w: self }
            }
            ///Bit 10 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif3(&mut self) -> CHTIF3_W {
                CHTIF3_W { w: self }
            }
            ///Bit 9 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif3(&mut self) -> CTCIF3_W {
                CTCIF3_W { w: self }
            }
            ///Bit 8 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif3(&mut self) -> CGIF3_W {
                CGIF3_W { w: self }
            }
            ///Bit 7 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif2(&mut self) -> CTEIF2_W {
                CTEIF2_W { w: self }
            }
            ///Bit 6 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif2(&mut self) -> CHTIF2_W {
                CHTIF2_W { w: self }
            }
            ///Bit 5 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif2(&mut self) -> CTCIF2_W {
                CTCIF2_W { w: self }
            }
            ///Bit 4 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif2(&mut self) -> CGIF2_W {
                CGIF2_W { w: self }
            }
            ///Bit 3 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif1(&mut self) -> CTEIF1_W {
                CTEIF1_W { w: self }
            }
            ///Bit 2 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif1(&mut self) -> CHTIF1_W {
                CHTIF1_W { w: self }
            }
            ///Bit 1 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif1(&mut self) -> CTCIF1_W {
                CTCIF1_W { w: self }
            }
            ///Bit 0 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif1(&mut self) -> CGIF1_W {
                CGIF1_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr1](ccr1) module
    pub type CCR1 = crate::Reg<u32, _CCR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR1;
    ///`read()` method returns [ccr1::R](ccr1::R) reader structure
    impl crate::Readable for CCR1 {}
    ///`write(|w| ..)` method takes [ccr1::W](ccr1::W) writer structure
    impl crate::Writable for CCR1 {}
    ///channel x configuration register
    pub mod ccr1 {
        ///Reader of register CCR1
        pub type R = crate::R<u32, super::CCR1>;
        ///Writer for register CCR1
        pub type W = crate::W<u32, super::CCR1>;
        ///Register CCR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr1](cndtr1) module
    pub type CNDTR1 = crate::Reg<u32, _CNDTR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR1;
    ///`read()` method returns [cndtr1::R](cndtr1::R) reader structure
    impl crate::Readable for CNDTR1 {}
    ///`write(|w| ..)` method takes [cndtr1::W](cndtr1::W) writer structure
    impl crate::Writable for CNDTR1 {}
    ///channel x number of data register
    pub mod cndtr1 {
        ///Reader of register CNDTR1
        pub type R = crate::R<u32, super::CNDTR1>;
        ///Writer for register CNDTR1
        pub type W = crate::W<u32, super::CNDTR1>;
        ///Register CNDTR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar1](cpar1) module
    pub type CPAR1 = crate::Reg<u32, _CPAR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR1;
    ///`read()` method returns [cpar1::R](cpar1::R) reader structure
    impl crate::Readable for CPAR1 {}
    ///`write(|w| ..)` method takes [cpar1::W](cpar1::W) writer structure
    impl crate::Writable for CPAR1 {}
    ///channel x peripheral address register
    pub mod cpar1 {
        ///Reader of register CPAR1
        pub type R = crate::R<u32, super::CPAR1>;
        ///Writer for register CPAR1
        pub type W = crate::W<u32, super::CPAR1>;
        ///Register CPAR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar1](cmar1) module
    pub type CMAR1 = crate::Reg<u32, _CMAR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR1;
    ///`read()` method returns [cmar1::R](cmar1::R) reader structure
    impl crate::Readable for CMAR1 {}
    ///`write(|w| ..)` method takes [cmar1::W](cmar1::W) writer structure
    impl crate::Writable for CMAR1 {}
    ///channel x memory address register
    pub mod cmar1 {
        ///Reader of register CMAR1
        pub type R = crate::R<u32, super::CMAR1>;
        ///Writer for register CMAR1
        pub type W = crate::W<u32, super::CMAR1>;
        ///Register CMAR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr2](ccr2) module
    pub type CCR2 = crate::Reg<u32, _CCR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR2;
    ///`read()` method returns [ccr2::R](ccr2::R) reader structure
    impl crate::Readable for CCR2 {}
    ///`write(|w| ..)` method takes [ccr2::W](ccr2::W) writer structure
    impl crate::Writable for CCR2 {}
    ///channel x configuration register
    pub mod ccr2 {
        ///Reader of register CCR2
        pub type R = crate::R<u32, super::CCR2>;
        ///Writer for register CCR2
        pub type W = crate::W<u32, super::CCR2>;
        ///Register CCR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr2](cndtr2) module
    pub type CNDTR2 = crate::Reg<u32, _CNDTR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR2;
    ///`read()` method returns [cndtr2::R](cndtr2::R) reader structure
    impl crate::Readable for CNDTR2 {}
    ///`write(|w| ..)` method takes [cndtr2::W](cndtr2::W) writer structure
    impl crate::Writable for CNDTR2 {}
    ///channel x number of data register
    pub mod cndtr2 {
        ///Reader of register CNDTR2
        pub type R = crate::R<u32, super::CNDTR2>;
        ///Writer for register CNDTR2
        pub type W = crate::W<u32, super::CNDTR2>;
        ///Register CNDTR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar2](cpar2) module
    pub type CPAR2 = crate::Reg<u32, _CPAR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR2;
    ///`read()` method returns [cpar2::R](cpar2::R) reader structure
    impl crate::Readable for CPAR2 {}
    ///`write(|w| ..)` method takes [cpar2::W](cpar2::W) writer structure
    impl crate::Writable for CPAR2 {}
    ///channel x peripheral address register
    pub mod cpar2 {
        ///Reader of register CPAR2
        pub type R = crate::R<u32, super::CPAR2>;
        ///Writer for register CPAR2
        pub type W = crate::W<u32, super::CPAR2>;
        ///Register CPAR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar2](cmar2) module
    pub type CMAR2 = crate::Reg<u32, _CMAR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR2;
    ///`read()` method returns [cmar2::R](cmar2::R) reader structure
    impl crate::Readable for CMAR2 {}
    ///`write(|w| ..)` method takes [cmar2::W](cmar2::W) writer structure
    impl crate::Writable for CMAR2 {}
    ///channel x memory address register
    pub mod cmar2 {
        ///Reader of register CMAR2
        pub type R = crate::R<u32, super::CMAR2>;
        ///Writer for register CMAR2
        pub type W = crate::W<u32, super::CMAR2>;
        ///Register CMAR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr3](ccr3) module
    pub type CCR3 = crate::Reg<u32, _CCR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR3;
    ///`read()` method returns [ccr3::R](ccr3::R) reader structure
    impl crate::Readable for CCR3 {}
    ///`write(|w| ..)` method takes [ccr3::W](ccr3::W) writer structure
    impl crate::Writable for CCR3 {}
    ///channel x configuration register
    pub mod ccr3 {
        ///Reader of register CCR3
        pub type R = crate::R<u32, super::CCR3>;
        ///Writer for register CCR3
        pub type W = crate::W<u32, super::CCR3>;
        ///Register CCR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr3](cndtr3) module
    pub type CNDTR3 = crate::Reg<u32, _CNDTR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR3;
    ///`read()` method returns [cndtr3::R](cndtr3::R) reader structure
    impl crate::Readable for CNDTR3 {}
    ///`write(|w| ..)` method takes [cndtr3::W](cndtr3::W) writer structure
    impl crate::Writable for CNDTR3 {}
    ///channel x number of data register
    pub mod cndtr3 {
        ///Reader of register CNDTR3
        pub type R = crate::R<u32, super::CNDTR3>;
        ///Writer for register CNDTR3
        pub type W = crate::W<u32, super::CNDTR3>;
        ///Register CNDTR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar3](cpar3) module
    pub type CPAR3 = crate::Reg<u32, _CPAR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR3;
    ///`read()` method returns [cpar3::R](cpar3::R) reader structure
    impl crate::Readable for CPAR3 {}
    ///`write(|w| ..)` method takes [cpar3::W](cpar3::W) writer structure
    impl crate::Writable for CPAR3 {}
    ///channel x peripheral address register
    pub mod cpar3 {
        ///Reader of register CPAR3
        pub type R = crate::R<u32, super::CPAR3>;
        ///Writer for register CPAR3
        pub type W = crate::W<u32, super::CPAR3>;
        ///Register CPAR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar3](cmar3) module
    pub type CMAR3 = crate::Reg<u32, _CMAR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR3;
    ///`read()` method returns [cmar3::R](cmar3::R) reader structure
    impl crate::Readable for CMAR3 {}
    ///`write(|w| ..)` method takes [cmar3::W](cmar3::W) writer structure
    impl crate::Writable for CMAR3 {}
    ///channel x memory address register
    pub mod cmar3 {
        ///Reader of register CMAR3
        pub type R = crate::R<u32, super::CMAR3>;
        ///Writer for register CMAR3
        pub type W = crate::W<u32, super::CMAR3>;
        ///Register CMAR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr4](ccr4) module
    pub type CCR4 = crate::Reg<u32, _CCR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR4;
    ///`read()` method returns [ccr4::R](ccr4::R) reader structure
    impl crate::Readable for CCR4 {}
    ///`write(|w| ..)` method takes [ccr4::W](ccr4::W) writer structure
    impl crate::Writable for CCR4 {}
    ///channel x configuration register
    pub mod ccr4 {
        ///Reader of register CCR4
        pub type R = crate::R<u32, super::CCR4>;
        ///Writer for register CCR4
        pub type W = crate::W<u32, super::CCR4>;
        ///Register CCR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr4](cndtr4) module
    pub type CNDTR4 = crate::Reg<u32, _CNDTR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR4;
    ///`read()` method returns [cndtr4::R](cndtr4::R) reader structure
    impl crate::Readable for CNDTR4 {}
    ///`write(|w| ..)` method takes [cndtr4::W](cndtr4::W) writer structure
    impl crate::Writable for CNDTR4 {}
    ///channel x number of data register
    pub mod cndtr4 {
        ///Reader of register CNDTR4
        pub type R = crate::R<u32, super::CNDTR4>;
        ///Writer for register CNDTR4
        pub type W = crate::W<u32, super::CNDTR4>;
        ///Register CNDTR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar4](cpar4) module
    pub type CPAR4 = crate::Reg<u32, _CPAR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR4;
    ///`read()` method returns [cpar4::R](cpar4::R) reader structure
    impl crate::Readable for CPAR4 {}
    ///`write(|w| ..)` method takes [cpar4::W](cpar4::W) writer structure
    impl crate::Writable for CPAR4 {}
    ///channel x peripheral address register
    pub mod cpar4 {
        ///Reader of register CPAR4
        pub type R = crate::R<u32, super::CPAR4>;
        ///Writer for register CPAR4
        pub type W = crate::W<u32, super::CPAR4>;
        ///Register CPAR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar4](cmar4) module
    pub type CMAR4 = crate::Reg<u32, _CMAR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR4;
    ///`read()` method returns [cmar4::R](cmar4::R) reader structure
    impl crate::Readable for CMAR4 {}
    ///`write(|w| ..)` method takes [cmar4::W](cmar4::W) writer structure
    impl crate::Writable for CMAR4 {}
    ///channel x memory address register
    pub mod cmar4 {
        ///Reader of register CMAR4
        pub type R = crate::R<u32, super::CMAR4>;
        ///Writer for register CMAR4
        pub type W = crate::W<u32, super::CMAR4>;
        ///Register CMAR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr5](ccr5) module
    pub type CCR5 = crate::Reg<u32, _CCR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR5;
    ///`read()` method returns [ccr5::R](ccr5::R) reader structure
    impl crate::Readable for CCR5 {}
    ///`write(|w| ..)` method takes [ccr5::W](ccr5::W) writer structure
    impl crate::Writable for CCR5 {}
    ///channel x configuration register
    pub mod ccr5 {
        ///Reader of register CCR5
        pub type R = crate::R<u32, super::CCR5>;
        ///Writer for register CCR5
        pub type W = crate::W<u32, super::CCR5>;
        ///Register CCR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr5](cndtr5) module
    pub type CNDTR5 = crate::Reg<u32, _CNDTR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR5;
    ///`read()` method returns [cndtr5::R](cndtr5::R) reader structure
    impl crate::Readable for CNDTR5 {}
    ///`write(|w| ..)` method takes [cndtr5::W](cndtr5::W) writer structure
    impl crate::Writable for CNDTR5 {}
    ///channel x number of data register
    pub mod cndtr5 {
        ///Reader of register CNDTR5
        pub type R = crate::R<u32, super::CNDTR5>;
        ///Writer for register CNDTR5
        pub type W = crate::W<u32, super::CNDTR5>;
        ///Register CNDTR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar5](cpar5) module
    pub type CPAR5 = crate::Reg<u32, _CPAR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR5;
    ///`read()` method returns [cpar5::R](cpar5::R) reader structure
    impl crate::Readable for CPAR5 {}
    ///`write(|w| ..)` method takes [cpar5::W](cpar5::W) writer structure
    impl crate::Writable for CPAR5 {}
    ///channel x peripheral address register
    pub mod cpar5 {
        ///Reader of register CPAR5
        pub type R = crate::R<u32, super::CPAR5>;
        ///Writer for register CPAR5
        pub type W = crate::W<u32, super::CPAR5>;
        ///Register CPAR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar5](cmar5) module
    pub type CMAR5 = crate::Reg<u32, _CMAR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR5;
    ///`read()` method returns [cmar5::R](cmar5::R) reader structure
    impl crate::Readable for CMAR5 {}
    ///`write(|w| ..)` method takes [cmar5::W](cmar5::W) writer structure
    impl crate::Writable for CMAR5 {}
    ///channel x memory address register
    pub mod cmar5 {
        ///Reader of register CMAR5
        pub type R = crate::R<u32, super::CMAR5>;
        ///Writer for register CMAR5
        pub type W = crate::W<u32, super::CMAR5>;
        ///Register CMAR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr6](ccr6) module
    pub type CCR6 = crate::Reg<u32, _CCR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR6;
    ///`read()` method returns [ccr6::R](ccr6::R) reader structure
    impl crate::Readable for CCR6 {}
    ///`write(|w| ..)` method takes [ccr6::W](ccr6::W) writer structure
    impl crate::Writable for CCR6 {}
    ///channel x configuration register
    pub mod ccr6 {
        ///Reader of register CCR6
        pub type R = crate::R<u32, super::CCR6>;
        ///Writer for register CCR6
        pub type W = crate::W<u32, super::CCR6>;
        ///Register CCR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr6](cndtr6) module
    pub type CNDTR6 = crate::Reg<u32, _CNDTR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR6;
    ///`read()` method returns [cndtr6::R](cndtr6::R) reader structure
    impl crate::Readable for CNDTR6 {}
    ///`write(|w| ..)` method takes [cndtr6::W](cndtr6::W) writer structure
    impl crate::Writable for CNDTR6 {}
    ///channel x number of data register
    pub mod cndtr6 {
        ///Reader of register CNDTR6
        pub type R = crate::R<u32, super::CNDTR6>;
        ///Writer for register CNDTR6
        pub type W = crate::W<u32, super::CNDTR6>;
        ///Register CNDTR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar6](cpar6) module
    pub type CPAR6 = crate::Reg<u32, _CPAR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR6;
    ///`read()` method returns [cpar6::R](cpar6::R) reader structure
    impl crate::Readable for CPAR6 {}
    ///`write(|w| ..)` method takes [cpar6::W](cpar6::W) writer structure
    impl crate::Writable for CPAR6 {}
    ///channel x peripheral address register
    pub mod cpar6 {
        ///Reader of register CPAR6
        pub type R = crate::R<u32, super::CPAR6>;
        ///Writer for register CPAR6
        pub type W = crate::W<u32, super::CPAR6>;
        ///Register CPAR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar6](cmar6) module
    pub type CMAR6 = crate::Reg<u32, _CMAR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR6;
    ///`read()` method returns [cmar6::R](cmar6::R) reader structure
    impl crate::Readable for CMAR6 {}
    ///`write(|w| ..)` method takes [cmar6::W](cmar6::W) writer structure
    impl crate::Writable for CMAR6 {}
    ///channel x memory address register
    pub mod cmar6 {
        ///Reader of register CMAR6
        pub type R = crate::R<u32, super::CMAR6>;
        ///Writer for register CMAR6
        pub type W = crate::W<u32, super::CMAR6>;
        ///Register CMAR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr7](ccr7) module
    pub type CCR7 = crate::Reg<u32, _CCR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR7;
    ///`read()` method returns [ccr7::R](ccr7::R) reader structure
    impl crate::Readable for CCR7 {}
    ///`write(|w| ..)` method takes [ccr7::W](ccr7::W) writer structure
    impl crate::Writable for CCR7 {}
    ///channel x configuration register
    pub mod ccr7 {
        ///Reader of register CCR7
        pub type R = crate::R<u32, super::CCR7>;
        ///Writer for register CCR7
        pub type W = crate::W<u32, super::CCR7>;
        ///Register CCR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr7](cndtr7) module
    pub type CNDTR7 = crate::Reg<u32, _CNDTR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR7;
    ///`read()` method returns [cndtr7::R](cndtr7::R) reader structure
    impl crate::Readable for CNDTR7 {}
    ///`write(|w| ..)` method takes [cndtr7::W](cndtr7::W) writer structure
    impl crate::Writable for CNDTR7 {}
    ///channel x number of data register
    pub mod cndtr7 {
        ///Reader of register CNDTR7
        pub type R = crate::R<u32, super::CNDTR7>;
        ///Writer for register CNDTR7
        pub type W = crate::W<u32, super::CNDTR7>;
        ///Register CNDTR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar7](cpar7) module
    pub type CPAR7 = crate::Reg<u32, _CPAR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR7;
    ///`read()` method returns [cpar7::R](cpar7::R) reader structure
    impl crate::Readable for CPAR7 {}
    ///`write(|w| ..)` method takes [cpar7::W](cpar7::W) writer structure
    impl crate::Writable for CPAR7 {}
    ///channel x peripheral address register
    pub mod cpar7 {
        ///Reader of register CPAR7
        pub type R = crate::R<u32, super::CPAR7>;
        ///Writer for register CPAR7
        pub type W = crate::W<u32, super::CPAR7>;
        ///Register CPAR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar7](cmar7) module
    pub type CMAR7 = crate::Reg<u32, _CMAR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR7;
    ///`read()` method returns [cmar7::R](cmar7::R) reader structure
    impl crate::Readable for CMAR7 {}
    ///`write(|w| ..)` method takes [cmar7::W](cmar7::W) writer structure
    impl crate::Writable for CMAR7 {}
    ///channel x memory address register
    pub mod cmar7 {
        ///Reader of register CMAR7
        pub type R = crate::R<u32, super::CMAR7>;
        ///Writer for register CMAR7
        pub type W = crate::W<u32, super::CMAR7>;
        ///Register CMAR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
}
///Direct memory access controller
pub struct DMA2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for DMA2 {}
impl DMA2 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const dma2::RegisterBlock {
        0x4002_0400 as *const _
    }
}
impl Deref for DMA2 {
    type Target = dma2::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*DMA2::ptr() }
    }
}
///Direct memory access controller
pub mod dma2 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - interrupt status register
        pub isr: ISR,
        ///0x04 - interrupt flag clear register
        pub ifcr: IFCR,
        ///0x08 - channel x configuration register
        pub ccr1: CCR1,
        ///0x0c - channel x number of data register
        pub cndtr1: CNDTR1,
        ///0x10 - channel x peripheral address register
        pub cpar1: CPAR1,
        ///0x14 - channel x memory address register
        pub cmar1: CMAR1,
        _reserved6: [u8; 4usize],
        ///0x1c - channel x configuration register
        pub ccr2: CCR2,
        ///0x20 - channel x number of data register
        pub cndtr2: CNDTR2,
        ///0x24 - channel x peripheral address register
        pub cpar2: CPAR2,
        ///0x28 - channel x memory address register
        pub cmar2: CMAR2,
        _reserved10: [u8; 4usize],
        ///0x30 - channel x configuration register
        pub ccr3: CCR3,
        ///0x34 - channel x number of data register
        pub cndtr3: CNDTR3,
        ///0x38 - channel x peripheral address register
        pub cpar3: CPAR3,
        ///0x3c - channel x memory address register
        pub cmar3: CMAR3,
        _reserved14: [u8; 4usize],
        ///0x44 - channel x configuration register
        pub ccr4: CCR4,
        ///0x48 - channel x number of data register
        pub cndtr4: CNDTR4,
        ///0x4c - channel x peripheral address register
        pub cpar4: CPAR4,
        ///0x50 - channel x memory address register
        pub cmar4: CMAR4,
        _reserved18: [u8; 4usize],
        ///0x58 - channel x configuration register
        pub ccr5: CCR5,
        ///0x5c - channel x number of data register
        pub cndtr5: CNDTR5,
        ///0x60 - channel x peripheral address register
        pub cpar5: CPAR5,
        ///0x64 - channel x memory address register
        pub cmar5: CMAR5,
        _reserved22: [u8; 4usize],
        ///0x6c - channel x configuration register
        pub ccr6: CCR6,
        ///0x70 - channel x number of data register
        pub cndtr6: CNDTR6,
        ///0x74 - channel x peripheral address register
        pub cpar6: CPAR6,
        ///0x78 - channel x memory address register
        pub cmar6: CMAR6,
        _reserved26: [u8; 4usize],
        ///0x80 - channel x configuration register
        pub ccr7: CCR7,
        ///0x84 - channel x number of data register
        pub cndtr7: CNDTR7,
        ///0x88 - channel x peripheral address register
        pub cpar7: CPAR7,
        ///0x8c - channel x memory address register
        pub cmar7: CMAR7,
        _reserved30: [u8; 24usize],
        ///0xa8 - channel selection register
        pub cselr: CSELR,
    }
    ///interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///interrupt status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Reader of field `TEIF7`
        pub type TEIF7_R = crate::R<bool, bool>;
        ///Reader of field `HTIF7`
        pub type HTIF7_R = crate::R<bool, bool>;
        ///Reader of field `TCIF7`
        pub type TCIF7_R = crate::R<bool, bool>;
        ///Reader of field `GIF7`
        pub type GIF7_R = crate::R<bool, bool>;
        ///Reader of field `TEIF6`
        pub type TEIF6_R = crate::R<bool, bool>;
        ///Reader of field `HTIF6`
        pub type HTIF6_R = crate::R<bool, bool>;
        ///Reader of field `TCIF6`
        pub type TCIF6_R = crate::R<bool, bool>;
        ///Reader of field `GIF6`
        pub type GIF6_R = crate::R<bool, bool>;
        ///Reader of field `TEIF5`
        pub type TEIF5_R = crate::R<bool, bool>;
        ///Reader of field `HTIF5`
        pub type HTIF5_R = crate::R<bool, bool>;
        ///Reader of field `TCIF5`
        pub type TCIF5_R = crate::R<bool, bool>;
        ///Reader of field `GIF5`
        pub type GIF5_R = crate::R<bool, bool>;
        ///Reader of field `TEIF4`
        pub type TEIF4_R = crate::R<bool, bool>;
        ///Reader of field `HTIF4`
        pub type HTIF4_R = crate::R<bool, bool>;
        ///Reader of field `TCIF4`
        pub type TCIF4_R = crate::R<bool, bool>;
        ///Reader of field `GIF4`
        pub type GIF4_R = crate::R<bool, bool>;
        ///Reader of field `TEIF3`
        pub type TEIF3_R = crate::R<bool, bool>;
        ///Reader of field `HTIF3`
        pub type HTIF3_R = crate::R<bool, bool>;
        ///Reader of field `TCIF3`
        pub type TCIF3_R = crate::R<bool, bool>;
        ///Reader of field `GIF3`
        pub type GIF3_R = crate::R<bool, bool>;
        ///Reader of field `TEIF2`
        pub type TEIF2_R = crate::R<bool, bool>;
        ///Reader of field `HTIF2`
        pub type HTIF2_R = crate::R<bool, bool>;
        ///Reader of field `TCIF2`
        pub type TCIF2_R = crate::R<bool, bool>;
        ///Reader of field `GIF2`
        pub type GIF2_R = crate::R<bool, bool>;
        ///Reader of field `TEIF1`
        pub type TEIF1_R = crate::R<bool, bool>;
        ///Reader of field `HTIF1`
        pub type HTIF1_R = crate::R<bool, bool>;
        ///Reader of field `TCIF1`
        pub type TCIF1_R = crate::R<bool, bool>;
        ///Reader of field `GIF1`
        pub type GIF1_R = crate::R<bool, bool>;
        impl R {
            ///Bit 27 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif7(&self) -> TEIF7_R {
                TEIF7_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif7(&self) -> HTIF7_R {
                HTIF7_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif7(&self) -> TCIF7_R {
                TCIF7_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif7(&self) -> GIF7_R {
                GIF7_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif6(&self) -> TEIF6_R {
                TEIF6_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif6(&self) -> HTIF6_R {
                HTIF6_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif6(&self) -> TCIF6_R {
                TCIF6_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif6(&self) -> GIF6_R {
                GIF6_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif5(&self) -> TEIF5_R {
                TEIF5_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif5(&self) -> HTIF5_R {
                HTIF5_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif5(&self) -> TCIF5_R {
                TCIF5_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif5(&self) -> GIF5_R {
                GIF5_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif4(&self) -> TEIF4_R {
                TEIF4_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif4(&self) -> HTIF4_R {
                HTIF4_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif4(&self) -> TCIF4_R {
                TCIF4_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif4(&self) -> GIF4_R {
                GIF4_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif3(&self) -> TEIF3_R {
                TEIF3_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif3(&self) -> HTIF3_R {
                HTIF3_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif3(&self) -> TCIF3_R {
                TCIF3_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif3(&self) -> GIF3_R {
                GIF3_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif2(&self) -> TEIF2_R {
                TEIF2_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif2(&self) -> HTIF2_R {
                HTIF2_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif2(&self) -> TCIF2_R {
                TCIF2_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif2(&self) -> GIF2_R {
                GIF2_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Channel x transfer error flag (x = 1 ..7)
            #[inline(always)]
            pub fn teif1(&self) -> TEIF1_R {
                TEIF1_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Channel x half transfer flag (x = 1 ..7)
            #[inline(always)]
            pub fn htif1(&self) -> HTIF1_R {
                HTIF1_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Channel x transfer complete flag (x = 1 ..7)
            #[inline(always)]
            pub fn tcif1(&self) -> TCIF1_R {
                TCIF1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel x global interrupt flag (x = 1 ..7)
            #[inline(always)]
            pub fn gif1(&self) -> GIF1_R {
                GIF1_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///interrupt flag clear register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ifcr](ifcr) module
    pub type IFCR = crate::Reg<u32, _IFCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IFCR;
    ///`write(|w| ..)` method takes [ifcr::W](ifcr::W) writer structure
    impl crate::Writable for IFCR {}
    ///interrupt flag clear register
    pub mod ifcr {
        ///Writer for register IFCR
        pub type W = crate::W<u32, super::IFCR>;
        ///Register IFCR `reset()`'s with value 0
        impl crate::ResetValue for super::IFCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `CTEIF7`
        pub struct CTEIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Write proxy for field `CHTIF7`
        pub struct CHTIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Write proxy for field `CTCIF7`
        pub struct CTCIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Write proxy for field `CGIF7`
        pub struct CGIF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Write proxy for field `CTEIF6`
        pub struct CTEIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Write proxy for field `CHTIF6`
        pub struct CHTIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Write proxy for field `CTCIF6`
        pub struct CTCIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `CGIF6`
        pub struct CGIF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `CTEIF5`
        pub struct CTEIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `CHTIF5`
        pub struct CHTIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `CTCIF5`
        pub struct CTCIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `CGIF5`
        pub struct CGIF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `CTEIF4`
        pub struct CTEIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Write proxy for field `CHTIF4`
        pub struct CHTIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `CTCIF4`
        pub struct CTCIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `CGIF4`
        pub struct CGIF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `CTEIF3`
        pub struct CTEIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `CHTIF3`
        pub struct CHTIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `CTCIF3`
        pub struct CTCIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `CGIF3`
        pub struct CGIF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `CTEIF2`
        pub struct CTEIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `CHTIF2`
        pub struct CHTIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `CTCIF2`
        pub struct CTCIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `CGIF2`
        pub struct CGIF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CTEIF1`
        pub struct CTEIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CHTIF1`
        pub struct CHTIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHTIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CTCIF1`
        pub struct CTCIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CGIF1`
        pub struct CGIF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CGIF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 27 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif7(&mut self) -> CTEIF7_W {
                CTEIF7_W { w: self }
            }
            ///Bit 26 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif7(&mut self) -> CHTIF7_W {
                CHTIF7_W { w: self }
            }
            ///Bit 25 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif7(&mut self) -> CTCIF7_W {
                CTCIF7_W { w: self }
            }
            ///Bit 24 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif7(&mut self) -> CGIF7_W {
                CGIF7_W { w: self }
            }
            ///Bit 23 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif6(&mut self) -> CTEIF6_W {
                CTEIF6_W { w: self }
            }
            ///Bit 22 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif6(&mut self) -> CHTIF6_W {
                CHTIF6_W { w: self }
            }
            ///Bit 21 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif6(&mut self) -> CTCIF6_W {
                CTCIF6_W { w: self }
            }
            ///Bit 20 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif6(&mut self) -> CGIF6_W {
                CGIF6_W { w: self }
            }
            ///Bit 19 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif5(&mut self) -> CTEIF5_W {
                CTEIF5_W { w: self }
            }
            ///Bit 18 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif5(&mut self) -> CHTIF5_W {
                CHTIF5_W { w: self }
            }
            ///Bit 17 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif5(&mut self) -> CTCIF5_W {
                CTCIF5_W { w: self }
            }
            ///Bit 16 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif5(&mut self) -> CGIF5_W {
                CGIF5_W { w: self }
            }
            ///Bit 15 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif4(&mut self) -> CTEIF4_W {
                CTEIF4_W { w: self }
            }
            ///Bit 14 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif4(&mut self) -> CHTIF4_W {
                CHTIF4_W { w: self }
            }
            ///Bit 13 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif4(&mut self) -> CTCIF4_W {
                CTCIF4_W { w: self }
            }
            ///Bit 12 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif4(&mut self) -> CGIF4_W {
                CGIF4_W { w: self }
            }
            ///Bit 11 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif3(&mut self) -> CTEIF3_W {
                CTEIF3_W { w: self }
            }
            ///Bit 10 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif3(&mut self) -> CHTIF3_W {
                CHTIF3_W { w: self }
            }
            ///Bit 9 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif3(&mut self) -> CTCIF3_W {
                CTCIF3_W { w: self }
            }
            ///Bit 8 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif3(&mut self) -> CGIF3_W {
                CGIF3_W { w: self }
            }
            ///Bit 7 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif2(&mut self) -> CTEIF2_W {
                CTEIF2_W { w: self }
            }
            ///Bit 6 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif2(&mut self) -> CHTIF2_W {
                CHTIF2_W { w: self }
            }
            ///Bit 5 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif2(&mut self) -> CTCIF2_W {
                CTCIF2_W { w: self }
            }
            ///Bit 4 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif2(&mut self) -> CGIF2_W {
                CGIF2_W { w: self }
            }
            ///Bit 3 - Channel x transfer error clear (x = 1 ..7)
            #[inline(always)]
            pub fn cteif1(&mut self) -> CTEIF1_W {
                CTEIF1_W { w: self }
            }
            ///Bit 2 - Channel x half transfer clear (x = 1 ..7)
            #[inline(always)]
            pub fn chtif1(&mut self) -> CHTIF1_W {
                CHTIF1_W { w: self }
            }
            ///Bit 1 - Channel x transfer complete clear (x = 1 ..7)
            #[inline(always)]
            pub fn ctcif1(&mut self) -> CTCIF1_W {
                CTCIF1_W { w: self }
            }
            ///Bit 0 - Channel x global interrupt clear (x = 1 ..7)
            #[inline(always)]
            pub fn cgif1(&mut self) -> CGIF1_W {
                CGIF1_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr1](ccr1) module
    pub type CCR1 = crate::Reg<u32, _CCR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR1;
    ///`read()` method returns [ccr1::R](ccr1::R) reader structure
    impl crate::Readable for CCR1 {}
    ///`write(|w| ..)` method takes [ccr1::W](ccr1::W) writer structure
    impl crate::Writable for CCR1 {}
    ///channel x configuration register
    pub mod ccr1 {
        ///Reader of register CCR1
        pub type R = crate::R<u32, super::CCR1>;
        ///Writer for register CCR1
        pub type W = crate::W<u32, super::CCR1>;
        ///Register CCR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr1](cndtr1) module
    pub type CNDTR1 = crate::Reg<u32, _CNDTR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR1;
    ///`read()` method returns [cndtr1::R](cndtr1::R) reader structure
    impl crate::Readable for CNDTR1 {}
    ///`write(|w| ..)` method takes [cndtr1::W](cndtr1::W) writer structure
    impl crate::Writable for CNDTR1 {}
    ///channel x number of data register
    pub mod cndtr1 {
        ///Reader of register CNDTR1
        pub type R = crate::R<u32, super::CNDTR1>;
        ///Writer for register CNDTR1
        pub type W = crate::W<u32, super::CNDTR1>;
        ///Register CNDTR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar1](cpar1) module
    pub type CPAR1 = crate::Reg<u32, _CPAR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR1;
    ///`read()` method returns [cpar1::R](cpar1::R) reader structure
    impl crate::Readable for CPAR1 {}
    ///`write(|w| ..)` method takes [cpar1::W](cpar1::W) writer structure
    impl crate::Writable for CPAR1 {}
    ///channel x peripheral address register
    pub mod cpar1 {
        ///Reader of register CPAR1
        pub type R = crate::R<u32, super::CPAR1>;
        ///Writer for register CPAR1
        pub type W = crate::W<u32, super::CPAR1>;
        ///Register CPAR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar1](cmar1) module
    pub type CMAR1 = crate::Reg<u32, _CMAR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR1;
    ///`read()` method returns [cmar1::R](cmar1::R) reader structure
    impl crate::Readable for CMAR1 {}
    ///`write(|w| ..)` method takes [cmar1::W](cmar1::W) writer structure
    impl crate::Writable for CMAR1 {}
    ///channel x memory address register
    pub mod cmar1 {
        ///Reader of register CMAR1
        pub type R = crate::R<u32, super::CMAR1>;
        ///Writer for register CMAR1
        pub type W = crate::W<u32, super::CMAR1>;
        ///Register CMAR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr2](ccr2) module
    pub type CCR2 = crate::Reg<u32, _CCR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR2;
    ///`read()` method returns [ccr2::R](ccr2::R) reader structure
    impl crate::Readable for CCR2 {}
    ///`write(|w| ..)` method takes [ccr2::W](ccr2::W) writer structure
    impl crate::Writable for CCR2 {}
    ///channel x configuration register
    pub mod ccr2 {
        ///Reader of register CCR2
        pub type R = crate::R<u32, super::CCR2>;
        ///Writer for register CCR2
        pub type W = crate::W<u32, super::CCR2>;
        ///Register CCR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr2](cndtr2) module
    pub type CNDTR2 = crate::Reg<u32, _CNDTR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR2;
    ///`read()` method returns [cndtr2::R](cndtr2::R) reader structure
    impl crate::Readable for CNDTR2 {}
    ///`write(|w| ..)` method takes [cndtr2::W](cndtr2::W) writer structure
    impl crate::Writable for CNDTR2 {}
    ///channel x number of data register
    pub mod cndtr2 {
        ///Reader of register CNDTR2
        pub type R = crate::R<u32, super::CNDTR2>;
        ///Writer for register CNDTR2
        pub type W = crate::W<u32, super::CNDTR2>;
        ///Register CNDTR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar2](cpar2) module
    pub type CPAR2 = crate::Reg<u32, _CPAR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR2;
    ///`read()` method returns [cpar2::R](cpar2::R) reader structure
    impl crate::Readable for CPAR2 {}
    ///`write(|w| ..)` method takes [cpar2::W](cpar2::W) writer structure
    impl crate::Writable for CPAR2 {}
    ///channel x peripheral address register
    pub mod cpar2 {
        ///Reader of register CPAR2
        pub type R = crate::R<u32, super::CPAR2>;
        ///Writer for register CPAR2
        pub type W = crate::W<u32, super::CPAR2>;
        ///Register CPAR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar2](cmar2) module
    pub type CMAR2 = crate::Reg<u32, _CMAR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR2;
    ///`read()` method returns [cmar2::R](cmar2::R) reader structure
    impl crate::Readable for CMAR2 {}
    ///`write(|w| ..)` method takes [cmar2::W](cmar2::W) writer structure
    impl crate::Writable for CMAR2 {}
    ///channel x memory address register
    pub mod cmar2 {
        ///Reader of register CMAR2
        pub type R = crate::R<u32, super::CMAR2>;
        ///Writer for register CMAR2
        pub type W = crate::W<u32, super::CMAR2>;
        ///Register CMAR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr3](ccr3) module
    pub type CCR3 = crate::Reg<u32, _CCR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR3;
    ///`read()` method returns [ccr3::R](ccr3::R) reader structure
    impl crate::Readable for CCR3 {}
    ///`write(|w| ..)` method takes [ccr3::W](ccr3::W) writer structure
    impl crate::Writable for CCR3 {}
    ///channel x configuration register
    pub mod ccr3 {
        ///Reader of register CCR3
        pub type R = crate::R<u32, super::CCR3>;
        ///Writer for register CCR3
        pub type W = crate::W<u32, super::CCR3>;
        ///Register CCR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr3](cndtr3) module
    pub type CNDTR3 = crate::Reg<u32, _CNDTR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR3;
    ///`read()` method returns [cndtr3::R](cndtr3::R) reader structure
    impl crate::Readable for CNDTR3 {}
    ///`write(|w| ..)` method takes [cndtr3::W](cndtr3::W) writer structure
    impl crate::Writable for CNDTR3 {}
    ///channel x number of data register
    pub mod cndtr3 {
        ///Reader of register CNDTR3
        pub type R = crate::R<u32, super::CNDTR3>;
        ///Writer for register CNDTR3
        pub type W = crate::W<u32, super::CNDTR3>;
        ///Register CNDTR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar3](cpar3) module
    pub type CPAR3 = crate::Reg<u32, _CPAR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR3;
    ///`read()` method returns [cpar3::R](cpar3::R) reader structure
    impl crate::Readable for CPAR3 {}
    ///`write(|w| ..)` method takes [cpar3::W](cpar3::W) writer structure
    impl crate::Writable for CPAR3 {}
    ///channel x peripheral address register
    pub mod cpar3 {
        ///Reader of register CPAR3
        pub type R = crate::R<u32, super::CPAR3>;
        ///Writer for register CPAR3
        pub type W = crate::W<u32, super::CPAR3>;
        ///Register CPAR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar3](cmar3) module
    pub type CMAR3 = crate::Reg<u32, _CMAR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR3;
    ///`read()` method returns [cmar3::R](cmar3::R) reader structure
    impl crate::Readable for CMAR3 {}
    ///`write(|w| ..)` method takes [cmar3::W](cmar3::W) writer structure
    impl crate::Writable for CMAR3 {}
    ///channel x memory address register
    pub mod cmar3 {
        ///Reader of register CMAR3
        pub type R = crate::R<u32, super::CMAR3>;
        ///Writer for register CMAR3
        pub type W = crate::W<u32, super::CMAR3>;
        ///Register CMAR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr4](ccr4) module
    pub type CCR4 = crate::Reg<u32, _CCR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR4;
    ///`read()` method returns [ccr4::R](ccr4::R) reader structure
    impl crate::Readable for CCR4 {}
    ///`write(|w| ..)` method takes [ccr4::W](ccr4::W) writer structure
    impl crate::Writable for CCR4 {}
    ///channel x configuration register
    pub mod ccr4 {
        ///Reader of register CCR4
        pub type R = crate::R<u32, super::CCR4>;
        ///Writer for register CCR4
        pub type W = crate::W<u32, super::CCR4>;
        ///Register CCR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr4](cndtr4) module
    pub type CNDTR4 = crate::Reg<u32, _CNDTR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR4;
    ///`read()` method returns [cndtr4::R](cndtr4::R) reader structure
    impl crate::Readable for CNDTR4 {}
    ///`write(|w| ..)` method takes [cndtr4::W](cndtr4::W) writer structure
    impl crate::Writable for CNDTR4 {}
    ///channel x number of data register
    pub mod cndtr4 {
        ///Reader of register CNDTR4
        pub type R = crate::R<u32, super::CNDTR4>;
        ///Writer for register CNDTR4
        pub type W = crate::W<u32, super::CNDTR4>;
        ///Register CNDTR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar4](cpar4) module
    pub type CPAR4 = crate::Reg<u32, _CPAR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR4;
    ///`read()` method returns [cpar4::R](cpar4::R) reader structure
    impl crate::Readable for CPAR4 {}
    ///`write(|w| ..)` method takes [cpar4::W](cpar4::W) writer structure
    impl crate::Writable for CPAR4 {}
    ///channel x peripheral address register
    pub mod cpar4 {
        ///Reader of register CPAR4
        pub type R = crate::R<u32, super::CPAR4>;
        ///Writer for register CPAR4
        pub type W = crate::W<u32, super::CPAR4>;
        ///Register CPAR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar4](cmar4) module
    pub type CMAR4 = crate::Reg<u32, _CMAR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR4;
    ///`read()` method returns [cmar4::R](cmar4::R) reader structure
    impl crate::Readable for CMAR4 {}
    ///`write(|w| ..)` method takes [cmar4::W](cmar4::W) writer structure
    impl crate::Writable for CMAR4 {}
    ///channel x memory address register
    pub mod cmar4 {
        ///Reader of register CMAR4
        pub type R = crate::R<u32, super::CMAR4>;
        ///Writer for register CMAR4
        pub type W = crate::W<u32, super::CMAR4>;
        ///Register CMAR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr5](ccr5) module
    pub type CCR5 = crate::Reg<u32, _CCR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR5;
    ///`read()` method returns [ccr5::R](ccr5::R) reader structure
    impl crate::Readable for CCR5 {}
    ///`write(|w| ..)` method takes [ccr5::W](ccr5::W) writer structure
    impl crate::Writable for CCR5 {}
    ///channel x configuration register
    pub mod ccr5 {
        ///Reader of register CCR5
        pub type R = crate::R<u32, super::CCR5>;
        ///Writer for register CCR5
        pub type W = crate::W<u32, super::CCR5>;
        ///Register CCR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr5](cndtr5) module
    pub type CNDTR5 = crate::Reg<u32, _CNDTR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR5;
    ///`read()` method returns [cndtr5::R](cndtr5::R) reader structure
    impl crate::Readable for CNDTR5 {}
    ///`write(|w| ..)` method takes [cndtr5::W](cndtr5::W) writer structure
    impl crate::Writable for CNDTR5 {}
    ///channel x number of data register
    pub mod cndtr5 {
        ///Reader of register CNDTR5
        pub type R = crate::R<u32, super::CNDTR5>;
        ///Writer for register CNDTR5
        pub type W = crate::W<u32, super::CNDTR5>;
        ///Register CNDTR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar5](cpar5) module
    pub type CPAR5 = crate::Reg<u32, _CPAR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR5;
    ///`read()` method returns [cpar5::R](cpar5::R) reader structure
    impl crate::Readable for CPAR5 {}
    ///`write(|w| ..)` method takes [cpar5::W](cpar5::W) writer structure
    impl crate::Writable for CPAR5 {}
    ///channel x peripheral address register
    pub mod cpar5 {
        ///Reader of register CPAR5
        pub type R = crate::R<u32, super::CPAR5>;
        ///Writer for register CPAR5
        pub type W = crate::W<u32, super::CPAR5>;
        ///Register CPAR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar5](cmar5) module
    pub type CMAR5 = crate::Reg<u32, _CMAR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR5;
    ///`read()` method returns [cmar5::R](cmar5::R) reader structure
    impl crate::Readable for CMAR5 {}
    ///`write(|w| ..)` method takes [cmar5::W](cmar5::W) writer structure
    impl crate::Writable for CMAR5 {}
    ///channel x memory address register
    pub mod cmar5 {
        ///Reader of register CMAR5
        pub type R = crate::R<u32, super::CMAR5>;
        ///Writer for register CMAR5
        pub type W = crate::W<u32, super::CMAR5>;
        ///Register CMAR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr6](ccr6) module
    pub type CCR6 = crate::Reg<u32, _CCR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR6;
    ///`read()` method returns [ccr6::R](ccr6::R) reader structure
    impl crate::Readable for CCR6 {}
    ///`write(|w| ..)` method takes [ccr6::W](ccr6::W) writer structure
    impl crate::Writable for CCR6 {}
    ///channel x configuration register
    pub mod ccr6 {
        ///Reader of register CCR6
        pub type R = crate::R<u32, super::CCR6>;
        ///Writer for register CCR6
        pub type W = crate::W<u32, super::CCR6>;
        ///Register CCR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr6](cndtr6) module
    pub type CNDTR6 = crate::Reg<u32, _CNDTR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR6;
    ///`read()` method returns [cndtr6::R](cndtr6::R) reader structure
    impl crate::Readable for CNDTR6 {}
    ///`write(|w| ..)` method takes [cndtr6::W](cndtr6::W) writer structure
    impl crate::Writable for CNDTR6 {}
    ///channel x number of data register
    pub mod cndtr6 {
        ///Reader of register CNDTR6
        pub type R = crate::R<u32, super::CNDTR6>;
        ///Writer for register CNDTR6
        pub type W = crate::W<u32, super::CNDTR6>;
        ///Register CNDTR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar6](cpar6) module
    pub type CPAR6 = crate::Reg<u32, _CPAR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR6;
    ///`read()` method returns [cpar6::R](cpar6::R) reader structure
    impl crate::Readable for CPAR6 {}
    ///`write(|w| ..)` method takes [cpar6::W](cpar6::W) writer structure
    impl crate::Writable for CPAR6 {}
    ///channel x peripheral address register
    pub mod cpar6 {
        ///Reader of register CPAR6
        pub type R = crate::R<u32, super::CPAR6>;
        ///Writer for register CPAR6
        pub type W = crate::W<u32, super::CPAR6>;
        ///Register CPAR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar6](cmar6) module
    pub type CMAR6 = crate::Reg<u32, _CMAR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR6;
    ///`read()` method returns [cmar6::R](cmar6::R) reader structure
    impl crate::Readable for CMAR6 {}
    ///`write(|w| ..)` method takes [cmar6::W](cmar6::W) writer structure
    impl crate::Writable for CMAR6 {}
    ///channel x memory address register
    pub mod cmar6 {
        ///Reader of register CMAR6
        pub type R = crate::R<u32, super::CMAR6>;
        ///Writer for register CMAR6
        pub type W = crate::W<u32, super::CMAR6>;
        ///Register CMAR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel x configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr7](ccr7) module
    pub type CCR7 = crate::Reg<u32, _CCR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR7;
    ///`read()` method returns [ccr7::R](ccr7::R) reader structure
    impl crate::Readable for CCR7 {}
    ///`write(|w| ..)` method takes [ccr7::W](ccr7::W) writer structure
    impl crate::Writable for CCR7 {}
    ///channel x configuration register
    pub mod ccr7 {
        ///Reader of register CCR7
        pub type R = crate::R<u32, super::CCR7>;
        ///Writer for register CCR7
        pub type W = crate::W<u32, super::CCR7>;
        ///Register CCR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM2MEM`
        pub type MEM2MEM_R = crate::R<bool, bool>;
        ///Write proxy for field `MEM2MEM`
        pub struct MEM2MEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM2MEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PL`
        pub type PL_R = crate::R<u8, u8>;
        ///Write proxy for field `PL`
        pub struct PL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MSIZE`
        pub type MSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIZE`
        pub struct MSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PSIZE`
        pub type PSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `PSIZE`
        pub struct PSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MINC`
        pub type MINC_R = crate::R<bool, bool>;
        ///Write proxy for field `MINC`
        pub struct MINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PINC`
        pub type PINC_R = crate::R<bool, bool>;
        ///Write proxy for field `PINC`
        pub struct PINC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PINC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CIRC`
        pub type CIRC_R = crate::R<bool, bool>;
        ///Write proxy for field `CIRC`
        pub struct CIRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CIRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `HTIE`
        pub type HTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HTIE`
        pub struct HTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&self) -> MEM2MEM_R {
                MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&self) -> PL_R {
                PL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&self) -> MSIZE_R {
                MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&self) -> PSIZE_R {
                PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&self) -> MINC_R {
                MINC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&self) -> PINC_R {
                PINC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&self) -> CIRC_R {
                CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&self) -> HTIE_R {
                HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Memory to memory mode
            #[inline(always)]
            pub fn mem2mem(&mut self) -> MEM2MEM_W {
                MEM2MEM_W { w: self }
            }
            ///Bits 12:13 - Channel priority level
            #[inline(always)]
            pub fn pl(&mut self) -> PL_W {
                PL_W { w: self }
            }
            ///Bits 10:11 - Memory size
            #[inline(always)]
            pub fn msize(&mut self) -> MSIZE_W {
                MSIZE_W { w: self }
            }
            ///Bits 8:9 - Peripheral size
            #[inline(always)]
            pub fn psize(&mut self) -> PSIZE_W {
                PSIZE_W { w: self }
            }
            ///Bit 7 - Memory increment mode
            #[inline(always)]
            pub fn minc(&mut self) -> MINC_W {
                MINC_W { w: self }
            }
            ///Bit 6 - Peripheral increment mode
            #[inline(always)]
            pub fn pinc(&mut self) -> PINC_W {
                PINC_W { w: self }
            }
            ///Bit 5 - Circular mode
            #[inline(always)]
            pub fn circ(&mut self) -> CIRC_W {
                CIRC_W { w: self }
            }
            ///Bit 4 - Data transfer direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bit 2 - Half transfer interrupt enable
            #[inline(always)]
            pub fn htie(&mut self) -> HTIE_W {
                HTIE_W { w: self }
            }
            ///Bit 1 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 0 - Channel enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///channel x number of data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cndtr7](cndtr7) module
    pub type CNDTR7 = crate::Reg<u32, _CNDTR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNDTR7;
    ///`read()` method returns [cndtr7::R](cndtr7::R) reader structure
    impl crate::Readable for CNDTR7 {}
    ///`write(|w| ..)` method takes [cndtr7::W](cndtr7::W) writer structure
    impl crate::Writable for CNDTR7 {}
    ///channel x number of data register
    pub mod cndtr7 {
        ///Reader of register CNDTR7
        pub type R = crate::R<u32, super::CNDTR7>;
        ///Writer for register CNDTR7
        pub type W = crate::W<u32, super::CNDTR7>;
        ///Register CNDTR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CNDTR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NDT`
        pub type NDT_R = crate::R<u16, u16>;
        ///Write proxy for field `NDT`
        pub struct NDT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NDT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&self) -> NDT_R {
                NDT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Number of data to transfer
            #[inline(always)]
            pub fn ndt(&mut self) -> NDT_W {
                NDT_W { w: self }
            }
        }
    }
    ///channel x peripheral address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpar7](cpar7) module
    pub type CPAR7 = crate::Reg<u32, _CPAR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPAR7;
    ///`read()` method returns [cpar7::R](cpar7::R) reader structure
    impl crate::Readable for CPAR7 {}
    ///`write(|w| ..)` method takes [cpar7::W](cpar7::W) writer structure
    impl crate::Writable for CPAR7 {}
    ///channel x peripheral address register
    pub mod cpar7 {
        ///Reader of register CPAR7
        pub type R = crate::R<u32, super::CPAR7>;
        ///Writer for register CPAR7
        pub type W = crate::W<u32, super::CPAR7>;
        ///Register CPAR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CPAR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PA`
        pub type PA_R = crate::R<u32, u32>;
        ///Write proxy for field `PA`
        pub struct PA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&self) -> PA_R {
                PA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Peripheral address
            #[inline(always)]
            pub fn pa(&mut self) -> PA_W {
                PA_W { w: self }
            }
        }
    }
    ///channel x memory address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmar7](cmar7) module
    pub type CMAR7 = crate::Reg<u32, _CMAR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMAR7;
    ///`read()` method returns [cmar7::R](cmar7::R) reader structure
    impl crate::Readable for CMAR7 {}
    ///`write(|w| ..)` method takes [cmar7::W](cmar7::W) writer structure
    impl crate::Writable for CMAR7 {}
    ///channel x memory address register
    pub mod cmar7 {
        ///Reader of register CMAR7
        pub type R = crate::R<u32, super::CMAR7>;
        ///Writer for register CMAR7
        pub type W = crate::W<u32, super::CMAR7>;
        ///Register CMAR7 `reset()`'s with value 0
        impl crate::ResetValue for super::CMAR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MA`
        pub type MA_R = crate::R<u32, u32>;
        ///Write proxy for field `MA`
        pub struct MA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&self) -> MA_R {
                MA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Memory address
            #[inline(always)]
            pub fn ma(&mut self) -> MA_W {
                MA_W { w: self }
            }
        }
    }
    ///channel selection register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cselr](cselr) module
    pub type CSELR = crate::Reg<u32, _CSELR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CSELR;
    ///`read()` method returns [cselr::R](cselr::R) reader structure
    impl crate::Readable for CSELR {}
    ///`write(|w| ..)` method takes [cselr::W](cselr::W) writer structure
    impl crate::Writable for CSELR {}
    ///channel selection register
    pub mod cselr {
        ///Reader of register CSELR
        pub type R = crate::R<u32, super::CSELR>;
        ///Writer for register CSELR
        pub type W = crate::W<u32, super::CSELR>;
        ///Register CSELR `reset()`'s with value 0
        impl crate::ResetValue for super::CSELR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `C7S`
        pub type C7S_R = crate::R<u8, u8>;
        ///Write proxy for field `C7S`
        pub struct C7S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C7S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `C6S`
        pub type C6S_R = crate::R<u8, u8>;
        ///Write proxy for field `C6S`
        pub struct C6S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C6S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `C5S`
        pub type C5S_R = crate::R<u8, u8>;
        ///Write proxy for field `C5S`
        pub struct C5S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C5S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `C4S`
        pub type C4S_R = crate::R<u8, u8>;
        ///Write proxy for field `C4S`
        pub struct C4S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C4S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `C3S`
        pub type C3S_R = crate::R<u8, u8>;
        ///Write proxy for field `C3S`
        pub struct C3S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C3S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `C2S`
        pub type C2S_R = crate::R<u8, u8>;
        ///Write proxy for field `C2S`
        pub struct C2S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C2S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `C1S`
        pub type C1S_R = crate::R<u8, u8>;
        ///Write proxy for field `C1S`
        pub struct C1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 24:27 - DMA channel 7 selection
            #[inline(always)]
            pub fn c7s(&self) -> C7S_R {
                C7S_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - DMA channel 6 selection
            #[inline(always)]
            pub fn c6s(&self) -> C6S_R {
                C6S_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - DMA channel 5 selection
            #[inline(always)]
            pub fn c5s(&self) -> C5S_R {
                C5S_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - DMA channel 4 selection
            #[inline(always)]
            pub fn c4s(&self) -> C4S_R {
                C4S_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - DMA channel 3 selection
            #[inline(always)]
            pub fn c3s(&self) -> C3S_R {
                C3S_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - DMA channel 2 selection
            #[inline(always)]
            pub fn c2s(&self) -> C2S_R {
                C2S_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - DMA channel 1 selection
            #[inline(always)]
            pub fn c1s(&self) -> C1S_R {
                C1S_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 24:27 - DMA channel 7 selection
            #[inline(always)]
            pub fn c7s(&mut self) -> C7S_W {
                C7S_W { w: self }
            }
            ///Bits 20:23 - DMA channel 6 selection
            #[inline(always)]
            pub fn c6s(&mut self) -> C6S_W {
                C6S_W { w: self }
            }
            ///Bits 16:19 - DMA channel 5 selection
            #[inline(always)]
            pub fn c5s(&mut self) -> C5S_W {
                C5S_W { w: self }
            }
            ///Bits 12:15 - DMA channel 4 selection
            #[inline(always)]
            pub fn c4s(&mut self) -> C4S_W {
                C4S_W { w: self }
            }
            ///Bits 8:11 - DMA channel 3 selection
            #[inline(always)]
            pub fn c3s(&mut self) -> C3S_W {
                C3S_W { w: self }
            }
            ///Bits 4:7 - DMA channel 2 selection
            #[inline(always)]
            pub fn c2s(&mut self) -> C2S_W {
                C2S_W { w: self }
            }
            ///Bits 0:3 - DMA channel 1 selection
            #[inline(always)]
            pub fn c1s(&mut self) -> C1S_W {
                C1S_W { w: self }
            }
        }
    }
}
///Direct memory access Multiplexer
pub struct DMAMUX1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for DMAMUX1 {}
impl DMAMUX1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const dmamux1::RegisterBlock {
        0x4002_0800 as *const _
    }
}
impl Deref for DMAMUX1 {
    type Target = dmamux1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*DMAMUX1::ptr() }
    }
}
///Direct memory access Multiplexer
pub mod dmamux1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - DMA Multiplexer Channel 0 Control register
        pub c0cr: C0CR,
        ///0x04 - DMA Multiplexer Channel 1 Control register
        pub c1cr: C1CR,
        ///0x08 - DMA Multiplexer Channel 2 Control register
        pub c2cr: C2CR,
        ///0x0c - DMA Multiplexer Channel 3 Control register
        pub c3cr: C3CR,
        ///0x10 - DMA Multiplexer Channel 4 Control register
        pub c4cr: C4CR,
        ///0x14 - DMA Multiplexer Channel 5 Control register
        pub c5cr: C5CR,
        ///0x18 - DMA Multiplexer Channel 6 Control register
        pub c6cr: C6CR,
        ///0x1c - DMA Multiplexer Channel 7 Control register
        pub c7cr: C7CR,
        ///0x20 - DMA Multiplexer Channel 8 Control register
        pub c8cr: C8CR,
        ///0x24 - DMA Multiplexer Channel 9 Control register
        pub c9cr: C9CR,
        ///0x28 - DMA Multiplexer Channel 10 Control register
        pub c10cr: C10CR,
        ///0x2c - DMA Multiplexer Channel 11 Control register
        pub c11cr: C11CR,
        ///0x30 - DMA Multiplexer Channel 12 Control register
        pub c12cr: C12CR,
        ///0x34 - DMA Multiplexer Channel 13 Control register
        pub c13cr: C13CR,
        _reserved14: [u8; 72usize],
        ///0x80 - DMA Multiplexer Channel Status register
        pub csr: CSR,
        ///0x84 - DMA Channel Clear Flag Register
        pub cfr: CFR,
        _reserved16: [u8; 120usize],
        ///0x100 - DMA Request Generator 0 Control Register
        pub rg0cr: RG0CR,
        ///0x104 - DMA Request Generator 1 Control Register
        pub rg1cr: RG1CR,
        ///0x108 - DMA Request Generator 2 Control Register
        pub rg2cr: RG2CR,
        ///0x10c - DMA Request Generator 3 Control Register
        pub rg3cr: RG3CR,
        _reserved20: [u8; 48usize],
        ///0x140 - DMA Request Generator Status Register
        pub rgsr: RGSR,
        ///0x144 - DMA Request Generator Clear Flag Register
        pub rgcfr: RGCFR,
    }
    ///DMA Multiplexer Channel 0 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c0cr](c0cr) module
    pub type C0CR = crate::Reg<u32, _C0CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C0CR;
    ///`read()` method returns [c0cr::R](c0cr::R) reader structure
    impl crate::Readable for C0CR {}
    ///`write(|w| ..)` method takes [c0cr::W](c0cr::W) writer structure
    impl crate::Writable for C0CR {}
    ///DMA Multiplexer Channel 0 Control register
    pub mod c0cr {
        ///Reader of register C0CR
        pub type R = crate::R<u32, super::C0CR>;
        ///Writer for register C0CR
        pub type W = crate::W<u32, super::C0CR>;
        ///Register C0CR `reset()`'s with value 0
        impl crate::ResetValue for super::C0CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 1 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1cr](c1cr) module
    pub type C1CR = crate::Reg<u32, _C1CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1CR;
    ///`read()` method returns [c1cr::R](c1cr::R) reader structure
    impl crate::Readable for C1CR {}
    ///`write(|w| ..)` method takes [c1cr::W](c1cr::W) writer structure
    impl crate::Writable for C1CR {}
    ///DMA Multiplexer Channel 1 Control register
    pub mod c1cr {
        ///Reader of register C1CR
        pub type R = crate::R<u32, super::C1CR>;
        ///Writer for register C1CR
        pub type W = crate::W<u32, super::C1CR>;
        ///Register C1CR `reset()`'s with value 0
        impl crate::ResetValue for super::C1CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 2 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2cr](c2cr) module
    pub type C2CR = crate::Reg<u32, _C2CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2CR;
    ///`read()` method returns [c2cr::R](c2cr::R) reader structure
    impl crate::Readable for C2CR {}
    ///`write(|w| ..)` method takes [c2cr::W](c2cr::W) writer structure
    impl crate::Writable for C2CR {}
    ///DMA Multiplexer Channel 2 Control register
    pub mod c2cr {
        ///Reader of register C2CR
        pub type R = crate::R<u32, super::C2CR>;
        ///Writer for register C2CR
        pub type W = crate::W<u32, super::C2CR>;
        ///Register C2CR `reset()`'s with value 0
        impl crate::ResetValue for super::C2CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 3 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c3cr](c3cr) module
    pub type C3CR = crate::Reg<u32, _C3CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C3CR;
    ///`read()` method returns [c3cr::R](c3cr::R) reader structure
    impl crate::Readable for C3CR {}
    ///`write(|w| ..)` method takes [c3cr::W](c3cr::W) writer structure
    impl crate::Writable for C3CR {}
    ///DMA Multiplexer Channel 3 Control register
    pub mod c3cr {
        ///Reader of register C3CR
        pub type R = crate::R<u32, super::C3CR>;
        ///Writer for register C3CR
        pub type W = crate::W<u32, super::C3CR>;
        ///Register C3CR `reset()`'s with value 0
        impl crate::ResetValue for super::C3CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 4 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c4cr](c4cr) module
    pub type C4CR = crate::Reg<u32, _C4CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C4CR;
    ///`read()` method returns [c4cr::R](c4cr::R) reader structure
    impl crate::Readable for C4CR {}
    ///`write(|w| ..)` method takes [c4cr::W](c4cr::W) writer structure
    impl crate::Writable for C4CR {}
    ///DMA Multiplexer Channel 4 Control register
    pub mod c4cr {
        ///Reader of register C4CR
        pub type R = crate::R<u32, super::C4CR>;
        ///Writer for register C4CR
        pub type W = crate::W<u32, super::C4CR>;
        ///Register C4CR `reset()`'s with value 0
        impl crate::ResetValue for super::C4CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 5 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c5cr](c5cr) module
    pub type C5CR = crate::Reg<u32, _C5CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C5CR;
    ///`read()` method returns [c5cr::R](c5cr::R) reader structure
    impl crate::Readable for C5CR {}
    ///`write(|w| ..)` method takes [c5cr::W](c5cr::W) writer structure
    impl crate::Writable for C5CR {}
    ///DMA Multiplexer Channel 5 Control register
    pub mod c5cr {
        ///Reader of register C5CR
        pub type R = crate::R<u32, super::C5CR>;
        ///Writer for register C5CR
        pub type W = crate::W<u32, super::C5CR>;
        ///Register C5CR `reset()`'s with value 0
        impl crate::ResetValue for super::C5CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 6 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c6cr](c6cr) module
    pub type C6CR = crate::Reg<u32, _C6CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C6CR;
    ///`read()` method returns [c6cr::R](c6cr::R) reader structure
    impl crate::Readable for C6CR {}
    ///`write(|w| ..)` method takes [c6cr::W](c6cr::W) writer structure
    impl crate::Writable for C6CR {}
    ///DMA Multiplexer Channel 6 Control register
    pub mod c6cr {
        ///Reader of register C6CR
        pub type R = crate::R<u32, super::C6CR>;
        ///Writer for register C6CR
        pub type W = crate::W<u32, super::C6CR>;
        ///Register C6CR `reset()`'s with value 0
        impl crate::ResetValue for super::C6CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 7 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c7cr](c7cr) module
    pub type C7CR = crate::Reg<u32, _C7CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C7CR;
    ///`read()` method returns [c7cr::R](c7cr::R) reader structure
    impl crate::Readable for C7CR {}
    ///`write(|w| ..)` method takes [c7cr::W](c7cr::W) writer structure
    impl crate::Writable for C7CR {}
    ///DMA Multiplexer Channel 7 Control register
    pub mod c7cr {
        ///Reader of register C7CR
        pub type R = crate::R<u32, super::C7CR>;
        ///Writer for register C7CR
        pub type W = crate::W<u32, super::C7CR>;
        ///Register C7CR `reset()`'s with value 0
        impl crate::ResetValue for super::C7CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 8 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c8cr](c8cr) module
    pub type C8CR = crate::Reg<u32, _C8CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C8CR;
    ///`read()` method returns [c8cr::R](c8cr::R) reader structure
    impl crate::Readable for C8CR {}
    ///`write(|w| ..)` method takes [c8cr::W](c8cr::W) writer structure
    impl crate::Writable for C8CR {}
    ///DMA Multiplexer Channel 8 Control register
    pub mod c8cr {
        ///Reader of register C8CR
        pub type R = crate::R<u32, super::C8CR>;
        ///Writer for register C8CR
        pub type W = crate::W<u32, super::C8CR>;
        ///Register C8CR `reset()`'s with value 0
        impl crate::ResetValue for super::C8CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 9 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c9cr](c9cr) module
    pub type C9CR = crate::Reg<u32, _C9CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C9CR;
    ///`read()` method returns [c9cr::R](c9cr::R) reader structure
    impl crate::Readable for C9CR {}
    ///`write(|w| ..)` method takes [c9cr::W](c9cr::W) writer structure
    impl crate::Writable for C9CR {}
    ///DMA Multiplexer Channel 9 Control register
    pub mod c9cr {
        ///Reader of register C9CR
        pub type R = crate::R<u32, super::C9CR>;
        ///Writer for register C9CR
        pub type W = crate::W<u32, super::C9CR>;
        ///Register C9CR `reset()`'s with value 0
        impl crate::ResetValue for super::C9CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 10 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c10cr](c10cr) module
    pub type C10CR = crate::Reg<u32, _C10CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C10CR;
    ///`read()` method returns [c10cr::R](c10cr::R) reader structure
    impl crate::Readable for C10CR {}
    ///`write(|w| ..)` method takes [c10cr::W](c10cr::W) writer structure
    impl crate::Writable for C10CR {}
    ///DMA Multiplexer Channel 10 Control register
    pub mod c10cr {
        ///Reader of register C10CR
        pub type R = crate::R<u32, super::C10CR>;
        ///Writer for register C10CR
        pub type W = crate::W<u32, super::C10CR>;
        ///Register C10CR `reset()`'s with value 0
        impl crate::ResetValue for super::C10CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 11 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c11cr](c11cr) module
    pub type C11CR = crate::Reg<u32, _C11CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C11CR;
    ///`read()` method returns [c11cr::R](c11cr::R) reader structure
    impl crate::Readable for C11CR {}
    ///`write(|w| ..)` method takes [c11cr::W](c11cr::W) writer structure
    impl crate::Writable for C11CR {}
    ///DMA Multiplexer Channel 11 Control register
    pub mod c11cr {
        ///Reader of register C11CR
        pub type R = crate::R<u32, super::C11CR>;
        ///Writer for register C11CR
        pub type W = crate::W<u32, super::C11CR>;
        ///Register C11CR `reset()`'s with value 0
        impl crate::ResetValue for super::C11CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 12 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c12cr](c12cr) module
    pub type C12CR = crate::Reg<u32, _C12CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C12CR;
    ///`read()` method returns [c12cr::R](c12cr::R) reader structure
    impl crate::Readable for C12CR {}
    ///`write(|w| ..)` method takes [c12cr::W](c12cr::W) writer structure
    impl crate::Writable for C12CR {}
    ///DMA Multiplexer Channel 12 Control register
    pub mod c12cr {
        ///Reader of register C12CR
        pub type R = crate::R<u32, super::C12CR>;
        ///Writer for register C12CR
        pub type W = crate::W<u32, super::C12CR>;
        ///Register C12CR `reset()`'s with value 0
        impl crate::ResetValue for super::C12CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel 13 Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c13cr](c13cr) module
    pub type C13CR = crate::Reg<u32, _C13CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C13CR;
    ///`read()` method returns [c13cr::R](c13cr::R) reader structure
    impl crate::Readable for C13CR {}
    ///`write(|w| ..)` method takes [c13cr::W](c13cr::W) writer structure
    impl crate::Writable for C13CR {}
    ///DMA Multiplexer Channel 13 Control register
    pub mod c13cr {
        ///Reader of register C13CR
        pub type R = crate::R<u32, super::C13CR>;
        ///Writer for register C13CR
        pub type W = crate::W<u32, super::C13CR>;
        ///Register C13CR `reset()`'s with value 0
        impl crate::ResetValue for super::C13CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNC_ID`
        pub type SYNC_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNC_ID`
        pub struct SYNC_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNC_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `NBREQ`
        pub type NBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `NBREQ`
        pub struct NBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `SPOL`
        pub type SPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `SPOL`
        pub struct SPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `SE`
        pub type SE_R = crate::R<bool, bool>;
        ///Write proxy for field `SE`
        pub struct SE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `EGE`
        pub type EGE_R = crate::R<bool, bool>;
        ///Write proxy for field `EGE`
        pub struct EGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SOIE`
        pub type SOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOIE`
        pub struct SOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAREQ_ID`
        pub type DMAREQ_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `DMAREQ_ID`
        pub struct DMAREQ_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAREQ_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&self) -> SYNC_ID_R {
                SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&self) -> NBREQ_R {
                NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&self) -> SPOL_R {
                SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&self) -> SE_R {
                SE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&self) -> EGE_R {
                EGE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&self) -> SOIE_R {
                SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&self) -> DMAREQ_ID_R {
                DMAREQ_ID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - SYNC_ID
            #[inline(always)]
            pub fn sync_id(&mut self) -> SYNC_ID_W {
                SYNC_ID_W { w: self }
            }
            ///Bits 19:23 - Nb request
            #[inline(always)]
            pub fn nbreq(&mut self) -> NBREQ_W {
                NBREQ_W { w: self }
            }
            ///Bits 17:18 - Sync polarity
            #[inline(always)]
            pub fn spol(&mut self) -> SPOL_W {
                SPOL_W { w: self }
            }
            ///Bit 16 - Synchronization enable
            #[inline(always)]
            pub fn se(&mut self) -> SE_W {
                SE_W { w: self }
            }
            ///Bit 9 - Event Generation Enable
            #[inline(always)]
            pub fn ege(&mut self) -> EGE_W {
                EGE_W { w: self }
            }
            ///Bit 8 - Synchronization Overrun Interrupt Enable
            #[inline(always)]
            pub fn soie(&mut self) -> SOIE_W {
                SOIE_W { w: self }
            }
            ///Bits 0:7 - DMA Request ID
            #[inline(always)]
            pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
                DMAREQ_ID_W { w: self }
            }
        }
    }
    ///DMA Multiplexer Channel Status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [csr](csr) module
    pub type CSR = crate::Reg<u32, _CSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CSR;
    ///`read()` method returns [csr::R](csr::R) reader structure
    impl crate::Readable for CSR {}
    ///DMA Multiplexer Channel Status register
    pub mod csr {
        ///Reader of register CSR
        pub type R = crate::R<u32, super::CSR>;
        ///Reader of field `SOF0`
        pub type SOF0_R = crate::R<bool, bool>;
        ///Reader of field `SOF1`
        pub type SOF1_R = crate::R<bool, bool>;
        ///Reader of field `SOF2`
        pub type SOF2_R = crate::R<bool, bool>;
        ///Reader of field `SOF3`
        pub type SOF3_R = crate::R<bool, bool>;
        ///Reader of field `SOF4`
        pub type SOF4_R = crate::R<bool, bool>;
        ///Reader of field `SOF5`
        pub type SOF5_R = crate::R<bool, bool>;
        ///Reader of field `SOF6`
        pub type SOF6_R = crate::R<bool, bool>;
        ///Reader of field `SOF7`
        pub type SOF7_R = crate::R<bool, bool>;
        ///Reader of field `SOF8`
        pub type SOF8_R = crate::R<bool, bool>;
        ///Reader of field `SOF9`
        pub type SOF9_R = crate::R<bool, bool>;
        ///Reader of field `SOF10`
        pub type SOF10_R = crate::R<bool, bool>;
        ///Reader of field `SOF11`
        pub type SOF11_R = crate::R<bool, bool>;
        ///Reader of field `SOF12`
        pub type SOF12_R = crate::R<bool, bool>;
        ///Reader of field `SOF13`
        pub type SOF13_R = crate::R<bool, bool>;
        impl R {
            ///Bit 0 - Synchronization Overrun Flag 0
            #[inline(always)]
            pub fn sof0(&self) -> SOF0_R {
                SOF0_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Synchronization Overrun Flag 1
            #[inline(always)]
            pub fn sof1(&self) -> SOF1_R {
                SOF1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Synchronization Overrun Flag 2
            #[inline(always)]
            pub fn sof2(&self) -> SOF2_R {
                SOF2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Synchronization Overrun Flag 3
            #[inline(always)]
            pub fn sof3(&self) -> SOF3_R {
                SOF3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Synchronization Overrun Flag 4
            #[inline(always)]
            pub fn sof4(&self) -> SOF4_R {
                SOF4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Synchronization Overrun Flag 5
            #[inline(always)]
            pub fn sof5(&self) -> SOF5_R {
                SOF5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Synchronization Overrun Flag 6
            #[inline(always)]
            pub fn sof6(&self) -> SOF6_R {
                SOF6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Synchronization Overrun Flag 7
            #[inline(always)]
            pub fn sof7(&self) -> SOF7_R {
                SOF7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Synchronization Overrun Flag 8
            #[inline(always)]
            pub fn sof8(&self) -> SOF8_R {
                SOF8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Synchronization Overrun Flag 9
            #[inline(always)]
            pub fn sof9(&self) -> SOF9_R {
                SOF9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Synchronization Overrun Flag 10
            #[inline(always)]
            pub fn sof10(&self) -> SOF10_R {
                SOF10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Synchronization Overrun Flag 11
            #[inline(always)]
            pub fn sof11(&self) -> SOF11_R {
                SOF11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Synchronization Overrun Flag 12
            #[inline(always)]
            pub fn sof12(&self) -> SOF12_R {
                SOF12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Synchronization Overrun Flag 13
            #[inline(always)]
            pub fn sof13(&self) -> SOF13_R {
                SOF13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
        }
    }
    ///DMA Channel Clear Flag Register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfr](cfr) module
    pub type CFR = crate::Reg<u32, _CFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFR;
    ///`write(|w| ..)` method takes [cfr::W](cfr::W) writer structure
    impl crate::Writable for CFR {}
    ///DMA Channel Clear Flag Register
    pub mod cfr {
        ///Writer for register CFR
        pub type W = crate::W<u32, super::CFR>;
        ///Register CFR `reset()`'s with value 0
        impl crate::ResetValue for super::CFR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `CSOF0`
        pub struct CSOF0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Write proxy for field `CSOF1`
        pub struct CSOF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CSOF2`
        pub struct CSOF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CSOF3`
        pub struct CSOF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CSOF4`
        pub struct CSOF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CSOF5`
        pub struct CSOF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `CSOF6`
        pub struct CSOF6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `CSOF7`
        pub struct CSOF7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `CSOF8`
        pub struct CSOF8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `CSOF9`
        pub struct CSOF9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `CSOF10`
        pub struct CSOF10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `CSOF11`
        pub struct CSOF11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `CSOF12`
        pub struct CSOF12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `CSOF13`
        pub struct CSOF13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSOF13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        impl W {
            ///Bit 0 - Synchronization Clear Overrun Flag 0
            #[inline(always)]
            pub fn csof0(&mut self) -> CSOF0_W {
                CSOF0_W { w: self }
            }
            ///Bit 1 - Synchronization Clear Overrun Flag 1
            #[inline(always)]
            pub fn csof1(&mut self) -> CSOF1_W {
                CSOF1_W { w: self }
            }
            ///Bit 2 - Synchronization Clear Overrun Flag 2
            #[inline(always)]
            pub fn csof2(&mut self) -> CSOF2_W {
                CSOF2_W { w: self }
            }
            ///Bit 3 - Synchronization Clear Overrun Flag 3
            #[inline(always)]
            pub fn csof3(&mut self) -> CSOF3_W {
                CSOF3_W { w: self }
            }
            ///Bit 4 - Synchronization Clear Overrun Flag 4
            #[inline(always)]
            pub fn csof4(&mut self) -> CSOF4_W {
                CSOF4_W { w: self }
            }
            ///Bit 5 - Synchronization Clear Overrun Flag 5
            #[inline(always)]
            pub fn csof5(&mut self) -> CSOF5_W {
                CSOF5_W { w: self }
            }
            ///Bit 6 - Synchronization Clear Overrun Flag 6
            #[inline(always)]
            pub fn csof6(&mut self) -> CSOF6_W {
                CSOF6_W { w: self }
            }
            ///Bit 7 - Synchronization Clear Overrun Flag 7
            #[inline(always)]
            pub fn csof7(&mut self) -> CSOF7_W {
                CSOF7_W { w: self }
            }
            ///Bit 8 - Synchronization Clear Overrun Flag 8
            #[inline(always)]
            pub fn csof8(&mut self) -> CSOF8_W {
                CSOF8_W { w: self }
            }
            ///Bit 9 - Synchronization Clear Overrun Flag 9
            #[inline(always)]
            pub fn csof9(&mut self) -> CSOF9_W {
                CSOF9_W { w: self }
            }
            ///Bit 10 - Synchronization Clear Overrun Flag 10
            #[inline(always)]
            pub fn csof10(&mut self) -> CSOF10_W {
                CSOF10_W { w: self }
            }
            ///Bit 11 - Synchronization Clear Overrun Flag 11
            #[inline(always)]
            pub fn csof11(&mut self) -> CSOF11_W {
                CSOF11_W { w: self }
            }
            ///Bit 12 - Synchronization Clear Overrun Flag 12
            #[inline(always)]
            pub fn csof12(&mut self) -> CSOF12_W {
                CSOF12_W { w: self }
            }
            ///Bit 13 - Synchronization Clear Overrun Flag 13
            #[inline(always)]
            pub fn csof13(&mut self) -> CSOF13_W {
                CSOF13_W { w: self }
            }
        }
    }
    ///DMA Request Generator 0 Control Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rg0cr](rg0cr) module
    pub type RG0CR = crate::Reg<u32, _RG0CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RG0CR;
    ///`read()` method returns [rg0cr::R](rg0cr::R) reader structure
    impl crate::Readable for RG0CR {}
    ///`write(|w| ..)` method takes [rg0cr::W](rg0cr::W) writer structure
    impl crate::Writable for RG0CR {}
    ///DMA Request Generator 0 Control Register
    pub mod rg0cr {
        ///Reader of register RG0CR
        pub type R = crate::R<u32, super::RG0CR>;
        ///Writer for register RG0CR
        pub type W = crate::W<u32, super::RG0CR>;
        ///Register RG0CR `reset()`'s with value 0
        impl crate::ResetValue for super::RG0CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `GNBREQ`
        pub type GNBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `GNBREQ`
        pub struct GNBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GNBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `GPOL`
        pub type GPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `GPOL`
        pub struct GPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `GE`
        pub type GE_R = crate::R<bool, bool>;
        ///Write proxy for field `GE`
        pub struct GE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OIE`
        pub type OIE_R = crate::R<bool, bool>;
        ///Write proxy for field `OIE`
        pub struct OIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `SIG_ID`
        pub type SIG_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SIG_ID`
        pub struct SIG_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SIG_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&self) -> GNBREQ_R {
                GNBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&self) -> GPOL_R {
                GPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&self) -> GE_R {
                GE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&self) -> OIE_R {
                OIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&self) -> SIG_ID_R {
                SIG_ID_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&mut self) -> GNBREQ_W {
                GNBREQ_W { w: self }
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&mut self) -> GPOL_W {
                GPOL_W { w: self }
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&mut self) -> GE_W {
                GE_W { w: self }
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&mut self) -> OIE_W {
                OIE_W { w: self }
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&mut self) -> SIG_ID_W {
                SIG_ID_W { w: self }
            }
        }
    }
    ///DMA Request Generator 1 Control Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rg1cr](rg1cr) module
    pub type RG1CR = crate::Reg<u32, _RG1CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RG1CR;
    ///`read()` method returns [rg1cr::R](rg1cr::R) reader structure
    impl crate::Readable for RG1CR {}
    ///`write(|w| ..)` method takes [rg1cr::W](rg1cr::W) writer structure
    impl crate::Writable for RG1CR {}
    ///DMA Request Generator 1 Control Register
    pub mod rg1cr {
        ///Reader of register RG1CR
        pub type R = crate::R<u32, super::RG1CR>;
        ///Writer for register RG1CR
        pub type W = crate::W<u32, super::RG1CR>;
        ///Register RG1CR `reset()`'s with value 0
        impl crate::ResetValue for super::RG1CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `GNBREQ`
        pub type GNBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `GNBREQ`
        pub struct GNBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GNBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `GPOL`
        pub type GPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `GPOL`
        pub struct GPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `GE`
        pub type GE_R = crate::R<bool, bool>;
        ///Write proxy for field `GE`
        pub struct GE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OIE`
        pub type OIE_R = crate::R<bool, bool>;
        ///Write proxy for field `OIE`
        pub struct OIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `SIG_ID`
        pub type SIG_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SIG_ID`
        pub struct SIG_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SIG_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&self) -> GNBREQ_R {
                GNBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&self) -> GPOL_R {
                GPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&self) -> GE_R {
                GE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&self) -> OIE_R {
                OIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&self) -> SIG_ID_R {
                SIG_ID_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&mut self) -> GNBREQ_W {
                GNBREQ_W { w: self }
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&mut self) -> GPOL_W {
                GPOL_W { w: self }
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&mut self) -> GE_W {
                GE_W { w: self }
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&mut self) -> OIE_W {
                OIE_W { w: self }
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&mut self) -> SIG_ID_W {
                SIG_ID_W { w: self }
            }
        }
    }
    ///DMA Request Generator 2 Control Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rg2cr](rg2cr) module
    pub type RG2CR = crate::Reg<u32, _RG2CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RG2CR;
    ///`read()` method returns [rg2cr::R](rg2cr::R) reader structure
    impl crate::Readable for RG2CR {}
    ///`write(|w| ..)` method takes [rg2cr::W](rg2cr::W) writer structure
    impl crate::Writable for RG2CR {}
    ///DMA Request Generator 2 Control Register
    pub mod rg2cr {
        ///Reader of register RG2CR
        pub type R = crate::R<u32, super::RG2CR>;
        ///Writer for register RG2CR
        pub type W = crate::W<u32, super::RG2CR>;
        ///Register RG2CR `reset()`'s with value 0
        impl crate::ResetValue for super::RG2CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `GNBREQ`
        pub type GNBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `GNBREQ`
        pub struct GNBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GNBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `GPOL`
        pub type GPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `GPOL`
        pub struct GPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `GE`
        pub type GE_R = crate::R<bool, bool>;
        ///Write proxy for field `GE`
        pub struct GE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OIE`
        pub type OIE_R = crate::R<bool, bool>;
        ///Write proxy for field `OIE`
        pub struct OIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `SIG_ID`
        pub type SIG_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SIG_ID`
        pub struct SIG_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SIG_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&self) -> GNBREQ_R {
                GNBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&self) -> GPOL_R {
                GPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&self) -> GE_R {
                GE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&self) -> OIE_R {
                OIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&self) -> SIG_ID_R {
                SIG_ID_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&mut self) -> GNBREQ_W {
                GNBREQ_W { w: self }
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&mut self) -> GPOL_W {
                GPOL_W { w: self }
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&mut self) -> GE_W {
                GE_W { w: self }
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&mut self) -> OIE_W {
                OIE_W { w: self }
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&mut self) -> SIG_ID_W {
                SIG_ID_W { w: self }
            }
        }
    }
    ///DMA Request Generator 3 Control Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rg3cr](rg3cr) module
    pub type RG3CR = crate::Reg<u32, _RG3CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RG3CR;
    ///`read()` method returns [rg3cr::R](rg3cr::R) reader structure
    impl crate::Readable for RG3CR {}
    ///`write(|w| ..)` method takes [rg3cr::W](rg3cr::W) writer structure
    impl crate::Writable for RG3CR {}
    ///DMA Request Generator 3 Control Register
    pub mod rg3cr {
        ///Reader of register RG3CR
        pub type R = crate::R<u32, super::RG3CR>;
        ///Writer for register RG3CR
        pub type W = crate::W<u32, super::RG3CR>;
        ///Register RG3CR `reset()`'s with value 0
        impl crate::ResetValue for super::RG3CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `GNBREQ`
        pub type GNBREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `GNBREQ`
        pub struct GNBREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GNBREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
                self.w
            }
        }
        ///Reader of field `GPOL`
        pub type GPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `GPOL`
        pub struct GPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `GE`
        pub type GE_R = crate::R<bool, bool>;
        ///Write proxy for field `GE`
        pub struct GE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OIE`
        pub type OIE_R = crate::R<bool, bool>;
        ///Write proxy for field `OIE`
        pub struct OIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `SIG_ID`
        pub type SIG_ID_R = crate::R<u8, u8>;
        ///Write proxy for field `SIG_ID`
        pub struct SIG_ID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SIG_ID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&self) -> GNBREQ_R {
                GNBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&self) -> GPOL_R {
                GPOL_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&self) -> GE_R {
                GE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&self) -> OIE_R {
                OIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&self) -> SIG_ID_R {
                SIG_ID_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 19:23 - Number of Request
            #[inline(always)]
            pub fn gnbreq(&mut self) -> GNBREQ_W {
                GNBREQ_W { w: self }
            }
            ///Bits 17:18 - Generation Polarity
            #[inline(always)]
            pub fn gpol(&mut self) -> GPOL_W {
                GPOL_W { w: self }
            }
            ///Bit 16 - Generation Enable
            #[inline(always)]
            pub fn ge(&mut self) -> GE_W {
                GE_W { w: self }
            }
            ///Bit 8 - Overrun Interrupt Enable
            #[inline(always)]
            pub fn oie(&mut self) -> OIE_W {
                OIE_W { w: self }
            }
            ///Bits 0:4 - Signal ID
            #[inline(always)]
            pub fn sig_id(&mut self) -> SIG_ID_W {
                SIG_ID_W { w: self }
            }
        }
    }
    ///DMA Request Generator Status Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rgsr](rgsr) module
    pub type RGSR = crate::Reg<u32, _RGSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RGSR;
    ///`read()` method returns [rgsr::R](rgsr::R) reader structure
    impl crate::Readable for RGSR {}
    ///DMA Request Generator Status Register
    pub mod rgsr {
        ///Reader of register RGSR
        pub type R = crate::R<u32, super::RGSR>;
        ///Reader of field `OF0`
        pub type OF0_R = crate::R<bool, bool>;
        ///Reader of field `OF1`
        pub type OF1_R = crate::R<bool, bool>;
        ///Reader of field `OF2`
        pub type OF2_R = crate::R<bool, bool>;
        ///Reader of field `OF3`
        pub type OF3_R = crate::R<bool, bool>;
        impl R {
            ///Bit 0 - Generator Overrun Flag 0
            #[inline(always)]
            pub fn of0(&self) -> OF0_R {
                OF0_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Generator Overrun Flag 1
            #[inline(always)]
            pub fn of1(&self) -> OF1_R {
                OF1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Generator Overrun Flag 2
            #[inline(always)]
            pub fn of2(&self) -> OF2_R {
                OF2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Generator Overrun Flag 3
            #[inline(always)]
            pub fn of3(&self) -> OF3_R {
                OF3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
        }
    }
    ///DMA Request Generator Clear Flag Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rgcfr](rgcfr) module
    pub type RGCFR = crate::Reg<u32, _RGCFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RGCFR;
    ///`read()` method returns [rgcfr::R](rgcfr::R) reader structure
    impl crate::Readable for RGCFR {}
    ///DMA Request Generator Clear Flag Register
    pub mod rgcfr {
        ///Reader of register RGCFR
        pub type R = crate::R<u32, super::RGCFR>;
        ///Reader of field `CSOF0`
        pub type CSOF0_R = crate::R<bool, bool>;
        ///Reader of field `CSOF1`
        pub type CSOF1_R = crate::R<bool, bool>;
        ///Reader of field `CSOF2`
        pub type CSOF2_R = crate::R<bool, bool>;
        ///Reader of field `CSOF3`
        pub type CSOF3_R = crate::R<bool, bool>;
        impl R {
            ///Bit 0 - Generator Clear Overrun Flag 0
            #[inline(always)]
            pub fn csof0(&self) -> CSOF0_R {
                CSOF0_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Generator Clear Overrun Flag 1
            #[inline(always)]
            pub fn csof1(&self) -> CSOF1_R {
                CSOF1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Generator Clear Overrun Flag 2
            #[inline(always)]
            pub fn csof2(&self) -> CSOF2_R {
                CSOF2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Generator Clear Overrun Flag 3
            #[inline(always)]
            pub fn csof3(&self) -> CSOF3_R {
                CSOF3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
        }
    }
}
///Cyclic redundancy check calculation unit
pub struct CRC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for CRC {}
impl CRC {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const crc::RegisterBlock {
        0x4002_3000 as *const _
    }
}
impl Deref for CRC {
    type Target = crc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*CRC::ptr() }
    }
}
///Cyclic redundancy check calculation unit
pub mod crc {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Data register
        pub dr: DR,
        ///0x04 - Independent data register
        pub idr: IDR,
        ///0x08 - Control register
        pub cr: CR,
        _reserved3: [u8; 4usize],
        ///0x10 - Initial CRC value
        pub init: INIT,
        ///0x14 - polynomial
        pub pol: POL,
    }
    ///Data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dr](dr) module
    pub type DR = crate::Reg<u32, _DR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DR;
    ///`read()` method returns [dr::R](dr::R) reader structure
    impl crate::Readable for DR {}
    ///`write(|w| ..)` method takes [dr::W](dr::W) writer structure
    impl crate::Writable for DR {}
    ///Data register
    pub mod dr {
        ///Reader of register DR
        pub type R = crate::R<u32, super::DR>;
        ///Writer for register DR
        pub type W = crate::W<u32, super::DR>;
        ///Register DR `reset()`'s with value 0xffff_ffff
        impl crate::ResetValue for super::DR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_ffff
            }
        }
        ///Reader of field `DR`
        pub type DR_R = crate::R<u32, u32>;
        ///Write proxy for field `DR`
        pub struct DR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Data register bits
            #[inline(always)]
            pub fn dr(&self) -> DR_R {
                DR_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Data register bits
            #[inline(always)]
            pub fn dr(&mut self) -> DR_W {
                DR_W { w: self }
            }
        }
    }
    ///Independent data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [idr](idr) module
    pub type IDR = crate::Reg<u32, _IDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IDR;
    ///`read()` method returns [idr::R](idr::R) reader structure
    impl crate::Readable for IDR {}
    ///`write(|w| ..)` method takes [idr::W](idr::W) writer structure
    impl crate::Writable for IDR {}
    ///Independent data register
    pub mod idr {
        ///Reader of register IDR
        pub type R = crate::R<u32, super::IDR>;
        ///Writer for register IDR
        pub type W = crate::W<u32, super::IDR>;
        ///Register IDR `reset()`'s with value 0
        impl crate::ResetValue for super::IDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `IDR`
        pub type IDR_R = crate::R<u32, u32>;
        ///Write proxy for field `IDR`
        pub struct IDR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IDR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - General-purpose 32-bit data register bits
            #[inline(always)]
            pub fn idr(&self) -> IDR_R {
                IDR_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - General-purpose 32-bit data register bits
            #[inline(always)]
            pub fn idr(&mut self) -> IDR_W {
                IDR_W { w: self }
            }
        }
    }
    ///Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `REV_OUT`
        pub type REV_OUT_R = crate::R<bool, bool>;
        ///Write proxy for field `REV_OUT`
        pub struct REV_OUT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> REV_OUT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `REV_IN`
        pub type REV_IN_R = crate::R<u8, u8>;
        ///Write proxy for field `REV_IN`
        pub struct REV_IN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> REV_IN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
                self.w
            }
        }
        ///Reader of field `POLYSIZE`
        pub type POLYSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `POLYSIZE`
        pub struct POLYSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> POLYSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
                self.w
            }
        }
        ///Reader of field `RESET`
        pub type RESET_R = crate::R<bool, bool>;
        ///Write proxy for field `RESET`
        pub struct RESET_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RESET_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 7 - Reverse output data
            #[inline(always)]
            pub fn rev_out(&self) -> REV_OUT_R {
                REV_OUT_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 5:6 - Reverse input data
            #[inline(always)]
            pub fn rev_in(&self) -> REV_IN_R {
                REV_IN_R::new(((self.bits >> 5) & 0x03) as u8)
            }
            ///Bits 3:4 - Polynomial size
            #[inline(always)]
            pub fn polysize(&self) -> POLYSIZE_R {
                POLYSIZE_R::new(((self.bits >> 3) & 0x03) as u8)
            }
            ///Bit 0 - RESET bit
            #[inline(always)]
            pub fn reset(&self) -> RESET_R {
                RESET_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 7 - Reverse output data
            #[inline(always)]
            pub fn rev_out(&mut self) -> REV_OUT_W {
                REV_OUT_W { w: self }
            }
            ///Bits 5:6 - Reverse input data
            #[inline(always)]
            pub fn rev_in(&mut self) -> REV_IN_W {
                REV_IN_W { w: self }
            }
            ///Bits 3:4 - Polynomial size
            #[inline(always)]
            pub fn polysize(&mut self) -> POLYSIZE_W {
                POLYSIZE_W { w: self }
            }
            ///Bit 0 - RESET bit
            #[inline(always)]
            pub fn reset(&mut self) -> RESET_W {
                RESET_W { w: self }
            }
        }
    }
    ///Initial CRC value
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [init](init) module
    pub type INIT = crate::Reg<u32, _INIT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _INIT;
    ///`read()` method returns [init::R](init::R) reader structure
    impl crate::Readable for INIT {}
    ///`write(|w| ..)` method takes [init::W](init::W) writer structure
    impl crate::Writable for INIT {}
    ///Initial CRC value
    pub mod init {
        ///Reader of register INIT
        pub type R = crate::R<u32, super::INIT>;
        ///Writer for register INIT
        pub type W = crate::W<u32, super::INIT>;
        ///Register INIT `reset()`'s with value 0xffff_ffff
        impl crate::ResetValue for super::INIT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_ffff
            }
        }
        ///Reader of field `CRC_INIT`
        pub type CRC_INIT_R = crate::R<u32, u32>;
        ///Write proxy for field `CRC_INIT`
        pub struct CRC_INIT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRC_INIT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Programmable initial CRC value
            #[inline(always)]
            pub fn crc_init(&self) -> CRC_INIT_R {
                CRC_INIT_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Programmable initial CRC value
            #[inline(always)]
            pub fn crc_init(&mut self) -> CRC_INIT_W {
                CRC_INIT_W { w: self }
            }
        }
    }
    ///polynomial
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pol](pol) module
    pub type POL = crate::Reg<u32, _POL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _POL;
    ///`read()` method returns [pol::R](pol::R) reader structure
    impl crate::Readable for POL {}
    ///`write(|w| ..)` method takes [pol::W](pol::W) writer structure
    impl crate::Writable for POL {}
    ///polynomial
    pub mod pol {
        ///Reader of register POL
        pub type R = crate::R<u32, super::POL>;
        ///Writer for register POL
        pub type W = crate::W<u32, super::POL>;
        ///Register POL `reset()`'s with value 0x04c1_1db7
        impl crate::ResetValue for super::POL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x04c1_1db7
            }
        }
        ///Reader of field `POL`
        pub type POL_R = crate::R<u32, u32>;
        ///Write proxy for field `POL`
        pub struct POL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> POL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Programmable polynomial
            #[inline(always)]
            pub fn pol(&self) -> POL_R {
                POL_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Programmable polynomial
            #[inline(always)]
            pub fn pol(&mut self) -> POL_W {
                POL_W { w: self }
            }
        }
    }
}
///Liquid crystal display controller
pub struct LCD {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LCD {}
impl LCD {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const lcd::RegisterBlock {
        0x4000_2400 as *const _
    }
}
impl Deref for LCD {
    type Target = lcd::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*LCD::ptr() }
    }
}
///Liquid crystal display controller
pub mod lcd {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register
        pub cr: CR,
        ///0x04 - frame control register
        pub fcr: FCR,
        ///0x08 - status register
        pub sr: SR,
        ///0x0c - clear register
        pub clr: CLR,
        _reserved4: [u8; 4usize],
        ///0x14 - display memory
        pub ram_com0: RAM_COM0,
        _reserved5: [u8; 4usize],
        ///0x1c - display memory
        pub ram_com1: RAM_COM1,
        _reserved6: [u8; 4usize],
        ///0x24 - display memory
        pub ram_com2: RAM_COM2,
        _reserved7: [u8; 4usize],
        ///0x2c - display memory
        pub ram_com3: RAM_COM3,
        _reserved8: [u8; 4usize],
        ///0x34 - display memory
        pub ram_com4: RAM_COM4,
        _reserved9: [u8; 4usize],
        ///0x3c - display memory
        pub ram_com5: RAM_COM5,
        _reserved10: [u8; 4usize],
        ///0x44 - display memory
        pub ram_com6: RAM_COM6,
        _reserved11: [u8; 4usize],
        ///0x4c - display memory
        pub ram_com7: RAM_COM7,
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BIAS`
        pub type BIAS_R = crate::R<u8, u8>;
        ///Write proxy for field `BIAS`
        pub struct BIAS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIAS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
                self.w
            }
        }
        ///Reader of field `DUTY`
        pub type DUTY_R = crate::R<u8, u8>;
        ///Write proxy for field `DUTY`
        pub struct DUTY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DUTY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 2)) | (((value as u32) & 0x07) << 2);
                self.w
            }
        }
        ///Reader of field `VSEL`
        pub type VSEL_R = crate::R<bool, bool>;
        ///Write proxy for field `VSEL`
        pub struct VSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> VSEL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LCDEN`
        pub type LCDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LCDEN`
        pub struct LCDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `MUX_SEG`
        pub type MUX_SEG_R = crate::R<bool, bool>;
        ///Write proxy for field `MUX_SEG`
        pub struct MUX_SEG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MUX_SEG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `BUFEN`
        pub type BUFEN_R = crate::R<bool, bool>;
        ///Write proxy for field `BUFEN`
        pub struct BUFEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BUFEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        impl R {
            ///Bits 5:6 - Bias selector
            #[inline(always)]
            pub fn bias(&self) -> BIAS_R {
                BIAS_R::new(((self.bits >> 5) & 0x03) as u8)
            }
            ///Bits 2:4 - Duty selection
            #[inline(always)]
            pub fn duty(&self) -> DUTY_R {
                DUTY_R::new(((self.bits >> 2) & 0x07) as u8)
            }
            ///Bit 1 - Voltage source selection
            #[inline(always)]
            pub fn vsel(&self) -> VSEL_R {
                VSEL_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - LCD controller enable
            #[inline(always)]
            pub fn lcden(&self) -> LCDEN_R {
                LCDEN_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 7 - Mux segment enable
            #[inline(always)]
            pub fn mux_seg(&self) -> MUX_SEG_R {
                MUX_SEG_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Voltage output buffer enable
            #[inline(always)]
            pub fn bufen(&self) -> BUFEN_R {
                BUFEN_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 5:6 - Bias selector
            #[inline(always)]
            pub fn bias(&mut self) -> BIAS_W {
                BIAS_W { w: self }
            }
            ///Bits 2:4 - Duty selection
            #[inline(always)]
            pub fn duty(&mut self) -> DUTY_W {
                DUTY_W { w: self }
            }
            ///Bit 1 - Voltage source selection
            #[inline(always)]
            pub fn vsel(&mut self) -> VSEL_W {
                VSEL_W { w: self }
            }
            ///Bit 0 - LCD controller enable
            #[inline(always)]
            pub fn lcden(&mut self) -> LCDEN_W {
                LCDEN_W { w: self }
            }
            ///Bit 7 - Mux segment enable
            #[inline(always)]
            pub fn mux_seg(&mut self) -> MUX_SEG_W {
                MUX_SEG_W { w: self }
            }
            ///Bit 8 - Voltage output buffer enable
            #[inline(always)]
            pub fn bufen(&mut self) -> BUFEN_W {
                BUFEN_W { w: self }
            }
        }
    }
    ///frame control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [fcr](fcr) module
    pub type FCR = crate::Reg<u32, _FCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _FCR;
    ///`read()` method returns [fcr::R](fcr::R) reader structure
    impl crate::Readable for FCR {}
    ///`write(|w| ..)` method takes [fcr::W](fcr::W) writer structure
    impl crate::Writable for FCR {}
    ///frame control register
    pub mod fcr {
        ///Reader of register FCR
        pub type R = crate::R<u32, super::FCR>;
        ///Writer for register FCR
        pub type W = crate::W<u32, super::FCR>;
        ///Register FCR `reset()`'s with value 0
        impl crate::ResetValue for super::FCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PS`
        pub type PS_R = crate::R<u8, u8>;
        ///Write proxy for field `PS`
        pub struct PS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 22)) | (((value as u32) & 0x0f) << 22);
                self.w
            }
        }
        ///Reader of field `DIV`
        pub type DIV_R = crate::R<u8, u8>;
        ///Write proxy for field `DIV`
        pub struct DIV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIV_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u32) & 0x0f) << 18);
                self.w
            }
        }
        ///Reader of field `BLINK`
        pub type BLINK_R = crate::R<u8, u8>;
        ///Write proxy for field `BLINK`
        pub struct BLINK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BLINK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `BLINKF`
        pub type BLINKF_R = crate::R<u8, u8>;
        ///Write proxy for field `BLINKF`
        pub struct BLINKF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BLINKF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 13)) | (((value as u32) & 0x07) << 13);
                self.w
            }
        }
        ///Reader of field `CC`
        pub type CC_R = crate::R<u8, u8>;
        ///Write proxy for field `CC`
        pub struct CC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 10)) | (((value as u32) & 0x07) << 10);
                self.w
            }
        }
        ///Reader of field `DEAD`
        pub type DEAD_R = crate::R<u8, u8>;
        ///Write proxy for field `DEAD`
        pub struct DEAD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEAD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 7)) | (((value as u32) & 0x07) << 7);
                self.w
            }
        }
        ///Reader of field `PON`
        pub type PON_R = crate::R<u8, u8>;
        ///Write proxy for field `PON`
        pub struct PON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PON_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `UDDIE`
        pub type UDDIE_R = crate::R<bool, bool>;
        ///Write proxy for field `UDDIE`
        pub struct UDDIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDDIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `SOFIE`
        pub type SOFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SOFIE`
        pub struct SOFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `HD`
        pub type HD_R = crate::R<bool, bool>;
        ///Write proxy for field `HD`
        pub struct HD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 22:25 - PS 16-bit prescaler
            #[inline(always)]
            pub fn ps(&self) -> PS_R {
                PS_R::new(((self.bits >> 22) & 0x0f) as u8)
            }
            ///Bits 18:21 - DIV clock divider
            #[inline(always)]
            pub fn div(&self) -> DIV_R {
                DIV_R::new(((self.bits >> 18) & 0x0f) as u8)
            }
            ///Bits 16:17 - Blink mode selection
            #[inline(always)]
            pub fn blink(&self) -> BLINK_R {
                BLINK_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 13:15 - Blink frequency selection
            #[inline(always)]
            pub fn blinkf(&self) -> BLINKF_R {
                BLINKF_R::new(((self.bits >> 13) & 0x07) as u8)
            }
            ///Bits 10:12 - Contrast control
            #[inline(always)]
            pub fn cc(&self) -> CC_R {
                CC_R::new(((self.bits >> 10) & 0x07) as u8)
            }
            ///Bits 7:9 - Dead time duration
            #[inline(always)]
            pub fn dead(&self) -> DEAD_R {
                DEAD_R::new(((self.bits >> 7) & 0x07) as u8)
            }
            ///Bits 4:6 - Pulse ON duration
            #[inline(always)]
            pub fn pon(&self) -> PON_R {
                PON_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Update display done interrupt enable
            #[inline(always)]
            pub fn uddie(&self) -> UDDIE_R {
                UDDIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Start of frame interrupt enable
            #[inline(always)]
            pub fn sofie(&self) -> SOFIE_R {
                SOFIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - High drive enable
            #[inline(always)]
            pub fn hd(&self) -> HD_R {
                HD_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 22:25 - PS 16-bit prescaler
            #[inline(always)]
            pub fn ps(&mut self) -> PS_W {
                PS_W { w: self }
            }
            ///Bits 18:21 - DIV clock divider
            #[inline(always)]
            pub fn div(&mut self) -> DIV_W {
                DIV_W { w: self }
            }
            ///Bits 16:17 - Blink mode selection
            #[inline(always)]
            pub fn blink(&mut self) -> BLINK_W {
                BLINK_W { w: self }
            }
            ///Bits 13:15 - Blink frequency selection
            #[inline(always)]
            pub fn blinkf(&mut self) -> BLINKF_W {
                BLINKF_W { w: self }
            }
            ///Bits 10:12 - Contrast control
            #[inline(always)]
            pub fn cc(&mut self) -> CC_W {
                CC_W { w: self }
            }
            ///Bits 7:9 - Dead time duration
            #[inline(always)]
            pub fn dead(&mut self) -> DEAD_W {
                DEAD_W { w: self }
            }
            ///Bits 4:6 - Pulse ON duration
            #[inline(always)]
            pub fn pon(&mut self) -> PON_W {
                PON_W { w: self }
            }
            ///Bit 3 - Update display done interrupt enable
            #[inline(always)]
            pub fn uddie(&mut self) -> UDDIE_W {
                UDDIE_W { w: self }
            }
            ///Bit 1 - Start of frame interrupt enable
            #[inline(always)]
            pub fn sofie(&mut self) -> SOFIE_W {
                SOFIE_W { w: self }
            }
            ///Bit 0 - High drive enable
            #[inline(always)]
            pub fn hd(&mut self) -> HD_W {
                HD_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0x20
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x20
            }
        }
        ///Reader of field `FCRSF`
        pub type FCRSF_R = crate::R<bool, bool>;
        ///Reader of field `RDY`
        pub type RDY_R = crate::R<bool, bool>;
        ///Reader of field `UDD`
        pub type UDD_R = crate::R<bool, bool>;
        ///Reader of field `UDR`
        pub type UDR_R = crate::R<bool, bool>;
        ///Write proxy for field `UDR`
        pub struct UDR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `SOF`
        pub type SOF_R = crate::R<bool, bool>;
        ///Reader of field `ENS`
        pub type ENS_R = crate::R<bool, bool>;
        impl R {
            ///Bit 5 - LCD Frame Control Register Synchronization flag
            #[inline(always)]
            pub fn fcrsf(&self) -> FCRSF_R {
                FCRSF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Ready flag
            #[inline(always)]
            pub fn rdy(&self) -> RDY_R {
                RDY_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Update Display Done
            #[inline(always)]
            pub fn udd(&self) -> UDD_R {
                UDD_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Update display request
            #[inline(always)]
            pub fn udr(&self) -> UDR_R {
                UDR_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Start of frame flag
            #[inline(always)]
            pub fn sof(&self) -> SOF_R {
                SOF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - ENS
            #[inline(always)]
            pub fn ens(&self) -> ENS_R {
                ENS_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 2 - Update display request
            #[inline(always)]
            pub fn udr(&mut self) -> UDR_W {
                UDR_W { w: self }
            }
        }
    }
    ///clear register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [clr](clr) module
    pub type CLR = crate::Reg<u32, _CLR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CLR;
    ///`write(|w| ..)` method takes [clr::W](clr::W) writer structure
    impl crate::Writable for CLR {}
    ///clear register
    pub mod clr {
        ///Writer for register CLR
        pub type W = crate::W<u32, super::CLR>;
        ///Register CLR `reset()`'s with value 0
        impl crate::ResetValue for super::CLR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `UDDC`
        pub struct UDDC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDDC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `SOFC`
        pub struct SOFC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOFC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        impl W {
            ///Bit 3 - Update display done clear
            #[inline(always)]
            pub fn uddc(&mut self) -> UDDC_W {
                UDDC_W { w: self }
            }
            ///Bit 1 - Start of frame flag clear
            #[inline(always)]
            pub fn sofc(&mut self) -> SOFC_W {
                SOFC_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com0](ram_com0) module
    pub type RAM_COM0 = crate::Reg<u32, _RAM_COM0>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM0;
    ///`read()` method returns [ram_com0::R](ram_com0::R) reader structure
    impl crate::Readable for RAM_COM0 {}
    ///`write(|w| ..)` method takes [ram_com0::W](ram_com0::W) writer structure
    impl crate::Writable for RAM_COM0 {}
    ///display memory
    pub mod ram_com0 {
        ///Reader of register RAM_COM0
        pub type R = crate::R<u32, super::RAM_COM0>;
        ///Writer for register RAM_COM0
        pub type W = crate::W<u32, super::RAM_COM0>;
        ///Register RAM_COM0 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM0 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com1](ram_com1) module
    pub type RAM_COM1 = crate::Reg<u32, _RAM_COM1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM1;
    ///`read()` method returns [ram_com1::R](ram_com1::R) reader structure
    impl crate::Readable for RAM_COM1 {}
    ///`write(|w| ..)` method takes [ram_com1::W](ram_com1::W) writer structure
    impl crate::Writable for RAM_COM1 {}
    ///display memory
    pub mod ram_com1 {
        ///Reader of register RAM_COM1
        pub type R = crate::R<u32, super::RAM_COM1>;
        ///Writer for register RAM_COM1
        pub type W = crate::W<u32, super::RAM_COM1>;
        ///Register RAM_COM1 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com2](ram_com2) module
    pub type RAM_COM2 = crate::Reg<u32, _RAM_COM2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM2;
    ///`read()` method returns [ram_com2::R](ram_com2::R) reader structure
    impl crate::Readable for RAM_COM2 {}
    ///`write(|w| ..)` method takes [ram_com2::W](ram_com2::W) writer structure
    impl crate::Writable for RAM_COM2 {}
    ///display memory
    pub mod ram_com2 {
        ///Reader of register RAM_COM2
        pub type R = crate::R<u32, super::RAM_COM2>;
        ///Writer for register RAM_COM2
        pub type W = crate::W<u32, super::RAM_COM2>;
        ///Register RAM_COM2 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com3](ram_com3) module
    pub type RAM_COM3 = crate::Reg<u32, _RAM_COM3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM3;
    ///`read()` method returns [ram_com3::R](ram_com3::R) reader structure
    impl crate::Readable for RAM_COM3 {}
    ///`write(|w| ..)` method takes [ram_com3::W](ram_com3::W) writer structure
    impl crate::Writable for RAM_COM3 {}
    ///display memory
    pub mod ram_com3 {
        ///Reader of register RAM_COM3
        pub type R = crate::R<u32, super::RAM_COM3>;
        ///Writer for register RAM_COM3
        pub type W = crate::W<u32, super::RAM_COM3>;
        ///Register RAM_COM3 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com4](ram_com4) module
    pub type RAM_COM4 = crate::Reg<u32, _RAM_COM4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM4;
    ///`read()` method returns [ram_com4::R](ram_com4::R) reader structure
    impl crate::Readable for RAM_COM4 {}
    ///`write(|w| ..)` method takes [ram_com4::W](ram_com4::W) writer structure
    impl crate::Writable for RAM_COM4 {}
    ///display memory
    pub mod ram_com4 {
        ///Reader of register RAM_COM4
        pub type R = crate::R<u32, super::RAM_COM4>;
        ///Writer for register RAM_COM4
        pub type W = crate::W<u32, super::RAM_COM4>;
        ///Register RAM_COM4 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com5](ram_com5) module
    pub type RAM_COM5 = crate::Reg<u32, _RAM_COM5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM5;
    ///`read()` method returns [ram_com5::R](ram_com5::R) reader structure
    impl crate::Readable for RAM_COM5 {}
    ///`write(|w| ..)` method takes [ram_com5::W](ram_com5::W) writer structure
    impl crate::Writable for RAM_COM5 {}
    ///display memory
    pub mod ram_com5 {
        ///Reader of register RAM_COM5
        pub type R = crate::R<u32, super::RAM_COM5>;
        ///Writer for register RAM_COM5
        pub type W = crate::W<u32, super::RAM_COM5>;
        ///Register RAM_COM5 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com6](ram_com6) module
    pub type RAM_COM6 = crate::Reg<u32, _RAM_COM6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM6;
    ///`read()` method returns [ram_com6::R](ram_com6::R) reader structure
    impl crate::Readable for RAM_COM6 {}
    ///`write(|w| ..)` method takes [ram_com6::W](ram_com6::W) writer structure
    impl crate::Writable for RAM_COM6 {}
    ///display memory
    pub mod ram_com6 {
        ///Reader of register RAM_COM6
        pub type R = crate::R<u32, super::RAM_COM6>;
        ///Writer for register RAM_COM6
        pub type W = crate::W<u32, super::RAM_COM6>;
        ///Register RAM_COM6 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
    ///display memory
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ram_com7](ram_com7) module
    pub type RAM_COM7 = crate::Reg<u32, _RAM_COM7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RAM_COM7;
    ///`read()` method returns [ram_com7::R](ram_com7::R) reader structure
    impl crate::Readable for RAM_COM7 {}
    ///`write(|w| ..)` method takes [ram_com7::W](ram_com7::W) writer structure
    impl crate::Writable for RAM_COM7 {}
    ///display memory
    pub mod ram_com7 {
        ///Reader of register RAM_COM7
        pub type R = crate::R<u32, super::RAM_COM7>;
        ///Writer for register RAM_COM7
        pub type W = crate::W<u32, super::RAM_COM7>;
        ///Register RAM_COM7 `reset()`'s with value 0
        impl crate::ResetValue for super::RAM_COM7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `S31`
        pub type S31_R = crate::R<bool, bool>;
        ///Write proxy for field `S31`
        pub struct S31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `S30`
        pub type S30_R = crate::R<bool, bool>;
        ///Write proxy for field `S30`
        pub struct S30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `S29`
        pub type S29_R = crate::R<bool, bool>;
        ///Write proxy for field `S29`
        pub struct S29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `S28`
        pub type S28_R = crate::R<bool, bool>;
        ///Write proxy for field `S28`
        pub struct S28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `S27`
        pub type S27_R = crate::R<bool, bool>;
        ///Write proxy for field `S27`
        pub struct S27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `S26`
        pub type S26_R = crate::R<bool, bool>;
        ///Write proxy for field `S26`
        pub struct S26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `S25`
        pub type S25_R = crate::R<bool, bool>;
        ///Write proxy for field `S25`
        pub struct S25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `S24`
        pub type S24_R = crate::R<bool, bool>;
        ///Write proxy for field `S24`
        pub struct S24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `S23`
        pub type S23_R = crate::R<bool, bool>;
        ///Write proxy for field `S23`
        pub struct S23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `S22`
        pub type S22_R = crate::R<bool, bool>;
        ///Write proxy for field `S22`
        pub struct S22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `S21`
        pub type S21_R = crate::R<bool, bool>;
        ///Write proxy for field `S21`
        pub struct S21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `S20`
        pub type S20_R = crate::R<bool, bool>;
        ///Write proxy for field `S20`
        pub struct S20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `S19`
        pub type S19_R = crate::R<bool, bool>;
        ///Write proxy for field `S19`
        pub struct S19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `S18`
        pub type S18_R = crate::R<bool, bool>;
        ///Write proxy for field `S18`
        pub struct S18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `S17`
        pub type S17_R = crate::R<bool, bool>;
        ///Write proxy for field `S17`
        pub struct S17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `S16`
        pub type S16_R = crate::R<bool, bool>;
        ///Write proxy for field `S16`
        pub struct S16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `S15`
        pub type S15_R = crate::R<bool, bool>;
        ///Write proxy for field `S15`
        pub struct S15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `S14`
        pub type S14_R = crate::R<bool, bool>;
        ///Write proxy for field `S14`
        pub struct S14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `S13`
        pub type S13_R = crate::R<bool, bool>;
        ///Write proxy for field `S13`
        pub struct S13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `S12`
        pub type S12_R = crate::R<bool, bool>;
        ///Write proxy for field `S12`
        pub struct S12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `S11`
        pub type S11_R = crate::R<bool, bool>;
        ///Write proxy for field `S11`
        pub struct S11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `S10`
        pub type S10_R = crate::R<bool, bool>;
        ///Write proxy for field `S10`
        pub struct S10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `S09`
        pub type S09_R = crate::R<bool, bool>;
        ///Write proxy for field `S09`
        pub struct S09_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S09_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `S08`
        pub type S08_R = crate::R<bool, bool>;
        ///Write proxy for field `S08`
        pub struct S08_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S08_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `S07`
        pub type S07_R = crate::R<bool, bool>;
        ///Write proxy for field `S07`
        pub struct S07_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S07_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `S06`
        pub type S06_R = crate::R<bool, bool>;
        ///Write proxy for field `S06`
        pub struct S06_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S06_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `S05`
        pub type S05_R = crate::R<bool, bool>;
        ///Write proxy for field `S05`
        pub struct S05_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S05_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `S04`
        pub type S04_R = crate::R<bool, bool>;
        ///Write proxy for field `S04`
        pub struct S04_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S04_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `S03`
        pub type S03_R = crate::R<bool, bool>;
        ///Write proxy for field `S03`
        pub struct S03_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S03_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `S02`
        pub type S02_R = crate::R<bool, bool>;
        ///Write proxy for field `S02`
        pub struct S02_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S02_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `S01`
        pub type S01_R = crate::R<bool, bool>;
        ///Write proxy for field `S01`
        pub struct S01_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S01_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `S00`
        pub type S00_R = crate::R<bool, bool>;
        ///Write proxy for field `S00`
        pub struct S00_W<'a> {
            w: &'a mut W,
        }
        impl<'a> S00_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&self) -> S31_R {
                S31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&self) -> S30_R {
                S30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&self) -> S29_R {
                S29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&self) -> S28_R {
                S28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&self) -> S27_R {
                S27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&self) -> S26_R {
                S26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&self) -> S25_R {
                S25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&self) -> S24_R {
                S24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&self) -> S23_R {
                S23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&self) -> S22_R {
                S22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&self) -> S21_R {
                S21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&self) -> S20_R {
                S20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&self) -> S19_R {
                S19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&self) -> S18_R {
                S18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&self) -> S17_R {
                S17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&self) -> S16_R {
                S16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&self) -> S15_R {
                S15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&self) -> S14_R {
                S14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&self) -> S13_R {
                S13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&self) -> S12_R {
                S12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&self) -> S11_R {
                S11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&self) -> S10_R {
                S10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&self) -> S09_R {
                S09_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&self) -> S08_R {
                S08_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&self) -> S07_R {
                S07_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&self) -> S06_R {
                S06_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&self) -> S05_R {
                S05_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&self) -> S04_R {
                S04_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&self) -> S03_R {
                S03_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&self) -> S02_R {
                S02_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&self) -> S01_R {
                S01_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&self) -> S00_R {
                S00_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - S31
            #[inline(always)]
            pub fn s31(&mut self) -> S31_W {
                S31_W { w: self }
            }
            ///Bit 30 - S30
            #[inline(always)]
            pub fn s30(&mut self) -> S30_W {
                S30_W { w: self }
            }
            ///Bit 29 - S29
            #[inline(always)]
            pub fn s29(&mut self) -> S29_W {
                S29_W { w: self }
            }
            ///Bit 28 - S28
            #[inline(always)]
            pub fn s28(&mut self) -> S28_W {
                S28_W { w: self }
            }
            ///Bit 27 - S27
            #[inline(always)]
            pub fn s27(&mut self) -> S27_W {
                S27_W { w: self }
            }
            ///Bit 26 - S26
            #[inline(always)]
            pub fn s26(&mut self) -> S26_W {
                S26_W { w: self }
            }
            ///Bit 25 - S25
            #[inline(always)]
            pub fn s25(&mut self) -> S25_W {
                S25_W { w: self }
            }
            ///Bit 24 - S24
            #[inline(always)]
            pub fn s24(&mut self) -> S24_W {
                S24_W { w: self }
            }
            ///Bit 23 - S23
            #[inline(always)]
            pub fn s23(&mut self) -> S23_W {
                S23_W { w: self }
            }
            ///Bit 22 - S22
            #[inline(always)]
            pub fn s22(&mut self) -> S22_W {
                S22_W { w: self }
            }
            ///Bit 21 - S21
            #[inline(always)]
            pub fn s21(&mut self) -> S21_W {
                S21_W { w: self }
            }
            ///Bit 20 - S20
            #[inline(always)]
            pub fn s20(&mut self) -> S20_W {
                S20_W { w: self }
            }
            ///Bit 19 - S19
            #[inline(always)]
            pub fn s19(&mut self) -> S19_W {
                S19_W { w: self }
            }
            ///Bit 18 - S18
            #[inline(always)]
            pub fn s18(&mut self) -> S18_W {
                S18_W { w: self }
            }
            ///Bit 17 - S17
            #[inline(always)]
            pub fn s17(&mut self) -> S17_W {
                S17_W { w: self }
            }
            ///Bit 16 - S16
            #[inline(always)]
            pub fn s16(&mut self) -> S16_W {
                S16_W { w: self }
            }
            ///Bit 15 - S15
            #[inline(always)]
            pub fn s15(&mut self) -> S15_W {
                S15_W { w: self }
            }
            ///Bit 14 - S14
            #[inline(always)]
            pub fn s14(&mut self) -> S14_W {
                S14_W { w: self }
            }
            ///Bit 13 - S13
            #[inline(always)]
            pub fn s13(&mut self) -> S13_W {
                S13_W { w: self }
            }
            ///Bit 12 - S12
            #[inline(always)]
            pub fn s12(&mut self) -> S12_W {
                S12_W { w: self }
            }
            ///Bit 11 - S11
            #[inline(always)]
            pub fn s11(&mut self) -> S11_W {
                S11_W { w: self }
            }
            ///Bit 10 - S10
            #[inline(always)]
            pub fn s10(&mut self) -> S10_W {
                S10_W { w: self }
            }
            ///Bit 9 - S09
            #[inline(always)]
            pub fn s09(&mut self) -> S09_W {
                S09_W { w: self }
            }
            ///Bit 8 - S08
            #[inline(always)]
            pub fn s08(&mut self) -> S08_W {
                S08_W { w: self }
            }
            ///Bit 7 - S07
            #[inline(always)]
            pub fn s07(&mut self) -> S07_W {
                S07_W { w: self }
            }
            ///Bit 6 - S06
            #[inline(always)]
            pub fn s06(&mut self) -> S06_W {
                S06_W { w: self }
            }
            ///Bit 5 - S05
            #[inline(always)]
            pub fn s05(&mut self) -> S05_W {
                S05_W { w: self }
            }
            ///Bit 4 - S04
            #[inline(always)]
            pub fn s04(&mut self) -> S04_W {
                S04_W { w: self }
            }
            ///Bit 3 - S03
            #[inline(always)]
            pub fn s03(&mut self) -> S03_W {
                S03_W { w: self }
            }
            ///Bit 2 - S02
            #[inline(always)]
            pub fn s02(&mut self) -> S02_W {
                S02_W { w: self }
            }
            ///Bit 1 - S01
            #[inline(always)]
            pub fn s01(&mut self) -> S01_W {
                S01_W { w: self }
            }
            ///Bit 0 - S00
            #[inline(always)]
            pub fn s00(&mut self) -> S00_W {
                S00_W { w: self }
            }
        }
    }
}
///Touch sensing controller
pub struct TSC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for TSC {}
impl TSC {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const tsc::RegisterBlock {
        0x4002_4000 as *const _
    }
}
impl Deref for TSC {
    type Target = tsc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*TSC::ptr() }
    }
}
///Touch sensing controller
pub mod tsc {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register
        pub cr: CR,
        ///0x04 - interrupt enable register
        pub ier: IER,
        ///0x08 - interrupt clear register
        pub icr: ICR,
        ///0x0c - interrupt status register
        pub isr: ISR,
        ///0x10 - I/O hysteresis control register
        pub iohcr: IOHCR,
        _reserved5: [u8; 4usize],
        ///0x18 - I/O analog switch control register
        pub ioascr: IOASCR,
        _reserved6: [u8; 4usize],
        ///0x20 - I/O sampling control register
        pub ioscr: IOSCR,
        _reserved7: [u8; 4usize],
        ///0x28 - I/O channel control register
        pub ioccr: IOCCR,
        _reserved8: [u8; 4usize],
        ///0x30 - I/O group control status register
        pub iogcsr: IOGCSR,
        ///0x34 - I/O group x counter register
        pub iog1cr: IOG1CR,
        ///0x38 - I/O group x counter register
        pub iog2cr: IOG2CR,
        ///0x3c - I/O group x counter register
        pub iog3cr: IOG3CR,
        ///0x40 - I/O group x counter register
        pub iog4cr: IOG4CR,
        ///0x44 - I/O group x counter register
        pub iog5cr: IOG5CR,
        ///0x48 - I/O group x counter register
        pub iog6cr: IOG6CR,
        ///0x4c - I/O group x counter register
        pub iog7cr: IOG7CR,
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CTPH`
        pub type CTPH_R = crate::R<u8, u8>;
        ///Write proxy for field `CTPH`
        pub struct CTPH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTPH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `CTPL`
        pub type CTPL_R = crate::R<u8, u8>;
        ///Write proxy for field `CTPL`
        pub struct CTPL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTPL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `SSD`
        pub type SSD_R = crate::R<u8, u8>;
        ///Write proxy for field `SSD`
        pub struct SSD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SSD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7f << 17)) | (((value as u32) & 0x7f) << 17);
                self.w
            }
        }
        ///Reader of field `SSE`
        pub type SSE_R = crate::R<bool, bool>;
        ///Write proxy for field `SSE`
        pub struct SSE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SSE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `SSPSC`
        pub type SSPSC_R = crate::R<bool, bool>;
        ///Write proxy for field `SSPSC`
        pub struct SSPSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SSPSC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PGPSC`
        pub type PGPSC_R = crate::R<u8, u8>;
        ///Write proxy for field `PGPSC`
        pub struct PGPSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PGPSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `MCV`
        pub type MCV_R = crate::R<u8, u8>;
        ///Write proxy for field `MCV`
        pub struct MCV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MCV_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5);
                self.w
            }
        }
        ///Reader of field `IODEF`
        pub type IODEF_R = crate::R<bool, bool>;
        ///Write proxy for field `IODEF`
        pub struct IODEF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IODEF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `SYNCPOL`
        pub type SYNCPOL_R = crate::R<bool, bool>;
        ///Write proxy for field `SYNCPOL`
        pub struct SYNCPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCPOL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `AM`
        pub type AM_R = crate::R<bool, bool>;
        ///Write proxy for field `AM`
        pub struct AM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `START`
        pub type START_R = crate::R<bool, bool>;
        ///Write proxy for field `START`
        pub struct START_W<'a> {
            w: &'a mut W,
        }
        impl<'a> START_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `TSCE`
        pub type TSCE_R = crate::R<bool, bool>;
        ///Write proxy for field `TSCE`
        pub struct TSCE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSCE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Charge transfer pulse high
            #[inline(always)]
            pub fn ctph(&self) -> CTPH_R {
                CTPH_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Charge transfer pulse low
            #[inline(always)]
            pub fn ctpl(&self) -> CTPL_R {
                CTPL_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 17:23 - Spread spectrum deviation
            #[inline(always)]
            pub fn ssd(&self) -> SSD_R {
                SSD_R::new(((self.bits >> 17) & 0x7f) as u8)
            }
            ///Bit 16 - Spread spectrum enable
            #[inline(always)]
            pub fn sse(&self) -> SSE_R {
                SSE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Spread spectrum prescaler
            #[inline(always)]
            pub fn sspsc(&self) -> SSPSC_R {
                SSPSC_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 12:14 - pulse generator prescaler
            #[inline(always)]
            pub fn pgpsc(&self) -> PGPSC_R {
                PGPSC_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 5:7 - Max count value
            #[inline(always)]
            pub fn mcv(&self) -> MCV_R {
                MCV_R::new(((self.bits >> 5) & 0x07) as u8)
            }
            ///Bit 4 - I/O Default mode
            #[inline(always)]
            pub fn iodef(&self) -> IODEF_R {
                IODEF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Synchronization pin polarity
            #[inline(always)]
            pub fn syncpol(&self) -> SYNCPOL_R {
                SYNCPOL_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Acquisition mode
            #[inline(always)]
            pub fn am(&self) -> AM_R {
                AM_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Start a new acquisition
            #[inline(always)]
            pub fn start(&self) -> START_R {
                START_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Touch sensing controller enable
            #[inline(always)]
            pub fn tsce(&self) -> TSCE_R {
                TSCE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 28:31 - Charge transfer pulse high
            #[inline(always)]
            pub fn ctph(&mut self) -> CTPH_W {
                CTPH_W { w: self }
            }
            ///Bits 24:27 - Charge transfer pulse low
            #[inline(always)]
            pub fn ctpl(&mut self) -> CTPL_W {
                CTPL_W { w: self }
            }
            ///Bits 17:23 - Spread spectrum deviation
            #[inline(always)]
            pub fn ssd(&mut self) -> SSD_W {
                SSD_W { w: self }
            }
            ///Bit 16 - Spread spectrum enable
            #[inline(always)]
            pub fn sse(&mut self) -> SSE_W {
                SSE_W { w: self }
            }
            ///Bit 15 - Spread spectrum prescaler
            #[inline(always)]
            pub fn sspsc(&mut self) -> SSPSC_W {
                SSPSC_W { w: self }
            }
            ///Bits 12:14 - pulse generator prescaler
            #[inline(always)]
            pub fn pgpsc(&mut self) -> PGPSC_W {
                PGPSC_W { w: self }
            }
            ///Bits 5:7 - Max count value
            #[inline(always)]
            pub fn mcv(&mut self) -> MCV_W {
                MCV_W { w: self }
            }
            ///Bit 4 - I/O Default mode
            #[inline(always)]
            pub fn iodef(&mut self) -> IODEF_W {
                IODEF_W { w: self }
            }
            ///Bit 3 - Synchronization pin polarity
            #[inline(always)]
            pub fn syncpol(&mut self) -> SYNCPOL_W {
                SYNCPOL_W { w: self }
            }
            ///Bit 2 - Acquisition mode
            #[inline(always)]
            pub fn am(&mut self) -> AM_W {
                AM_W { w: self }
            }
            ///Bit 1 - Start a new acquisition
            #[inline(always)]
            pub fn start(&mut self) -> START_W {
                START_W { w: self }
            }
            ///Bit 0 - Touch sensing controller enable
            #[inline(always)]
            pub fn tsce(&mut self) -> TSCE_W {
                TSCE_W { w: self }
            }
        }
    }
    ///interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ier](ier) module
    pub type IER = crate::Reg<u32, _IER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IER;
    ///`read()` method returns [ier::R](ier::R) reader structure
    impl crate::Readable for IER {}
    ///`write(|w| ..)` method takes [ier::W](ier::W) writer structure
    impl crate::Writable for IER {}
    ///interrupt enable register
    pub mod ier {
        ///Reader of register IER
        pub type R = crate::R<u32, super::IER>;
        ///Writer for register IER
        pub type W = crate::W<u32, super::IER>;
        ///Register IER `reset()`'s with value 0
        impl crate::ResetValue for super::IER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MCEIE`
        pub type MCEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `MCEIE`
        pub struct MCEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MCEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EOAIE`
        pub type EOAIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EOAIE`
        pub struct EOAIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOAIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 1 - Max count error interrupt enable
            #[inline(always)]
            pub fn mceie(&self) -> MCEIE_R {
                MCEIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - End of acquisition interrupt enable
            #[inline(always)]
            pub fn eoaie(&self) -> EOAIE_R {
                EOAIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 1 - Max count error interrupt enable
            #[inline(always)]
            pub fn mceie(&mut self) -> MCEIE_W {
                MCEIE_W { w: self }
            }
            ///Bit 0 - End of acquisition interrupt enable
            #[inline(always)]
            pub fn eoaie(&mut self) -> EOAIE_W {
                EOAIE_W { w: self }
            }
        }
    }
    ///interrupt clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [icr](icr) module
    pub type ICR = crate::Reg<u32, _ICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ICR;
    ///`read()` method returns [icr::R](icr::R) reader structure
    impl crate::Readable for ICR {}
    ///`write(|w| ..)` method takes [icr::W](icr::W) writer structure
    impl crate::Writable for ICR {}
    ///interrupt clear register
    pub mod icr {
        ///Reader of register ICR
        pub type R = crate::R<u32, super::ICR>;
        ///Writer for register ICR
        pub type W = crate::W<u32, super::ICR>;
        ///Register ICR `reset()`'s with value 0
        impl crate::ResetValue for super::ICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MCEIC`
        pub type MCEIC_R = crate::R<bool, bool>;
        ///Write proxy for field `MCEIC`
        pub struct MCEIC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MCEIC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EOAIC`
        pub type EOAIC_R = crate::R<bool, bool>;
        ///Write proxy for field `EOAIC`
        pub struct EOAIC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOAIC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 1 - Max count error interrupt clear
            #[inline(always)]
            pub fn mceic(&self) -> MCEIC_R {
                MCEIC_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - End of acquisition interrupt clear
            #[inline(always)]
            pub fn eoaic(&self) -> EOAIC_R {
                EOAIC_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 1 - Max count error interrupt clear
            #[inline(always)]
            pub fn mceic(&mut self) -> MCEIC_W {
                MCEIC_W { w: self }
            }
            ///Bit 0 - End of acquisition interrupt clear
            #[inline(always)]
            pub fn eoaic(&mut self) -> EOAIC_W {
                EOAIC_W { w: self }
            }
        }
    }
    ///interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///`write(|w| ..)` method takes [isr::W](isr::W) writer structure
    impl crate::Writable for ISR {}
    ///interrupt status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Writer for register ISR
        pub type W = crate::W<u32, super::ISR>;
        ///Register ISR `reset()`'s with value 0
        impl crate::ResetValue for super::ISR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MCEF`
        pub type MCEF_R = crate::R<bool, bool>;
        ///Write proxy for field `MCEF`
        pub struct MCEF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MCEF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EOAF`
        pub type EOAF_R = crate::R<bool, bool>;
        ///Write proxy for field `EOAF`
        pub struct EOAF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOAF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 1 - Max count error flag
            #[inline(always)]
            pub fn mcef(&self) -> MCEF_R {
                MCEF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - End of acquisition flag
            #[inline(always)]
            pub fn eoaf(&self) -> EOAF_R {
                EOAF_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 1 - Max count error flag
            #[inline(always)]
            pub fn mcef(&mut self) -> MCEF_W {
                MCEF_W { w: self }
            }
            ///Bit 0 - End of acquisition flag
            #[inline(always)]
            pub fn eoaf(&mut self) -> EOAF_W {
                EOAF_W { w: self }
            }
        }
    }
    ///I/O hysteresis control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iohcr](iohcr) module
    pub type IOHCR = crate::Reg<u32, _IOHCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOHCR;
    ///`read()` method returns [iohcr::R](iohcr::R) reader structure
    impl crate::Readable for IOHCR {}
    ///`write(|w| ..)` method takes [iohcr::W](iohcr::W) writer structure
    impl crate::Writable for IOHCR {}
    ///I/O hysteresis control register
    pub mod iohcr {
        ///Reader of register IOHCR
        pub type R = crate::R<u32, super::IOHCR>;
        ///Writer for register IOHCR
        pub type W = crate::W<u32, super::IOHCR>;
        ///Register IOHCR `reset()`'s with value 0xffff_ffff
        impl crate::ResetValue for super::IOHCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_ffff
            }
        }
        ///Reader of field `G7_IO4`
        pub type G7_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO4`
        pub struct G7_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `G7_IO3`
        pub type G7_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO3`
        pub struct G7_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `G7_IO2`
        pub type G7_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO2`
        pub struct G7_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `G7_IO1`
        pub type G7_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO1`
        pub struct G7_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `G6_IO4`
        pub type G6_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO4`
        pub struct G6_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `G6_IO3`
        pub type G6_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO3`
        pub struct G6_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `G6_IO2`
        pub type G6_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO2`
        pub struct G6_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `G6_IO1`
        pub type G6_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO1`
        pub struct G6_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `G5_IO4`
        pub type G5_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO4`
        pub struct G5_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `G5_IO3`
        pub type G5_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO3`
        pub struct G5_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `G5_IO2`
        pub type G5_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO2`
        pub struct G5_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `G5_IO1`
        pub type G5_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO1`
        pub struct G5_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `G4_IO4`
        pub type G4_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO4`
        pub struct G4_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `G4_IO3`
        pub type G4_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO3`
        pub struct G4_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `G4_IO2`
        pub type G4_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO2`
        pub struct G4_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `G4_IO1`
        pub type G4_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO1`
        pub struct G4_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `G3_IO4`
        pub type G3_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO4`
        pub struct G3_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `G3_IO3`
        pub type G3_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO3`
        pub struct G3_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `G3_IO2`
        pub type G3_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO2`
        pub struct G3_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `G3_IO1`
        pub type G3_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO1`
        pub struct G3_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `G2_IO4`
        pub type G2_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO4`
        pub struct G2_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `G2_IO3`
        pub type G2_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO3`
        pub struct G2_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `G2_IO2`
        pub type G2_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO2`
        pub struct G2_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `G2_IO1`
        pub type G2_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO1`
        pub struct G2_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `G1_IO4`
        pub type G1_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO4`
        pub struct G1_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `G1_IO3`
        pub type G1_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO3`
        pub struct G1_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `G1_IO2`
        pub type G1_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO2`
        pub struct G1_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `G1_IO1`
        pub type G1_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO1`
        pub struct G1_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&self) -> G7_IO4_R {
                G7_IO4_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&self) -> G7_IO3_R {
                G7_IO3_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&self) -> G7_IO2_R {
                G7_IO2_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&self) -> G7_IO1_R {
                G7_IO1_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&self) -> G6_IO4_R {
                G6_IO4_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&self) -> G6_IO3_R {
                G6_IO3_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&self) -> G6_IO2_R {
                G6_IO2_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&self) -> G6_IO1_R {
                G6_IO1_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&self) -> G5_IO4_R {
                G5_IO4_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&self) -> G5_IO3_R {
                G5_IO3_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&self) -> G5_IO2_R {
                G5_IO2_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&self) -> G5_IO1_R {
                G5_IO1_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&self) -> G4_IO4_R {
                G4_IO4_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&self) -> G4_IO3_R {
                G4_IO3_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&self) -> G4_IO2_R {
                G4_IO2_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&self) -> G4_IO1_R {
                G4_IO1_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&self) -> G3_IO4_R {
                G3_IO4_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&self) -> G3_IO3_R {
                G3_IO3_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&self) -> G3_IO2_R {
                G3_IO2_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&self) -> G3_IO1_R {
                G3_IO1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&self) -> G2_IO4_R {
                G2_IO4_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&self) -> G2_IO3_R {
                G2_IO3_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&self) -> G2_IO2_R {
                G2_IO2_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&self) -> G2_IO1_R {
                G2_IO1_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&self) -> G1_IO4_R {
                G1_IO4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&self) -> G1_IO3_R {
                G1_IO3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&self) -> G1_IO2_R {
                G1_IO2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&self) -> G1_IO1_R {
                G1_IO1_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&mut self) -> G7_IO4_W {
                G7_IO4_W { w: self }
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&mut self) -> G7_IO3_W {
                G7_IO3_W { w: self }
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&mut self) -> G7_IO2_W {
                G7_IO2_W { w: self }
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&mut self) -> G7_IO1_W {
                G7_IO1_W { w: self }
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&mut self) -> G6_IO4_W {
                G6_IO4_W { w: self }
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&mut self) -> G6_IO3_W {
                G6_IO3_W { w: self }
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&mut self) -> G6_IO2_W {
                G6_IO2_W { w: self }
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&mut self) -> G6_IO1_W {
                G6_IO1_W { w: self }
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&mut self) -> G5_IO4_W {
                G5_IO4_W { w: self }
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&mut self) -> G5_IO3_W {
                G5_IO3_W { w: self }
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&mut self) -> G5_IO2_W {
                G5_IO2_W { w: self }
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&mut self) -> G5_IO1_W {
                G5_IO1_W { w: self }
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&mut self) -> G4_IO4_W {
                G4_IO4_W { w: self }
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&mut self) -> G4_IO3_W {
                G4_IO3_W { w: self }
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&mut self) -> G4_IO2_W {
                G4_IO2_W { w: self }
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&mut self) -> G4_IO1_W {
                G4_IO1_W { w: self }
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&mut self) -> G3_IO4_W {
                G3_IO4_W { w: self }
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&mut self) -> G3_IO3_W {
                G3_IO3_W { w: self }
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&mut self) -> G3_IO2_W {
                G3_IO2_W { w: self }
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&mut self) -> G3_IO1_W {
                G3_IO1_W { w: self }
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&mut self) -> G2_IO4_W {
                G2_IO4_W { w: self }
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&mut self) -> G2_IO3_W {
                G2_IO3_W { w: self }
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&mut self) -> G2_IO2_W {
                G2_IO2_W { w: self }
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&mut self) -> G2_IO1_W {
                G2_IO1_W { w: self }
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&mut self) -> G1_IO4_W {
                G1_IO4_W { w: self }
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&mut self) -> G1_IO3_W {
                G1_IO3_W { w: self }
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&mut self) -> G1_IO2_W {
                G1_IO2_W { w: self }
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&mut self) -> G1_IO1_W {
                G1_IO1_W { w: self }
            }
        }
    }
    ///I/O analog switch control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ioascr](ioascr) module
    pub type IOASCR = crate::Reg<u32, _IOASCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOASCR;
    ///`read()` method returns [ioascr::R](ioascr::R) reader structure
    impl crate::Readable for IOASCR {}
    ///`write(|w| ..)` method takes [ioascr::W](ioascr::W) writer structure
    impl crate::Writable for IOASCR {}
    ///I/O analog switch control register
    pub mod ioascr {
        ///Reader of register IOASCR
        pub type R = crate::R<u32, super::IOASCR>;
        ///Writer for register IOASCR
        pub type W = crate::W<u32, super::IOASCR>;
        ///Register IOASCR `reset()`'s with value 0
        impl crate::ResetValue for super::IOASCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `G7_IO4`
        pub type G7_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO4`
        pub struct G7_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `G7_IO3`
        pub type G7_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO3`
        pub struct G7_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `G7_IO2`
        pub type G7_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO2`
        pub struct G7_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `G7_IO1`
        pub type G7_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO1`
        pub struct G7_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `G6_IO4`
        pub type G6_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO4`
        pub struct G6_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `G6_IO3`
        pub type G6_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO3`
        pub struct G6_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `G6_IO2`
        pub type G6_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO2`
        pub struct G6_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `G6_IO1`
        pub type G6_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO1`
        pub struct G6_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `G5_IO4`
        pub type G5_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO4`
        pub struct G5_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `G5_IO3`
        pub type G5_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO3`
        pub struct G5_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `G5_IO2`
        pub type G5_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO2`
        pub struct G5_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `G5_IO1`
        pub type G5_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO1`
        pub struct G5_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `G4_IO4`
        pub type G4_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO4`
        pub struct G4_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `G4_IO3`
        pub type G4_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO3`
        pub struct G4_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `G4_IO2`
        pub type G4_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO2`
        pub struct G4_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `G4_IO1`
        pub type G4_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO1`
        pub struct G4_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `G3_IO4`
        pub type G3_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO4`
        pub struct G3_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `G3_IO3`
        pub type G3_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO3`
        pub struct G3_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `G3_IO2`
        pub type G3_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO2`
        pub struct G3_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `G3_IO1`
        pub type G3_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO1`
        pub struct G3_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `G2_IO4`
        pub type G2_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO4`
        pub struct G2_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `G2_IO3`
        pub type G2_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO3`
        pub struct G2_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `G2_IO2`
        pub type G2_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO2`
        pub struct G2_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `G2_IO1`
        pub type G2_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO1`
        pub struct G2_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `G1_IO4`
        pub type G1_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO4`
        pub struct G1_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `G1_IO3`
        pub type G1_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO3`
        pub struct G1_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `G1_IO2`
        pub type G1_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO2`
        pub struct G1_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `G1_IO1`
        pub type G1_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO1`
        pub struct G1_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&self) -> G7_IO4_R {
                G7_IO4_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&self) -> G7_IO3_R {
                G7_IO3_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&self) -> G7_IO2_R {
                G7_IO2_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&self) -> G7_IO1_R {
                G7_IO1_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&self) -> G6_IO4_R {
                G6_IO4_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&self) -> G6_IO3_R {
                G6_IO3_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&self) -> G6_IO2_R {
                G6_IO2_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&self) -> G6_IO1_R {
                G6_IO1_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&self) -> G5_IO4_R {
                G5_IO4_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&self) -> G5_IO3_R {
                G5_IO3_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&self) -> G5_IO2_R {
                G5_IO2_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&self) -> G5_IO1_R {
                G5_IO1_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&self) -> G4_IO4_R {
                G4_IO4_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&self) -> G4_IO3_R {
                G4_IO3_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&self) -> G4_IO2_R {
                G4_IO2_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&self) -> G4_IO1_R {
                G4_IO1_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&self) -> G3_IO4_R {
                G3_IO4_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&self) -> G3_IO3_R {
                G3_IO3_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&self) -> G3_IO2_R {
                G3_IO2_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&self) -> G3_IO1_R {
                G3_IO1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&self) -> G2_IO4_R {
                G2_IO4_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&self) -> G2_IO3_R {
                G2_IO3_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&self) -> G2_IO2_R {
                G2_IO2_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&self) -> G2_IO1_R {
                G2_IO1_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&self) -> G1_IO4_R {
                G1_IO4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&self) -> G1_IO3_R {
                G1_IO3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&self) -> G1_IO2_R {
                G1_IO2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&self) -> G1_IO1_R {
                G1_IO1_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&mut self) -> G7_IO4_W {
                G7_IO4_W { w: self }
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&mut self) -> G7_IO3_W {
                G7_IO3_W { w: self }
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&mut self) -> G7_IO2_W {
                G7_IO2_W { w: self }
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&mut self) -> G7_IO1_W {
                G7_IO1_W { w: self }
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&mut self) -> G6_IO4_W {
                G6_IO4_W { w: self }
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&mut self) -> G6_IO3_W {
                G6_IO3_W { w: self }
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&mut self) -> G6_IO2_W {
                G6_IO2_W { w: self }
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&mut self) -> G6_IO1_W {
                G6_IO1_W { w: self }
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&mut self) -> G5_IO4_W {
                G5_IO4_W { w: self }
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&mut self) -> G5_IO3_W {
                G5_IO3_W { w: self }
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&mut self) -> G5_IO2_W {
                G5_IO2_W { w: self }
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&mut self) -> G5_IO1_W {
                G5_IO1_W { w: self }
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&mut self) -> G4_IO4_W {
                G4_IO4_W { w: self }
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&mut self) -> G4_IO3_W {
                G4_IO3_W { w: self }
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&mut self) -> G4_IO2_W {
                G4_IO2_W { w: self }
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&mut self) -> G4_IO1_W {
                G4_IO1_W { w: self }
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&mut self) -> G3_IO4_W {
                G3_IO4_W { w: self }
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&mut self) -> G3_IO3_W {
                G3_IO3_W { w: self }
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&mut self) -> G3_IO2_W {
                G3_IO2_W { w: self }
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&mut self) -> G3_IO1_W {
                G3_IO1_W { w: self }
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&mut self) -> G2_IO4_W {
                G2_IO4_W { w: self }
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&mut self) -> G2_IO3_W {
                G2_IO3_W { w: self }
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&mut self) -> G2_IO2_W {
                G2_IO2_W { w: self }
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&mut self) -> G2_IO1_W {
                G2_IO1_W { w: self }
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&mut self) -> G1_IO4_W {
                G1_IO4_W { w: self }
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&mut self) -> G1_IO3_W {
                G1_IO3_W { w: self }
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&mut self) -> G1_IO2_W {
                G1_IO2_W { w: self }
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&mut self) -> G1_IO1_W {
                G1_IO1_W { w: self }
            }
        }
    }
    ///I/O sampling control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ioscr](ioscr) module
    pub type IOSCR = crate::Reg<u32, _IOSCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOSCR;
    ///`read()` method returns [ioscr::R](ioscr::R) reader structure
    impl crate::Readable for IOSCR {}
    ///`write(|w| ..)` method takes [ioscr::W](ioscr::W) writer structure
    impl crate::Writable for IOSCR {}
    ///I/O sampling control register
    pub mod ioscr {
        ///Reader of register IOSCR
        pub type R = crate::R<u32, super::IOSCR>;
        ///Writer for register IOSCR
        pub type W = crate::W<u32, super::IOSCR>;
        ///Register IOSCR `reset()`'s with value 0
        impl crate::ResetValue for super::IOSCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `G7_IO4`
        pub type G7_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO4`
        pub struct G7_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `G7_IO3`
        pub type G7_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO3`
        pub struct G7_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `G7_IO2`
        pub type G7_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO2`
        pub struct G7_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `G7_IO1`
        pub type G7_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO1`
        pub struct G7_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `G6_IO4`
        pub type G6_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO4`
        pub struct G6_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `G6_IO3`
        pub type G6_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO3`
        pub struct G6_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `G6_IO2`
        pub type G6_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO2`
        pub struct G6_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `G6_IO1`
        pub type G6_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO1`
        pub struct G6_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `G5_IO4`
        pub type G5_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO4`
        pub struct G5_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `G5_IO3`
        pub type G5_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO3`
        pub struct G5_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `G5_IO2`
        pub type G5_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO2`
        pub struct G5_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `G5_IO1`
        pub type G5_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO1`
        pub struct G5_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `G4_IO4`
        pub type G4_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO4`
        pub struct G4_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `G4_IO3`
        pub type G4_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO3`
        pub struct G4_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `G4_IO2`
        pub type G4_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO2`
        pub struct G4_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `G4_IO1`
        pub type G4_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO1`
        pub struct G4_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `G3_IO4`
        pub type G3_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO4`
        pub struct G3_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `G3_IO3`
        pub type G3_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO3`
        pub struct G3_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `G3_IO2`
        pub type G3_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO2`
        pub struct G3_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `G3_IO1`
        pub type G3_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO1`
        pub struct G3_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `G2_IO4`
        pub type G2_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO4`
        pub struct G2_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `G2_IO3`
        pub type G2_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO3`
        pub struct G2_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `G2_IO2`
        pub type G2_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO2`
        pub struct G2_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `G2_IO1`
        pub type G2_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO1`
        pub struct G2_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `G1_IO4`
        pub type G1_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO4`
        pub struct G1_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `G1_IO3`
        pub type G1_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO3`
        pub struct G1_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `G1_IO2`
        pub type G1_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO2`
        pub struct G1_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `G1_IO1`
        pub type G1_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO1`
        pub struct G1_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&self) -> G7_IO4_R {
                G7_IO4_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&self) -> G7_IO3_R {
                G7_IO3_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&self) -> G7_IO2_R {
                G7_IO2_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&self) -> G7_IO1_R {
                G7_IO1_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&self) -> G6_IO4_R {
                G6_IO4_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&self) -> G6_IO3_R {
                G6_IO3_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&self) -> G6_IO2_R {
                G6_IO2_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&self) -> G6_IO1_R {
                G6_IO1_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&self) -> G5_IO4_R {
                G5_IO4_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&self) -> G5_IO3_R {
                G5_IO3_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&self) -> G5_IO2_R {
                G5_IO2_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&self) -> G5_IO1_R {
                G5_IO1_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&self) -> G4_IO4_R {
                G4_IO4_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&self) -> G4_IO3_R {
                G4_IO3_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&self) -> G4_IO2_R {
                G4_IO2_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&self) -> G4_IO1_R {
                G4_IO1_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&self) -> G3_IO4_R {
                G3_IO4_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&self) -> G3_IO3_R {
                G3_IO3_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&self) -> G3_IO2_R {
                G3_IO2_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&self) -> G3_IO1_R {
                G3_IO1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&self) -> G2_IO4_R {
                G2_IO4_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&self) -> G2_IO3_R {
                G2_IO3_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&self) -> G2_IO2_R {
                G2_IO2_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&self) -> G2_IO1_R {
                G2_IO1_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&self) -> G1_IO4_R {
                G1_IO4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&self) -> G1_IO3_R {
                G1_IO3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&self) -> G1_IO2_R {
                G1_IO2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&self) -> G1_IO1_R {
                G1_IO1_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&mut self) -> G7_IO4_W {
                G7_IO4_W { w: self }
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&mut self) -> G7_IO3_W {
                G7_IO3_W { w: self }
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&mut self) -> G7_IO2_W {
                G7_IO2_W { w: self }
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&mut self) -> G7_IO1_W {
                G7_IO1_W { w: self }
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&mut self) -> G6_IO4_W {
                G6_IO4_W { w: self }
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&mut self) -> G6_IO3_W {
                G6_IO3_W { w: self }
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&mut self) -> G6_IO2_W {
                G6_IO2_W { w: self }
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&mut self) -> G6_IO1_W {
                G6_IO1_W { w: self }
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&mut self) -> G5_IO4_W {
                G5_IO4_W { w: self }
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&mut self) -> G5_IO3_W {
                G5_IO3_W { w: self }
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&mut self) -> G5_IO2_W {
                G5_IO2_W { w: self }
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&mut self) -> G5_IO1_W {
                G5_IO1_W { w: self }
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&mut self) -> G4_IO4_W {
                G4_IO4_W { w: self }
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&mut self) -> G4_IO3_W {
                G4_IO3_W { w: self }
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&mut self) -> G4_IO2_W {
                G4_IO2_W { w: self }
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&mut self) -> G4_IO1_W {
                G4_IO1_W { w: self }
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&mut self) -> G3_IO4_W {
                G3_IO4_W { w: self }
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&mut self) -> G3_IO3_W {
                G3_IO3_W { w: self }
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&mut self) -> G3_IO2_W {
                G3_IO2_W { w: self }
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&mut self) -> G3_IO1_W {
                G3_IO1_W { w: self }
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&mut self) -> G2_IO4_W {
                G2_IO4_W { w: self }
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&mut self) -> G2_IO3_W {
                G2_IO3_W { w: self }
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&mut self) -> G2_IO2_W {
                G2_IO2_W { w: self }
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&mut self) -> G2_IO1_W {
                G2_IO1_W { w: self }
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&mut self) -> G1_IO4_W {
                G1_IO4_W { w: self }
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&mut self) -> G1_IO3_W {
                G1_IO3_W { w: self }
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&mut self) -> G1_IO2_W {
                G1_IO2_W { w: self }
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&mut self) -> G1_IO1_W {
                G1_IO1_W { w: self }
            }
        }
    }
    ///I/O channel control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ioccr](ioccr) module
    pub type IOCCR = crate::Reg<u32, _IOCCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOCCR;
    ///`read()` method returns [ioccr::R](ioccr::R) reader structure
    impl crate::Readable for IOCCR {}
    ///`write(|w| ..)` method takes [ioccr::W](ioccr::W) writer structure
    impl crate::Writable for IOCCR {}
    ///I/O channel control register
    pub mod ioccr {
        ///Reader of register IOCCR
        pub type R = crate::R<u32, super::IOCCR>;
        ///Writer for register IOCCR
        pub type W = crate::W<u32, super::IOCCR>;
        ///Register IOCCR `reset()`'s with value 0
        impl crate::ResetValue for super::IOCCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `G7_IO4`
        pub type G7_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO4`
        pub struct G7_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `G7_IO3`
        pub type G7_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO3`
        pub struct G7_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `G7_IO2`
        pub type G7_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO2`
        pub struct G7_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `G7_IO1`
        pub type G7_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G7_IO1`
        pub struct G7_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `G6_IO4`
        pub type G6_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO4`
        pub struct G6_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `G6_IO3`
        pub type G6_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO3`
        pub struct G6_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `G6_IO2`
        pub type G6_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO2`
        pub struct G6_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `G6_IO1`
        pub type G6_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G6_IO1`
        pub struct G6_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `G5_IO4`
        pub type G5_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO4`
        pub struct G5_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `G5_IO3`
        pub type G5_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO3`
        pub struct G5_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `G5_IO2`
        pub type G5_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO2`
        pub struct G5_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `G5_IO1`
        pub type G5_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G5_IO1`
        pub struct G5_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `G4_IO4`
        pub type G4_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO4`
        pub struct G4_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `G4_IO3`
        pub type G4_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO3`
        pub struct G4_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `G4_IO2`
        pub type G4_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO2`
        pub struct G4_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `G4_IO1`
        pub type G4_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G4_IO1`
        pub struct G4_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `G3_IO4`
        pub type G3_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO4`
        pub struct G3_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `G3_IO3`
        pub type G3_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO3`
        pub struct G3_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `G3_IO2`
        pub type G3_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO2`
        pub struct G3_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `G3_IO1`
        pub type G3_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G3_IO1`
        pub struct G3_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `G2_IO4`
        pub type G2_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO4`
        pub struct G2_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `G2_IO3`
        pub type G2_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO3`
        pub struct G2_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `G2_IO2`
        pub type G2_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO2`
        pub struct G2_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `G2_IO1`
        pub type G2_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G2_IO1`
        pub struct G2_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `G1_IO4`
        pub type G1_IO4_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO4`
        pub struct G1_IO4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `G1_IO3`
        pub type G1_IO3_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO3`
        pub struct G1_IO3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `G1_IO2`
        pub type G1_IO2_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO2`
        pub struct G1_IO2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `G1_IO1`
        pub type G1_IO1_R = crate::R<bool, bool>;
        ///Write proxy for field `G1_IO1`
        pub struct G1_IO1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1_IO1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&self) -> G7_IO4_R {
                G7_IO4_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&self) -> G7_IO3_R {
                G7_IO3_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&self) -> G7_IO2_R {
                G7_IO2_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&self) -> G7_IO1_R {
                G7_IO1_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&self) -> G6_IO4_R {
                G6_IO4_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&self) -> G6_IO3_R {
                G6_IO3_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&self) -> G6_IO2_R {
                G6_IO2_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&self) -> G6_IO1_R {
                G6_IO1_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&self) -> G5_IO4_R {
                G5_IO4_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&self) -> G5_IO3_R {
                G5_IO3_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&self) -> G5_IO2_R {
                G5_IO2_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&self) -> G5_IO1_R {
                G5_IO1_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&self) -> G4_IO4_R {
                G4_IO4_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&self) -> G4_IO3_R {
                G4_IO3_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&self) -> G4_IO2_R {
                G4_IO2_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&self) -> G4_IO1_R {
                G4_IO1_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&self) -> G3_IO4_R {
                G3_IO4_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&self) -> G3_IO3_R {
                G3_IO3_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&self) -> G3_IO2_R {
                G3_IO2_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&self) -> G3_IO1_R {
                G3_IO1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&self) -> G2_IO4_R {
                G2_IO4_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&self) -> G2_IO3_R {
                G2_IO3_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&self) -> G2_IO2_R {
                G2_IO2_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&self) -> G2_IO1_R {
                G2_IO1_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&self) -> G1_IO4_R {
                G1_IO4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&self) -> G1_IO3_R {
                G1_IO3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&self) -> G1_IO2_R {
                G1_IO2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&self) -> G1_IO1_R {
                G1_IO1_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 27 - G7_IO4
            #[inline(always)]
            pub fn g7_io4(&mut self) -> G7_IO4_W {
                G7_IO4_W { w: self }
            }
            ///Bit 26 - G7_IO3
            #[inline(always)]
            pub fn g7_io3(&mut self) -> G7_IO3_W {
                G7_IO3_W { w: self }
            }
            ///Bit 25 - G7_IO2
            #[inline(always)]
            pub fn g7_io2(&mut self) -> G7_IO2_W {
                G7_IO2_W { w: self }
            }
            ///Bit 24 - G7_IO1
            #[inline(always)]
            pub fn g7_io1(&mut self) -> G7_IO1_W {
                G7_IO1_W { w: self }
            }
            ///Bit 23 - G6_IO4
            #[inline(always)]
            pub fn g6_io4(&mut self) -> G6_IO4_W {
                G6_IO4_W { w: self }
            }
            ///Bit 22 - G6_IO3
            #[inline(always)]
            pub fn g6_io3(&mut self) -> G6_IO3_W {
                G6_IO3_W { w: self }
            }
            ///Bit 21 - G6_IO2
            #[inline(always)]
            pub fn g6_io2(&mut self) -> G6_IO2_W {
                G6_IO2_W { w: self }
            }
            ///Bit 20 - G6_IO1
            #[inline(always)]
            pub fn g6_io1(&mut self) -> G6_IO1_W {
                G6_IO1_W { w: self }
            }
            ///Bit 19 - G5_IO4
            #[inline(always)]
            pub fn g5_io4(&mut self) -> G5_IO4_W {
                G5_IO4_W { w: self }
            }
            ///Bit 18 - G5_IO3
            #[inline(always)]
            pub fn g5_io3(&mut self) -> G5_IO3_W {
                G5_IO3_W { w: self }
            }
            ///Bit 17 - G5_IO2
            #[inline(always)]
            pub fn g5_io2(&mut self) -> G5_IO2_W {
                G5_IO2_W { w: self }
            }
            ///Bit 16 - G5_IO1
            #[inline(always)]
            pub fn g5_io1(&mut self) -> G5_IO1_W {
                G5_IO1_W { w: self }
            }
            ///Bit 15 - G4_IO4
            #[inline(always)]
            pub fn g4_io4(&mut self) -> G4_IO4_W {
                G4_IO4_W { w: self }
            }
            ///Bit 14 - G4_IO3
            #[inline(always)]
            pub fn g4_io3(&mut self) -> G4_IO3_W {
                G4_IO3_W { w: self }
            }
            ///Bit 13 - G4_IO2
            #[inline(always)]
            pub fn g4_io2(&mut self) -> G4_IO2_W {
                G4_IO2_W { w: self }
            }
            ///Bit 12 - G4_IO1
            #[inline(always)]
            pub fn g4_io1(&mut self) -> G4_IO1_W {
                G4_IO1_W { w: self }
            }
            ///Bit 11 - G3_IO4
            #[inline(always)]
            pub fn g3_io4(&mut self) -> G3_IO4_W {
                G3_IO4_W { w: self }
            }
            ///Bit 10 - G3_IO3
            #[inline(always)]
            pub fn g3_io3(&mut self) -> G3_IO3_W {
                G3_IO3_W { w: self }
            }
            ///Bit 9 - G3_IO2
            #[inline(always)]
            pub fn g3_io2(&mut self) -> G3_IO2_W {
                G3_IO2_W { w: self }
            }
            ///Bit 8 - G3_IO1
            #[inline(always)]
            pub fn g3_io1(&mut self) -> G3_IO1_W {
                G3_IO1_W { w: self }
            }
            ///Bit 7 - G2_IO4
            #[inline(always)]
            pub fn g2_io4(&mut self) -> G2_IO4_W {
                G2_IO4_W { w: self }
            }
            ///Bit 6 - G2_IO3
            #[inline(always)]
            pub fn g2_io3(&mut self) -> G2_IO3_W {
                G2_IO3_W { w: self }
            }
            ///Bit 5 - G2_IO2
            #[inline(always)]
            pub fn g2_io2(&mut self) -> G2_IO2_W {
                G2_IO2_W { w: self }
            }
            ///Bit 4 - G2_IO1
            #[inline(always)]
            pub fn g2_io1(&mut self) -> G2_IO1_W {
                G2_IO1_W { w: self }
            }
            ///Bit 3 - G1_IO4
            #[inline(always)]
            pub fn g1_io4(&mut self) -> G1_IO4_W {
                G1_IO4_W { w: self }
            }
            ///Bit 2 - G1_IO3
            #[inline(always)]
            pub fn g1_io3(&mut self) -> G1_IO3_W {
                G1_IO3_W { w: self }
            }
            ///Bit 1 - G1_IO2
            #[inline(always)]
            pub fn g1_io2(&mut self) -> G1_IO2_W {
                G1_IO2_W { w: self }
            }
            ///Bit 0 - G1_IO1
            #[inline(always)]
            pub fn g1_io1(&mut self) -> G1_IO1_W {
                G1_IO1_W { w: self }
            }
        }
    }
    ///I/O group control status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iogcsr](iogcsr) module
    pub type IOGCSR = crate::Reg<u32, _IOGCSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOGCSR;
    ///`read()` method returns [iogcsr::R](iogcsr::R) reader structure
    impl crate::Readable for IOGCSR {}
    ///`write(|w| ..)` method takes [iogcsr::W](iogcsr::W) writer structure
    impl crate::Writable for IOGCSR {}
    ///I/O group control status register
    pub mod iogcsr {
        ///Reader of register IOGCSR
        pub type R = crate::R<u32, super::IOGCSR>;
        ///Writer for register IOGCSR
        pub type W = crate::W<u32, super::IOGCSR>;
        ///Register IOGCSR `reset()`'s with value 0
        impl crate::ResetValue for super::IOGCSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `G7S`
        pub type G7S_R = crate::R<bool, bool>;
        ///Reader of field `G6S`
        pub type G6S_R = crate::R<bool, bool>;
        ///Reader of field `G5S`
        pub type G5S_R = crate::R<bool, bool>;
        ///Reader of field `G4S`
        pub type G4S_R = crate::R<bool, bool>;
        ///Reader of field `G3S`
        pub type G3S_R = crate::R<bool, bool>;
        ///Reader of field `G2S`
        pub type G2S_R = crate::R<bool, bool>;
        ///Reader of field `G1S`
        pub type G1S_R = crate::R<bool, bool>;
        ///Reader of field `G7E`
        pub type G7E_R = crate::R<bool, bool>;
        ///Write proxy for field `G7E`
        pub struct G7E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G7E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `G6E`
        pub type G6E_R = crate::R<bool, bool>;
        ///Write proxy for field `G6E`
        pub struct G6E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G6E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `G5E`
        pub type G5E_R = crate::R<bool, bool>;
        ///Write proxy for field `G5E`
        pub struct G5E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G5E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `G4E`
        pub type G4E_R = crate::R<bool, bool>;
        ///Write proxy for field `G4E`
        pub struct G4E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G4E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `G3E`
        pub type G3E_R = crate::R<bool, bool>;
        ///Write proxy for field `G3E`
        pub struct G3E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G3E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `G2E`
        pub type G2E_R = crate::R<bool, bool>;
        ///Write proxy for field `G2E`
        pub struct G2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `G1E`
        pub type G1E_R = crate::R<bool, bool>;
        ///Write proxy for field `G1E`
        pub struct G1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> G1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 22 - Analog I/O group x status
            #[inline(always)]
            pub fn g7s(&self) -> G7S_R {
                G7S_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - Analog I/O group x status
            #[inline(always)]
            pub fn g6s(&self) -> G6S_R {
                G6S_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - Analog I/O group x status
            #[inline(always)]
            pub fn g5s(&self) -> G5S_R {
                G5S_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Analog I/O group x status
            #[inline(always)]
            pub fn g4s(&self) -> G4S_R {
                G4S_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - Analog I/O group x status
            #[inline(always)]
            pub fn g3s(&self) -> G3S_R {
                G3S_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - Analog I/O group x status
            #[inline(always)]
            pub fn g2s(&self) -> G2S_R {
                G2S_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - Analog I/O group x status
            #[inline(always)]
            pub fn g1s(&self) -> G1S_R {
                G1S_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 6 - Analog I/O group x enable
            #[inline(always)]
            pub fn g7e(&self) -> G7E_R {
                G7E_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Analog I/O group x enable
            #[inline(always)]
            pub fn g6e(&self) -> G6E_R {
                G6E_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Analog I/O group x enable
            #[inline(always)]
            pub fn g5e(&self) -> G5E_R {
                G5E_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Analog I/O group x enable
            #[inline(always)]
            pub fn g4e(&self) -> G4E_R {
                G4E_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Analog I/O group x enable
            #[inline(always)]
            pub fn g3e(&self) -> G3E_R {
                G3E_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Analog I/O group x enable
            #[inline(always)]
            pub fn g2e(&self) -> G2E_R {
                G2E_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Analog I/O group x enable
            #[inline(always)]
            pub fn g1e(&self) -> G1E_R {
                G1E_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 6 - Analog I/O group x enable
            #[inline(always)]
            pub fn g7e(&mut self) -> G7E_W {
                G7E_W { w: self }
            }
            ///Bit 5 - Analog I/O group x enable
            #[inline(always)]
            pub fn g6e(&mut self) -> G6E_W {
                G6E_W { w: self }
            }
            ///Bit 4 - Analog I/O group x enable
            #[inline(always)]
            pub fn g5e(&mut self) -> G5E_W {
                G5E_W { w: self }
            }
            ///Bit 3 - Analog I/O group x enable
            #[inline(always)]
            pub fn g4e(&mut self) -> G4E_W {
                G4E_W { w: self }
            }
            ///Bit 2 - Analog I/O group x enable
            #[inline(always)]
            pub fn g3e(&mut self) -> G3E_W {
                G3E_W { w: self }
            }
            ///Bit 1 - Analog I/O group x enable
            #[inline(always)]
            pub fn g2e(&mut self) -> G2E_W {
                G2E_W { w: self }
            }
            ///Bit 0 - Analog I/O group x enable
            #[inline(always)]
            pub fn g1e(&mut self) -> G1E_W {
                G1E_W { w: self }
            }
        }
    }
    ///I/O group x counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iog1cr](iog1cr) module
    pub type IOG1CR = crate::Reg<u32, _IOG1CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOG1CR;
    ///`read()` method returns [iog1cr::R](iog1cr::R) reader structure
    impl crate::Readable for IOG1CR {}
    ///I/O group x counter register
    pub mod iog1cr {
        ///Reader of register IOG1CR
        pub type R = crate::R<u32, super::IOG1CR>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:13 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0x3fff) as u16)
            }
        }
    }
    ///I/O group x counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iog2cr](iog2cr) module
    pub type IOG2CR = crate::Reg<u32, _IOG2CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOG2CR;
    ///`read()` method returns [iog2cr::R](iog2cr::R) reader structure
    impl crate::Readable for IOG2CR {}
    ///I/O group x counter register
    pub mod iog2cr {
        ///Reader of register IOG2CR
        pub type R = crate::R<u32, super::IOG2CR>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:13 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0x3fff) as u16)
            }
        }
    }
    ///I/O group x counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iog3cr](iog3cr) module
    pub type IOG3CR = crate::Reg<u32, _IOG3CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOG3CR;
    ///`read()` method returns [iog3cr::R](iog3cr::R) reader structure
    impl crate::Readable for IOG3CR {}
    ///I/O group x counter register
    pub mod iog3cr {
        ///Reader of register IOG3CR
        pub type R = crate::R<u32, super::IOG3CR>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:13 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0x3fff) as u16)
            }
        }
    }
    ///I/O group x counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iog4cr](iog4cr) module
    pub type IOG4CR = crate::Reg<u32, _IOG4CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOG4CR;
    ///`read()` method returns [iog4cr::R](iog4cr::R) reader structure
    impl crate::Readable for IOG4CR {}
    ///I/O group x counter register
    pub mod iog4cr {
        ///Reader of register IOG4CR
        pub type R = crate::R<u32, super::IOG4CR>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:13 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0x3fff) as u16)
            }
        }
    }
    ///I/O group x counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iog5cr](iog5cr) module
    pub type IOG5CR = crate::Reg<u32, _IOG5CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOG5CR;
    ///`read()` method returns [iog5cr::R](iog5cr::R) reader structure
    impl crate::Readable for IOG5CR {}
    ///I/O group x counter register
    pub mod iog5cr {
        ///Reader of register IOG5CR
        pub type R = crate::R<u32, super::IOG5CR>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:13 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0x3fff) as u16)
            }
        }
    }
    ///I/O group x counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iog6cr](iog6cr) module
    pub type IOG6CR = crate::Reg<u32, _IOG6CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOG6CR;
    ///`read()` method returns [iog6cr::R](iog6cr::R) reader structure
    impl crate::Readable for IOG6CR {}
    ///I/O group x counter register
    pub mod iog6cr {
        ///Reader of register IOG6CR
        pub type R = crate::R<u32, super::IOG6CR>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:13 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0x3fff) as u16)
            }
        }
    }
    ///I/O group x counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [iog7cr](iog7cr) module
    pub type IOG7CR = crate::Reg<u32, _IOG7CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IOG7CR;
    ///`read()` method returns [iog7cr::R](iog7cr::R) reader structure
    impl crate::Readable for IOG7CR {}
    ///I/O group x counter register
    pub mod iog7cr {
        ///Reader of register IOG7CR
        pub type R = crate::R<u32, super::IOG7CR>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:13 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0x3fff) as u16)
            }
        }
    }
}
///Independent watchdog
pub struct IWDG {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for IWDG {}
impl IWDG {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const iwdg::RegisterBlock {
        0x4000_3000 as *const _
    }
}
impl Deref for IWDG {
    type Target = iwdg::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*IWDG::ptr() }
    }
}
///Independent watchdog
pub mod iwdg {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Key register
        pub kr: KR,
        ///0x04 - Prescaler register
        pub pr: PR,
        ///0x08 - Reload register
        pub rlr: RLR,
        ///0x0c - Status register
        pub sr: SR,
        ///0x10 - Window register
        pub winr: WINR,
    }
    ///Key register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [kr](kr) module
    pub type KR = crate::Reg<u32, _KR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KR;
    ///`write(|w| ..)` method takes [kr::W](kr::W) writer structure
    impl crate::Writable for KR {}
    ///Key register
    pub mod kr {
        ///Writer for register KR
        pub type W = crate::W<u32, super::KR>;
        ///Register KR `reset()`'s with value 0
        impl crate::ResetValue for super::KR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `KEY`
        pub struct KEY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl W {
            ///Bits 0:15 - Key value (write only, read 0x0000)
            #[inline(always)]
            pub fn key(&mut self) -> KEY_W {
                KEY_W { w: self }
            }
        }
    }
    ///Prescaler register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pr](pr) module
    pub type PR = crate::Reg<u32, _PR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PR;
    ///`read()` method returns [pr::R](pr::R) reader structure
    impl crate::Readable for PR {}
    ///`write(|w| ..)` method takes [pr::W](pr::W) writer structure
    impl crate::Writable for PR {}
    ///Prescaler register
    pub mod pr {
        ///Reader of register PR
        pub type R = crate::R<u32, super::PR>;
        ///Writer for register PR
        pub type W = crate::W<u32, super::PR>;
        ///Register PR `reset()`'s with value 0
        impl crate::ResetValue for super::PR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PR`
        pub type PR_R = crate::R<u8, u8>;
        ///Write proxy for field `PR`
        pub struct PR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 0:2 - Prescaler divider
            #[inline(always)]
            pub fn pr(&self) -> PR_R {
                PR_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 0:2 - Prescaler divider
            #[inline(always)]
            pub fn pr(&mut self) -> PR_W {
                PR_W { w: self }
            }
        }
    }
    ///Reload register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr](rlr) module
    pub type RLR = crate::Reg<u32, _RLR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR;
    ///`read()` method returns [rlr::R](rlr::R) reader structure
    impl crate::Readable for RLR {}
    ///`write(|w| ..)` method takes [rlr::W](rlr::W) writer structure
    impl crate::Writable for RLR {}
    ///Reload register
    pub mod rlr {
        ///Reader of register RLR
        pub type R = crate::R<u32, super::RLR>;
        ///Writer for register RLR
        pub type W = crate::W<u32, super::RLR>;
        ///Register RLR `reset()`'s with value 0x0fff
        impl crate::ResetValue for super::RLR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0fff
            }
        }
        ///Reader of field `RL`
        pub type RL_R = crate::R<u16, u16>;
        ///Write proxy for field `RL`
        pub struct RL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        impl R {
            ///Bits 0:11 - Watchdog counter reload value
            #[inline(always)]
            pub fn rl(&self) -> RL_R {
                RL_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            ///Bits 0:11 - Watchdog counter reload value
            #[inline(always)]
            pub fn rl(&mut self) -> RL_W {
                RL_W { w: self }
            }
        }
    }
    ///Status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///Status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Reader of field `WVU`
        pub type WVU_R = crate::R<bool, bool>;
        ///Reader of field `RVU`
        pub type RVU_R = crate::R<bool, bool>;
        ///Reader of field `PVU`
        pub type PVU_R = crate::R<bool, bool>;
        impl R {
            ///Bit 2 - Watchdog counter window value update
            #[inline(always)]
            pub fn wvu(&self) -> WVU_R {
                WVU_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Watchdog counter reload value update
            #[inline(always)]
            pub fn rvu(&self) -> RVU_R {
                RVU_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Watchdog prescaler value update
            #[inline(always)]
            pub fn pvu(&self) -> PVU_R {
                PVU_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///Window register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [winr](winr) module
    pub type WINR = crate::Reg<u32, _WINR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _WINR;
    ///`read()` method returns [winr::R](winr::R) reader structure
    impl crate::Readable for WINR {}
    ///`write(|w| ..)` method takes [winr::W](winr::W) writer structure
    impl crate::Writable for WINR {}
    ///Window register
    pub mod winr {
        ///Reader of register WINR
        pub type R = crate::R<u32, super::WINR>;
        ///Writer for register WINR
        pub type W = crate::W<u32, super::WINR>;
        ///Register WINR `reset()`'s with value 0x0fff
        impl crate::ResetValue for super::WINR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0fff
            }
        }
        ///Reader of field `WIN`
        pub type WIN_R = crate::R<u16, u16>;
        ///Write proxy for field `WIN`
        pub struct WIN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WIN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        impl R {
            ///Bits 0:11 - Watchdog counter window value
            #[inline(always)]
            pub fn win(&self) -> WIN_R {
                WIN_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            ///Bits 0:11 - Watchdog counter window value
            #[inline(always)]
            pub fn win(&mut self) -> WIN_W {
                WIN_W { w: self }
            }
        }
    }
}
///System window watchdog
pub struct WWDG {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for WWDG {}
impl WWDG {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const wwdg::RegisterBlock {
        0x4000_2c00 as *const _
    }
}
impl Deref for WWDG {
    type Target = wwdg::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*WWDG::ptr() }
    }
}
///System window watchdog
pub mod wwdg {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Control register
        pub cr: CR,
        ///0x04 - Configuration register
        pub cfr: CFR,
        ///0x08 - Status register
        pub sr: SR,
    }
    ///Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0x7f
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x7f
            }
        }
        ///Reader of field `WDGA`
        pub type WDGA_R = crate::R<bool, bool>;
        ///Write proxy for field `WDGA`
        pub struct WDGA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WDGA_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `T`
        pub type T_R = crate::R<u8, u8>;
        ///Write proxy for field `T`
        pub struct T_W<'a> {
            w: &'a mut W,
        }
        impl<'a> T_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
                self.w
            }
        }
        impl R {
            ///Bit 7 - Activation bit
            #[inline(always)]
            pub fn wdga(&self) -> WDGA_R {
                WDGA_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 0:6 - 7-bit counter (MSB to LSB)
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new((self.bits & 0x7f) as u8)
            }
        }
        impl W {
            ///Bit 7 - Activation bit
            #[inline(always)]
            pub fn wdga(&mut self) -> WDGA_W {
                WDGA_W { w: self }
            }
            ///Bits 0:6 - 7-bit counter (MSB to LSB)
            #[inline(always)]
            pub fn t(&mut self) -> T_W {
                T_W { w: self }
            }
        }
    }
    ///Configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfr](cfr) module
    pub type CFR = crate::Reg<u32, _CFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFR;
    ///`read()` method returns [cfr::R](cfr::R) reader structure
    impl crate::Readable for CFR {}
    ///`write(|w| ..)` method takes [cfr::W](cfr::W) writer structure
    impl crate::Writable for CFR {}
    ///Configuration register
    pub mod cfr {
        ///Reader of register CFR
        pub type R = crate::R<u32, super::CFR>;
        ///Writer for register CFR
        pub type W = crate::W<u32, super::CFR>;
        ///Register CFR `reset()`'s with value 0x7f
        impl crate::ResetValue for super::CFR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x7f
            }
        }
        ///Reader of field `WDGTB`
        pub type WDGTB_R = crate::R<u8, u8>;
        ///Write proxy for field `WDGTB`
        pub struct WDGTB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WDGTB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 11)) | (((value as u32) & 0x07) << 11);
                self.w
            }
        }
        ///Reader of field `EWI`
        pub type EWI_R = crate::R<bool, bool>;
        ///Write proxy for field `EWI`
        pub struct EWI_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWI_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `W`
        pub type W_R = crate::R<u8, u8>;
        ///Write proxy for field `W`
        pub struct W_W<'a> {
            w: &'a mut W,
        }
        impl<'a> W_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
                self.w
            }
        }
        impl R {
            ///Bits 11:13 - Timer base
            #[inline(always)]
            pub fn wdgtb(&self) -> WDGTB_R {
                WDGTB_R::new(((self.bits >> 11) & 0x07) as u8)
            }
            ///Bit 9 - Early wakeup interrupt
            #[inline(always)]
            pub fn ewi(&self) -> EWI_R {
                EWI_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bits 0:6 - 7-bit window value
            #[inline(always)]
            pub fn w(&self) -> W_R {
                W_R::new((self.bits & 0x7f) as u8)
            }
        }
        impl W {
            ///Bits 11:13 - Timer base
            #[inline(always)]
            pub fn wdgtb(&mut self) -> WDGTB_W {
                WDGTB_W { w: self }
            }
            ///Bit 9 - Early wakeup interrupt
            #[inline(always)]
            pub fn ewi(&mut self) -> EWI_W {
                EWI_W { w: self }
            }
            ///Bits 0:6 - 7-bit window value
            #[inline(always)]
            pub fn w(&mut self) -> W_W {
                W_W { w: self }
            }
        }
    }
    ///Status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///Status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EWIF`
        pub type EWIF_R = crate::R<bool, bool>;
        ///Write proxy for field `EWIF`
        pub struct EWIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Early wakeup interrupt flag
            #[inline(always)]
            pub fn ewif(&self) -> EWIF_R {
                EWIF_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Early wakeup interrupt flag
            #[inline(always)]
            pub fn ewif(&mut self) -> EWIF_W {
                EWIF_W { w: self }
            }
        }
    }
}
///Comparator instance 1
pub struct COMP {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for COMP {}
impl COMP {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const comp::RegisterBlock {
        0x4001_0200 as *const _
    }
}
impl Deref for COMP {
    type Target = comp::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*COMP::ptr() }
    }
}
///Comparator instance 1
pub mod comp {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Comparator control and status register
        pub comp1_csr: COMP1_CSR,
        ///0x04 - Comparator 2 control and status register
        pub comp2_csr: COMP2_CSR,
    }
    ///Comparator control and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [comp1_csr](comp1_csr) module
    pub type COMP1_CSR = crate::Reg<u32, _COMP1_CSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COMP1_CSR;
    ///`read()` method returns [comp1_csr::R](comp1_csr::R) reader structure
    impl crate::Readable for COMP1_CSR {}
    ///`write(|w| ..)` method takes [comp1_csr::W](comp1_csr::W) writer structure
    impl crate::Writable for COMP1_CSR {}
    ///Comparator control and status register
    pub mod comp1_csr {
        ///Reader of register COMP1_CSR
        pub type R = crate::R<u32, super::COMP1_CSR>;
        ///Writer for register COMP1_CSR
        pub type W = crate::W<u32, super::COMP1_CSR>;
        ///Register COMP1_CSR `reset()`'s with value 0
        impl crate::ResetValue for super::COMP1_CSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COMP1_EN`
        pub type COMP1_EN_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP1_EN`
        pub struct COMP1_EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `COMP1_PWRMODE`
        pub type COMP1_PWRMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP1_PWRMODE`
        pub struct COMP1_PWRMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_PWRMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `COMP1_INMSEL`
        pub type COMP1_INMSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP1_INMSEL`
        pub struct COMP1_INMSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_INMSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `COMP1_INPSEL`
        pub type COMP1_INPSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP1_INPSEL`
        pub struct COMP1_INPSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_INPSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 7)) | (((value as u32) & 0x03) << 7);
                self.w
            }
        }
        ///Reader of field `COMP1_POLARITY`
        pub type COMP1_POLARITY_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP1_POLARITY`
        pub struct COMP1_POLARITY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_POLARITY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `COMP1_HYST`
        pub type COMP1_HYST_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP1_HYST`
        pub struct COMP1_HYST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_HYST_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `COMP1_BLANKING`
        pub type COMP1_BLANKING_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP1_BLANKING`
        pub struct COMP1_BLANKING_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_BLANKING_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 18)) | (((value as u32) & 0x07) << 18);
                self.w
            }
        }
        ///Reader of field `COMP1_BRGEN`
        pub type COMP1_BRGEN_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP1_BRGEN`
        pub struct COMP1_BRGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_BRGEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `COMP1_SCALEN`
        pub type COMP1_SCALEN_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP1_SCALEN`
        pub struct COMP1_SCALEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_SCALEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `COMP1_INMESEL`
        pub type COMP1_INMESEL_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP1_INMESEL`
        pub struct COMP1_INMESEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_INMESEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 25)) | (((value as u32) & 0x03) << 25);
                self.w
            }
        }
        ///Reader of field `COMP1_VALUE`
        pub type COMP1_VALUE_R = crate::R<bool, bool>;
        ///Reader of field `COMP1_LOCK`
        pub type COMP1_LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP1_LOCK`
        pub struct COMP1_LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP1_LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Comparator enable
            #[inline(always)]
            pub fn comp1_en(&self) -> COMP1_EN_R {
                COMP1_EN_R::new((self.bits & 0x01) != 0)
            }
            ///Bits 2:3 - Comparator power mode
            #[inline(always)]
            pub fn comp1_pwrmode(&self) -> COMP1_PWRMODE_R {
                COMP1_PWRMODE_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 4:6 - Comparator input minus selection
            #[inline(always)]
            pub fn comp1_inmsel(&self) -> COMP1_INMSEL_R {
                COMP1_INMSEL_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 7:8 - Comparator input plus selection
            #[inline(always)]
            pub fn comp1_inpsel(&self) -> COMP1_INPSEL_R {
                COMP1_INPSEL_R::new(((self.bits >> 7) & 0x03) as u8)
            }
            ///Bit 15 - Comparator output polarity
            #[inline(always)]
            pub fn comp1_polarity(&self) -> COMP1_POLARITY_R {
                COMP1_POLARITY_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 16:17 - Comparator hysteresis
            #[inline(always)]
            pub fn comp1_hyst(&self) -> COMP1_HYST_R {
                COMP1_HYST_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 18:20 - Comparator blanking source
            #[inline(always)]
            pub fn comp1_blanking(&self) -> COMP1_BLANKING_R {
                COMP1_BLANKING_R::new(((self.bits >> 18) & 0x07) as u8)
            }
            ///Bit 22 - Comparator voltage scaler enable
            #[inline(always)]
            pub fn comp1_brgen(&self) -> COMP1_BRGEN_R {
                COMP1_BRGEN_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 23 - Comparator scaler bridge enable
            #[inline(always)]
            pub fn comp1_scalen(&self) -> COMP1_SCALEN_R {
                COMP1_SCALEN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bits 25:26 - Comparator input minus extended selection
            #[inline(always)]
            pub fn comp1_inmesel(&self) -> COMP1_INMESEL_R {
                COMP1_INMESEL_R::new(((self.bits >> 25) & 0x03) as u8)
            }
            ///Bit 30 - Comparator output level
            #[inline(always)]
            pub fn comp1_value(&self) -> COMP1_VALUE_R {
                COMP1_VALUE_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - Comparator lock
            #[inline(always)]
            pub fn comp1_lock(&self) -> COMP1_LOCK_R {
                COMP1_LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Comparator enable
            #[inline(always)]
            pub fn comp1_en(&mut self) -> COMP1_EN_W {
                COMP1_EN_W { w: self }
            }
            ///Bits 2:3 - Comparator power mode
            #[inline(always)]
            pub fn comp1_pwrmode(&mut self) -> COMP1_PWRMODE_W {
                COMP1_PWRMODE_W { w: self }
            }
            ///Bits 4:6 - Comparator input minus selection
            #[inline(always)]
            pub fn comp1_inmsel(&mut self) -> COMP1_INMSEL_W {
                COMP1_INMSEL_W { w: self }
            }
            ///Bits 7:8 - Comparator input plus selection
            #[inline(always)]
            pub fn comp1_inpsel(&mut self) -> COMP1_INPSEL_W {
                COMP1_INPSEL_W { w: self }
            }
            ///Bit 15 - Comparator output polarity
            #[inline(always)]
            pub fn comp1_polarity(&mut self) -> COMP1_POLARITY_W {
                COMP1_POLARITY_W { w: self }
            }
            ///Bits 16:17 - Comparator hysteresis
            #[inline(always)]
            pub fn comp1_hyst(&mut self) -> COMP1_HYST_W {
                COMP1_HYST_W { w: self }
            }
            ///Bits 18:20 - Comparator blanking source
            #[inline(always)]
            pub fn comp1_blanking(&mut self) -> COMP1_BLANKING_W {
                COMP1_BLANKING_W { w: self }
            }
            ///Bit 22 - Comparator voltage scaler enable
            #[inline(always)]
            pub fn comp1_brgen(&mut self) -> COMP1_BRGEN_W {
                COMP1_BRGEN_W { w: self }
            }
            ///Bit 23 - Comparator scaler bridge enable
            #[inline(always)]
            pub fn comp1_scalen(&mut self) -> COMP1_SCALEN_W {
                COMP1_SCALEN_W { w: self }
            }
            ///Bits 25:26 - Comparator input minus extended selection
            #[inline(always)]
            pub fn comp1_inmesel(&mut self) -> COMP1_INMESEL_W {
                COMP1_INMESEL_W { w: self }
            }
            ///Bit 31 - Comparator lock
            #[inline(always)]
            pub fn comp1_lock(&mut self) -> COMP1_LOCK_W {
                COMP1_LOCK_W { w: self }
            }
        }
    }
    ///Comparator 2 control and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [comp2_csr](comp2_csr) module
    pub type COMP2_CSR = crate::Reg<u32, _COMP2_CSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COMP2_CSR;
    ///`read()` method returns [comp2_csr::R](comp2_csr::R) reader structure
    impl crate::Readable for COMP2_CSR {}
    ///`write(|w| ..)` method takes [comp2_csr::W](comp2_csr::W) writer structure
    impl crate::Writable for COMP2_CSR {}
    ///Comparator 2 control and status register
    pub mod comp2_csr {
        ///Reader of register COMP2_CSR
        pub type R = crate::R<u32, super::COMP2_CSR>;
        ///Writer for register COMP2_CSR
        pub type W = crate::W<u32, super::COMP2_CSR>;
        ///Register COMP2_CSR `reset()`'s with value 0
        impl crate::ResetValue for super::COMP2_CSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COMP2_EN`
        pub type COMP2_EN_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP2_EN`
        pub struct COMP2_EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `COMP2_PWRMODE`
        pub type COMP2_PWRMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP2_PWRMODE`
        pub struct COMP2_PWRMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_PWRMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `COMP2_INMSEL`
        pub type COMP2_INMSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP2_INMSEL`
        pub struct COMP2_INMSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_INMSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `COMP2_INPSEL`
        pub type COMP2_INPSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP2_INPSEL`
        pub struct COMP2_INPSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_INPSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 7)) | (((value as u32) & 0x03) << 7);
                self.w
            }
        }
        ///Reader of field `COMP2_WINMODE`
        pub type COMP2_WINMODE_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP2_WINMODE`
        pub struct COMP2_WINMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_WINMODE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `COMP2_POLARITY`
        pub type COMP2_POLARITY_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP2_POLARITY`
        pub struct COMP2_POLARITY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_POLARITY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `COMP2_HYST`
        pub type COMP2_HYST_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP2_HYST`
        pub struct COMP2_HYST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_HYST_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `COMP2_BLANKING`
        pub type COMP2_BLANKING_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP2_BLANKING`
        pub struct COMP2_BLANKING_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_BLANKING_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 18)) | (((value as u32) & 0x07) << 18);
                self.w
            }
        }
        ///Reader of field `COMP2_BRGEN`
        pub type COMP2_BRGEN_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP2_BRGEN`
        pub struct COMP2_BRGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_BRGEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `COMP2_SCALEN`
        pub type COMP2_SCALEN_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP2_SCALEN`
        pub struct COMP2_SCALEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_SCALEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `COMP2_INMESEL`
        pub type COMP2_INMESEL_R = crate::R<u8, u8>;
        ///Write proxy for field `COMP2_INMESEL`
        pub struct COMP2_INMESEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_INMESEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 25)) | (((value as u32) & 0x03) << 25);
                self.w
            }
        }
        ///Reader of field `COMP2_VALUE`
        pub type COMP2_VALUE_R = crate::R<bool, bool>;
        ///Reader of field `COMP2_LOCK`
        pub type COMP2_LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP2_LOCK`
        pub struct COMP2_LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP2_LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Comparator 2 enable bit
            #[inline(always)]
            pub fn comp2_en(&self) -> COMP2_EN_R {
                COMP2_EN_R::new((self.bits & 0x01) != 0)
            }
            ///Bits 2:3 - Power Mode of the comparator 2
            #[inline(always)]
            pub fn comp2_pwrmode(&self) -> COMP2_PWRMODE_R {
                COMP2_PWRMODE_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 4:5 - Comparator 2 input minus selection bits
            #[inline(always)]
            pub fn comp2_inmsel(&self) -> COMP2_INMSEL_R {
                COMP2_INMSEL_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 7:8 - Comparator 1 input plus selection bit
            #[inline(always)]
            pub fn comp2_inpsel(&self) -> COMP2_INPSEL_R {
                COMP2_INPSEL_R::new(((self.bits >> 7) & 0x03) as u8)
            }
            ///Bit 9 - Windows mode selection bit
            #[inline(always)]
            pub fn comp2_winmode(&self) -> COMP2_WINMODE_R {
                COMP2_WINMODE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 15 - Comparator 2 polarity selection bit
            #[inline(always)]
            pub fn comp2_polarity(&self) -> COMP2_POLARITY_R {
                COMP2_POLARITY_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 16:17 - Comparator 2 hysteresis selection bits
            #[inline(always)]
            pub fn comp2_hyst(&self) -> COMP2_HYST_R {
                COMP2_HYST_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 18:20 - Comparator 2 blanking source selection bits
            #[inline(always)]
            pub fn comp2_blanking(&self) -> COMP2_BLANKING_R {
                COMP2_BLANKING_R::new(((self.bits >> 18) & 0x07) as u8)
            }
            ///Bit 22 - Scaler bridge enable
            #[inline(always)]
            pub fn comp2_brgen(&self) -> COMP2_BRGEN_R {
                COMP2_BRGEN_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 23 - Voltage scaler enable bit
            #[inline(always)]
            pub fn comp2_scalen(&self) -> COMP2_SCALEN_R {
                COMP2_SCALEN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bits 25:26 - comparator 2 input minus extended selection bits.
            #[inline(always)]
            pub fn comp2_inmesel(&self) -> COMP2_INMESEL_R {
                COMP2_INMESEL_R::new(((self.bits >> 25) & 0x03) as u8)
            }
            ///Bit 30 - Comparator 2 output status bit
            #[inline(always)]
            pub fn comp2_value(&self) -> COMP2_VALUE_R {
                COMP2_VALUE_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - CSR register lock bit
            #[inline(always)]
            pub fn comp2_lock(&self) -> COMP2_LOCK_R {
                COMP2_LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Comparator 2 enable bit
            #[inline(always)]
            pub fn comp2_en(&mut self) -> COMP2_EN_W {
                COMP2_EN_W { w: self }
            }
            ///Bits 2:3 - Power Mode of the comparator 2
            #[inline(always)]
            pub fn comp2_pwrmode(&mut self) -> COMP2_PWRMODE_W {
                COMP2_PWRMODE_W { w: self }
            }
            ///Bits 4:5 - Comparator 2 input minus selection bits
            #[inline(always)]
            pub fn comp2_inmsel(&mut self) -> COMP2_INMSEL_W {
                COMP2_INMSEL_W { w: self }
            }
            ///Bits 7:8 - Comparator 1 input plus selection bit
            #[inline(always)]
            pub fn comp2_inpsel(&mut self) -> COMP2_INPSEL_W {
                COMP2_INPSEL_W { w: self }
            }
            ///Bit 9 - Windows mode selection bit
            #[inline(always)]
            pub fn comp2_winmode(&mut self) -> COMP2_WINMODE_W {
                COMP2_WINMODE_W { w: self }
            }
            ///Bit 15 - Comparator 2 polarity selection bit
            #[inline(always)]
            pub fn comp2_polarity(&mut self) -> COMP2_POLARITY_W {
                COMP2_POLARITY_W { w: self }
            }
            ///Bits 16:17 - Comparator 2 hysteresis selection bits
            #[inline(always)]
            pub fn comp2_hyst(&mut self) -> COMP2_HYST_W {
                COMP2_HYST_W { w: self }
            }
            ///Bits 18:20 - Comparator 2 blanking source selection bits
            #[inline(always)]
            pub fn comp2_blanking(&mut self) -> COMP2_BLANKING_W {
                COMP2_BLANKING_W { w: self }
            }
            ///Bit 22 - Scaler bridge enable
            #[inline(always)]
            pub fn comp2_brgen(&mut self) -> COMP2_BRGEN_W {
                COMP2_BRGEN_W { w: self }
            }
            ///Bit 23 - Voltage scaler enable bit
            #[inline(always)]
            pub fn comp2_scalen(&mut self) -> COMP2_SCALEN_W {
                COMP2_SCALEN_W { w: self }
            }
            ///Bits 25:26 - comparator 2 input minus extended selection bits.
            #[inline(always)]
            pub fn comp2_inmesel(&mut self) -> COMP2_INMESEL_W {
                COMP2_INMESEL_W { w: self }
            }
            ///Bit 31 - CSR register lock bit
            #[inline(always)]
            pub fn comp2_lock(&mut self) -> COMP2_LOCK_W {
                COMP2_LOCK_W { w: self }
            }
        }
    }
}
///Inter-integrated circuit
pub struct I2C1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C1 {}
impl I2C1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const i2c1::RegisterBlock {
        0x4000_5400 as *const _
    }
}
impl Deref for I2C1 {
    type Target = i2c1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*I2C1::ptr() }
    }
}
///Inter-integrated circuit
pub mod i2c1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Control register 1
        pub cr1: CR1,
        ///0x04 - Control register 2
        pub cr2: CR2,
        ///0x08 - Own address register 1
        pub oar1: OAR1,
        ///0x0c - Own address register 2
        pub oar2: OAR2,
        ///0x10 - Timing register
        pub timingr: TIMINGR,
        ///0x14 - Status register 1
        pub timeoutr: TIMEOUTR,
        ///0x18 - Interrupt and Status register
        pub isr: ISR,
        ///0x1c - Interrupt clear register
        pub icr: ICR,
        ///0x20 - PEC register
        pub pecr: PECR,
        ///0x24 - Receive data register
        pub rxdr: RXDR,
        ///0x28 - Transmit data register
        pub txdr: TXDR,
    }
    ///Control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///Control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PE`
        pub type PE_R = crate::R<bool, bool>;
        ///Write proxy for field `PE`
        pub struct PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `TXIE`
        pub type TXIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXIE`
        pub struct TXIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `RXIE`
        pub type RXIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RXIE`
        pub struct RXIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ADDRIE`
        pub type ADDRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ADDRIE`
        pub struct ADDRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `NACKIE`
        pub type NACKIE_R = crate::R<bool, bool>;
        ///Write proxy for field `NACKIE`
        pub struct NACKIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NACKIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `STOPIE`
        pub type STOPIE_R = crate::R<bool, bool>;
        ///Write proxy for field `STOPIE`
        pub struct STOPIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STOPIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `ERRIE`
        pub type ERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRIE`
        pub struct ERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `DNF`
        pub type DNF_R = crate::R<u8, u8>;
        ///Write proxy for field `DNF`
        pub struct DNF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DNF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `ANFOFF`
        pub type ANFOFF_R = crate::R<bool, bool>;
        ///Write proxy for field `ANFOFF`
        pub struct ANFOFF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ANFOFF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TXDMAEN`
        pub type TXDMAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TXDMAEN`
        pub struct TXDMAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXDMAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `RXDMAEN`
        pub type RXDMAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RXDMAEN`
        pub struct RXDMAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXDMAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `SBC`
        pub type SBC_R = crate::R<bool, bool>;
        ///Write proxy for field `SBC`
        pub struct SBC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SBC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `NOSTRETCH`
        pub type NOSTRETCH_R = crate::R<bool, bool>;
        ///Write proxy for field `NOSTRETCH`
        pub struct NOSTRETCH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NOSTRETCH_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `WUPEN`
        pub type WUPEN_R = crate::R<bool, bool>;
        ///Write proxy for field `WUPEN`
        pub struct WUPEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUPEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `GCEN`
        pub type GCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GCEN`
        pub struct GCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `SMBHEN`
        pub type SMBHEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SMBHEN`
        pub struct SMBHEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMBHEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `SMBDEN`
        pub type SMBDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SMBDEN`
        pub struct SMBDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMBDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `ALERTEN`
        pub type ALERTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ALERTEN`
        pub struct ALERTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALERTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `PECEN`
        pub type PECEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PECEN`
        pub struct PECEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PECEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Peripheral enable
            #[inline(always)]
            pub fn pe(&self) -> PE_R {
                PE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - TX Interrupt enable
            #[inline(always)]
            pub fn txie(&self) -> TXIE_R {
                TXIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - RX Interrupt enable
            #[inline(always)]
            pub fn rxie(&self) -> RXIE_R {
                RXIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Address match interrupt enable (slave only)
            #[inline(always)]
            pub fn addrie(&self) -> ADDRIE_R {
                ADDRIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Not acknowledge received interrupt enable
            #[inline(always)]
            pub fn nackie(&self) -> NACKIE_R {
                NACKIE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - STOP detection Interrupt enable
            #[inline(always)]
            pub fn stopie(&self) -> STOPIE_R {
                STOPIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Transfer Complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Error interrupts enable
            #[inline(always)]
            pub fn errie(&self) -> ERRIE_R {
                ERRIE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:11 - Digital noise filter
            #[inline(always)]
            pub fn dnf(&self) -> DNF_R {
                DNF_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bit 12 - Analog noise filter OFF
            #[inline(always)]
            pub fn anfoff(&self) -> ANFOFF_R {
                ANFOFF_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 14 - DMA transmission requests enable
            #[inline(always)]
            pub fn txdmaen(&self) -> TXDMAEN_R {
                TXDMAEN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - DMA reception requests enable
            #[inline(always)]
            pub fn rxdmaen(&self) -> RXDMAEN_R {
                RXDMAEN_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Slave byte control
            #[inline(always)]
            pub fn sbc(&self) -> SBC_R {
                SBC_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Clock stretching disable
            #[inline(always)]
            pub fn nostretch(&self) -> NOSTRETCH_R {
                NOSTRETCH_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - Wakeup from STOP enable
            #[inline(always)]
            pub fn wupen(&self) -> WUPEN_R {
                WUPEN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - General call enable
            #[inline(always)]
            pub fn gcen(&self) -> GCEN_R {
                GCEN_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 20 - SMBus Host address enable
            #[inline(always)]
            pub fn smbhen(&self) -> SMBHEN_R {
                SMBHEN_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 21 - SMBus Device Default address enable
            #[inline(always)]
            pub fn smbden(&self) -> SMBDEN_R {
                SMBDEN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 22 - SMBUS alert enable
            #[inline(always)]
            pub fn alerten(&self) -> ALERTEN_R {
                ALERTEN_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 23 - PEC enable
            #[inline(always)]
            pub fn pecen(&self) -> PECEN_R {
                PECEN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Peripheral enable
            #[inline(always)]
            pub fn pe(&mut self) -> PE_W {
                PE_W { w: self }
            }
            ///Bit 1 - TX Interrupt enable
            #[inline(always)]
            pub fn txie(&mut self) -> TXIE_W {
                TXIE_W { w: self }
            }
            ///Bit 2 - RX Interrupt enable
            #[inline(always)]
            pub fn rxie(&mut self) -> RXIE_W {
                RXIE_W { w: self }
            }
            ///Bit 3 - Address match interrupt enable (slave only)
            #[inline(always)]
            pub fn addrie(&mut self) -> ADDRIE_W {
                ADDRIE_W { w: self }
            }
            ///Bit 4 - Not acknowledge received interrupt enable
            #[inline(always)]
            pub fn nackie(&mut self) -> NACKIE_W {
                NACKIE_W { w: self }
            }
            ///Bit 5 - STOP detection Interrupt enable
            #[inline(always)]
            pub fn stopie(&mut self) -> STOPIE_W {
                STOPIE_W { w: self }
            }
            ///Bit 6 - Transfer Complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 7 - Error interrupts enable
            #[inline(always)]
            pub fn errie(&mut self) -> ERRIE_W {
                ERRIE_W { w: self }
            }
            ///Bits 8:11 - Digital noise filter
            #[inline(always)]
            pub fn dnf(&mut self) -> DNF_W {
                DNF_W { w: self }
            }
            ///Bit 12 - Analog noise filter OFF
            #[inline(always)]
            pub fn anfoff(&mut self) -> ANFOFF_W {
                ANFOFF_W { w: self }
            }
            ///Bit 14 - DMA transmission requests enable
            #[inline(always)]
            pub fn txdmaen(&mut self) -> TXDMAEN_W {
                TXDMAEN_W { w: self }
            }
            ///Bit 15 - DMA reception requests enable
            #[inline(always)]
            pub fn rxdmaen(&mut self) -> RXDMAEN_W {
                RXDMAEN_W { w: self }
            }
            ///Bit 16 - Slave byte control
            #[inline(always)]
            pub fn sbc(&mut self) -> SBC_W {
                SBC_W { w: self }
            }
            ///Bit 17 - Clock stretching disable
            #[inline(always)]
            pub fn nostretch(&mut self) -> NOSTRETCH_W {
                NOSTRETCH_W { w: self }
            }
            ///Bit 18 - Wakeup from STOP enable
            #[inline(always)]
            pub fn wupen(&mut self) -> WUPEN_W {
                WUPEN_W { w: self }
            }
            ///Bit 19 - General call enable
            #[inline(always)]
            pub fn gcen(&mut self) -> GCEN_W {
                GCEN_W { w: self }
            }
            ///Bit 20 - SMBus Host address enable
            #[inline(always)]
            pub fn smbhen(&mut self) -> SMBHEN_W {
                SMBHEN_W { w: self }
            }
            ///Bit 21 - SMBus Device Default address enable
            #[inline(always)]
            pub fn smbden(&mut self) -> SMBDEN_W {
                SMBDEN_W { w: self }
            }
            ///Bit 22 - SMBUS alert enable
            #[inline(always)]
            pub fn alerten(&mut self) -> ALERTEN_W {
                ALERTEN_W { w: self }
            }
            ///Bit 23 - PEC enable
            #[inline(always)]
            pub fn pecen(&mut self) -> PECEN_W {
                PECEN_W { w: self }
            }
        }
    }
    ///Control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///Control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PECBYTE`
        pub type PECBYTE_R = crate::R<bool, bool>;
        ///Write proxy for field `PECBYTE`
        pub struct PECBYTE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PECBYTE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `AUTOEND`
        pub type AUTOEND_R = crate::R<bool, bool>;
        ///Write proxy for field `AUTOEND`
        pub struct AUTOEND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AUTOEND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `RELOAD`
        pub type RELOAD_R = crate::R<bool, bool>;
        ///Write proxy for field `RELOAD`
        pub struct RELOAD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RELOAD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `NBYTES`
        pub type NBYTES_R = crate::R<u8, u8>;
        ///Write proxy for field `NBYTES`
        pub struct NBYTES_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBYTES_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
                self.w
            }
        }
        ///Reader of field `NACK`
        pub type NACK_R = crate::R<bool, bool>;
        ///Write proxy for field `NACK`
        pub struct NACK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NACK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `STOP`
        pub type STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `STOP`
        pub struct STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `START`
        pub type START_R = crate::R<bool, bool>;
        ///Write proxy for field `START`
        pub struct START_W<'a> {
            w: &'a mut W,
        }
        impl<'a> START_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `HEAD10R`
        pub type HEAD10R_R = crate::R<bool, bool>;
        ///Write proxy for field `HEAD10R`
        pub struct HEAD10R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HEAD10R_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ADD10`
        pub type ADD10_R = crate::R<bool, bool>;
        ///Write proxy for field `ADD10`
        pub struct ADD10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADD10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `RD_WRN`
        pub type RD_WRN_R = crate::R<bool, bool>;
        ///Write proxy for field `RD_WRN`
        pub struct RD_WRN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RD_WRN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `SADD`
        pub type SADD_R = crate::R<u16, u16>;
        ///Write proxy for field `SADD`
        pub struct SADD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SADD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bit 26 - Packet error checking byte
            #[inline(always)]
            pub fn pecbyte(&self) -> PECBYTE_R {
                PECBYTE_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - Automatic end mode (master mode)
            #[inline(always)]
            pub fn autoend(&self) -> AUTOEND_R {
                AUTOEND_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - NBYTES reload mode
            #[inline(always)]
            pub fn reload(&self) -> RELOAD_R {
                RELOAD_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bits 16:23 - Number of bytes
            #[inline(always)]
            pub fn nbytes(&self) -> NBYTES_R {
                NBYTES_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            ///Bit 15 - NACK generation (slave mode)
            #[inline(always)]
            pub fn nack(&self) -> NACK_R {
                NACK_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Stop generation (master mode)
            #[inline(always)]
            pub fn stop(&self) -> STOP_R {
                STOP_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Start generation
            #[inline(always)]
            pub fn start(&self) -> START_R {
                START_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - 10-bit address header only read direction (master receiver mode)
            #[inline(always)]
            pub fn head10r(&self) -> HEAD10R_R {
                HEAD10R_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - 10-bit addressing mode (master mode)
            #[inline(always)]
            pub fn add10(&self) -> ADD10_R {
                ADD10_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Transfer direction (master mode)
            #[inline(always)]
            pub fn rd_wrn(&self) -> RD_WRN_R {
                RD_WRN_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bits 0:9 - Slave address bit (master mode)
            #[inline(always)]
            pub fn sadd(&self) -> SADD_R {
                SADD_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bit 26 - Packet error checking byte
            #[inline(always)]
            pub fn pecbyte(&mut self) -> PECBYTE_W {
                PECBYTE_W { w: self }
            }
            ///Bit 25 - Automatic end mode (master mode)
            #[inline(always)]
            pub fn autoend(&mut self) -> AUTOEND_W {
                AUTOEND_W { w: self }
            }
            ///Bit 24 - NBYTES reload mode
            #[inline(always)]
            pub fn reload(&mut self) -> RELOAD_W {
                RELOAD_W { w: self }
            }
            ///Bits 16:23 - Number of bytes
            #[inline(always)]
            pub fn nbytes(&mut self) -> NBYTES_W {
                NBYTES_W { w: self }
            }
            ///Bit 15 - NACK generation (slave mode)
            #[inline(always)]
            pub fn nack(&mut self) -> NACK_W {
                NACK_W { w: self }
            }
            ///Bit 14 - Stop generation (master mode)
            #[inline(always)]
            pub fn stop(&mut self) -> STOP_W {
                STOP_W { w: self }
            }
            ///Bit 13 - Start generation
            #[inline(always)]
            pub fn start(&mut self) -> START_W {
                START_W { w: self }
            }
            ///Bit 12 - 10-bit address header only read direction (master receiver mode)
            #[inline(always)]
            pub fn head10r(&mut self) -> HEAD10R_W {
                HEAD10R_W { w: self }
            }
            ///Bit 11 - 10-bit addressing mode (master mode)
            #[inline(always)]
            pub fn add10(&mut self) -> ADD10_W {
                ADD10_W { w: self }
            }
            ///Bit 10 - Transfer direction (master mode)
            #[inline(always)]
            pub fn rd_wrn(&mut self) -> RD_WRN_W {
                RD_WRN_W { w: self }
            }
            ///Bits 0:9 - Slave address bit (master mode)
            #[inline(always)]
            pub fn sadd(&mut self) -> SADD_W {
                SADD_W { w: self }
            }
        }
    }
    ///Own address register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [oar1](oar1) module
    pub type OAR1 = crate::Reg<u32, _OAR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OAR1;
    ///`read()` method returns [oar1::R](oar1::R) reader structure
    impl crate::Readable for OAR1 {}
    ///`write(|w| ..)` method takes [oar1::W](oar1::W) writer structure
    impl crate::Writable for OAR1 {}
    ///Own address register 1
    pub mod oar1 {
        ///Reader of register OAR1
        pub type R = crate::R<u32, super::OAR1>;
        ///Writer for register OAR1
        pub type W = crate::W<u32, super::OAR1>;
        ///Register OAR1 `reset()`'s with value 0
        impl crate::ResetValue for super::OAR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OA1`
        pub type OA1_R = crate::R<u16, u16>;
        ///Write proxy for field `OA1`
        pub struct OA1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OA1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
                self.w
            }
        }
        ///Reader of field `OA1MODE`
        pub type OA1MODE_R = crate::R<bool, bool>;
        ///Write proxy for field `OA1MODE`
        pub struct OA1MODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OA1MODE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OA1EN`
        pub type OA1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `OA1EN`
        pub struct OA1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OA1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Interface address
            #[inline(always)]
            pub fn oa1(&self) -> OA1_R {
                OA1_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bit 10 - Own Address 1 10-bit mode
            #[inline(always)]
            pub fn oa1mode(&self) -> OA1MODE_R {
                OA1MODE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 15 - Own Address 1 enable
            #[inline(always)]
            pub fn oa1en(&self) -> OA1EN_R {
                OA1EN_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:9 - Interface address
            #[inline(always)]
            pub fn oa1(&mut self) -> OA1_W {
                OA1_W { w: self }
            }
            ///Bit 10 - Own Address 1 10-bit mode
            #[inline(always)]
            pub fn oa1mode(&mut self) -> OA1MODE_W {
                OA1MODE_W { w: self }
            }
            ///Bit 15 - Own Address 1 enable
            #[inline(always)]
            pub fn oa1en(&mut self) -> OA1EN_W {
                OA1EN_W { w: self }
            }
        }
    }
    ///Own address register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [oar2](oar2) module
    pub type OAR2 = crate::Reg<u32, _OAR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OAR2;
    ///`read()` method returns [oar2::R](oar2::R) reader structure
    impl crate::Readable for OAR2 {}
    ///`write(|w| ..)` method takes [oar2::W](oar2::W) writer structure
    impl crate::Writable for OAR2 {}
    ///Own address register 2
    pub mod oar2 {
        ///Reader of register OAR2
        pub type R = crate::R<u32, super::OAR2>;
        ///Writer for register OAR2
        pub type W = crate::W<u32, super::OAR2>;
        ///Register OAR2 `reset()`'s with value 0
        impl crate::ResetValue for super::OAR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OA2`
        pub type OA2_R = crate::R<u8, u8>;
        ///Write proxy for field `OA2`
        pub struct OA2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OA2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7f << 1)) | (((value as u32) & 0x7f) << 1);
                self.w
            }
        }
        ///Reader of field `OA2MSK`
        pub type OA2MSK_R = crate::R<u8, u8>;
        ///Write proxy for field `OA2MSK`
        pub struct OA2MSK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OA2MSK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `OA2EN`
        pub type OA2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `OA2EN`
        pub struct OA2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OA2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 1:7 - Interface address
            #[inline(always)]
            pub fn oa2(&self) -> OA2_R {
                OA2_R::new(((self.bits >> 1) & 0x7f) as u8)
            }
            ///Bits 8:10 - Own Address 2 masks
            #[inline(always)]
            pub fn oa2msk(&self) -> OA2MSK_R {
                OA2MSK_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bit 15 - Own Address 2 enable
            #[inline(always)]
            pub fn oa2en(&self) -> OA2EN_R {
                OA2EN_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 1:7 - Interface address
            #[inline(always)]
            pub fn oa2(&mut self) -> OA2_W {
                OA2_W { w: self }
            }
            ///Bits 8:10 - Own Address 2 masks
            #[inline(always)]
            pub fn oa2msk(&mut self) -> OA2MSK_W {
                OA2MSK_W { w: self }
            }
            ///Bit 15 - Own Address 2 enable
            #[inline(always)]
            pub fn oa2en(&mut self) -> OA2EN_W {
                OA2EN_W { w: self }
            }
        }
    }
    ///Timing register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [timingr](timingr) module
    pub type TIMINGR = crate::Reg<u32, _TIMINGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TIMINGR;
    ///`read()` method returns [timingr::R](timingr::R) reader structure
    impl crate::Readable for TIMINGR {}
    ///`write(|w| ..)` method takes [timingr::W](timingr::W) writer structure
    impl crate::Writable for TIMINGR {}
    ///Timing register
    pub mod timingr {
        ///Reader of register TIMINGR
        pub type R = crate::R<u32, super::TIMINGR>;
        ///Writer for register TIMINGR
        pub type W = crate::W<u32, super::TIMINGR>;
        ///Register TIMINGR `reset()`'s with value 0
        impl crate::ResetValue for super::TIMINGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SCLL`
        pub type SCLL_R = crate::R<u8, u8>;
        ///Write proxy for field `SCLL`
        pub struct SCLL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SCLL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        ///Reader of field `SCLH`
        pub type SCLH_R = crate::R<u8, u8>;
        ///Write proxy for field `SCLH`
        pub struct SCLH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SCLH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
                self.w
            }
        }
        ///Reader of field `SDADEL`
        pub type SDADEL_R = crate::R<u8, u8>;
        ///Write proxy for field `SDADEL`
        pub struct SDADEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SDADEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `SCLDEL`
        pub type SCLDEL_R = crate::R<u8, u8>;
        ///Write proxy for field `SCLDEL`
        pub struct SCLDEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SCLDEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `PRESC`
        pub type PRESC_R = crate::R<u8, u8>;
        ///Write proxy for field `PRESC`
        pub struct PRESC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRESC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - SCL low period (master mode)
            #[inline(always)]
            pub fn scll(&self) -> SCLL_R {
                SCLL_R::new((self.bits & 0xff) as u8)
            }
            ///Bits 8:15 - SCL high period (master mode)
            #[inline(always)]
            pub fn sclh(&self) -> SCLH_R {
                SCLH_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            ///Bits 16:19 - Data hold time
            #[inline(always)]
            pub fn sdadel(&self) -> SDADEL_R {
                SDADEL_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 20:23 - Data setup time
            #[inline(always)]
            pub fn scldel(&self) -> SCLDEL_R {
                SCLDEL_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 28:31 - Timing prescaler
            #[inline(always)]
            pub fn presc(&self) -> PRESC_R {
                PRESC_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - SCL low period (master mode)
            #[inline(always)]
            pub fn scll(&mut self) -> SCLL_W {
                SCLL_W { w: self }
            }
            ///Bits 8:15 - SCL high period (master mode)
            #[inline(always)]
            pub fn sclh(&mut self) -> SCLH_W {
                SCLH_W { w: self }
            }
            ///Bits 16:19 - Data hold time
            #[inline(always)]
            pub fn sdadel(&mut self) -> SDADEL_W {
                SDADEL_W { w: self }
            }
            ///Bits 20:23 - Data setup time
            #[inline(always)]
            pub fn scldel(&mut self) -> SCLDEL_W {
                SCLDEL_W { w: self }
            }
            ///Bits 28:31 - Timing prescaler
            #[inline(always)]
            pub fn presc(&mut self) -> PRESC_W {
                PRESC_W { w: self }
            }
        }
    }
    ///Status register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [timeoutr](timeoutr) module
    pub type TIMEOUTR = crate::Reg<u32, _TIMEOUTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TIMEOUTR;
    ///`read()` method returns [timeoutr::R](timeoutr::R) reader structure
    impl crate::Readable for TIMEOUTR {}
    ///`write(|w| ..)` method takes [timeoutr::W](timeoutr::W) writer structure
    impl crate::Writable for TIMEOUTR {}
    ///Status register 1
    pub mod timeoutr {
        ///Reader of register TIMEOUTR
        pub type R = crate::R<u32, super::TIMEOUTR>;
        ///Writer for register TIMEOUTR
        pub type W = crate::W<u32, super::TIMEOUTR>;
        ///Register TIMEOUTR `reset()`'s with value 0
        impl crate::ResetValue for super::TIMEOUTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TIMEOUTA`
        pub type TIMEOUTA_R = crate::R<u16, u16>;
        ///Write proxy for field `TIMEOUTA`
        pub struct TIMEOUTA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIMEOUTA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        ///Reader of field `TIDLE`
        pub type TIDLE_R = crate::R<bool, bool>;
        ///Write proxy for field `TIDLE`
        pub struct TIDLE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIDLE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TIMOUTEN`
        pub type TIMOUTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIMOUTEN`
        pub struct TIMOUTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIMOUTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `TIMEOUTB`
        pub type TIMEOUTB_R = crate::R<u16, u16>;
        ///Write proxy for field `TIMEOUTB`
        pub struct TIMEOUTB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIMEOUTB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0fff << 16)) | (((value as u32) & 0x0fff) << 16);
                self.w
            }
        }
        ///Reader of field `TEXTEN`
        pub type TEXTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TEXTEN`
        pub struct TEXTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEXTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:11 - Bus timeout A
            #[inline(always)]
            pub fn timeouta(&self) -> TIMEOUTA_R {
                TIMEOUTA_R::new((self.bits & 0x0fff) as u16)
            }
            ///Bit 12 - Idle clock timeout detection
            #[inline(always)]
            pub fn tidle(&self) -> TIDLE_R {
                TIDLE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 15 - Clock timeout enable
            #[inline(always)]
            pub fn timouten(&self) -> TIMOUTEN_R {
                TIMOUTEN_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 16:27 - Bus timeout B
            #[inline(always)]
            pub fn timeoutb(&self) -> TIMEOUTB_R {
                TIMEOUTB_R::new(((self.bits >> 16) & 0x0fff) as u16)
            }
            ///Bit 31 - Extended clock timeout enable
            #[inline(always)]
            pub fn texten(&self) -> TEXTEN_R {
                TEXTEN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:11 - Bus timeout A
            #[inline(always)]
            pub fn timeouta(&mut self) -> TIMEOUTA_W {
                TIMEOUTA_W { w: self }
            }
            ///Bit 12 - Idle clock timeout detection
            #[inline(always)]
            pub fn tidle(&mut self) -> TIDLE_W {
                TIDLE_W { w: self }
            }
            ///Bit 15 - Clock timeout enable
            #[inline(always)]
            pub fn timouten(&mut self) -> TIMOUTEN_W {
                TIMOUTEN_W { w: self }
            }
            ///Bits 16:27 - Bus timeout B
            #[inline(always)]
            pub fn timeoutb(&mut self) -> TIMEOUTB_W {
                TIMEOUTB_W { w: self }
            }
            ///Bit 31 - Extended clock timeout enable
            #[inline(always)]
            pub fn texten(&mut self) -> TEXTEN_W {
                TEXTEN_W { w: self }
            }
        }
    }
    ///Interrupt and Status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///`write(|w| ..)` method takes [isr::W](isr::W) writer structure
    impl crate::Writable for ISR {}
    ///Interrupt and Status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Writer for register ISR
        pub type W = crate::W<u32, super::ISR>;
        ///Register ISR `reset()`'s with value 0x01
        impl crate::ResetValue for super::ISR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x01
            }
        }
        ///Reader of field `ADDCODE`
        pub type ADDCODE_R = crate::R<u8, u8>;
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Reader of field `BUSY`
        pub type BUSY_R = crate::R<bool, bool>;
        ///Reader of field `ALERT`
        pub type ALERT_R = crate::R<bool, bool>;
        ///Reader of field `TIMEOUT`
        pub type TIMEOUT_R = crate::R<bool, bool>;
        ///Reader of field `PECERR`
        pub type PECERR_R = crate::R<bool, bool>;
        ///Reader of field `OVR`
        pub type OVR_R = crate::R<bool, bool>;
        ///Reader of field `ARLO`
        pub type ARLO_R = crate::R<bool, bool>;
        ///Reader of field `BERR`
        pub type BERR_R = crate::R<bool, bool>;
        ///Reader of field `TCR`
        pub type TCR_R = crate::R<bool, bool>;
        ///Reader of field `TC`
        pub type TC_R = crate::R<bool, bool>;
        ///Reader of field `STOPF`
        pub type STOPF_R = crate::R<bool, bool>;
        ///Reader of field `NACKF`
        pub type NACKF_R = crate::R<bool, bool>;
        ///Reader of field `ADDR`
        pub type ADDR_R = crate::R<bool, bool>;
        ///Reader of field `RXNE`
        pub type RXNE_R = crate::R<bool, bool>;
        ///Reader of field `TXIS`
        pub type TXIS_R = crate::R<bool, bool>;
        ///Write proxy for field `TXIS`
        pub struct TXIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `TXE`
        pub type TXE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXE`
        pub struct TXE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 17:23 - Address match code (Slave mode)
            #[inline(always)]
            pub fn addcode(&self) -> ADDCODE_R {
                ADDCODE_R::new(((self.bits >> 17) & 0x7f) as u8)
            }
            ///Bit 16 - Transfer direction (Slave mode)
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Bus busy
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 13 - SMBus alert
            #[inline(always)]
            pub fn alert(&self) -> ALERT_R {
                ALERT_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Timeout or t_low detection flag
            #[inline(always)]
            pub fn timeout(&self) -> TIMEOUT_R {
                TIMEOUT_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - PEC Error in reception
            #[inline(always)]
            pub fn pecerr(&self) -> PECERR_R {
                PECERR_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Overrun/Underrun (slave mode)
            #[inline(always)]
            pub fn ovr(&self) -> OVR_R {
                OVR_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Arbitration lost
            #[inline(always)]
            pub fn arlo(&self) -> ARLO_R {
                ARLO_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Bus error
            #[inline(always)]
            pub fn berr(&self) -> BERR_R {
                BERR_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Transfer Complete Reload
            #[inline(always)]
            pub fn tcr(&self) -> TCR_R {
                TCR_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Transfer Complete (master mode)
            #[inline(always)]
            pub fn tc(&self) -> TC_R {
                TC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Stop detection flag
            #[inline(always)]
            pub fn stopf(&self) -> STOPF_R {
                STOPF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Not acknowledge received flag
            #[inline(always)]
            pub fn nackf(&self) -> NACKF_R {
                NACKF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Address matched (slave mode)
            #[inline(always)]
            pub fn addr(&self) -> ADDR_R {
                ADDR_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Receive data register not empty (receivers)
            #[inline(always)]
            pub fn rxne(&self) -> RXNE_R {
                RXNE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transmit interrupt status (transmitters)
            #[inline(always)]
            pub fn txis(&self) -> TXIS_R {
                TXIS_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Transmit data register empty (transmitters)
            #[inline(always)]
            pub fn txe(&self) -> TXE_R {
                TXE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 1 - Transmit interrupt status (transmitters)
            #[inline(always)]
            pub fn txis(&mut self) -> TXIS_W {
                TXIS_W { w: self }
            }
            ///Bit 0 - Transmit data register empty (transmitters)
            #[inline(always)]
            pub fn txe(&mut self) -> TXE_W {
                TXE_W { w: self }
            }
        }
    }
    ///Interrupt clear register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [icr](icr) module
    pub type ICR = crate::Reg<u32, _ICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ICR;
    ///`write(|w| ..)` method takes [icr::W](icr::W) writer structure
    impl crate::Writable for ICR {}
    ///Interrupt clear register
    pub mod icr {
        ///Writer for register ICR
        pub type W = crate::W<u32, super::ICR>;
        ///Register ICR `reset()`'s with value 0
        impl crate::ResetValue for super::ICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `ALERTCF`
        pub struct ALERTCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALERTCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `TIMOUTCF`
        pub struct TIMOUTCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIMOUTCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `PECCF`
        pub struct PECCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PECCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `OVRCF`
        pub struct OVRCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVRCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `ARLOCF`
        pub struct ARLOCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARLOCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `BERRCF`
        pub struct BERRCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BERRCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `STOPCF`
        pub struct STOPCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STOPCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `NACKCF`
        pub struct NACKCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NACKCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `ADDRCF`
        pub struct ADDRCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDRCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        impl W {
            ///Bit 13 - Alert flag clear
            #[inline(always)]
            pub fn alertcf(&mut self) -> ALERTCF_W {
                ALERTCF_W { w: self }
            }
            ///Bit 12 - Timeout detection flag clear
            #[inline(always)]
            pub fn timoutcf(&mut self) -> TIMOUTCF_W {
                TIMOUTCF_W { w: self }
            }
            ///Bit 11 - PEC Error flag clear
            #[inline(always)]
            pub fn peccf(&mut self) -> PECCF_W {
                PECCF_W { w: self }
            }
            ///Bit 10 - Overrun/Underrun flag clear
            #[inline(always)]
            pub fn ovrcf(&mut self) -> OVRCF_W {
                OVRCF_W { w: self }
            }
            ///Bit 9 - Arbitration lost flag clear
            #[inline(always)]
            pub fn arlocf(&mut self) -> ARLOCF_W {
                ARLOCF_W { w: self }
            }
            ///Bit 8 - Bus error flag clear
            #[inline(always)]
            pub fn berrcf(&mut self) -> BERRCF_W {
                BERRCF_W { w: self }
            }
            ///Bit 5 - Stop detection flag clear
            #[inline(always)]
            pub fn stopcf(&mut self) -> STOPCF_W {
                STOPCF_W { w: self }
            }
            ///Bit 4 - Not Acknowledge flag clear
            #[inline(always)]
            pub fn nackcf(&mut self) -> NACKCF_W {
                NACKCF_W { w: self }
            }
            ///Bit 3 - Address Matched flag clear
            #[inline(always)]
            pub fn addrcf(&mut self) -> ADDRCF_W {
                ADDRCF_W { w: self }
            }
        }
    }
    ///PEC register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pecr](pecr) module
    pub type PECR = crate::Reg<u32, _PECR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PECR;
    ///`read()` method returns [pecr::R](pecr::R) reader structure
    impl crate::Readable for PECR {}
    ///PEC register
    pub mod pecr {
        ///Reader of register PECR
        pub type R = crate::R<u32, super::PECR>;
        ///Reader of field `PEC`
        pub type PEC_R = crate::R<u8, u8>;
        impl R {
            ///Bits 0:7 - Packet error checking register
            #[inline(always)]
            pub fn pec(&self) -> PEC_R {
                PEC_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Receive data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rxdr](rxdr) module
    pub type RXDR = crate::Reg<u32, _RXDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RXDR;
    ///`read()` method returns [rxdr::R](rxdr::R) reader structure
    impl crate::Readable for RXDR {}
    ///Receive data register
    pub mod rxdr {
        ///Reader of register RXDR
        pub type R = crate::R<u32, super::RXDR>;
        ///Reader of field `RXDATA`
        pub type RXDATA_R = crate::R<u8, u8>;
        impl R {
            ///Bits 0:7 - 8-bit receive data
            #[inline(always)]
            pub fn rxdata(&self) -> RXDATA_R {
                RXDATA_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Transmit data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [txdr](txdr) module
    pub type TXDR = crate::Reg<u32, _TXDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TXDR;
    ///`read()` method returns [txdr::R](txdr::R) reader structure
    impl crate::Readable for TXDR {}
    ///`write(|w| ..)` method takes [txdr::W](txdr::W) writer structure
    impl crate::Writable for TXDR {}
    ///Transmit data register
    pub mod txdr {
        ///Reader of register TXDR
        pub type R = crate::R<u32, super::TXDR>;
        ///Writer for register TXDR
        pub type W = crate::W<u32, super::TXDR>;
        ///Register TXDR `reset()`'s with value 0
        impl crate::ResetValue for super::TXDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TXDATA`
        pub type TXDATA_R = crate::R<u8, u8>;
        ///Write proxy for field `TXDATA`
        pub struct TXDATA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXDATA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - 8-bit transmit data
            #[inline(always)]
            pub fn txdata(&self) -> TXDATA_R {
                TXDATA_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - 8-bit transmit data
            #[inline(always)]
            pub fn txdata(&mut self) -> TXDATA_W {
                TXDATA_W { w: self }
            }
        }
    }
}
///Inter-integrated circuit
pub struct I2C3 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C3 {}
impl I2C3 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const i2c1::RegisterBlock {
        0x4000_5c00 as *const _
    }
}
impl Deref for I2C3 {
    type Target = i2c1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*I2C3::ptr() }
    }
}
///Flash
pub struct FLASH {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for FLASH {}
impl FLASH {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const flash::RegisterBlock {
        0x5800_4000 as *const _
    }
}
impl Deref for FLASH {
    type Target = flash::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*FLASH::ptr() }
    }
}
///Flash
pub mod flash {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Access control register
        pub acr: ACR,
        _reserved1: [u8; 4usize],
        ///0x08 - Flash key register
        pub keyr: KEYR,
        ///0x0c - Option byte key register
        pub optkeyr: OPTKEYR,
        ///0x10 - Status register
        pub sr: SR,
        ///0x14 - Flash control register
        pub cr: CR,
        ///0x18 - Flash ECC register
        pub eccr: ECCR,
        _reserved6: [u8; 4usize],
        ///0x20 - Flash option register
        pub optr: OPTR,
        ///0x24 - Flash Bank 1 PCROP Start address zone A register
        pub pcrop1asr: PCROP1ASR,
        ///0x28 - Flash Bank 1 PCROP End address zone A register
        pub pcrop1aer: PCROP1AER,
        ///0x2c - Flash Bank 1 WRP area A address register
        pub wrp1ar: WRP1AR,
        ///0x30 - Flash Bank 1 WRP area B address register
        pub wrp1br: WRP1BR,
        ///0x34 - Flash Bank 1 PCROP Start address area B register
        pub pcrop1bsr: PCROP1BSR,
        ///0x38 - Flash Bank 1 PCROP End address area B register
        pub pcrop1ber: PCROP1BER,
        ///0x3c - IPCC mailbox data buffer address register
        pub ipccbr: IPCCBR,
        _reserved14: [u8; 28usize],
        ///0x5c - CPU2 cortex M0 access control register
        pub c2acr: C2ACR,
        ///0x60 - CPU2 cortex M0 status register
        pub c2sr: C2SR,
        ///0x64 - CPU2 cortex M0 control register
        pub c2cr: C2CR,
        _reserved17: [u8; 24usize],
        ///0x80 - Secure flash start address register
        pub sfr: SFR,
        ///0x84 - Secure SRAM2 start address and cortex M0 reset vector register
        pub srrvr: SRRVR,
    }
    ///Access control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [acr](acr) module
    pub type ACR = crate::Reg<u32, _ACR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ACR;
    ///`read()` method returns [acr::R](acr::R) reader structure
    impl crate::Readable for ACR {}
    ///`write(|w| ..)` method takes [acr::W](acr::W) writer structure
    impl crate::Writable for ACR {}
    ///Access control register
    pub mod acr {
        ///Reader of register ACR
        pub type R = crate::R<u32, super::ACR>;
        ///Writer for register ACR
        pub type W = crate::W<u32, super::ACR>;
        ///Register ACR `reset()`'s with value 0x0600
        impl crate::ResetValue for super::ACR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0600
            }
        }
        ///Reader of field `LATENCY`
        pub type LATENCY_R = crate::R<u8, u8>;
        ///Write proxy for field `LATENCY`
        pub struct LATENCY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LATENCY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        ///Reader of field `PRFTEN`
        pub type PRFTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PRFTEN`
        pub struct PRFTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRFTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `ICEN`
        pub type ICEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ICEN`
        pub struct ICEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ICEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `DCEN`
        pub type DCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DCEN`
        pub struct DCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `ICRST`
        pub type ICRST_R = crate::R<bool, bool>;
        ///Write proxy for field `ICRST`
        pub struct ICRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ICRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `DCRST`
        pub type DCRST_R = crate::R<bool, bool>;
        ///Write proxy for field `DCRST`
        pub struct DCRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DCRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PES`
        pub type PES_R = crate::R<bool, bool>;
        ///Write proxy for field `PES`
        pub struct PES_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PES_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `EMPTY`
        pub type EMPTY_R = crate::R<bool, bool>;
        ///Write proxy for field `EMPTY`
        pub struct EMPTY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EMPTY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        impl R {
            ///Bits 0:2 - Latency
            #[inline(always)]
            pub fn latency(&self) -> LATENCY_R {
                LATENCY_R::new((self.bits & 0x07) as u8)
            }
            ///Bit 8 - Prefetch enable
            #[inline(always)]
            pub fn prften(&self) -> PRFTEN_R {
                PRFTEN_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Instruction cache enable
            #[inline(always)]
            pub fn icen(&self) -> ICEN_R {
                ICEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Data cache enable
            #[inline(always)]
            pub fn dcen(&self) -> DCEN_R {
                DCEN_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Instruction cache reset
            #[inline(always)]
            pub fn icrst(&self) -> ICRST_R {
                ICRST_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Data cache reset
            #[inline(always)]
            pub fn dcrst(&self) -> DCRST_R {
                DCRST_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 15 - CPU1 CortexM4 program erase suspend request
            #[inline(always)]
            pub fn pes(&self) -> PES_R {
                PES_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Flash User area empty
            #[inline(always)]
            pub fn empty(&self) -> EMPTY_R {
                EMPTY_R::new(((self.bits >> 16) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:2 - Latency
            #[inline(always)]
            pub fn latency(&mut self) -> LATENCY_W {
                LATENCY_W { w: self }
            }
            ///Bit 8 - Prefetch enable
            #[inline(always)]
            pub fn prften(&mut self) -> PRFTEN_W {
                PRFTEN_W { w: self }
            }
            ///Bit 9 - Instruction cache enable
            #[inline(always)]
            pub fn icen(&mut self) -> ICEN_W {
                ICEN_W { w: self }
            }
            ///Bit 10 - Data cache enable
            #[inline(always)]
            pub fn dcen(&mut self) -> DCEN_W {
                DCEN_W { w: self }
            }
            ///Bit 11 - Instruction cache reset
            #[inline(always)]
            pub fn icrst(&mut self) -> ICRST_W {
                ICRST_W { w: self }
            }
            ///Bit 12 - Data cache reset
            #[inline(always)]
            pub fn dcrst(&mut self) -> DCRST_W {
                DCRST_W { w: self }
            }
            ///Bit 15 - CPU1 CortexM4 program erase suspend request
            #[inline(always)]
            pub fn pes(&mut self) -> PES_W {
                PES_W { w: self }
            }
            ///Bit 16 - Flash User area empty
            #[inline(always)]
            pub fn empty(&mut self) -> EMPTY_W {
                EMPTY_W { w: self }
            }
        }
    }
    ///Flash key register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr](keyr) module
    pub type KEYR = crate::Reg<u32, _KEYR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR;
    ///`write(|w| ..)` method takes [keyr::W](keyr::W) writer structure
    impl crate::Writable for KEYR {}
    ///Flash key register
    pub mod keyr {
        ///Writer for register KEYR
        pub type W = crate::W<u32, super::KEYR>;
        ///Register KEYR `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `KEYR`
        pub struct KEYR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEYR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl W {
            ///Bits 0:31 - KEYR
            #[inline(always)]
            pub fn keyr(&mut self) -> KEYR_W {
                KEYR_W { w: self }
            }
        }
    }
    ///Option byte key register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [optkeyr](optkeyr) module
    pub type OPTKEYR = crate::Reg<u32, _OPTKEYR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OPTKEYR;
    ///`write(|w| ..)` method takes [optkeyr::W](optkeyr::W) writer structure
    impl crate::Writable for OPTKEYR {}
    ///Option byte key register
    pub mod optkeyr {
        ///Writer for register OPTKEYR
        pub type W = crate::W<u32, super::OPTKEYR>;
        ///Register OPTKEYR `reset()`'s with value 0
        impl crate::ResetValue for super::OPTKEYR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `OPTKEYR`
        pub struct OPTKEYR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPTKEYR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl W {
            ///Bits 0:31 - Option byte key
            #[inline(always)]
            pub fn optkeyr(&mut self) -> OPTKEYR_W {
                OPTKEYR_W { w: self }
            }
        }
    }
    ///Status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///Status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EOP`
        pub type EOP_R = crate::R<bool, bool>;
        ///Write proxy for field `EOP`
        pub struct EOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `OPERR`
        pub type OPERR_R = crate::R<bool, bool>;
        ///Write proxy for field `OPERR`
        pub struct OPERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PROGERR`
        pub type PROGERR_R = crate::R<bool, bool>;
        ///Write proxy for field `PROGERR`
        pub struct PROGERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROGERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `WRPERR`
        pub type WRPERR_R = crate::R<bool, bool>;
        ///Write proxy for field `WRPERR`
        pub struct WRPERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WRPERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PGAERR`
        pub type PGAERR_R = crate::R<bool, bool>;
        ///Write proxy for field `PGAERR`
        pub struct PGAERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PGAERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `SIZERR`
        pub type SIZERR_R = crate::R<bool, bool>;
        ///Write proxy for field `SIZERR`
        pub struct SIZERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SIZERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PGSERR`
        pub type PGSERR_R = crate::R<bool, bool>;
        ///Write proxy for field `PGSERR`
        pub struct PGSERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PGSERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `MISERR`
        pub type MISERR_R = crate::R<bool, bool>;
        ///Write proxy for field `MISERR`
        pub struct MISERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MISERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `FASTERR`
        pub type FASTERR_R = crate::R<bool, bool>;
        ///Write proxy for field `FASTERR`
        pub struct FASTERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FASTERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OPTNV`
        pub type OPTNV_R = crate::R<bool, bool>;
        ///Reader of field `RDERR`
        pub type RDERR_R = crate::R<bool, bool>;
        ///Write proxy for field `RDERR`
        pub struct RDERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RDERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `OPTVERR`
        pub type OPTVERR_R = crate::R<bool, bool>;
        ///Write proxy for field `OPTVERR`
        pub struct OPTVERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPTVERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `BSY`
        pub type BSY_R = crate::R<bool, bool>;
        ///Reader of field `CFGBSY`
        pub type CFGBSY_R = crate::R<bool, bool>;
        ///Reader of field `PESD`
        pub type PESD_R = crate::R<bool, bool>;
        impl R {
            ///Bit 0 - End of operation
            #[inline(always)]
            pub fn eop(&self) -> EOP_R {
                EOP_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Operation error
            #[inline(always)]
            pub fn operr(&self) -> OPERR_R {
                OPERR_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 3 - Programming error
            #[inline(always)]
            pub fn progerr(&self) -> PROGERR_R {
                PROGERR_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Write protected error
            #[inline(always)]
            pub fn wrperr(&self) -> WRPERR_R {
                WRPERR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Programming alignment error
            #[inline(always)]
            pub fn pgaerr(&self) -> PGAERR_R {
                PGAERR_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Size error
            #[inline(always)]
            pub fn sizerr(&self) -> SIZERR_R {
                SIZERR_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Programming sequence error
            #[inline(always)]
            pub fn pgserr(&self) -> PGSERR_R {
                PGSERR_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Fast programming data miss error
            #[inline(always)]
            pub fn miserr(&self) -> MISERR_R {
                MISERR_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Fast programming error
            #[inline(always)]
            pub fn fasterr(&self) -> FASTERR_R {
                FASTERR_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 13 - User Option OPTVAL indication
            #[inline(always)]
            pub fn optnv(&self) -> OPTNV_R {
                OPTNV_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - PCROP read error
            #[inline(always)]
            pub fn rderr(&self) -> RDERR_R {
                RDERR_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Option validity error
            #[inline(always)]
            pub fn optverr(&self) -> OPTVERR_R {
                OPTVERR_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Busy
            #[inline(always)]
            pub fn bsy(&self) -> BSY_R {
                BSY_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 18 - Programming or erase configuration busy
            #[inline(always)]
            pub fn cfgbsy(&self) -> CFGBSY_R {
                CFGBSY_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - Programming or erase operation suspended
            #[inline(always)]
            pub fn pesd(&self) -> PESD_R {
                PESD_R::new(((self.bits >> 19) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - End of operation
            #[inline(always)]
            pub fn eop(&mut self) -> EOP_W {
                EOP_W { w: self }
            }
            ///Bit 1 - Operation error
            #[inline(always)]
            pub fn operr(&mut self) -> OPERR_W {
                OPERR_W { w: self }
            }
            ///Bit 3 - Programming error
            #[inline(always)]
            pub fn progerr(&mut self) -> PROGERR_W {
                PROGERR_W { w: self }
            }
            ///Bit 4 - Write protected error
            #[inline(always)]
            pub fn wrperr(&mut self) -> WRPERR_W {
                WRPERR_W { w: self }
            }
            ///Bit 5 - Programming alignment error
            #[inline(always)]
            pub fn pgaerr(&mut self) -> PGAERR_W {
                PGAERR_W { w: self }
            }
            ///Bit 6 - Size error
            #[inline(always)]
            pub fn sizerr(&mut self) -> SIZERR_W {
                SIZERR_W { w: self }
            }
            ///Bit 7 - Programming sequence error
            #[inline(always)]
            pub fn pgserr(&mut self) -> PGSERR_W {
                PGSERR_W { w: self }
            }
            ///Bit 8 - Fast programming data miss error
            #[inline(always)]
            pub fn miserr(&mut self) -> MISERR_W {
                MISERR_W { w: self }
            }
            ///Bit 9 - Fast programming error
            #[inline(always)]
            pub fn fasterr(&mut self) -> FASTERR_W {
                FASTERR_W { w: self }
            }
            ///Bit 14 - PCROP read error
            #[inline(always)]
            pub fn rderr(&mut self) -> RDERR_W {
                RDERR_W { w: self }
            }
            ///Bit 15 - Option validity error
            #[inline(always)]
            pub fn optverr(&mut self) -> OPTVERR_W {
                OPTVERR_W { w: self }
            }
        }
    }
    ///Flash control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Flash control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0xc000_0000
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xc000_0000
            }
        }
        ///Reader of field `PG`
        pub type PG_R = crate::R<bool, bool>;
        ///Write proxy for field `PG`
        pub struct PG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `PER`
        pub type PER_R = crate::R<bool, bool>;
        ///Write proxy for field `PER`
        pub struct PER_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PER_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `MER`
        pub type MER_R = crate::R<bool, bool>;
        ///Write proxy for field `MER`
        pub struct MER_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MER_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PNB`
        pub type PNB_R = crate::R<u8, u8>;
        ///Write proxy for field `PNB`
        pub struct PNB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PNB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 3)) | (((value as u32) & 0xff) << 3);
                self.w
            }
        }
        ///Reader of field `STRT`
        pub type STRT_R = crate::R<bool, bool>;
        ///Write proxy for field `STRT`
        pub struct STRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STRT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OPTSTRT`
        pub type OPTSTRT_R = crate::R<bool, bool>;
        ///Write proxy for field `OPTSTRT`
        pub struct OPTSTRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPTSTRT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `FSTPG`
        pub type FSTPG_R = crate::R<bool, bool>;
        ///Write proxy for field `FSTPG`
        pub struct FSTPG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FSTPG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `EOPIE`
        pub type EOPIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EOPIE`
        pub struct EOPIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOPIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `ERRIE`
        pub type ERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRIE`
        pub struct ERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `RDERRIE`
        pub type RDERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RDERRIE`
        pub struct RDERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RDERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `OBL_LAUNCH`
        pub type OBL_LAUNCH_R = crate::R<bool, bool>;
        ///Write proxy for field `OBL_LAUNCH`
        pub struct OBL_LAUNCH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OBL_LAUNCH_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `OPTLOCK`
        pub type OPTLOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `OPTLOCK`
        pub struct OPTLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPTLOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Programming
            #[inline(always)]
            pub fn pg(&self) -> PG_R {
                PG_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Page erase
            #[inline(always)]
            pub fn per(&self) -> PER_R {
                PER_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - This bit triggers the mass erase (all user pages) when set
            #[inline(always)]
            pub fn mer(&self) -> MER_R {
                MER_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bits 3:10 - Page number selection
            #[inline(always)]
            pub fn pnb(&self) -> PNB_R {
                PNB_R::new(((self.bits >> 3) & 0xff) as u8)
            }
            ///Bit 16 - Start
            #[inline(always)]
            pub fn strt(&self) -> STRT_R {
                STRT_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Options modification start
            #[inline(always)]
            pub fn optstrt(&self) -> OPTSTRT_R {
                OPTSTRT_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - Fast programming
            #[inline(always)]
            pub fn fstpg(&self) -> FSTPG_R {
                FSTPG_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 24 - End of operation interrupt enable
            #[inline(always)]
            pub fn eopie(&self) -> EOPIE_R {
                EOPIE_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 25 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&self) -> ERRIE_R {
                ERRIE_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 26 - PCROP read error interrupt enable
            #[inline(always)]
            pub fn rderrie(&self) -> RDERRIE_R {
                RDERRIE_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 27 - Force the option byte loading
            #[inline(always)]
            pub fn obl_launch(&self) -> OBL_LAUNCH_R {
                OBL_LAUNCH_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 30 - Options Lock
            #[inline(always)]
            pub fn optlock(&self) -> OPTLOCK_R {
                OPTLOCK_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - FLASH_CR Lock
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Programming
            #[inline(always)]
            pub fn pg(&mut self) -> PG_W {
                PG_W { w: self }
            }
            ///Bit 1 - Page erase
            #[inline(always)]
            pub fn per(&mut self) -> PER_W {
                PER_W { w: self }
            }
            ///Bit 2 - This bit triggers the mass erase (all user pages) when set
            #[inline(always)]
            pub fn mer(&mut self) -> MER_W {
                MER_W { w: self }
            }
            ///Bits 3:10 - Page number selection
            #[inline(always)]
            pub fn pnb(&mut self) -> PNB_W {
                PNB_W { w: self }
            }
            ///Bit 16 - Start
            #[inline(always)]
            pub fn strt(&mut self) -> STRT_W {
                STRT_W { w: self }
            }
            ///Bit 17 - Options modification start
            #[inline(always)]
            pub fn optstrt(&mut self) -> OPTSTRT_W {
                OPTSTRT_W { w: self }
            }
            ///Bit 18 - Fast programming
            #[inline(always)]
            pub fn fstpg(&mut self) -> FSTPG_W {
                FSTPG_W { w: self }
            }
            ///Bit 24 - End of operation interrupt enable
            #[inline(always)]
            pub fn eopie(&mut self) -> EOPIE_W {
                EOPIE_W { w: self }
            }
            ///Bit 25 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&mut self) -> ERRIE_W {
                ERRIE_W { w: self }
            }
            ///Bit 26 - PCROP read error interrupt enable
            #[inline(always)]
            pub fn rderrie(&mut self) -> RDERRIE_W {
                RDERRIE_W { w: self }
            }
            ///Bit 27 - Force the option byte loading
            #[inline(always)]
            pub fn obl_launch(&mut self) -> OBL_LAUNCH_W {
                OBL_LAUNCH_W { w: self }
            }
            ///Bit 30 - Options Lock
            #[inline(always)]
            pub fn optlock(&mut self) -> OPTLOCK_W {
                OPTLOCK_W { w: self }
            }
            ///Bit 31 - FLASH_CR Lock
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
        }
    }
    ///Flash ECC register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [eccr](eccr) module
    pub type ECCR = crate::Reg<u32, _ECCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ECCR;
    ///`read()` method returns [eccr::R](eccr::R) reader structure
    impl crate::Readable for ECCR {}
    ///`write(|w| ..)` method takes [eccr::W](eccr::W) writer structure
    impl crate::Writable for ECCR {}
    ///Flash ECC register
    pub mod eccr {
        ///Reader of register ECCR
        pub type R = crate::R<u32, super::ECCR>;
        ///Writer for register ECCR
        pub type W = crate::W<u32, super::ECCR>;
        ///Register ECCR `reset()`'s with value 0
        impl crate::ResetValue for super::ECCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR_ECC`
        pub type ADDR_ECC_R = crate::R<u32, u32>;
        ///Reader of field `SYSF_ECC`
        pub type SYSF_ECC_R = crate::R<bool, bool>;
        ///Reader of field `ECCCIE`
        pub type ECCCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ECCCIE`
        pub struct ECCCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ECCCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `CPUID`
        pub type CPUID_R = crate::R<u8, u8>;
        ///Reader of field `ECCC`
        pub type ECCC_R = crate::R<bool, bool>;
        ///Write proxy for field `ECCC`
        pub struct ECCC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ECCC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `ECCD`
        pub type ECCD_R = crate::R<bool, bool>;
        ///Write proxy for field `ECCD`
        pub struct ECCD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ECCD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:16 - ECC fail address
            #[inline(always)]
            pub fn addr_ecc(&self) -> ADDR_ECC_R {
                ADDR_ECC_R::new((self.bits & 0x0001_ffff) as u32)
            }
            ///Bit 20 - System Flash ECC fail
            #[inline(always)]
            pub fn sysf_ecc(&self) -> SYSF_ECC_R {
                SYSF_ECC_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 24 - ECC correction interrupt enable
            #[inline(always)]
            pub fn ecccie(&self) -> ECCCIE_R {
                ECCCIE_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bits 26:28 - CPU identification
            #[inline(always)]
            pub fn cpuid(&self) -> CPUID_R {
                CPUID_R::new(((self.bits >> 26) & 0x07) as u8)
            }
            ///Bit 30 - ECC correction
            #[inline(always)]
            pub fn eccc(&self) -> ECCC_R {
                ECCC_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - ECC detection
            #[inline(always)]
            pub fn eccd(&self) -> ECCD_R {
                ECCD_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 24 - ECC correction interrupt enable
            #[inline(always)]
            pub fn ecccie(&mut self) -> ECCCIE_W {
                ECCCIE_W { w: self }
            }
            ///Bit 30 - ECC correction
            #[inline(always)]
            pub fn eccc(&mut self) -> ECCC_W {
                ECCC_W { w: self }
            }
            ///Bit 31 - ECC detection
            #[inline(always)]
            pub fn eccd(&mut self) -> ECCD_W {
                ECCD_W { w: self }
            }
        }
    }
    ///Flash option register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [optr](optr) module
    pub type OPTR = crate::Reg<u32, _OPTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OPTR;
    ///`read()` method returns [optr::R](optr::R) reader structure
    impl crate::Readable for OPTR {}
    ///`write(|w| ..)` method takes [optr::W](optr::W) writer structure
    impl crate::Writable for OPTR {}
    ///Flash option register
    pub mod optr {
        ///Reader of register OPTR
        pub type R = crate::R<u32, super::OPTR>;
        ///Writer for register OPTR
        pub type W = crate::W<u32, super::OPTR>;
        ///Register OPTR `reset()`'s with value 0x1070_8000
        impl crate::ResetValue for super::OPTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x1070_8000
            }
        }
        ///Reader of field `RDP`
        pub type RDP_R = crate::R<u8, u8>;
        ///Write proxy for field `RDP`
        pub struct RDP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RDP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        ///Reader of field `ESE`
        pub type ESE_R = crate::R<bool, bool>;
        ///Write proxy for field `ESE`
        pub struct ESE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ESE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `BOR_LEV`
        pub type BOR_LEV_R = crate::R<u8, u8>;
        ///Write proxy for field `BOR_LEV`
        pub struct BOR_LEV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BOR_LEV_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 9)) | (((value as u32) & 0x07) << 9);
                self.w
            }
        }
        ///Reader of field `nRST_STOP`
        pub type NRST_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `nRST_STOP`
        pub struct NRST_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NRST_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `nRST_STDBY`
        pub type NRST_STDBY_R = crate::R<bool, bool>;
        ///Write proxy for field `nRST_STDBY`
        pub struct NRST_STDBY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NRST_STDBY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `nRST_SHDW`
        pub type NRST_SHDW_R = crate::R<bool, bool>;
        ///Write proxy for field `nRST_SHDW`
        pub struct NRST_SHDW_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NRST_SHDW_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `IDWG_SW`
        pub type IDWG_SW_R = crate::R<bool, bool>;
        ///Write proxy for field `IDWG_SW`
        pub struct IDWG_SW_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IDWG_SW_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `IWDG_STOP`
        pub type IWDG_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `IWDG_STOP`
        pub struct IWDG_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IWDG_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `IWDG_STDBY`
        pub type IWDG_STDBY_R = crate::R<bool, bool>;
        ///Write proxy for field `IWDG_STDBY`
        pub struct IWDG_STDBY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IWDG_STDBY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `WWDG_SW`
        pub type WWDG_SW_R = crate::R<bool, bool>;
        ///Write proxy for field `WWDG_SW`
        pub struct WWDG_SW_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WWDG_SW_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `nBOOT1`
        pub type NBOOT1_R = crate::R<bool, bool>;
        ///Write proxy for field `nBOOT1`
        pub struct NBOOT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBOOT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `SRAM2_PE`
        pub type SRAM2_PE_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM2_PE`
        pub struct SRAM2_PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM2_PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `SRAM2_RST`
        pub type SRAM2_RST_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM2_RST`
        pub struct SRAM2_RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM2_RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `nSWBOOT0`
        pub type NSWBOOT0_R = crate::R<bool, bool>;
        ///Write proxy for field `nSWBOOT0`
        pub struct NSWBOOT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NSWBOOT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `nBOOT0`
        pub type NBOOT0_R = crate::R<bool, bool>;
        ///Write proxy for field `nBOOT0`
        pub struct NBOOT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBOOT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `AGC_TRIM`
        pub type AGC_TRIM_R = crate::R<u8, u8>;
        ///Write proxy for field `AGC_TRIM`
        pub struct AGC_TRIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AGC_TRIM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Read protection level
            #[inline(always)]
            pub fn rdp(&self) -> RDP_R {
                RDP_R::new((self.bits & 0xff) as u8)
            }
            ///Bit 8 - Security enabled
            #[inline(always)]
            pub fn ese(&self) -> ESE_R {
                ESE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:11 - BOR reset Level
            #[inline(always)]
            pub fn bor_lev(&self) -> BOR_LEV_R {
                BOR_LEV_R::new(((self.bits >> 9) & 0x07) as u8)
            }
            ///Bit 12 - nRST_STOP
            #[inline(always)]
            pub fn n_rst_stop(&self) -> NRST_STOP_R {
                NRST_STOP_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - nRST_STDBY
            #[inline(always)]
            pub fn n_rst_stdby(&self) -> NRST_STDBY_R {
                NRST_STDBY_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - nRST_SHDW
            #[inline(always)]
            pub fn n_rst_shdw(&self) -> NRST_SHDW_R {
                NRST_SHDW_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 16 - Independent watchdog selection
            #[inline(always)]
            pub fn idwg_sw(&self) -> IDWG_SW_R {
                IDWG_SW_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Independent watchdog counter freeze in Stop mode
            #[inline(always)]
            pub fn iwdg_stop(&self) -> IWDG_STOP_R {
                IWDG_STOP_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - Independent watchdog counter freeze in Standby mode
            #[inline(always)]
            pub fn iwdg_stdby(&self) -> IWDG_STDBY_R {
                IWDG_STDBY_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - Window watchdog selection
            #[inline(always)]
            pub fn wwdg_sw(&self) -> WWDG_SW_R {
                WWDG_SW_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 23 - Boot configuration
            #[inline(always)]
            pub fn n_boot1(&self) -> NBOOT1_R {
                NBOOT1_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 24 - SRAM2 parity check enable
            #[inline(always)]
            pub fn sram2_pe(&self) -> SRAM2_PE_R {
                SRAM2_PE_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 25 - SRAM2 Erase when system reset
            #[inline(always)]
            pub fn sram2_rst(&self) -> SRAM2_RST_R {
                SRAM2_RST_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 26 - Software Boot0
            #[inline(always)]
            pub fn n_swboot0(&self) -> NSWBOOT0_R {
                NSWBOOT0_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 27 - nBoot0 option bit
            #[inline(always)]
            pub fn n_boot0(&self) -> NBOOT0_R {
                NBOOT0_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bits 29:31 - Radio Automatic Gain Control Trimming
            #[inline(always)]
            pub fn agc_trim(&self) -> AGC_TRIM_R {
                AGC_TRIM_R::new(((self.bits >> 29) & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - Read protection level
            #[inline(always)]
            pub fn rdp(&mut self) -> RDP_W {
                RDP_W { w: self }
            }
            ///Bit 8 - Security enabled
            #[inline(always)]
            pub fn ese(&mut self) -> ESE_W {
                ESE_W { w: self }
            }
            ///Bits 9:11 - BOR reset Level
            #[inline(always)]
            pub fn bor_lev(&mut self) -> BOR_LEV_W {
                BOR_LEV_W { w: self }
            }
            ///Bit 12 - nRST_STOP
            #[inline(always)]
            pub fn n_rst_stop(&mut self) -> NRST_STOP_W {
                NRST_STOP_W { w: self }
            }
            ///Bit 13 - nRST_STDBY
            #[inline(always)]
            pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W {
                NRST_STDBY_W { w: self }
            }
            ///Bit 14 - nRST_SHDW
            #[inline(always)]
            pub fn n_rst_shdw(&mut self) -> NRST_SHDW_W {
                NRST_SHDW_W { w: self }
            }
            ///Bit 16 - Independent watchdog selection
            #[inline(always)]
            pub fn idwg_sw(&mut self) -> IDWG_SW_W {
                IDWG_SW_W { w: self }
            }
            ///Bit 17 - Independent watchdog counter freeze in Stop mode
            #[inline(always)]
            pub fn iwdg_stop(&mut self) -> IWDG_STOP_W {
                IWDG_STOP_W { w: self }
            }
            ///Bit 18 - Independent watchdog counter freeze in Standby mode
            #[inline(always)]
            pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W {
                IWDG_STDBY_W { w: self }
            }
            ///Bit 19 - Window watchdog selection
            #[inline(always)]
            pub fn wwdg_sw(&mut self) -> WWDG_SW_W {
                WWDG_SW_W { w: self }
            }
            ///Bit 23 - Boot configuration
            #[inline(always)]
            pub fn n_boot1(&mut self) -> NBOOT1_W {
                NBOOT1_W { w: self }
            }
            ///Bit 24 - SRAM2 parity check enable
            #[inline(always)]
            pub fn sram2_pe(&mut self) -> SRAM2_PE_W {
                SRAM2_PE_W { w: self }
            }
            ///Bit 25 - SRAM2 Erase when system reset
            #[inline(always)]
            pub fn sram2_rst(&mut self) -> SRAM2_RST_W {
                SRAM2_RST_W { w: self }
            }
            ///Bit 26 - Software Boot0
            #[inline(always)]
            pub fn n_swboot0(&mut self) -> NSWBOOT0_W {
                NSWBOOT0_W { w: self }
            }
            ///Bit 27 - nBoot0 option bit
            #[inline(always)]
            pub fn n_boot0(&mut self) -> NBOOT0_W {
                NBOOT0_W { w: self }
            }
            ///Bits 29:31 - Radio Automatic Gain Control Trimming
            #[inline(always)]
            pub fn agc_trim(&mut self) -> AGC_TRIM_W {
                AGC_TRIM_W { w: self }
            }
        }
    }
    ///Flash Bank 1 PCROP Start address zone A register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pcrop1asr](pcrop1asr) module
    pub type PCROP1ASR = crate::Reg<u32, _PCROP1ASR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PCROP1ASR;
    ///`read()` method returns [pcrop1asr::R](pcrop1asr::R) reader structure
    impl crate::Readable for PCROP1ASR {}
    ///`write(|w| ..)` method takes [pcrop1asr::W](pcrop1asr::W) writer structure
    impl crate::Writable for PCROP1ASR {}
    ///Flash Bank 1 PCROP Start address zone A register
    pub mod pcrop1asr {
        ///Reader of register PCROP1ASR
        pub type R = crate::R<u32, super::PCROP1ASR>;
        ///Writer for register PCROP1ASR
        pub type W = crate::W<u32, super::PCROP1ASR>;
        ///Register PCROP1ASR `reset()`'s with value 0xffff_fe00
        impl crate::ResetValue for super::PCROP1ASR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_fe00
            }
        }
        ///Reader of field `PCROP1A_STRT`
        pub type PCROP1A_STRT_R = crate::R<u16, u16>;
        ///Write proxy for field `PCROP1A_STRT`
        pub struct PCROP1A_STRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PCROP1A_STRT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:8 - Bank 1 PCROPQ area start offset
            #[inline(always)]
            pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R {
                PCROP1A_STRT_R::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            ///Bits 0:8 - Bank 1 PCROPQ area start offset
            #[inline(always)]
            pub fn pcrop1a_strt(&mut self) -> PCROP1A_STRT_W {
                PCROP1A_STRT_W { w: self }
            }
        }
    }
    ///Flash Bank 1 PCROP End address zone A register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pcrop1aer](pcrop1aer) module
    pub type PCROP1AER = crate::Reg<u32, _PCROP1AER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PCROP1AER;
    ///`read()` method returns [pcrop1aer::R](pcrop1aer::R) reader structure
    impl crate::Readable for PCROP1AER {}
    ///`write(|w| ..)` method takes [pcrop1aer::W](pcrop1aer::W) writer structure
    impl crate::Writable for PCROP1AER {}
    ///Flash Bank 1 PCROP End address zone A register
    pub mod pcrop1aer {
        ///Reader of register PCROP1AER
        pub type R = crate::R<u32, super::PCROP1AER>;
        ///Writer for register PCROP1AER
        pub type W = crate::W<u32, super::PCROP1AER>;
        ///Register PCROP1AER `reset()`'s with value 0x7fff_fe00
        impl crate::ResetValue for super::PCROP1AER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x7fff_fe00
            }
        }
        ///Reader of field `PCROP1A_END`
        pub type PCROP1A_END_R = crate::R<u16, u16>;
        ///Write proxy for field `PCROP1A_END`
        pub struct PCROP1A_END_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PCROP1A_END_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
                self.w
            }
        }
        ///Reader of field `PCROP_RDP`
        pub type PCROP_RDP_R = crate::R<bool, bool>;
        ///Write proxy for field `PCROP_RDP`
        pub struct PCROP_RDP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PCROP_RDP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:8 - Bank 1 PCROP area end offset
            #[inline(always)]
            pub fn pcrop1a_end(&self) -> PCROP1A_END_R {
                PCROP1A_END_R::new((self.bits & 0x01ff) as u16)
            }
            ///Bit 31 - PCROP area preserved when RDP level decreased
            #[inline(always)]
            pub fn pcrop_rdp(&self) -> PCROP_RDP_R {
                PCROP_RDP_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:8 - Bank 1 PCROP area end offset
            #[inline(always)]
            pub fn pcrop1a_end(&mut self) -> PCROP1A_END_W {
                PCROP1A_END_W { w: self }
            }
            ///Bit 31 - PCROP area preserved when RDP level decreased
            #[inline(always)]
            pub fn pcrop_rdp(&mut self) -> PCROP_RDP_W {
                PCROP_RDP_W { w: self }
            }
        }
    }
    ///Flash Bank 1 WRP area A address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [wrp1ar](wrp1ar) module
    pub type WRP1AR = crate::Reg<u32, _WRP1AR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _WRP1AR;
    ///`read()` method returns [wrp1ar::R](wrp1ar::R) reader structure
    impl crate::Readable for WRP1AR {}
    ///`write(|w| ..)` method takes [wrp1ar::W](wrp1ar::W) writer structure
    impl crate::Writable for WRP1AR {}
    ///Flash Bank 1 WRP area A address register
    pub mod wrp1ar {
        ///Reader of register WRP1AR
        pub type R = crate::R<u32, super::WRP1AR>;
        ///Writer for register WRP1AR
        pub type W = crate::W<u32, super::WRP1AR>;
        ///Register WRP1AR `reset()`'s with value 0xff00_ff00
        impl crate::ResetValue for super::WRP1AR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xff00_ff00
            }
        }
        ///Reader of field `WRP1A_STRT`
        pub type WRP1A_STRT_R = crate::R<u8, u8>;
        ///Write proxy for field `WRP1A_STRT`
        pub struct WRP1A_STRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WRP1A_STRT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        ///Reader of field `WRP1A_END`
        pub type WRP1A_END_R = crate::R<u8, u8>;
        ///Write proxy for field `WRP1A_END`
        pub struct WRP1A_END_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WRP1A_END_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Bank 1 WRP first area A start offset
            #[inline(always)]
            pub fn wrp1a_strt(&self) -> WRP1A_STRT_R {
                WRP1A_STRT_R::new((self.bits & 0xff) as u8)
            }
            ///Bits 16:23 - Bank 1 WRP first area A end offset
            #[inline(always)]
            pub fn wrp1a_end(&self) -> WRP1A_END_R {
                WRP1A_END_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - Bank 1 WRP first area A start offset
            #[inline(always)]
            pub fn wrp1a_strt(&mut self) -> WRP1A_STRT_W {
                WRP1A_STRT_W { w: self }
            }
            ///Bits 16:23 - Bank 1 WRP first area A end offset
            #[inline(always)]
            pub fn wrp1a_end(&mut self) -> WRP1A_END_W {
                WRP1A_END_W { w: self }
            }
        }
    }
    ///Flash Bank 1 WRP area B address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [wrp1br](wrp1br) module
    pub type WRP1BR = crate::Reg<u32, _WRP1BR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _WRP1BR;
    ///`read()` method returns [wrp1br::R](wrp1br::R) reader structure
    impl crate::Readable for WRP1BR {}
    ///`write(|w| ..)` method takes [wrp1br::W](wrp1br::W) writer structure
    impl crate::Writable for WRP1BR {}
    ///Flash Bank 1 WRP area B address register
    pub mod wrp1br {
        ///Reader of register WRP1BR
        pub type R = crate::R<u32, super::WRP1BR>;
        ///Writer for register WRP1BR
        pub type W = crate::W<u32, super::WRP1BR>;
        ///Register WRP1BR `reset()`'s with value 0xff00_ff00
        impl crate::ResetValue for super::WRP1BR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xff00_ff00
            }
        }
        ///Reader of field `WRP1B_STRT`
        pub type WRP1B_STRT_R = crate::R<u8, u8>;
        ///Write proxy for field `WRP1B_STRT`
        pub struct WRP1B_STRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WRP1B_STRT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
                self.w
            }
        }
        ///Reader of field `WRP1B_END`
        pub type WRP1B_END_R = crate::R<u8, u8>;
        ///Write proxy for field `WRP1B_END`
        pub struct WRP1B_END_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WRP1B_END_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 16:23 - Bank 1 WRP second area B end offset
            #[inline(always)]
            pub fn wrp1b_strt(&self) -> WRP1B_STRT_R {
                WRP1B_STRT_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            ///Bits 0:7 - Bank 1 WRP second area B start offset
            #[inline(always)]
            pub fn wrp1b_end(&self) -> WRP1B_END_R {
                WRP1B_END_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 16:23 - Bank 1 WRP second area B end offset
            #[inline(always)]
            pub fn wrp1b_strt(&mut self) -> WRP1B_STRT_W {
                WRP1B_STRT_W { w: self }
            }
            ///Bits 0:7 - Bank 1 WRP second area B start offset
            #[inline(always)]
            pub fn wrp1b_end(&mut self) -> WRP1B_END_W {
                WRP1B_END_W { w: self }
            }
        }
    }
    ///Flash Bank 1 PCROP Start address area B register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pcrop1bsr](pcrop1bsr) module
    pub type PCROP1BSR = crate::Reg<u32, _PCROP1BSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PCROP1BSR;
    ///`read()` method returns [pcrop1bsr::R](pcrop1bsr::R) reader structure
    impl crate::Readable for PCROP1BSR {}
    ///`write(|w| ..)` method takes [pcrop1bsr::W](pcrop1bsr::W) writer structure
    impl crate::Writable for PCROP1BSR {}
    ///Flash Bank 1 PCROP Start address area B register
    pub mod pcrop1bsr {
        ///Reader of register PCROP1BSR
        pub type R = crate::R<u32, super::PCROP1BSR>;
        ///Writer for register PCROP1BSR
        pub type W = crate::W<u32, super::PCROP1BSR>;
        ///Register PCROP1BSR `reset()`'s with value 0xffff_fe00
        impl crate::ResetValue for super::PCROP1BSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_fe00
            }
        }
        ///Reader of field `PCROP1B_STRT`
        pub type PCROP1B_STRT_R = crate::R<u16, u16>;
        ///Write proxy for field `PCROP1B_STRT`
        pub struct PCROP1B_STRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PCROP1B_STRT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:8 - Bank 1 PCROP area B start offset
            #[inline(always)]
            pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R {
                PCROP1B_STRT_R::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            ///Bits 0:8 - Bank 1 PCROP area B start offset
            #[inline(always)]
            pub fn pcrop1b_strt(&mut self) -> PCROP1B_STRT_W {
                PCROP1B_STRT_W { w: self }
            }
        }
    }
    ///Flash Bank 1 PCROP End address area B register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pcrop1ber](pcrop1ber) module
    pub type PCROP1BER = crate::Reg<u32, _PCROP1BER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PCROP1BER;
    ///`read()` method returns [pcrop1ber::R](pcrop1ber::R) reader structure
    impl crate::Readable for PCROP1BER {}
    ///`write(|w| ..)` method takes [pcrop1ber::W](pcrop1ber::W) writer structure
    impl crate::Writable for PCROP1BER {}
    ///Flash Bank 1 PCROP End address area B register
    pub mod pcrop1ber {
        ///Reader of register PCROP1BER
        pub type R = crate::R<u32, super::PCROP1BER>;
        ///Writer for register PCROP1BER
        pub type W = crate::W<u32, super::PCROP1BER>;
        ///Register PCROP1BER `reset()`'s with value 0xffff_fe00
        impl crate::ResetValue for super::PCROP1BER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_fe00
            }
        }
        ///Reader of field `PCROP1B_END`
        pub type PCROP1B_END_R = crate::R<u16, u16>;
        ///Write proxy for field `PCROP1B_END`
        pub struct PCROP1B_END_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PCROP1B_END_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:8 - Bank 1 PCROP area end area B offset
            #[inline(always)]
            pub fn pcrop1b_end(&self) -> PCROP1B_END_R {
                PCROP1B_END_R::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            ///Bits 0:8 - Bank 1 PCROP area end area B offset
            #[inline(always)]
            pub fn pcrop1b_end(&mut self) -> PCROP1B_END_W {
                PCROP1B_END_W { w: self }
            }
        }
    }
    ///IPCC mailbox data buffer address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ipccbr](ipccbr) module
    pub type IPCCBR = crate::Reg<u32, _IPCCBR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IPCCBR;
    ///`read()` method returns [ipccbr::R](ipccbr::R) reader structure
    impl crate::Readable for IPCCBR {}
    ///`write(|w| ..)` method takes [ipccbr::W](ipccbr::W) writer structure
    impl crate::Writable for IPCCBR {}
    ///IPCC mailbox data buffer address register
    pub mod ipccbr {
        ///Reader of register IPCCBR
        pub type R = crate::R<u32, super::IPCCBR>;
        ///Writer for register IPCCBR
        pub type W = crate::W<u32, super::IPCCBR>;
        ///Register IPCCBR `reset()`'s with value 0xffff_c000
        impl crate::ResetValue for super::IPCCBR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_c000
            }
        }
        ///Reader of field `IPCCDBA`
        pub type IPCCDBA_R = crate::R<u16, u16>;
        ///Write proxy for field `IPCCDBA`
        pub struct IPCCDBA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IPCCDBA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x3fff) | ((value as u32) & 0x3fff);
                self.w
            }
        }
        impl R {
            ///Bits 0:13 - PCC mailbox data buffer base address
            #[inline(always)]
            pub fn ipccdba(&self) -> IPCCDBA_R {
                IPCCDBA_R::new((self.bits & 0x3fff) as u16)
            }
        }
        impl W {
            ///Bits 0:13 - PCC mailbox data buffer base address
            #[inline(always)]
            pub fn ipccdba(&mut self) -> IPCCDBA_W {
                IPCCDBA_W { w: self }
            }
        }
    }
    ///CPU2 cortex M0 access control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2acr](c2acr) module
    pub type C2ACR = crate::Reg<u32, _C2ACR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2ACR;
    ///`read()` method returns [c2acr::R](c2acr::R) reader structure
    impl crate::Readable for C2ACR {}
    ///`write(|w| ..)` method takes [c2acr::W](c2acr::W) writer structure
    impl crate::Writable for C2ACR {}
    ///CPU2 cortex M0 access control register
    pub mod c2acr {
        ///Reader of register C2ACR
        pub type R = crate::R<u32, super::C2ACR>;
        ///Writer for register C2ACR
        pub type W = crate::W<u32, super::C2ACR>;
        ///Register C2ACR `reset()`'s with value 0x0600
        impl crate::ResetValue for super::C2ACR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0600
            }
        }
        ///Reader of field `PRFTEN`
        pub type PRFTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PRFTEN`
        pub struct PRFTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRFTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `ICEN`
        pub type ICEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ICEN`
        pub struct ICEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ICEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `ICRST`
        pub type ICRST_R = crate::R<bool, bool>;
        ///Write proxy for field `ICRST`
        pub struct ICRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ICRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PES`
        pub type PES_R = crate::R<bool, bool>;
        ///Write proxy for field `PES`
        pub struct PES_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PES_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bit 8 - CPU2 cortex M0 prefetch enable
            #[inline(always)]
            pub fn prften(&self) -> PRFTEN_R {
                PRFTEN_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - CPU2 cortex M0 instruction cache enable
            #[inline(always)]
            pub fn icen(&self) -> ICEN_R {
                ICEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 11 - CPU2 cortex M0 instruction cache reset
            #[inline(always)]
            pub fn icrst(&self) -> ICRST_R {
                ICRST_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 15 - CPU2 cortex M0 program erase suspend request
            #[inline(always)]
            pub fn pes(&self) -> PES_R {
                PES_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 8 - CPU2 cortex M0 prefetch enable
            #[inline(always)]
            pub fn prften(&mut self) -> PRFTEN_W {
                PRFTEN_W { w: self }
            }
            ///Bit 9 - CPU2 cortex M0 instruction cache enable
            #[inline(always)]
            pub fn icen(&mut self) -> ICEN_W {
                ICEN_W { w: self }
            }
            ///Bit 11 - CPU2 cortex M0 instruction cache reset
            #[inline(always)]
            pub fn icrst(&mut self) -> ICRST_W {
                ICRST_W { w: self }
            }
            ///Bit 15 - CPU2 cortex M0 program erase suspend request
            #[inline(always)]
            pub fn pes(&mut self) -> PES_W {
                PES_W { w: self }
            }
        }
    }
    ///CPU2 cortex M0 status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2sr](c2sr) module
    pub type C2SR = crate::Reg<u32, _C2SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2SR;
    ///`read()` method returns [c2sr::R](c2sr::R) reader structure
    impl crate::Readable for C2SR {}
    ///`write(|w| ..)` method takes [c2sr::W](c2sr::W) writer structure
    impl crate::Writable for C2SR {}
    ///CPU2 cortex M0 status register
    pub mod c2sr {
        ///Reader of register C2SR
        pub type R = crate::R<u32, super::C2SR>;
        ///Writer for register C2SR
        pub type W = crate::W<u32, super::C2SR>;
        ///Register C2SR `reset()`'s with value 0
        impl crate::ResetValue for super::C2SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EOP`
        pub type EOP_R = crate::R<bool, bool>;
        ///Write proxy for field `EOP`
        pub struct EOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `OPERR`
        pub type OPERR_R = crate::R<bool, bool>;
        ///Write proxy for field `OPERR`
        pub struct OPERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PROGERR`
        pub type PROGERR_R = crate::R<bool, bool>;
        ///Write proxy for field `PROGERR`
        pub struct PROGERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROGERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `WRPERR`
        pub type WRPERR_R = crate::R<bool, bool>;
        ///Write proxy for field `WRPERR`
        pub struct WRPERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WRPERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PGAERR`
        pub type PGAERR_R = crate::R<bool, bool>;
        ///Write proxy for field `PGAERR`
        pub struct PGAERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PGAERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `SIZERR`
        pub type SIZERR_R = crate::R<bool, bool>;
        ///Write proxy for field `SIZERR`
        pub struct SIZERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SIZERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PGSERR`
        pub type PGSERR_R = crate::R<bool, bool>;
        ///Write proxy for field `PGSERR`
        pub struct PGSERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PGSERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `MISSERR`
        pub type MISSERR_R = crate::R<bool, bool>;
        ///Write proxy for field `MISSERR`
        pub struct MISSERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MISSERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `FASTERR`
        pub type FASTERR_R = crate::R<bool, bool>;
        ///Write proxy for field `FASTERR`
        pub struct FASTERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FASTERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `RDERR`
        pub type RDERR_R = crate::R<bool, bool>;
        ///Write proxy for field `RDERR`
        pub struct RDERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RDERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `BSY`
        pub type BSY_R = crate::R<bool, bool>;
        ///Write proxy for field `BSY`
        pub struct BSY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BSY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CFGBSY`
        pub type CFGBSY_R = crate::R<bool, bool>;
        ///Write proxy for field `CFGBSY`
        pub struct CFGBSY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CFGBSY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `PESD`
        pub type PESD_R = crate::R<bool, bool>;
        ///Write proxy for field `PESD`
        pub struct PESD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PESD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        impl R {
            ///Bit 0 - End of operation
            #[inline(always)]
            pub fn eop(&self) -> EOP_R {
                EOP_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Operation error
            #[inline(always)]
            pub fn operr(&self) -> OPERR_R {
                OPERR_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 3 - Programming error
            #[inline(always)]
            pub fn progerr(&self) -> PROGERR_R {
                PROGERR_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - write protection error
            #[inline(always)]
            pub fn wrperr(&self) -> WRPERR_R {
                WRPERR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Programming alignment error
            #[inline(always)]
            pub fn pgaerr(&self) -> PGAERR_R {
                PGAERR_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Size error
            #[inline(always)]
            pub fn sizerr(&self) -> SIZERR_R {
                SIZERR_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Programming sequence error
            #[inline(always)]
            pub fn pgserr(&self) -> PGSERR_R {
                PGSERR_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Fast programming data miss error
            #[inline(always)]
            pub fn misserr(&self) -> MISSERR_R {
                MISSERR_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Fast programming error
            #[inline(always)]
            pub fn fasterr(&self) -> FASTERR_R {
                FASTERR_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 14 - PCROP read error
            #[inline(always)]
            pub fn rderr(&self) -> RDERR_R {
                RDERR_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 16 - Busy
            #[inline(always)]
            pub fn bsy(&self) -> BSY_R {
                BSY_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 18 - Programming or erase configuration busy
            #[inline(always)]
            pub fn cfgbsy(&self) -> CFGBSY_R {
                CFGBSY_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - Programming or erase operation suspended
            #[inline(always)]
            pub fn pesd(&self) -> PESD_R {
                PESD_R::new(((self.bits >> 19) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - End of operation
            #[inline(always)]
            pub fn eop(&mut self) -> EOP_W {
                EOP_W { w: self }
            }
            ///Bit 1 - Operation error
            #[inline(always)]
            pub fn operr(&mut self) -> OPERR_W {
                OPERR_W { w: self }
            }
            ///Bit 3 - Programming error
            #[inline(always)]
            pub fn progerr(&mut self) -> PROGERR_W {
                PROGERR_W { w: self }
            }
            ///Bit 4 - write protection error
            #[inline(always)]
            pub fn wrperr(&mut self) -> WRPERR_W {
                WRPERR_W { w: self }
            }
            ///Bit 5 - Programming alignment error
            #[inline(always)]
            pub fn pgaerr(&mut self) -> PGAERR_W {
                PGAERR_W { w: self }
            }
            ///Bit 6 - Size error
            #[inline(always)]
            pub fn sizerr(&mut self) -> SIZERR_W {
                SIZERR_W { w: self }
            }
            ///Bit 7 - Programming sequence error
            #[inline(always)]
            pub fn pgserr(&mut self) -> PGSERR_W {
                PGSERR_W { w: self }
            }
            ///Bit 8 - Fast programming data miss error
            #[inline(always)]
            pub fn misserr(&mut self) -> MISSERR_W {
                MISSERR_W { w: self }
            }
            ///Bit 9 - Fast programming error
            #[inline(always)]
            pub fn fasterr(&mut self) -> FASTERR_W {
                FASTERR_W { w: self }
            }
            ///Bit 14 - PCROP read error
            #[inline(always)]
            pub fn rderr(&mut self) -> RDERR_W {
                RDERR_W { w: self }
            }
            ///Bit 16 - Busy
            #[inline(always)]
            pub fn bsy(&mut self) -> BSY_W {
                BSY_W { w: self }
            }
            ///Bit 18 - Programming or erase configuration busy
            #[inline(always)]
            pub fn cfgbsy(&mut self) -> CFGBSY_W {
                CFGBSY_W { w: self }
            }
            ///Bit 19 - Programming or erase operation suspended
            #[inline(always)]
            pub fn pesd(&mut self) -> PESD_W {
                PESD_W { w: self }
            }
        }
    }
    ///CPU2 cortex M0 control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2cr](c2cr) module
    pub type C2CR = crate::Reg<u32, _C2CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2CR;
    ///`read()` method returns [c2cr::R](c2cr::R) reader structure
    impl crate::Readable for C2CR {}
    ///`write(|w| ..)` method takes [c2cr::W](c2cr::W) writer structure
    impl crate::Writable for C2CR {}
    ///CPU2 cortex M0 control register
    pub mod c2cr {
        ///Reader of register C2CR
        pub type R = crate::R<u32, super::C2CR>;
        ///Writer for register C2CR
        pub type W = crate::W<u32, super::C2CR>;
        ///Register C2CR `reset()`'s with value 0
        impl crate::ResetValue for super::C2CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PG`
        pub type PG_R = crate::R<bool, bool>;
        ///Write proxy for field `PG`
        pub struct PG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `PER`
        pub type PER_R = crate::R<bool, bool>;
        ///Write proxy for field `PER`
        pub struct PER_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PER_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `MER`
        pub type MER_R = crate::R<bool, bool>;
        ///Write proxy for field `MER`
        pub struct MER_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MER_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PNB`
        pub type PNB_R = crate::R<u8, u8>;
        ///Write proxy for field `PNB`
        pub struct PNB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PNB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 3)) | (((value as u32) & 0xff) << 3);
                self.w
            }
        }
        ///Reader of field `STRT`
        pub type STRT_R = crate::R<bool, bool>;
        ///Write proxy for field `STRT`
        pub struct STRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STRT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `FSTPG`
        pub type FSTPG_R = crate::R<bool, bool>;
        ///Write proxy for field `FSTPG`
        pub struct FSTPG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FSTPG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `EOPIE`
        pub type EOPIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EOPIE`
        pub struct EOPIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOPIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `ERRIE`
        pub type ERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRIE`
        pub struct ERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `RDERRIE`
        pub type RDERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RDERRIE`
        pub struct RDERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RDERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Programming
            #[inline(always)]
            pub fn pg(&self) -> PG_R {
                PG_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Page erase
            #[inline(always)]
            pub fn per(&self) -> PER_R {
                PER_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Masse erase
            #[inline(always)]
            pub fn mer(&self) -> MER_R {
                MER_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bits 3:10 - Page Number selection
            #[inline(always)]
            pub fn pnb(&self) -> PNB_R {
                PNB_R::new(((self.bits >> 3) & 0xff) as u8)
            }
            ///Bit 16 - Start
            #[inline(always)]
            pub fn strt(&self) -> STRT_R {
                STRT_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 18 - Fast programming
            #[inline(always)]
            pub fn fstpg(&self) -> FSTPG_R {
                FSTPG_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 24 - End of operation interrupt enable
            #[inline(always)]
            pub fn eopie(&self) -> EOPIE_R {
                EOPIE_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 25 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&self) -> ERRIE_R {
                ERRIE_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 26 - PCROP read error interrupt enable
            #[inline(always)]
            pub fn rderrie(&self) -> RDERRIE_R {
                RDERRIE_R::new(((self.bits >> 26) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Programming
            #[inline(always)]
            pub fn pg(&mut self) -> PG_W {
                PG_W { w: self }
            }
            ///Bit 1 - Page erase
            #[inline(always)]
            pub fn per(&mut self) -> PER_W {
                PER_W { w: self }
            }
            ///Bit 2 - Masse erase
            #[inline(always)]
            pub fn mer(&mut self) -> MER_W {
                MER_W { w: self }
            }
            ///Bits 3:10 - Page Number selection
            #[inline(always)]
            pub fn pnb(&mut self) -> PNB_W {
                PNB_W { w: self }
            }
            ///Bit 16 - Start
            #[inline(always)]
            pub fn strt(&mut self) -> STRT_W {
                STRT_W { w: self }
            }
            ///Bit 18 - Fast programming
            #[inline(always)]
            pub fn fstpg(&mut self) -> FSTPG_W {
                FSTPG_W { w: self }
            }
            ///Bit 24 - End of operation interrupt enable
            #[inline(always)]
            pub fn eopie(&mut self) -> EOPIE_W {
                EOPIE_W { w: self }
            }
            ///Bit 25 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&mut self) -> ERRIE_W {
                ERRIE_W { w: self }
            }
            ///Bit 26 - PCROP read error interrupt enable
            #[inline(always)]
            pub fn rderrie(&mut self) -> RDERRIE_W {
                RDERRIE_W { w: self }
            }
        }
    }
    ///Secure flash start address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sfr](sfr) module
    pub type SFR = crate::Reg<u32, _SFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SFR;
    ///`read()` method returns [sfr::R](sfr::R) reader structure
    impl crate::Readable for SFR {}
    ///`write(|w| ..)` method takes [sfr::W](sfr::W) writer structure
    impl crate::Writable for SFR {}
    ///Secure flash start address register
    pub mod sfr {
        ///Reader of register SFR
        pub type R = crate::R<u32, super::SFR>;
        ///Writer for register SFR
        pub type W = crate::W<u32, super::SFR>;
        ///Register SFR `reset()`'s with value 0xffff_ee00
        impl crate::ResetValue for super::SFR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_ee00
            }
        }
        ///Reader of field `SFSA`
        pub type SFSA_R = crate::R<u8, u8>;
        ///Write proxy for field `SFSA`
        pub struct SFSA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SFSA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        ///Reader of field `DDS`
        pub type DDS_R = crate::R<bool, bool>;
        ///Write proxy for field `DDS`
        pub struct DDS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DDS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `FSD`
        pub type FSD_R = crate::R<bool, bool>;
        ///Write proxy for field `FSD`
        pub struct FSD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FSD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Secure flash start address
            #[inline(always)]
            pub fn sfsa(&self) -> SFSA_R {
                SFSA_R::new((self.bits & 0xff) as u8)
            }
            ///Bit 12 - Disable Cortex M0 debug access
            #[inline(always)]
            pub fn dds(&self) -> DDS_R {
                DDS_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 8 - Flash security disable
            #[inline(always)]
            pub fn fsd(&self) -> FSD_R {
                FSD_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:7 - Secure flash start address
            #[inline(always)]
            pub fn sfsa(&mut self) -> SFSA_W {
                SFSA_W { w: self }
            }
            ///Bit 12 - Disable Cortex M0 debug access
            #[inline(always)]
            pub fn dds(&mut self) -> DDS_W {
                DDS_W { w: self }
            }
            ///Bit 8 - Flash security disable
            #[inline(always)]
            pub fn fsd(&mut self) -> FSD_W {
                FSD_W { w: self }
            }
        }
    }
    ///Secure SRAM2 start address and cortex M0 reset vector register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [srrvr](srrvr) module
    pub type SRRVR = crate::Reg<u32, _SRRVR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SRRVR;
    ///`read()` method returns [srrvr::R](srrvr::R) reader structure
    impl crate::Readable for SRRVR {}
    ///`write(|w| ..)` method takes [srrvr::W](srrvr::W) writer structure
    impl crate::Writable for SRRVR {}
    ///Secure SRAM2 start address and cortex M0 reset vector register
    pub mod srrvr {
        ///Reader of register SRRVR
        pub type R = crate::R<u32, super::SRRVR>;
        ///Writer for register SRRVR
        pub type W = crate::W<u32, super::SRRVR>;
        ///Register SRRVR `reset()`'s with value 0x0100_0000
        impl crate::ResetValue for super::SRRVR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0100_0000
            }
        }
        ///Reader of field `SBRV`
        pub type SBRV_R = crate::R<u32, u32>;
        ///Write proxy for field `SBRV`
        pub struct SBRV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SBRV_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0003_ffff) | ((value as u32) & 0x0003_ffff);
                self.w
            }
        }
        ///Reader of field `SBRSA`
        pub type SBRSA_R = crate::R<u8, u8>;
        ///Write proxy for field `SBRSA`
        pub struct SBRSA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SBRSA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 18)) | (((value as u32) & 0x1f) << 18);
                self.w
            }
        }
        ///Reader of field `BRSD`
        pub type BRSD_R = crate::R<bool, bool>;
        ///Write proxy for field `BRSD`
        pub struct BRSD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BRSD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `SNBRSA`
        pub type SNBRSA_R = crate::R<u8, u8>;
        ///Write proxy for field `SNBRSA`
        pub struct SNBRSA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SNBRSA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 25)) | (((value as u32) & 0x1f) << 25);
                self.w
            }
        }
        ///Reader of field `C2OPT`
        pub type C2OPT_R = crate::R<bool, bool>;
        ///Write proxy for field `C2OPT`
        pub struct C2OPT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C2OPT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `NBRSD`
        pub type NBRSD_R = crate::R<bool, bool>;
        ///Write proxy for field `NBRSD`
        pub struct NBRSD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NBRSD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        impl R {
            ///Bits 0:17 - cortex M0 access control register
            #[inline(always)]
            pub fn sbrv(&self) -> SBRV_R {
                SBRV_R::new((self.bits & 0x0003_ffff) as u32)
            }
            ///Bits 18:22 - Secure backup SRAM2a start address
            #[inline(always)]
            pub fn sbrsa(&self) -> SBRSA_R {
                SBRSA_R::new(((self.bits >> 18) & 0x1f) as u8)
            }
            ///Bit 23 - backup SRAM2a security disable
            #[inline(always)]
            pub fn brsd(&self) -> BRSD_R {
                BRSD_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bits 25:29 - Secure non backup SRAM2a start address
            #[inline(always)]
            pub fn snbrsa(&self) -> SNBRSA_R {
                SNBRSA_R::new(((self.bits >> 25) & 0x1f) as u8)
            }
            ///Bit 31 - CPU2 cortex M0 boot reset vector memory selection
            #[inline(always)]
            pub fn c2opt(&self) -> C2OPT_R {
                C2OPT_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - non-backup SRAM2b security disable
            #[inline(always)]
            pub fn nbrsd(&self) -> NBRSD_R {
                NBRSD_R::new(((self.bits >> 30) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:17 - cortex M0 access control register
            #[inline(always)]
            pub fn sbrv(&mut self) -> SBRV_W {
                SBRV_W { w: self }
            }
            ///Bits 18:22 - Secure backup SRAM2a start address
            #[inline(always)]
            pub fn sbrsa(&mut self) -> SBRSA_W {
                SBRSA_W { w: self }
            }
            ///Bit 23 - backup SRAM2a security disable
            #[inline(always)]
            pub fn brsd(&mut self) -> BRSD_W {
                BRSD_W { w: self }
            }
            ///Bits 25:29 - Secure non backup SRAM2a start address
            #[inline(always)]
            pub fn snbrsa(&mut self) -> SNBRSA_W {
                SNBRSA_W { w: self }
            }
            ///Bit 31 - CPU2 cortex M0 boot reset vector memory selection
            #[inline(always)]
            pub fn c2opt(&mut self) -> C2OPT_W {
                C2OPT_W { w: self }
            }
            ///Bit 30 - non-backup SRAM2b security disable
            #[inline(always)]
            pub fn nbrsd(&mut self) -> NBRSD_W {
                NBRSD_W { w: self }
            }
        }
    }
}
///QuadSPI interface
pub struct QUADSPI {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for QUADSPI {}
impl QUADSPI {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const quadspi::RegisterBlock {
        0xa000_1000 as *const _
    }
}
impl Deref for QUADSPI {
    type Target = quadspi::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*QUADSPI::ptr() }
    }
}
///QuadSPI interface
pub mod quadspi {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register
        pub cr: CR,
        ///0x04 - device configuration register
        pub dcr: DCR,
        ///0x08 - status register
        pub sr: SR,
        ///0x0c - flag clear register
        pub fcr: FCR,
        ///0x10 - data length register
        pub dlr: DLR,
        ///0x14 - communication configuration register
        pub ccr: CCR,
        ///0x18 - address register
        pub ar: AR,
        ///0x1c - ABR
        pub abr: ABR,
        ///0x20 - data register
        pub dr: DR,
        ///0x24 - polling status mask register
        pub psmkr: PSMKR,
        ///0x28 - polling status match register
        pub psmar: PSMAR,
        ///0x2c - polling interval register
        pub pir: PIR,
        ///0x30 - low-power timeout register
        pub lptr: LPTR,
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PRESCALER`
        pub type PRESCALER_R = crate::R<u8, u8>;
        ///Write proxy for field `PRESCALER`
        pub struct PRESCALER_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRESCALER_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
                self.w
            }
        }
        ///Reader of field `PMM`
        pub type PMM_R = crate::R<bool, bool>;
        ///Write proxy for field `PMM`
        pub struct PMM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PMM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `APMS`
        pub type APMS_R = crate::R<bool, bool>;
        ///Write proxy for field `APMS`
        pub struct APMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> APMS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `TOIE`
        pub type TOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TOIE`
        pub struct TOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `SMIE`
        pub type SMIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SMIE`
        pub struct SMIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `FTIE`
        pub type FTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `FTIE`
        pub struct FTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `TEIE`
        pub type TEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TEIE`
        pub struct TEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `FTHRES`
        pub type FTHRES_R = crate::R<u8, u8>;
        ///Write proxy for field `FTHRES`
        pub struct FTHRES_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FTHRES_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `SSHIFT`
        pub type SSHIFT_R = crate::R<bool, bool>;
        ///Write proxy for field `SSHIFT`
        pub struct SSHIFT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SSHIFT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TCEN`
        pub type TCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TCEN`
        pub struct TCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `DMAEN`
        pub type DMAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAEN`
        pub struct DMAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ABORT`
        pub type ABORT_R = crate::R<bool, bool>;
        ///Write proxy for field `ABORT`
        pub struct ABORT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ABORT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 24:31 - Clock prescaler
            #[inline(always)]
            pub fn prescaler(&self) -> PRESCALER_R {
                PRESCALER_R::new(((self.bits >> 24) & 0xff) as u8)
            }
            ///Bit 23 - Polling match mode
            #[inline(always)]
            pub fn pmm(&self) -> PMM_R {
                PMM_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - Automatic poll mode stop
            #[inline(always)]
            pub fn apms(&self) -> APMS_R {
                APMS_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 20 - TimeOut interrupt enable
            #[inline(always)]
            pub fn toie(&self) -> TOIE_R {
                TOIE_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Status match interrupt enable
            #[inline(always)]
            pub fn smie(&self) -> SMIE_R {
                SMIE_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - FIFO threshold interrupt enable
            #[inline(always)]
            pub fn ftie(&self) -> FTIE_R {
                FTIE_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&self) -> TEIE_R {
                TEIE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 8:11 - FIFO threshold level
            #[inline(always)]
            pub fn fthres(&self) -> FTHRES_R {
                FTHRES_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bit 4 - Sample shift
            #[inline(always)]
            pub fn sshift(&self) -> SSHIFT_R {
                SSHIFT_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Timeout counter enable
            #[inline(always)]
            pub fn tcen(&self) -> TCEN_R {
                TCEN_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - DMA enable
            #[inline(always)]
            pub fn dmaen(&self) -> DMAEN_R {
                DMAEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Abort request
            #[inline(always)]
            pub fn abort(&self) -> ABORT_R {
                ABORT_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 24:31 - Clock prescaler
            #[inline(always)]
            pub fn prescaler(&mut self) -> PRESCALER_W {
                PRESCALER_W { w: self }
            }
            ///Bit 23 - Polling match mode
            #[inline(always)]
            pub fn pmm(&mut self) -> PMM_W {
                PMM_W { w: self }
            }
            ///Bit 22 - Automatic poll mode stop
            #[inline(always)]
            pub fn apms(&mut self) -> APMS_W {
                APMS_W { w: self }
            }
            ///Bit 20 - TimeOut interrupt enable
            #[inline(always)]
            pub fn toie(&mut self) -> TOIE_W {
                TOIE_W { w: self }
            }
            ///Bit 19 - Status match interrupt enable
            #[inline(always)]
            pub fn smie(&mut self) -> SMIE_W {
                SMIE_W { w: self }
            }
            ///Bit 18 - FIFO threshold interrupt enable
            #[inline(always)]
            pub fn ftie(&mut self) -> FTIE_W {
                FTIE_W { w: self }
            }
            ///Bit 17 - Transfer complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 16 - Transfer error interrupt enable
            #[inline(always)]
            pub fn teie(&mut self) -> TEIE_W {
                TEIE_W { w: self }
            }
            ///Bits 8:11 - FIFO threshold level
            #[inline(always)]
            pub fn fthres(&mut self) -> FTHRES_W {
                FTHRES_W { w: self }
            }
            ///Bit 4 - Sample shift
            #[inline(always)]
            pub fn sshift(&mut self) -> SSHIFT_W {
                SSHIFT_W { w: self }
            }
            ///Bit 3 - Timeout counter enable
            #[inline(always)]
            pub fn tcen(&mut self) -> TCEN_W {
                TCEN_W { w: self }
            }
            ///Bit 2 - DMA enable
            #[inline(always)]
            pub fn dmaen(&mut self) -> DMAEN_W {
                DMAEN_W { w: self }
            }
            ///Bit 1 - Abort request
            #[inline(always)]
            pub fn abort(&mut self) -> ABORT_W {
                ABORT_W { w: self }
            }
            ///Bit 0 - Enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///device configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dcr](dcr) module
    pub type DCR = crate::Reg<u32, _DCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DCR;
    ///`read()` method returns [dcr::R](dcr::R) reader structure
    impl crate::Readable for DCR {}
    ///`write(|w| ..)` method takes [dcr::W](dcr::W) writer structure
    impl crate::Writable for DCR {}
    ///device configuration register
    pub mod dcr {
        ///Reader of register DCR
        pub type R = crate::R<u32, super::DCR>;
        ///Writer for register DCR
        pub type W = crate::W<u32, super::DCR>;
        ///Register DCR `reset()`'s with value 0
        impl crate::ResetValue for super::DCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `FSIZE`
        pub type FSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `FSIZE`
        pub struct FSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 16)) | (((value as u32) & 0x1f) << 16);
                self.w
            }
        }
        ///Reader of field `CSHT`
        pub type CSHT_R = crate::R<u8, u8>;
        ///Write proxy for field `CSHT`
        pub struct CSHT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSHT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `CKMODE`
        pub type CKMODE_R = crate::R<bool, bool>;
        ///Write proxy for field `CKMODE`
        pub struct CKMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKMODE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 16:20 - FLASH memory size
            #[inline(always)]
            pub fn fsize(&self) -> FSIZE_R {
                FSIZE_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            ///Bits 8:10 - Chip select high time
            #[inline(always)]
            pub fn csht(&self) -> CSHT_R {
                CSHT_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bit 0 - Mode 0 / mode 3
            #[inline(always)]
            pub fn ckmode(&self) -> CKMODE_R {
                CKMODE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 16:20 - FLASH memory size
            #[inline(always)]
            pub fn fsize(&mut self) -> FSIZE_W {
                FSIZE_W { w: self }
            }
            ///Bits 8:10 - Chip select high time
            #[inline(always)]
            pub fn csht(&mut self) -> CSHT_W {
                CSHT_W { w: self }
            }
            ///Bit 0 - Mode 0 / mode 3
            #[inline(always)]
            pub fn ckmode(&mut self) -> CKMODE_W {
                CKMODE_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Reader of field `FLEVEL`
        pub type FLEVEL_R = crate::R<u8, u8>;
        ///Reader of field `BUSY`
        pub type BUSY_R = crate::R<bool, bool>;
        ///Reader of field `TOF`
        pub type TOF_R = crate::R<bool, bool>;
        ///Reader of field `SMF`
        pub type SMF_R = crate::R<bool, bool>;
        ///Reader of field `FTF`
        pub type FTF_R = crate::R<bool, bool>;
        ///Reader of field `TCF`
        pub type TCF_R = crate::R<bool, bool>;
        ///Reader of field `TEF`
        pub type TEF_R = crate::R<bool, bool>;
        impl R {
            ///Bits 8:12 - FIFO level
            #[inline(always)]
            pub fn flevel(&self) -> FLEVEL_R {
                FLEVEL_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            ///Bit 5 - Busy
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Timeout flag
            #[inline(always)]
            pub fn tof(&self) -> TOF_R {
                TOF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Status match flag
            #[inline(always)]
            pub fn smf(&self) -> SMF_R {
                SMF_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - FIFO threshold flag
            #[inline(always)]
            pub fn ftf(&self) -> FTF_R {
                FTF_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Transfer complete flag
            #[inline(always)]
            pub fn tcf(&self) -> TCF_R {
                TCF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Transfer error flag
            #[inline(always)]
            pub fn tef(&self) -> TEF_R {
                TEF_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///flag clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [fcr](fcr) module
    pub type FCR = crate::Reg<u32, _FCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _FCR;
    ///`read()` method returns [fcr::R](fcr::R) reader structure
    impl crate::Readable for FCR {}
    ///`write(|w| ..)` method takes [fcr::W](fcr::W) writer structure
    impl crate::Writable for FCR {}
    ///flag clear register
    pub mod fcr {
        ///Reader of register FCR
        pub type R = crate::R<u32, super::FCR>;
        ///Writer for register FCR
        pub type W = crate::W<u32, super::FCR>;
        ///Register FCR `reset()`'s with value 0
        impl crate::ResetValue for super::FCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CTOF`
        pub type CTOF_R = crate::R<bool, bool>;
        ///Write proxy for field `CTOF`
        pub struct CTOF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTOF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CSMF`
        pub type CSMF_R = crate::R<bool, bool>;
        ///Write proxy for field `CSMF`
        pub struct CSMF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSMF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CTCF`
        pub type CTCF_R = crate::R<bool, bool>;
        ///Write proxy for field `CTCF`
        pub struct CTCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CTEF`
        pub type CTEF_R = crate::R<bool, bool>;
        ///Write proxy for field `CTEF`
        pub struct CTEF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTEF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 4 - Clear timeout flag
            #[inline(always)]
            pub fn ctof(&self) -> CTOF_R {
                CTOF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Clear status match flag
            #[inline(always)]
            pub fn csmf(&self) -> CSMF_R {
                CSMF_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Clear transfer complete flag
            #[inline(always)]
            pub fn ctcf(&self) -> CTCF_R {
                CTCF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Clear transfer error flag
            #[inline(always)]
            pub fn ctef(&self) -> CTEF_R {
                CTEF_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 4 - Clear timeout flag
            #[inline(always)]
            pub fn ctof(&mut self) -> CTOF_W {
                CTOF_W { w: self }
            }
            ///Bit 3 - Clear status match flag
            #[inline(always)]
            pub fn csmf(&mut self) -> CSMF_W {
                CSMF_W { w: self }
            }
            ///Bit 1 - Clear transfer complete flag
            #[inline(always)]
            pub fn ctcf(&mut self) -> CTCF_W {
                CTCF_W { w: self }
            }
            ///Bit 0 - Clear transfer error flag
            #[inline(always)]
            pub fn ctef(&mut self) -> CTEF_W {
                CTEF_W { w: self }
            }
        }
    }
    ///data length register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dlr](dlr) module
    pub type DLR = crate::Reg<u32, _DLR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DLR;
    ///`read()` method returns [dlr::R](dlr::R) reader structure
    impl crate::Readable for DLR {}
    ///`write(|w| ..)` method takes [dlr::W](dlr::W) writer structure
    impl crate::Writable for DLR {}
    ///data length register
    pub mod dlr {
        ///Reader of register DLR
        pub type R = crate::R<u32, super::DLR>;
        ///Writer for register DLR
        pub type W = crate::W<u32, super::DLR>;
        ///Register DLR `reset()`'s with value 0
        impl crate::ResetValue for super::DLR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DL`
        pub type DL_R = crate::R<u32, u32>;
        ///Write proxy for field `DL`
        pub struct DL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Data length
            #[inline(always)]
            pub fn dl(&self) -> DL_R {
                DL_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Data length
            #[inline(always)]
            pub fn dl(&mut self) -> DL_W {
                DL_W { w: self }
            }
        }
    }
    ///communication configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr](ccr) module
    pub type CCR = crate::Reg<u32, _CCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR;
    ///`read()` method returns [ccr::R](ccr::R) reader structure
    impl crate::Readable for CCR {}
    ///`write(|w| ..)` method takes [ccr::W](ccr::W) writer structure
    impl crate::Writable for CCR {}
    ///communication configuration register
    pub mod ccr {
        ///Reader of register CCR
        pub type R = crate::R<u32, super::CCR>;
        ///Writer for register CCR
        pub type W = crate::W<u32, super::CCR>;
        ///Register CCR `reset()`'s with value 0
        impl crate::ResetValue for super::CCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DDRM`
        pub type DDRM_R = crate::R<bool, bool>;
        ///Write proxy for field `DDRM`
        pub struct DDRM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DDRM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `SIOO`
        pub type SIOO_R = crate::R<bool, bool>;
        ///Write proxy for field `SIOO`
        pub struct SIOO_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SIOO_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `FMODE`
        pub type FMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `FMODE`
        pub struct FMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `DMODE`
        pub type DMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `DMODE`
        pub struct DMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `DCYC`
        pub type DCYC_R = crate::R<u8, u8>;
        ///Write proxy for field `DCYC`
        pub struct DCYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DCYC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 18)) | (((value as u32) & 0x1f) << 18);
                self.w
            }
        }
        ///Reader of field `ABSIZE`
        pub type ABSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `ABSIZE`
        pub struct ABSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ABSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `ABMODE`
        pub type ABMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `ABMODE`
        pub struct ABMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ABMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `ADSIZE`
        pub type ADSIZE_R = crate::R<u8, u8>;
        ///Write proxy for field `ADSIZE`
        pub struct ADSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADSIZE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `ADMODE`
        pub type ADMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `ADMODE`
        pub struct ADMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `IMODE`
        pub type IMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `IMODE`
        pub struct IMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `INSTRUCTION`
        pub type INSTRUCTION_R = crate::R<u8, u8>;
        ///Write proxy for field `INSTRUCTION`
        pub struct INSTRUCTION_W<'a> {
            w: &'a mut W,
        }
        impl<'a> INSTRUCTION_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - Double data rate mode
            #[inline(always)]
            pub fn ddrm(&self) -> DDRM_R {
                DDRM_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 28 - Send instruction only once mode
            #[inline(always)]
            pub fn sioo(&self) -> SIOO_R {
                SIOO_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bits 26:27 - Functional mode
            #[inline(always)]
            pub fn fmode(&self) -> FMODE_R {
                FMODE_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Data mode
            #[inline(always)]
            pub fn dmode(&self) -> DMODE_R {
                DMODE_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 18:22 - Number of dummy cycles
            #[inline(always)]
            pub fn dcyc(&self) -> DCYC_R {
                DCYC_R::new(((self.bits >> 18) & 0x1f) as u8)
            }
            ///Bits 16:17 - Alternate bytes size
            #[inline(always)]
            pub fn absize(&self) -> ABSIZE_R {
                ABSIZE_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Alternate bytes mode
            #[inline(always)]
            pub fn abmode(&self) -> ABMODE_R {
                ABMODE_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Address size
            #[inline(always)]
            pub fn adsize(&self) -> ADSIZE_R {
                ADSIZE_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Address mode
            #[inline(always)]
            pub fn admode(&self) -> ADMODE_R {
                ADMODE_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Instruction mode
            #[inline(always)]
            pub fn imode(&self) -> IMODE_R {
                IMODE_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 0:7 - Instruction
            #[inline(always)]
            pub fn instruction(&self) -> INSTRUCTION_R {
                INSTRUCTION_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - Double data rate mode
            #[inline(always)]
            pub fn ddrm(&mut self) -> DDRM_W {
                DDRM_W { w: self }
            }
            ///Bit 28 - Send instruction only once mode
            #[inline(always)]
            pub fn sioo(&mut self) -> SIOO_W {
                SIOO_W { w: self }
            }
            ///Bits 26:27 - Functional mode
            #[inline(always)]
            pub fn fmode(&mut self) -> FMODE_W {
                FMODE_W { w: self }
            }
            ///Bits 24:25 - Data mode
            #[inline(always)]
            pub fn dmode(&mut self) -> DMODE_W {
                DMODE_W { w: self }
            }
            ///Bits 18:22 - Number of dummy cycles
            #[inline(always)]
            pub fn dcyc(&mut self) -> DCYC_W {
                DCYC_W { w: self }
            }
            ///Bits 16:17 - Alternate bytes size
            #[inline(always)]
            pub fn absize(&mut self) -> ABSIZE_W {
                ABSIZE_W { w: self }
            }
            ///Bits 14:15 - Alternate bytes mode
            #[inline(always)]
            pub fn abmode(&mut self) -> ABMODE_W {
                ABMODE_W { w: self }
            }
            ///Bits 12:13 - Address size
            #[inline(always)]
            pub fn adsize(&mut self) -> ADSIZE_W {
                ADSIZE_W { w: self }
            }
            ///Bits 10:11 - Address mode
            #[inline(always)]
            pub fn admode(&mut self) -> ADMODE_W {
                ADMODE_W { w: self }
            }
            ///Bits 8:9 - Instruction mode
            #[inline(always)]
            pub fn imode(&mut self) -> IMODE_W {
                IMODE_W { w: self }
            }
            ///Bits 0:7 - Instruction
            #[inline(always)]
            pub fn instruction(&mut self) -> INSTRUCTION_W {
                INSTRUCTION_W { w: self }
            }
        }
    }
    ///address register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ar](ar) module
    pub type AR = crate::Reg<u32, _AR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AR;
    ///`read()` method returns [ar::R](ar::R) reader structure
    impl crate::Readable for AR {}
    ///`write(|w| ..)` method takes [ar::W](ar::W) writer structure
    impl crate::Writable for AR {}
    ///address register
    pub mod ar {
        ///Reader of register AR
        pub type R = crate::R<u32, super::AR>;
        ///Writer for register AR
        pub type W = crate::W<u32, super::AR>;
        ///Register AR `reset()`'s with value 0
        impl crate::ResetValue for super::AR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDRESS`
        pub type ADDRESS_R = crate::R<u32, u32>;
        ///Write proxy for field `ADDRESS`
        pub struct ADDRESS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDRESS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Address
            #[inline(always)]
            pub fn address(&self) -> ADDRESS_R {
                ADDRESS_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Address
            #[inline(always)]
            pub fn address(&mut self) -> ADDRESS_W {
                ADDRESS_W { w: self }
            }
        }
    }
    ///ABR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [abr](abr) module
    pub type ABR = crate::Reg<u32, _ABR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ABR;
    ///`read()` method returns [abr::R](abr::R) reader structure
    impl crate::Readable for ABR {}
    ///`write(|w| ..)` method takes [abr::W](abr::W) writer structure
    impl crate::Writable for ABR {}
    ///ABR
    pub mod abr {
        ///Reader of register ABR
        pub type R = crate::R<u32, super::ABR>;
        ///Writer for register ABR
        pub type W = crate::W<u32, super::ABR>;
        ///Register ABR `reset()`'s with value 0
        impl crate::ResetValue for super::ABR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ALTERNATE`
        pub type ALTERNATE_R = crate::R<u32, u32>;
        ///Write proxy for field `ALTERNATE`
        pub struct ALTERNATE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALTERNATE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - ALTERNATE
            #[inline(always)]
            pub fn alternate(&self) -> ALTERNATE_R {
                ALTERNATE_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - ALTERNATE
            #[inline(always)]
            pub fn alternate(&mut self) -> ALTERNATE_W {
                ALTERNATE_W { w: self }
            }
        }
    }
    ///data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dr](dr) module
    pub type DR = crate::Reg<u32, _DR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DR;
    ///`read()` method returns [dr::R](dr::R) reader structure
    impl crate::Readable for DR {}
    ///`write(|w| ..)` method takes [dr::W](dr::W) writer structure
    impl crate::Writable for DR {}
    ///data register
    pub mod dr {
        ///Reader of register DR
        pub type R = crate::R<u32, super::DR>;
        ///Writer for register DR
        pub type W = crate::W<u32, super::DR>;
        ///Register DR `reset()`'s with value 0
        impl crate::ResetValue for super::DR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DATA`
        pub type DATA_R = crate::R<u32, u32>;
        ///Write proxy for field `DATA`
        pub struct DATA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DATA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Data
            #[inline(always)]
            pub fn data(&self) -> DATA_R {
                DATA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Data
            #[inline(always)]
            pub fn data(&mut self) -> DATA_W {
                DATA_W { w: self }
            }
        }
    }
    ///polling status mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [psmkr](psmkr) module
    pub type PSMKR = crate::Reg<u32, _PSMKR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PSMKR;
    ///`read()` method returns [psmkr::R](psmkr::R) reader structure
    impl crate::Readable for PSMKR {}
    ///`write(|w| ..)` method takes [psmkr::W](psmkr::W) writer structure
    impl crate::Writable for PSMKR {}
    ///polling status mask register
    pub mod psmkr {
        ///Reader of register PSMKR
        pub type R = crate::R<u32, super::PSMKR>;
        ///Writer for register PSMKR
        pub type W = crate::W<u32, super::PSMKR>;
        ///Register PSMKR `reset()`'s with value 0
        impl crate::ResetValue for super::PSMKR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MASK`
        pub type MASK_R = crate::R<u32, u32>;
        ///Write proxy for field `MASK`
        pub struct MASK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MASK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Status mask
            #[inline(always)]
            pub fn mask(&self) -> MASK_R {
                MASK_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Status mask
            #[inline(always)]
            pub fn mask(&mut self) -> MASK_W {
                MASK_W { w: self }
            }
        }
    }
    ///polling status match register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [psmar](psmar) module
    pub type PSMAR = crate::Reg<u32, _PSMAR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PSMAR;
    ///`read()` method returns [psmar::R](psmar::R) reader structure
    impl crate::Readable for PSMAR {}
    ///`write(|w| ..)` method takes [psmar::W](psmar::W) writer structure
    impl crate::Writable for PSMAR {}
    ///polling status match register
    pub mod psmar {
        ///Reader of register PSMAR
        pub type R = crate::R<u32, super::PSMAR>;
        ///Writer for register PSMAR
        pub type W = crate::W<u32, super::PSMAR>;
        ///Register PSMAR `reset()`'s with value 0
        impl crate::ResetValue for super::PSMAR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MATCH`
        pub type MATCH_R = crate::R<u32, u32>;
        ///Write proxy for field `MATCH`
        pub struct MATCH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MATCH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Status match
            #[inline(always)]
            pub fn match_(&self) -> MATCH_R {
                MATCH_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Status match
            #[inline(always)]
            pub fn match_(&mut self) -> MATCH_W {
                MATCH_W { w: self }
            }
        }
    }
    ///polling interval register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pir](pir) module
    pub type PIR = crate::Reg<u32, _PIR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PIR;
    ///`read()` method returns [pir::R](pir::R) reader structure
    impl crate::Readable for PIR {}
    ///`write(|w| ..)` method takes [pir::W](pir::W) writer structure
    impl crate::Writable for PIR {}
    ///polling interval register
    pub mod pir {
        ///Reader of register PIR
        pub type R = crate::R<u32, super::PIR>;
        ///Writer for register PIR
        pub type W = crate::W<u32, super::PIR>;
        ///Register PIR `reset()`'s with value 0
        impl crate::ResetValue for super::PIR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `INTERVAL`
        pub type INTERVAL_R = crate::R<u16, u16>;
        ///Write proxy for field `INTERVAL`
        pub struct INTERVAL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> INTERVAL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Polling interval
            #[inline(always)]
            pub fn interval(&self) -> INTERVAL_R {
                INTERVAL_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Polling interval
            #[inline(always)]
            pub fn interval(&mut self) -> INTERVAL_W {
                INTERVAL_W { w: self }
            }
        }
    }
    ///low-power timeout register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [lptr](lptr) module
    pub type LPTR = crate::Reg<u32, _LPTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LPTR;
    ///`read()` method returns [lptr::R](lptr::R) reader structure
    impl crate::Readable for LPTR {}
    ///`write(|w| ..)` method takes [lptr::W](lptr::W) writer structure
    impl crate::Writable for LPTR {}
    ///low-power timeout register
    pub mod lptr {
        ///Reader of register LPTR
        pub type R = crate::R<u32, super::LPTR>;
        ///Writer for register LPTR
        pub type W = crate::W<u32, super::LPTR>;
        ///Register LPTR `reset()`'s with value 0
        impl crate::ResetValue for super::LPTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TIMEOUT`
        pub type TIMEOUT_R = crate::R<u16, u16>;
        ///Write proxy for field `TIMEOUT`
        pub struct TIMEOUT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIMEOUT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Timeout period
            #[inline(always)]
            pub fn timeout(&self) -> TIMEOUT_R {
                TIMEOUT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Timeout period
            #[inline(always)]
            pub fn timeout(&mut self) -> TIMEOUT_W {
                TIMEOUT_W { w: self }
            }
        }
    }
}
///Reset and clock control
pub struct RCC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for RCC {}
impl RCC {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const rcc::RegisterBlock {
        0x5800_0000 as *const _
    }
}
impl Deref for RCC {
    type Target = rcc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*RCC::ptr() }
    }
}
///Reset and clock control
pub mod rcc {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Clock control register
        pub cr: CR,
        ///0x04 - Internal clock sources calibration register
        pub icscr: ICSCR,
        ///0x08 - Clock configuration register
        pub cfgr: CFGR,
        ///0x0c - PLLSYS configuration register
        pub pllcfgr: PLLCFGR,
        ///0x10 - PLLSAI1 configuration register
        pub pllsai1cfgr: PLLSAI1CFGR,
        _reserved5: [u8; 4usize],
        ///0x18 - Clock interrupt enable register
        pub cier: CIER,
        ///0x1c - Clock interrupt flag register
        pub cifr: CIFR,
        ///0x20 - Clock interrupt clear register
        pub cicr: CICR,
        ///0x24 - Step Down converter control register
        pub smpscr: SMPSCR,
        ///0x28 - AHB1 peripheral reset register
        pub ahb1rstr: AHB1RSTR,
        ///0x2c - AHB2 peripheral reset register
        pub ahb2rstr: AHB2RSTR,
        ///0x30 - AHB3 peripheral reset register
        pub ahb3rstr: AHB3RSTR,
        _reserved12: [u8; 4usize],
        ///0x38 - APB1 peripheral reset register 1
        pub apb1rstr1: APB1RSTR1,
        ///0x3c - APB1 peripheral reset register 2
        pub apb1rstr2: APB1RSTR2,
        ///0x40 - APB2 peripheral reset register
        pub apb2rstr: APB2RSTR,
        ///0x44 - APB3 peripheral reset register
        pub apb3rstr: APB3RSTR,
        ///0x48 - AHB1 peripheral clock enable register
        pub ahb1enr: AHB1ENR,
        ///0x4c - AHB2 peripheral clock enable register
        pub ahb2enr: AHB2ENR,
        ///0x50 - AHB3 peripheral clock enable register
        pub ahb3enr: AHB3ENR,
        _reserved19: [u8; 4usize],
        ///0x58 - APB1ENR1
        pub apb1enr1: APB1ENR1,
        ///0x5c - APB1 peripheral clock enable register 2
        pub apb1enr2: APB1ENR2,
        ///0x60 - APB2ENR
        pub apb2enr: APB2ENR,
        _reserved22: [u8; 4usize],
        ///0x68 - AHB1 peripheral clocks enable in Sleep and Stop modes register
        pub ahb1smenr: AHB1SMENR,
        ///0x6c - AHB2 peripheral clocks enable in Sleep and Stop modes register
        pub ahb2smenr: AHB2SMENR,
        ///0x70 - AHB3 peripheral clocks enable in Sleep and Stop modes register
        pub ahb3smenr: AHB3SMENR,
        _reserved25: [u8; 4usize],
        ///0x78 - APB1SMENR1
        pub apb1smenr1: APB1SMENR1,
        ///0x7c - APB1 peripheral clocks enable in Sleep and Stop modes register 2
        pub apb1smenr2: APB1SMENR2,
        ///0x80 - APB2SMENR
        pub apb2smenr: APB2SMENR,
        _reserved28: [u8; 4usize],
        ///0x88 - CCIPR
        pub ccipr: CCIPR,
        _reserved29: [u8; 4usize],
        ///0x90 - BDCR
        pub bdcr: BDCR,
        ///0x94 - CSR
        pub csr: CSR,
        ///0x98 - Clock recovery RC register
        pub crrcr: CRRCR,
        ///0x9c - Clock HSE register
        pub hsecr: HSECR,
        _reserved33: [u8; 104usize],
        ///0x108 - Extended clock recovery register
        pub extcfgr: EXTCFGR,
        _reserved34: [u8; 60usize],
        ///0x148 - CPU2 AHB1 peripheral clock enable register
        pub c2ahb1enr: C2AHB1ENR,
        ///0x14c - CPU2 AHB2 peripheral clock enable register
        pub c2ahb2enr: C2AHB2ENR,
        ///0x150 - CPU2 AHB3 peripheral clock enable register
        pub c2ahb3enr: C2AHB3ENR,
        _reserved37: [u8; 4usize],
        ///0x158 - CPU2 APB1ENR1
        pub c2apb1enr1: C2APB1ENR1,
        ///0x15c - CPU2 APB1 peripheral clock enable register 2
        pub c2apb1enr2: C2APB1ENR2,
        ///0x160 - CPU2 APB2ENR
        pub c2apb2enr: C2APB2ENR,
        ///0x164 - CPU2 APB3ENR
        pub c2apb3enr: C2APB3ENR,
        ///0x168 - CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
        pub c2ahb1smenr: C2AHB1SMENR,
        ///0x16c - CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
        pub c2ahb2smenr: C2AHB2SMENR,
        ///0x170 - CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
        pub c2ahb3smenr: C2AHB3SMENR,
        _reserved44: [u8; 4usize],
        ///0x178 - CPU2 APB1SMENR1
        pub c2apb1smenr1: C2APB1SMENR1,
        ///0x17c - CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
        pub c2apb1smenr2: C2APB1SMENR2,
        ///0x180 - CPU2 APB2SMENR
        pub c2apb2smenr: C2APB2SMENR,
        ///0x184 - CPU2 APB3SMENR
        pub c2apb3smenr: C2APB3SMENR,
    }
    ///Clock control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Clock control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0x61
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x61
            }
        }
        ///Reader of field `PLLSAI1RDY`
        pub type PLLSAI1RDY_R = crate::R<bool, bool>;
        ///Reader of field `PLLSAI1ON`
        pub type PLLSAI1ON_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLSAI1ON`
        pub struct PLLSAI1ON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLSAI1ON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `PLLRDY`
        pub type PLLRDY_R = crate::R<bool, bool>;
        ///Reader of field `PLLON`
        pub type PLLON_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLON`
        pub struct PLLON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `HSEPRE`
        pub type HSEPRE_R = crate::R<bool, bool>;
        ///Write proxy for field `HSEPRE`
        pub struct HSEPRE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSEPRE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `CSSON`
        pub struct CSSON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSSON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `HSEBYP`
        pub type HSEBYP_R = crate::R<bool, bool>;
        ///Write proxy for field `HSEBYP`
        pub struct HSEBYP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSEBYP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `HSERDY`
        pub type HSERDY_R = crate::R<bool, bool>;
        ///Reader of field `HSEON`
        pub type HSEON_R = crate::R<bool, bool>;
        ///Write proxy for field `HSEON`
        pub struct HSEON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSEON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `HSIKERDY`
        pub type HSIKERDY_R = crate::R<bool, bool>;
        ///Reader of field `HSIASFS`
        pub type HSIASFS_R = crate::R<bool, bool>;
        ///Write proxy for field `HSIASFS`
        pub struct HSIASFS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSIASFS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `HSIRDY`
        pub type HSIRDY_R = crate::R<bool, bool>;
        ///Reader of field `HSIKERON`
        pub type HSIKERON_R = crate::R<bool, bool>;
        ///Write proxy for field `HSIKERON`
        pub struct HSIKERON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSIKERON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `HSION`
        pub type HSION_R = crate::R<bool, bool>;
        ///Write proxy for field `HSION`
        pub struct HSION_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSION_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `MSIRANGE`
        pub type MSIRANGE_R = crate::R<u8, u8>;
        ///Write proxy for field `MSIRANGE`
        pub struct MSIRANGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIRANGE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `MSIPLLEN`
        pub type MSIPLLEN_R = crate::R<bool, bool>;
        ///Write proxy for field `MSIPLLEN`
        pub struct MSIPLLEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIPLLEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `MSIRDY`
        pub type MSIRDY_R = crate::R<bool, bool>;
        ///Reader of field `MSION`
        pub type MSION_R = crate::R<bool, bool>;
        ///Write proxy for field `MSION`
        pub struct MSION_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSION_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 27 - SAI1 PLL clock ready flag
            #[inline(always)]
            pub fn pllsai1rdy(&self) -> PLLSAI1RDY_R {
                PLLSAI1RDY_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - SAI1 PLL enable
            #[inline(always)]
            pub fn pllsai1on(&self) -> PLLSAI1ON_R {
                PLLSAI1ON_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - Main PLL clock ready flag
            #[inline(always)]
            pub fn pllrdy(&self) -> PLLRDY_R {
                PLLRDY_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - Main PLL enable
            #[inline(always)]
            pub fn pllon(&self) -> PLLON_R {
                PLLON_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 20 - HSE sysclk and PLL M divider prescaler
            #[inline(always)]
            pub fn hsepre(&self) -> HSEPRE_R {
                HSEPRE_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 18 - HSE crystal oscillator bypass
            #[inline(always)]
            pub fn hsebyp(&self) -> HSEBYP_R {
                HSEBYP_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - HSE clock ready flag
            #[inline(always)]
            pub fn hserdy(&self) -> HSERDY_R {
                HSERDY_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - HSE clock enabled
            #[inline(always)]
            pub fn hseon(&self) -> HSEON_R {
                HSEON_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 12 - HSI kernel clock ready flag for peripherals requests
            #[inline(always)]
            pub fn hsikerdy(&self) -> HSIKERDY_R {
                HSIKERDY_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - HSI automatic start from Stop
            #[inline(always)]
            pub fn hsiasfs(&self) -> HSIASFS_R {
                HSIASFS_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - HSI clock ready flag
            #[inline(always)]
            pub fn hsirdy(&self) -> HSIRDY_R {
                HSIRDY_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - HSI always enable for peripheral kernels
            #[inline(always)]
            pub fn hsikeron(&self) -> HSIKERON_R {
                HSIKERON_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - HSI clock enabled
            #[inline(always)]
            pub fn hsion(&self) -> HSION_R {
                HSION_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 4:7 - MSI clock ranges
            #[inline(always)]
            pub fn msirange(&self) -> MSIRANGE_R {
                MSIRANGE_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bit 2 - MSI clock PLL enable
            #[inline(always)]
            pub fn msipllen(&self) -> MSIPLLEN_R {
                MSIPLLEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - MSI clock ready flag
            #[inline(always)]
            pub fn msirdy(&self) -> MSIRDY_R {
                MSIRDY_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - MSI clock enable
            #[inline(always)]
            pub fn msion(&self) -> MSION_R {
                MSION_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 26 - SAI1 PLL enable
            #[inline(always)]
            pub fn pllsai1on(&mut self) -> PLLSAI1ON_W {
                PLLSAI1ON_W { w: self }
            }
            ///Bit 24 - Main PLL enable
            #[inline(always)]
            pub fn pllon(&mut self) -> PLLON_W {
                PLLON_W { w: self }
            }
            ///Bit 20 - HSE sysclk and PLL M divider prescaler
            #[inline(always)]
            pub fn hsepre(&mut self) -> HSEPRE_W {
                HSEPRE_W { w: self }
            }
            ///Bit 19 - HSE Clock security system enable
            #[inline(always)]
            pub fn csson(&mut self) -> CSSON_W {
                CSSON_W { w: self }
            }
            ///Bit 18 - HSE crystal oscillator bypass
            #[inline(always)]
            pub fn hsebyp(&mut self) -> HSEBYP_W {
                HSEBYP_W { w: self }
            }
            ///Bit 16 - HSE clock enabled
            #[inline(always)]
            pub fn hseon(&mut self) -> HSEON_W {
                HSEON_W { w: self }
            }
            ///Bit 11 - HSI automatic start from Stop
            #[inline(always)]
            pub fn hsiasfs(&mut self) -> HSIASFS_W {
                HSIASFS_W { w: self }
            }
            ///Bit 9 - HSI always enable for peripheral kernels
            #[inline(always)]
            pub fn hsikeron(&mut self) -> HSIKERON_W {
                HSIKERON_W { w: self }
            }
            ///Bit 8 - HSI clock enabled
            #[inline(always)]
            pub fn hsion(&mut self) -> HSION_W {
                HSION_W { w: self }
            }
            ///Bits 4:7 - MSI clock ranges
            #[inline(always)]
            pub fn msirange(&mut self) -> MSIRANGE_W {
                MSIRANGE_W { w: self }
            }
            ///Bit 2 - MSI clock PLL enable
            #[inline(always)]
            pub fn msipllen(&mut self) -> MSIPLLEN_W {
                MSIPLLEN_W { w: self }
            }
            ///Bit 0 - MSI clock enable
            #[inline(always)]
            pub fn msion(&mut self) -> MSION_W {
                MSION_W { w: self }
            }
        }
    }
    ///Internal clock sources calibration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [icscr](icscr) module
    pub type ICSCR = crate::Reg<u32, _ICSCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ICSCR;
    ///`read()` method returns [icscr::R](icscr::R) reader structure
    impl crate::Readable for ICSCR {}
    ///`write(|w| ..)` method takes [icscr::W](icscr::W) writer structure
    impl crate::Writable for ICSCR {}
    ///Internal clock sources calibration register
    pub mod icscr {
        ///Reader of register ICSCR
        pub type R = crate::R<u32, super::ICSCR>;
        ///Writer for register ICSCR
        pub type W = crate::W<u32, super::ICSCR>;
        ///Register ICSCR `reset()`'s with value 0x4000_0000
        impl crate::ResetValue for super::ICSCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x4000_0000
            }
        }
        ///Reader of field `HSITRIM`
        pub type HSITRIM_R = crate::R<u8, u8>;
        ///Write proxy for field `HSITRIM`
        pub struct HSITRIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSITRIM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7f << 24)) | (((value as u32) & 0x7f) << 24);
                self.w
            }
        }
        ///Reader of field `HSICAL`
        pub type HSICAL_R = crate::R<u8, u8>;
        ///Reader of field `MSITRIM`
        pub type MSITRIM_R = crate::R<u8, u8>;
        ///Write proxy for field `MSITRIM`
        pub struct MSITRIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSITRIM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
                self.w
            }
        }
        ///Reader of field `MSICAL`
        pub type MSICAL_R = crate::R<u8, u8>;
        impl R {
            ///Bits 24:30 - HSI clock trimming
            #[inline(always)]
            pub fn hsitrim(&self) -> HSITRIM_R {
                HSITRIM_R::new(((self.bits >> 24) & 0x7f) as u8)
            }
            ///Bits 16:23 - HSI clock calibration
            #[inline(always)]
            pub fn hsical(&self) -> HSICAL_R {
                HSICAL_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            ///Bits 8:15 - MSI clock trimming
            #[inline(always)]
            pub fn msitrim(&self) -> MSITRIM_R {
                MSITRIM_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            ///Bits 0:7 - MSI clock calibration
            #[inline(always)]
            pub fn msical(&self) -> MSICAL_R {
                MSICAL_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 24:30 - HSI clock trimming
            #[inline(always)]
            pub fn hsitrim(&mut self) -> HSITRIM_W {
                HSITRIM_W { w: self }
            }
            ///Bits 8:15 - MSI clock trimming
            #[inline(always)]
            pub fn msitrim(&mut self) -> MSITRIM_W {
                MSITRIM_W { w: self }
            }
        }
    }
    ///Clock configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfgr](cfgr) module
    pub type CFGR = crate::Reg<u32, _CFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFGR;
    ///`read()` method returns [cfgr::R](cfgr::R) reader structure
    impl crate::Readable for CFGR {}
    ///`write(|w| ..)` method takes [cfgr::W](cfgr::W) writer structure
    impl crate::Writable for CFGR {}
    ///Clock configuration register
    pub mod cfgr {
        ///Reader of register CFGR
        pub type R = crate::R<u32, super::CFGR>;
        ///Writer for register CFGR
        pub type W = crate::W<u32, super::CFGR>;
        ///Register CFGR `reset()`'s with value 0x0007_0000
        impl crate::ResetValue for super::CFGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0007_0000
            }
        }
        ///Reader of field `MCOPRE`
        pub type MCOPRE_R = crate::R<u8, u8>;
        ///Write proxy for field `MCOPRE`
        pub struct MCOPRE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MCOPRE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 28)) | (((value as u32) & 0x07) << 28);
                self.w
            }
        }
        ///Reader of field `MCOSEL`
        pub type MCOSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `MCOSEL`
        pub struct MCOSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MCOSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `PPRE2F`
        pub type PPRE2F_R = crate::R<bool, bool>;
        ///Reader of field `PPRE1F`
        pub type PPRE1F_R = crate::R<bool, bool>;
        ///Reader of field `HPREF`
        pub type HPREF_R = crate::R<bool, bool>;
        ///Reader of field `STOPWUCK`
        pub type STOPWUCK_R = crate::R<bool, bool>;
        ///Write proxy for field `STOPWUCK`
        pub struct STOPWUCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STOPWUCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PPRE2`
        pub type PPRE2_R = crate::R<u8, u8>;
        ///Write proxy for field `PPRE2`
        pub struct PPRE2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PPRE2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 11)) | (((value as u32) & 0x07) << 11);
                self.w
            }
        }
        ///Reader of field `PPRE1`
        pub type PPRE1_R = crate::R<u8, u8>;
        ///Write proxy for field `PPRE1`
        pub struct PPRE1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PPRE1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `HPRE`
        pub type HPRE_R = crate::R<u8, u8>;
        ///Write proxy for field `HPRE`
        pub struct HPRE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HPRE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `SWS`
        pub type SWS_R = crate::R<u8, u8>;
        ///Reader of field `SW`
        pub type SW_R = crate::R<u8, u8>;
        ///Write proxy for field `SW`
        pub struct SW_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SW_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 28:30 - Microcontroller clock output prescaler
            #[inline(always)]
            pub fn mcopre(&self) -> MCOPRE_R {
                MCOPRE_R::new(((self.bits >> 28) & 0x07) as u8)
            }
            ///Bits 24:27 - Microcontroller clock output
            #[inline(always)]
            pub fn mcosel(&self) -> MCOSEL_R {
                MCOSEL_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bit 18 - APB2 prescaler flag
            #[inline(always)]
            pub fn ppre2f(&self) -> PPRE2F_R {
                PPRE2F_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - APB1 prescaler flag
            #[inline(always)]
            pub fn ppre1f(&self) -> PPRE1F_R {
                PPRE1F_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - AHB prescaler flag
            #[inline(always)]
            pub fn hpref(&self) -> HPREF_R {
                HPREF_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Wakeup from Stop and CSS backup clock selection
            #[inline(always)]
            pub fn stopwuck(&self) -> STOPWUCK_R {
                STOPWUCK_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 11:13 - APB high-speed prescaler (APB2)
            #[inline(always)]
            pub fn ppre2(&self) -> PPRE2_R {
                PPRE2_R::new(((self.bits >> 11) & 0x07) as u8)
            }
            ///Bits 8:10 - PB low-speed prescaler (APB1)
            #[inline(always)]
            pub fn ppre1(&self) -> PPRE1_R {
                PPRE1_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bits 4:7 - AHB prescaler
            #[inline(always)]
            pub fn hpre(&self) -> HPRE_R {
                HPRE_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 2:3 - System clock switch status
            #[inline(always)]
            pub fn sws(&self) -> SWS_R {
                SWS_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - System clock switch
            #[inline(always)]
            pub fn sw(&self) -> SW_R {
                SW_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 28:30 - Microcontroller clock output prescaler
            #[inline(always)]
            pub fn mcopre(&mut self) -> MCOPRE_W {
                MCOPRE_W { w: self }
            }
            ///Bits 24:27 - Microcontroller clock output
            #[inline(always)]
            pub fn mcosel(&mut self) -> MCOSEL_W {
                MCOSEL_W { w: self }
            }
            ///Bit 15 - Wakeup from Stop and CSS backup clock selection
            #[inline(always)]
            pub fn stopwuck(&mut self) -> STOPWUCK_W {
                STOPWUCK_W { w: self }
            }
            ///Bits 11:13 - APB high-speed prescaler (APB2)
            #[inline(always)]
            pub fn ppre2(&mut self) -> PPRE2_W {
                PPRE2_W { w: self }
            }
            ///Bits 8:10 - PB low-speed prescaler (APB1)
            #[inline(always)]
            pub fn ppre1(&mut self) -> PPRE1_W {
                PPRE1_W { w: self }
            }
            ///Bits 4:7 - AHB prescaler
            #[inline(always)]
            pub fn hpre(&mut self) -> HPRE_W {
                HPRE_W { w: self }
            }
            ///Bits 0:1 - System clock switch
            #[inline(always)]
            pub fn sw(&mut self) -> SW_W {
                SW_W { w: self }
            }
        }
    }
    ///PLLSYS configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pllcfgr](pllcfgr) module
    pub type PLLCFGR = crate::Reg<u32, _PLLCFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PLLCFGR;
    ///`read()` method returns [pllcfgr::R](pllcfgr::R) reader structure
    impl crate::Readable for PLLCFGR {}
    ///`write(|w| ..)` method takes [pllcfgr::W](pllcfgr::W) writer structure
    impl crate::Writable for PLLCFGR {}
    ///PLLSYS configuration register
    pub mod pllcfgr {
        ///Reader of register PLLCFGR
        pub type R = crate::R<u32, super::PLLCFGR>;
        ///Writer for register PLLCFGR
        pub type W = crate::W<u32, super::PLLCFGR>;
        ///Register PLLCFGR `reset()`'s with value 0x2204_0100
        impl crate::ResetValue for super::PLLCFGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x2204_0100
            }
        }
        ///Reader of field `PLLR`
        pub type PLLR_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLR`
        pub struct PLLR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
                self.w
            }
        }
        ///Reader of field `PLLREN`
        pub type PLLREN_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLREN`
        pub struct PLLREN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLREN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `PLLQ`
        pub type PLLQ_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLQ`
        pub struct PLLQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 25)) | (((value as u32) & 0x07) << 25);
                self.w
            }
        }
        ///Reader of field `PLLQEN`
        pub type PLLQEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLQEN`
        pub struct PLLQEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLQEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `PLLP`
        pub type PLLP_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLP`
        pub struct PLLP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 17)) | (((value as u32) & 0x1f) << 17);
                self.w
            }
        }
        ///Reader of field `PLLPEN`
        pub type PLLPEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLPEN`
        pub struct PLLPEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLPEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `PLLN`
        pub type PLLN_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLN`
        pub struct PLLN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
                self.w
            }
        }
        ///Reader of field `PLLM`
        pub type PLLM_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLM`
        pub struct PLLM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `PLLSRC`
        pub type PLLSRC_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLSRC`
        pub struct PLLSRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLSRC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)
            #[inline(always)]
            pub fn pllr(&self) -> PLLR_R {
                PLLR_R::new(((self.bits >> 29) & 0x07) as u8)
            }
            ///Bit 28 - Main PLLSYSR PLLCLK output enable
            #[inline(always)]
            pub fn pllren(&self) -> PLLREN_R {
                PLLREN_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK
            #[inline(always)]
            pub fn pllq(&self) -> PLLQ_R {
                PLLQ_R::new(((self.bits >> 25) & 0x07) as u8)
            }
            ///Bit 24 - Main PLLSYSQ output enable
            #[inline(always)]
            pub fn pllqen(&self) -> PLLQEN_R {
                PLLQEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK
            #[inline(always)]
            pub fn pllp(&self) -> PLLP_R {
                PLLP_R::new(((self.bits >> 17) & 0x1f) as u8)
            }
            ///Bit 16 - Main PLLSYSP output enable
            #[inline(always)]
            pub fn pllpen(&self) -> PLLPEN_R {
                PLLPEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 8:14 - Main PLLSYS multiplication factor N
            #[inline(always)]
            pub fn plln(&self) -> PLLN_R {
                PLLN_R::new(((self.bits >> 8) & 0x7f) as u8)
            }
            ///Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
            #[inline(always)]
            pub fn pllm(&self) -> PLLM_R {
                PLLM_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source
            #[inline(always)]
            pub fn pllsrc(&self) -> PLLSRC_R {
                PLLSRC_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)
            #[inline(always)]
            pub fn pllr(&mut self) -> PLLR_W {
                PLLR_W { w: self }
            }
            ///Bit 28 - Main PLLSYSR PLLCLK output enable
            #[inline(always)]
            pub fn pllren(&mut self) -> PLLREN_W {
                PLLREN_W { w: self }
            }
            ///Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK
            #[inline(always)]
            pub fn pllq(&mut self) -> PLLQ_W {
                PLLQ_W { w: self }
            }
            ///Bit 24 - Main PLLSYSQ output enable
            #[inline(always)]
            pub fn pllqen(&mut self) -> PLLQEN_W {
                PLLQEN_W { w: self }
            }
            ///Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK
            #[inline(always)]
            pub fn pllp(&mut self) -> PLLP_W {
                PLLP_W { w: self }
            }
            ///Bit 16 - Main PLLSYSP output enable
            #[inline(always)]
            pub fn pllpen(&mut self) -> PLLPEN_W {
                PLLPEN_W { w: self }
            }
            ///Bits 8:14 - Main PLLSYS multiplication factor N
            #[inline(always)]
            pub fn plln(&mut self) -> PLLN_W {
                PLLN_W { w: self }
            }
            ///Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
            #[inline(always)]
            pub fn pllm(&mut self) -> PLLM_W {
                PLLM_W { w: self }
            }
            ///Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source
            #[inline(always)]
            pub fn pllsrc(&mut self) -> PLLSRC_W {
                PLLSRC_W { w: self }
            }
        }
    }
    ///PLLSAI1 configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pllsai1cfgr](pllsai1cfgr) module
    pub type PLLSAI1CFGR = crate::Reg<u32, _PLLSAI1CFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PLLSAI1CFGR;
    ///`read()` method returns [pllsai1cfgr::R](pllsai1cfgr::R) reader structure
    impl crate::Readable for PLLSAI1CFGR {}
    ///`write(|w| ..)` method takes [pllsai1cfgr::W](pllsai1cfgr::W) writer structure
    impl crate::Writable for PLLSAI1CFGR {}
    ///PLLSAI1 configuration register
    pub mod pllsai1cfgr {
        ///Reader of register PLLSAI1CFGR
        pub type R = crate::R<u32, super::PLLSAI1CFGR>;
        ///Writer for register PLLSAI1CFGR
        pub type W = crate::W<u32, super::PLLSAI1CFGR>;
        ///Register PLLSAI1CFGR `reset()`'s with value 0x2204_0100
        impl crate::ResetValue for super::PLLSAI1CFGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x2204_0100
            }
        }
        ///Reader of field `PLLR`
        pub type PLLR_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLR`
        pub struct PLLR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
                self.w
            }
        }
        ///Reader of field `PLLREN`
        pub type PLLREN_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLREN`
        pub struct PLLREN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLREN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `PLLQ`
        pub type PLLQ_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLQ`
        pub struct PLLQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 25)) | (((value as u32) & 0x07) << 25);
                self.w
            }
        }
        ///Reader of field `PLLQEN`
        pub type PLLQEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLQEN`
        pub struct PLLQEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLQEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `PLLP`
        pub type PLLP_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLP`
        pub struct PLLP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 17)) | (((value as u32) & 0x1f) << 17);
                self.w
            }
        }
        ///Reader of field `PLLPEN`
        pub type PLLPEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLPEN`
        pub struct PLLPEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLPEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `PLLN`
        pub type PLLN_R = crate::R<u8, u8>;
        ///Write proxy for field `PLLN`
        pub struct PLLN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
                self.w
            }
        }
        impl R {
            ///Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)
            #[inline(always)]
            pub fn pllr(&self) -> PLLR_R {
                PLLR_R::new(((self.bits >> 29) & 0x07) as u8)
            }
            ///Bit 28 - PLLSAI PLLADC1CLK output enable
            #[inline(always)]
            pub fn pllren(&self) -> PLLREN_R {
                PLLREN_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
            #[inline(always)]
            pub fn pllq(&self) -> PLLQ_R {
                PLLQ_R::new(((self.bits >> 25) & 0x07) as u8)
            }
            ///Bit 24 - SAIPLL PLLSAIUSBCLK output enable
            #[inline(always)]
            pub fn pllqen(&self) -> PLLQEN_R {
                PLLQEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)
            #[inline(always)]
            pub fn pllp(&self) -> PLLP_R {
                PLLP_R::new(((self.bits >> 17) & 0x1f) as u8)
            }
            ///Bit 16 - SAIPLL PLLSAI1CLK output enable
            #[inline(always)]
            pub fn pllpen(&self) -> PLLPEN_R {
                PLLPEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 8:14 - SAIPLL multiplication factor for VCO
            #[inline(always)]
            pub fn plln(&self) -> PLLN_R {
                PLLN_R::new(((self.bits >> 8) & 0x7f) as u8)
            }
        }
        impl W {
            ///Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)
            #[inline(always)]
            pub fn pllr(&mut self) -> PLLR_W {
                PLLR_W { w: self }
            }
            ///Bit 28 - PLLSAI PLLADC1CLK output enable
            #[inline(always)]
            pub fn pllren(&mut self) -> PLLREN_W {
                PLLREN_W { w: self }
            }
            ///Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
            #[inline(always)]
            pub fn pllq(&mut self) -> PLLQ_W {
                PLLQ_W { w: self }
            }
            ///Bit 24 - SAIPLL PLLSAIUSBCLK output enable
            #[inline(always)]
            pub fn pllqen(&mut self) -> PLLQEN_W {
                PLLQEN_W { w: self }
            }
            ///Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)
            #[inline(always)]
            pub fn pllp(&mut self) -> PLLP_W {
                PLLP_W { w: self }
            }
            ///Bit 16 - SAIPLL PLLSAI1CLK output enable
            #[inline(always)]
            pub fn pllpen(&mut self) -> PLLPEN_W {
                PLLPEN_W { w: self }
            }
            ///Bits 8:14 - SAIPLL multiplication factor for VCO
            #[inline(always)]
            pub fn plln(&mut self) -> PLLN_W {
                PLLN_W { w: self }
            }
        }
    }
    ///Clock interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cier](cier) module
    pub type CIER = crate::Reg<u32, _CIER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CIER;
    ///`read()` method returns [cier::R](cier::R) reader structure
    impl crate::Readable for CIER {}
    ///`write(|w| ..)` method takes [cier::W](cier::W) writer structure
    impl crate::Writable for CIER {}
    ///Clock interrupt enable register
    pub mod cier {
        ///Reader of register CIER
        pub type R = crate::R<u32, super::CIER>;
        ///Writer for register CIER
        pub type W = crate::W<u32, super::CIER>;
        ///Register CIER `reset()`'s with value 0
        impl crate::ResetValue for super::CIER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LSI2RDYIE`
        pub type LSI2RDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `LSI2RDYIE`
        pub struct LSI2RDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI2RDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `HSI48RDYIE`
        pub type HSI48RDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HSI48RDYIE`
        pub struct HSI48RDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSI48RDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LSECSSIE`
        pub type LSECSSIE_R = crate::R<bool, bool>;
        ///Write proxy for field `LSECSSIE`
        pub struct LSECSSIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSECSSIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PLLSAI1RDYIE`
        pub type PLLSAI1RDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLSAI1RDYIE`
        pub struct PLLSAI1RDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLSAI1RDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PLLRDYIE`
        pub type PLLRDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `PLLRDYIE`
        pub struct PLLRDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLRDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `HSERDYIE`
        pub type HSERDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HSERDYIE`
        pub struct HSERDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSERDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `HSIRDYIE`
        pub type HSIRDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `HSIRDYIE`
        pub struct HSIRDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSIRDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `MSIRDYIE`
        pub type MSIRDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `MSIRDYIE`
        pub struct MSIRDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIRDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `LSERDYIE`
        pub type LSERDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `LSERDYIE`
        pub struct LSERDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSERDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LSI1RDYIE`
        pub type LSI1RDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `LSI1RDYIE`
        pub struct LSI1RDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI1RDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 11 - LSI2 ready interrupt enable
            #[inline(always)]
            pub fn lsi2rdyie(&self) -> LSI2RDYIE_R {
                LSI2RDYIE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - HSI48 ready interrupt enable
            #[inline(always)]
            pub fn hsi48rdyie(&self) -> HSI48RDYIE_R {
                HSI48RDYIE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - LSE clock security system interrupt enable
            #[inline(always)]
            pub fn lsecssie(&self) -> LSECSSIE_R {
                LSECSSIE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 6 - PLLSAI1 ready interrupt enable
            #[inline(always)]
            pub fn pllsai1rdyie(&self) -> PLLSAI1RDYIE_R {
                PLLSAI1RDYIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - PLLSYS ready interrupt enable
            #[inline(always)]
            pub fn pllrdyie(&self) -> PLLRDYIE_R {
                PLLRDYIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - HSE ready interrupt enable
            #[inline(always)]
            pub fn hserdyie(&self) -> HSERDYIE_R {
                HSERDYIE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - HSI ready interrupt enable
            #[inline(always)]
            pub fn hsirdyie(&self) -> HSIRDYIE_R {
                HSIRDYIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - MSI ready interrupt enable
            #[inline(always)]
            pub fn msirdyie(&self) -> MSIRDYIE_R {
                MSIRDYIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - LSE ready interrupt enable
            #[inline(always)]
            pub fn lserdyie(&self) -> LSERDYIE_R {
                LSERDYIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - LSI1 ready interrupt enable
            #[inline(always)]
            pub fn lsi1rdyie(&self) -> LSI1RDYIE_R {
                LSI1RDYIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 11 - LSI2 ready interrupt enable
            #[inline(always)]
            pub fn lsi2rdyie(&mut self) -> LSI2RDYIE_W {
                LSI2RDYIE_W { w: self }
            }
            ///Bit 10 - HSI48 ready interrupt enable
            #[inline(always)]
            pub fn hsi48rdyie(&mut self) -> HSI48RDYIE_W {
                HSI48RDYIE_W { w: self }
            }
            ///Bit 9 - LSE clock security system interrupt enable
            #[inline(always)]
            pub fn lsecssie(&mut self) -> LSECSSIE_W {
                LSECSSIE_W { w: self }
            }
            ///Bit 6 - PLLSAI1 ready interrupt enable
            #[inline(always)]
            pub fn pllsai1rdyie(&mut self) -> PLLSAI1RDYIE_W {
                PLLSAI1RDYIE_W { w: self }
            }
            ///Bit 5 - PLLSYS ready interrupt enable
            #[inline(always)]
            pub fn pllrdyie(&mut self) -> PLLRDYIE_W {
                PLLRDYIE_W { w: self }
            }
            ///Bit 4 - HSE ready interrupt enable
            #[inline(always)]
            pub fn hserdyie(&mut self) -> HSERDYIE_W {
                HSERDYIE_W { w: self }
            }
            ///Bit 3 - HSI ready interrupt enable
            #[inline(always)]
            pub fn hsirdyie(&mut self) -> HSIRDYIE_W {
                HSIRDYIE_W { w: self }
            }
            ///Bit 2 - MSI ready interrupt enable
            #[inline(always)]
            pub fn msirdyie(&mut self) -> MSIRDYIE_W {
                MSIRDYIE_W { w: self }
            }
            ///Bit 1 - LSE ready interrupt enable
            #[inline(always)]
            pub fn lserdyie(&mut self) -> LSERDYIE_W {
                LSERDYIE_W { w: self }
            }
            ///Bit 0 - LSI1 ready interrupt enable
            #[inline(always)]
            pub fn lsi1rdyie(&mut self) -> LSI1RDYIE_W {
                LSI1RDYIE_W { w: self }
            }
        }
    }
    ///Clock interrupt flag register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cifr](cifr) module
    pub type CIFR = crate::Reg<u32, _CIFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CIFR;
    ///`read()` method returns [cifr::R](cifr::R) reader structure
    impl crate::Readable for CIFR {}
    ///Clock interrupt flag register
    pub mod cifr {
        ///Reader of register CIFR
        pub type R = crate::R<u32, super::CIFR>;
        ///Reader of field `LSI2RDYF`
        pub type LSI2RDYF_R = crate::R<bool, bool>;
        ///Reader of field `HSI48RDYF`
        pub type HSI48RDYF_R = crate::R<bool, bool>;
        ///Reader of field `LSECSSF`
        pub type LSECSSF_R = crate::R<bool, bool>;
        ///Reader of field `HSECSSF`
        pub type HSECSSF_R = crate::R<bool, bool>;
        ///Reader of field `PLLSAI1RDYF`
        pub type PLLSAI1RDYF_R = crate::R<bool, bool>;
        ///Reader of field `PLLRDYF`
        pub type PLLRDYF_R = crate::R<bool, bool>;
        ///Reader of field `HSERDYF`
        pub type HSERDYF_R = crate::R<bool, bool>;
        ///Reader of field `HSIRDYF`
        pub type HSIRDYF_R = crate::R<bool, bool>;
        ///Reader of field `MSIRDYF`
        pub type MSIRDYF_R = crate::R<bool, bool>;
        ///Reader of field `LSERDYF`
        pub type LSERDYF_R = crate::R<bool, bool>;
        ///Reader of field `LSI1RDYF`
        pub type LSI1RDYF_R = crate::R<bool, bool>;
        impl R {
            ///Bit 11 - LSI2 ready interrupt flag
            #[inline(always)]
            pub fn lsi2rdyf(&self) -> LSI2RDYF_R {
                LSI2RDYF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - HSI48 ready interrupt flag
            #[inline(always)]
            pub fn hsi48rdyf(&self) -> HSI48RDYF_R {
                HSI48RDYF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - LSE Clock security system interrupt flag
            #[inline(always)]
            pub fn lsecssf(&self) -> LSECSSF_R {
                LSECSSF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - HSE Clock security system interrupt flag
            #[inline(always)]
            pub fn hsecssf(&self) -> HSECSSF_R {
                HSECSSF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 6 - PLLSAI1 ready interrupt flag
            #[inline(always)]
            pub fn pllsai1rdyf(&self) -> PLLSAI1RDYF_R {
                PLLSAI1RDYF_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - PLL ready interrupt flag
            #[inline(always)]
            pub fn pllrdyf(&self) -> PLLRDYF_R {
                PLLRDYF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - HSE ready interrupt flag
            #[inline(always)]
            pub fn hserdyf(&self) -> HSERDYF_R {
                HSERDYF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - HSI ready interrupt flag
            #[inline(always)]
            pub fn hsirdyf(&self) -> HSIRDYF_R {
                HSIRDYF_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - MSI ready interrupt flag
            #[inline(always)]
            pub fn msirdyf(&self) -> MSIRDYF_R {
                MSIRDYF_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - LSE ready interrupt flag
            #[inline(always)]
            pub fn lserdyf(&self) -> LSERDYF_R {
                LSERDYF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - LSI1 ready interrupt flag
            #[inline(always)]
            pub fn lsi1rdyf(&self) -> LSI1RDYF_R {
                LSI1RDYF_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///Clock interrupt clear register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cicr](cicr) module
    pub type CICR = crate::Reg<u32, _CICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CICR;
    ///`write(|w| ..)` method takes [cicr::W](cicr::W) writer structure
    impl crate::Writable for CICR {}
    ///Clock interrupt clear register
    pub mod cicr {
        ///Writer for register CICR
        pub type W = crate::W<u32, super::CICR>;
        ///Register CICR `reset()`'s with value 0
        impl crate::ResetValue for super::CICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `LSI2RDYC`
        pub struct LSI2RDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI2RDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `HSI48RDYC`
        pub struct HSI48RDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSI48RDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `LSECSSC`
        pub struct LSECSSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSECSSC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `HSECSSC`
        pub struct HSECSSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSECSSC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `PLLSAI1RDYC`
        pub struct PLLSAI1RDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLSAI1RDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `PLLRDYC`
        pub struct PLLRDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLLRDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `HSERDYC`
        pub struct HSERDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSERDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `HSIRDYC`
        pub struct HSIRDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSIRDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `MSIRDYC`
        pub struct MSIRDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSIRDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `LSERDYC`
        pub struct LSERDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSERDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `LSI1RDYC`
        pub struct LSI1RDYC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI1RDYC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 11 - LSI2 ready interrupt clear
            #[inline(always)]
            pub fn lsi2rdyc(&mut self) -> LSI2RDYC_W {
                LSI2RDYC_W { w: self }
            }
            ///Bit 10 - HSI48 ready interrupt clear
            #[inline(always)]
            pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W {
                HSI48RDYC_W { w: self }
            }
            ///Bit 9 - LSE Clock security system interrupt clear
            #[inline(always)]
            pub fn lsecssc(&mut self) -> LSECSSC_W {
                LSECSSC_W { w: self }
            }
            ///Bit 8 - HSE Clock security system interrupt clear
            #[inline(always)]
            pub fn hsecssc(&mut self) -> HSECSSC_W {
                HSECSSC_W { w: self }
            }
            ///Bit 6 - PLLSAI1 ready interrupt clear
            #[inline(always)]
            pub fn pllsai1rdyc(&mut self) -> PLLSAI1RDYC_W {
                PLLSAI1RDYC_W { w: self }
            }
            ///Bit 5 - PLL ready interrupt clear
            #[inline(always)]
            pub fn pllrdyc(&mut self) -> PLLRDYC_W {
                PLLRDYC_W { w: self }
            }
            ///Bit 4 - HSE ready interrupt clear
            #[inline(always)]
            pub fn hserdyc(&mut self) -> HSERDYC_W {
                HSERDYC_W { w: self }
            }
            ///Bit 3 - HSI ready interrupt clear
            #[inline(always)]
            pub fn hsirdyc(&mut self) -> HSIRDYC_W {
                HSIRDYC_W { w: self }
            }
            ///Bit 2 - MSI ready interrupt clear
            #[inline(always)]
            pub fn msirdyc(&mut self) -> MSIRDYC_W {
                MSIRDYC_W { w: self }
            }
            ///Bit 1 - LSE ready interrupt clear
            #[inline(always)]
            pub fn lserdyc(&mut self) -> LSERDYC_W {
                LSERDYC_W { w: self }
            }
            ///Bit 0 - LSI1 ready interrupt clear
            #[inline(always)]
            pub fn lsi1rdyc(&mut self) -> LSI1RDYC_W {
                LSI1RDYC_W { w: self }
            }
        }
    }
    ///Step Down converter control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [smpscr](smpscr) module
    pub type SMPSCR = crate::Reg<u32, _SMPSCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SMPSCR;
    ///`read()` method returns [smpscr::R](smpscr::R) reader structure
    impl crate::Readable for SMPSCR {}
    ///`write(|w| ..)` method takes [smpscr::W](smpscr::W) writer structure
    impl crate::Writable for SMPSCR {}
    ///Step Down converter control register
    pub mod smpscr {
        ///Reader of register SMPSCR
        pub type R = crate::R<u32, super::SMPSCR>;
        ///Writer for register SMPSCR
        pub type W = crate::W<u32, super::SMPSCR>;
        ///Register SMPSCR `reset()`'s with value 0x0301
        impl crate::ResetValue for super::SMPSCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0301
            }
        }
        ///Reader of field `SMPSSWS`
        pub type SMPSSWS_R = crate::R<u8, u8>;
        ///Reader of field `SMPSDIV`
        pub type SMPSDIV_R = crate::R<u8, u8>;
        ///Write proxy for field `SMPSDIV`
        pub struct SMPSDIV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMPSDIV_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `SMPSSEL`
        pub type SMPSSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `SMPSSEL`
        pub struct SMPSSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMPSSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 8:9 - Step Down converter clock switch status
            #[inline(always)]
            pub fn smpssws(&self) -> SMPSSWS_R {
                SMPSSWS_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 4:5 - Step Down converter clock prescaler
            #[inline(always)]
            pub fn smpsdiv(&self) -> SMPSDIV_R {
                SMPSDIV_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 0:1 - Step Down converter clock selection
            #[inline(always)]
            pub fn smpssel(&self) -> SMPSSEL_R {
                SMPSSEL_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 4:5 - Step Down converter clock prescaler
            #[inline(always)]
            pub fn smpsdiv(&mut self) -> SMPSDIV_W {
                SMPSDIV_W { w: self }
            }
            ///Bits 0:1 - Step Down converter clock selection
            #[inline(always)]
            pub fn smpssel(&mut self) -> SMPSSEL_W {
                SMPSSEL_W { w: self }
            }
        }
    }
    ///AHB1 peripheral reset register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb1rstr](ahb1rstr) module
    pub type AHB1RSTR = crate::Reg<u32, _AHB1RSTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB1RSTR;
    ///`read()` method returns [ahb1rstr::R](ahb1rstr::R) reader structure
    impl crate::Readable for AHB1RSTR {}
    ///`write(|w| ..)` method takes [ahb1rstr::W](ahb1rstr::W) writer structure
    impl crate::Writable for AHB1RSTR {}
    ///AHB1 peripheral reset register
    pub mod ahb1rstr {
        ///Reader of register AHB1RSTR
        pub type R = crate::R<u32, super::AHB1RSTR>;
        ///Writer for register AHB1RSTR
        pub type W = crate::W<u32, super::AHB1RSTR>;
        ///Register AHB1RSTR `reset()`'s with value 0
        impl crate::ResetValue for super::AHB1RSTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TSCRST`
        pub type TSCRST_R = crate::R<bool, bool>;
        ///Write proxy for field `TSCRST`
        pub struct TSCRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSCRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CRCRST`
        pub type CRCRST_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCRST`
        pub struct CRCRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DMAMUXRST`
        pub type DMAMUXRST_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAMUXRST`
        pub struct DMAMUXRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAMUXRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DMA2RST`
        pub type DMA2RST_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2RST`
        pub struct DMA2RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DMA1RST`
        pub type DMA1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1RST`
        pub struct DMA1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Touch Sensing Controller reset
            #[inline(always)]
            pub fn tscrst(&self) -> TSCRST_R {
                TSCRST_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 12 - CRC reset
            #[inline(always)]
            pub fn crcrst(&self) -> CRCRST_R {
                CRCRST_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 2 - DMAMUX reset
            #[inline(always)]
            pub fn dmamuxrst(&self) -> DMAMUXRST_R {
                DMAMUXRST_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - DMA2 reset
            #[inline(always)]
            pub fn dma2rst(&self) -> DMA2RST_R {
                DMA2RST_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - DMA1 reset
            #[inline(always)]
            pub fn dma1rst(&self) -> DMA1RST_R {
                DMA1RST_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - Touch Sensing Controller reset
            #[inline(always)]
            pub fn tscrst(&mut self) -> TSCRST_W {
                TSCRST_W { w: self }
            }
            ///Bit 12 - CRC reset
            #[inline(always)]
            pub fn crcrst(&mut self) -> CRCRST_W {
                CRCRST_W { w: self }
            }
            ///Bit 2 - DMAMUX reset
            #[inline(always)]
            pub fn dmamuxrst(&mut self) -> DMAMUXRST_W {
                DMAMUXRST_W { w: self }
            }
            ///Bit 1 - DMA2 reset
            #[inline(always)]
            pub fn dma2rst(&mut self) -> DMA2RST_W {
                DMA2RST_W { w: self }
            }
            ///Bit 0 - DMA1 reset
            #[inline(always)]
            pub fn dma1rst(&mut self) -> DMA1RST_W {
                DMA1RST_W { w: self }
            }
        }
    }
    ///AHB2 peripheral reset register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb2rstr](ahb2rstr) module
    pub type AHB2RSTR = crate::Reg<u32, _AHB2RSTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB2RSTR;
    ///`read()` method returns [ahb2rstr::R](ahb2rstr::R) reader structure
    impl crate::Readable for AHB2RSTR {}
    ///`write(|w| ..)` method takes [ahb2rstr::W](ahb2rstr::W) writer structure
    impl crate::Writable for AHB2RSTR {}
    ///AHB2 peripheral reset register
    pub mod ahb2rstr {
        ///Reader of register AHB2RSTR
        pub type R = crate::R<u32, super::AHB2RSTR>;
        ///Writer for register AHB2RSTR
        pub type W = crate::W<u32, super::AHB2RSTR>;
        ///Register AHB2RSTR `reset()`'s with value 0
        impl crate::ResetValue for super::AHB2RSTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES1RST`
        pub type AES1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `AES1RST`
        pub struct AES1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `ADCRST`
        pub type ADCRST_R = crate::R<bool, bool>;
        ///Write proxy for field `ADCRST`
        pub struct ADCRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `GPIOHRST`
        pub type GPIOHRST_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOHRST`
        pub struct GPIOHRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOHRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `GPIOERST`
        pub type GPIOERST_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOERST`
        pub struct GPIOERST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOERST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `GPIODRST`
        pub type GPIODRST_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIODRST`
        pub struct GPIODRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIODRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `GPIOCRST`
        pub type GPIOCRST_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOCRST`
        pub struct GPIOCRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOCRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `GPIOBRST`
        pub type GPIOBRST_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOBRST`
        pub struct GPIOBRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOBRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `GPIOARST`
        pub type GPIOARST_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOARST`
        pub struct GPIOARST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOARST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - AES1 hardware accelerator reset
            #[inline(always)]
            pub fn aes1rst(&self) -> AES1RST_R {
                AES1RST_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 13 - ADC reset
            #[inline(always)]
            pub fn adcrst(&self) -> ADCRST_R {
                ADCRST_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 7 - IO port H reset
            #[inline(always)]
            pub fn gpiohrst(&self) -> GPIOHRST_R {
                GPIOHRST_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 4 - IO port E reset
            #[inline(always)]
            pub fn gpioerst(&self) -> GPIOERST_R {
                GPIOERST_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - IO port D reset
            #[inline(always)]
            pub fn gpiodrst(&self) -> GPIODRST_R {
                GPIODRST_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - IO port C reset
            #[inline(always)]
            pub fn gpiocrst(&self) -> GPIOCRST_R {
                GPIOCRST_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - IO port B reset
            #[inline(always)]
            pub fn gpiobrst(&self) -> GPIOBRST_R {
                GPIOBRST_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - IO port A reset
            #[inline(always)]
            pub fn gpioarst(&self) -> GPIOARST_R {
                GPIOARST_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - AES1 hardware accelerator reset
            #[inline(always)]
            pub fn aes1rst(&mut self) -> AES1RST_W {
                AES1RST_W { w: self }
            }
            ///Bit 13 - ADC reset
            #[inline(always)]
            pub fn adcrst(&mut self) -> ADCRST_W {
                ADCRST_W { w: self }
            }
            ///Bit 7 - IO port H reset
            #[inline(always)]
            pub fn gpiohrst(&mut self) -> GPIOHRST_W {
                GPIOHRST_W { w: self }
            }
            ///Bit 4 - IO port E reset
            #[inline(always)]
            pub fn gpioerst(&mut self) -> GPIOERST_W {
                GPIOERST_W { w: self }
            }
            ///Bit 3 - IO port D reset
            #[inline(always)]
            pub fn gpiodrst(&mut self) -> GPIODRST_W {
                GPIODRST_W { w: self }
            }
            ///Bit 2 - IO port C reset
            #[inline(always)]
            pub fn gpiocrst(&mut self) -> GPIOCRST_W {
                GPIOCRST_W { w: self }
            }
            ///Bit 1 - IO port B reset
            #[inline(always)]
            pub fn gpiobrst(&mut self) -> GPIOBRST_W {
                GPIOBRST_W { w: self }
            }
            ///Bit 0 - IO port A reset
            #[inline(always)]
            pub fn gpioarst(&mut self) -> GPIOARST_W {
                GPIOARST_W { w: self }
            }
        }
    }
    ///AHB3 peripheral reset register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb3rstr](ahb3rstr) module
    pub type AHB3RSTR = crate::Reg<u32, _AHB3RSTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB3RSTR;
    ///`read()` method returns [ahb3rstr::R](ahb3rstr::R) reader structure
    impl crate::Readable for AHB3RSTR {}
    ///`write(|w| ..)` method takes [ahb3rstr::W](ahb3rstr::W) writer structure
    impl crate::Writable for AHB3RSTR {}
    ///AHB3 peripheral reset register
    pub mod ahb3rstr {
        ///Reader of register AHB3RSTR
        pub type R = crate::R<u32, super::AHB3RSTR>;
        ///Writer for register AHB3RSTR
        pub type W = crate::W<u32, super::AHB3RSTR>;
        ///Register AHB3RSTR `reset()`'s with value 0
        impl crate::ResetValue for super::AHB3RSTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `FLASHRST`
        pub type FLASHRST_R = crate::R<bool, bool>;
        ///Write proxy for field `FLASHRST`
        pub struct FLASHRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FLASHRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `IPCCRST`
        pub type IPCCRST_R = crate::R<bool, bool>;
        ///Write proxy for field `IPCCRST`
        pub struct IPCCRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IPCCRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `HSEMRST`
        pub type HSEMRST_R = crate::R<bool, bool>;
        ///Write proxy for field `HSEMRST`
        pub struct HSEMRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSEMRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `RNGRST`
        pub type RNGRST_R = crate::R<bool, bool>;
        ///Write proxy for field `RNGRST`
        pub struct RNGRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNGRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `AES2RST`
        pub type AES2RST_R = crate::R<bool, bool>;
        ///Write proxy for field `AES2RST`
        pub struct AES2RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES2RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `PKARST`
        pub type PKARST_R = crate::R<bool, bool>;
        ///Write proxy for field `PKARST`
        pub struct PKARST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PKARST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `QSPIRST`
        pub type QSPIRST_R = crate::R<bool, bool>;
        ///Write proxy for field `QSPIRST`
        pub struct QSPIRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> QSPIRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 25 - Flash interface reset
            #[inline(always)]
            pub fn flashrst(&self) -> FLASHRST_R {
                FLASHRST_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 20 - IPCC interface reset
            #[inline(always)]
            pub fn ipccrst(&self) -> IPCCRST_R {
                IPCCRST_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - HSEM interface reset
            #[inline(always)]
            pub fn hsemrst(&self) -> HSEMRST_R {
                HSEMRST_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - RNG interface reset
            #[inline(always)]
            pub fn rngrst(&self) -> RNGRST_R {
                RNGRST_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - AES2 interface reset
            #[inline(always)]
            pub fn aes2rst(&self) -> AES2RST_R {
                AES2RST_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - PKA interface reset
            #[inline(always)]
            pub fn pkarst(&self) -> PKARST_R {
                PKARST_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - Quad SPI memory interface reset
            #[inline(always)]
            pub fn qspirst(&self) -> QSPIRST_R {
                QSPIRST_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 25 - Flash interface reset
            #[inline(always)]
            pub fn flashrst(&mut self) -> FLASHRST_W {
                FLASHRST_W { w: self }
            }
            ///Bit 20 - IPCC interface reset
            #[inline(always)]
            pub fn ipccrst(&mut self) -> IPCCRST_W {
                IPCCRST_W { w: self }
            }
            ///Bit 19 - HSEM interface reset
            #[inline(always)]
            pub fn hsemrst(&mut self) -> HSEMRST_W {
                HSEMRST_W { w: self }
            }
            ///Bit 18 - RNG interface reset
            #[inline(always)]
            pub fn rngrst(&mut self) -> RNGRST_W {
                RNGRST_W { w: self }
            }
            ///Bit 17 - AES2 interface reset
            #[inline(always)]
            pub fn aes2rst(&mut self) -> AES2RST_W {
                AES2RST_W { w: self }
            }
            ///Bit 16 - PKA interface reset
            #[inline(always)]
            pub fn pkarst(&mut self) -> PKARST_W {
                PKARST_W { w: self }
            }
            ///Bit 8 - Quad SPI memory interface reset
            #[inline(always)]
            pub fn qspirst(&mut self) -> QSPIRST_W {
                QSPIRST_W { w: self }
            }
        }
    }
    ///APB1 peripheral reset register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1rstr1](apb1rstr1) module
    pub type APB1RSTR1 = crate::Reg<u32, _APB1RSTR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1RSTR1;
    ///`read()` method returns [apb1rstr1::R](apb1rstr1::R) reader structure
    impl crate::Readable for APB1RSTR1 {}
    ///`write(|w| ..)` method takes [apb1rstr1::W](apb1rstr1::W) writer structure
    impl crate::Writable for APB1RSTR1 {}
    ///APB1 peripheral reset register 1
    pub mod apb1rstr1 {
        ///Reader of register APB1RSTR1
        pub type R = crate::R<u32, super::APB1RSTR1>;
        ///Writer for register APB1RSTR1
        pub type W = crate::W<u32, super::APB1RSTR1>;
        ///Register APB1RSTR1 `reset()`'s with value 0
        impl crate::ResetValue for super::APB1RSTR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LPTIM1RST`
        pub type LPTIM1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM1RST`
        pub struct LPTIM1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `USBFSRST`
        pub type USBFSRST_R = crate::R<bool, bool>;
        ///Write proxy for field `USBFSRST`
        pub struct USBFSRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USBFSRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `CRSRST`
        pub type CRSRST_R = crate::R<bool, bool>;
        ///Write proxy for field `CRSRST`
        pub struct CRSRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRSRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `I2C3RST`
        pub type I2C3RST_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C3RST`
        pub struct I2C3RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C3RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `I2C1RST`
        pub type I2C1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C1RST`
        pub struct I2C1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `SPI2RST`
        pub type SPI2RST_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI2RST`
        pub struct SPI2RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI2RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `LCDRST`
        pub type LCDRST_R = crate::R<bool, bool>;
        ///Write proxy for field `LCDRST`
        pub struct LCDRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCDRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `TIM2RST`
        pub type TIM2RST_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM2RST`
        pub struct TIM2RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM2RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - Low Power Timer 1 reset
            #[inline(always)]
            pub fn lptim1rst(&self) -> LPTIM1RST_R {
                LPTIM1RST_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 26 - USB FS reset
            #[inline(always)]
            pub fn usbfsrst(&self) -> USBFSRST_R {
                USBFSRST_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 24 - CRS reset
            #[inline(always)]
            pub fn crsrst(&self) -> CRSRST_R {
                CRSRST_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - I2C3 reset
            #[inline(always)]
            pub fn i2c3rst(&self) -> I2C3RST_R {
                I2C3RST_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 21 - I2C1 reset
            #[inline(always)]
            pub fn i2c1rst(&self) -> I2C1RST_R {
                I2C1RST_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 14 - SPI2 reset
            #[inline(always)]
            pub fn spi2rst(&self) -> SPI2RST_R {
                SPI2RST_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 9 - LCD interface reset
            #[inline(always)]
            pub fn lcdrst(&self) -> LCDRST_R {
                LCDRST_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 0 - TIM2 timer reset
            #[inline(always)]
            pub fn tim2rst(&self) -> TIM2RST_R {
                TIM2RST_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - Low Power Timer 1 reset
            #[inline(always)]
            pub fn lptim1rst(&mut self) -> LPTIM1RST_W {
                LPTIM1RST_W { w: self }
            }
            ///Bit 26 - USB FS reset
            #[inline(always)]
            pub fn usbfsrst(&mut self) -> USBFSRST_W {
                USBFSRST_W { w: self }
            }
            ///Bit 24 - CRS reset
            #[inline(always)]
            pub fn crsrst(&mut self) -> CRSRST_W {
                CRSRST_W { w: self }
            }
            ///Bit 23 - I2C3 reset
            #[inline(always)]
            pub fn i2c3rst(&mut self) -> I2C3RST_W {
                I2C3RST_W { w: self }
            }
            ///Bit 21 - I2C1 reset
            #[inline(always)]
            pub fn i2c1rst(&mut self) -> I2C1RST_W {
                I2C1RST_W { w: self }
            }
            ///Bit 14 - SPI2 reset
            #[inline(always)]
            pub fn spi2rst(&mut self) -> SPI2RST_W {
                SPI2RST_W { w: self }
            }
            ///Bit 9 - LCD interface reset
            #[inline(always)]
            pub fn lcdrst(&mut self) -> LCDRST_W {
                LCDRST_W { w: self }
            }
            ///Bit 0 - TIM2 timer reset
            #[inline(always)]
            pub fn tim2rst(&mut self) -> TIM2RST_W {
                TIM2RST_W { w: self }
            }
        }
    }
    ///APB1 peripheral reset register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1rstr2](apb1rstr2) module
    pub type APB1RSTR2 = crate::Reg<u32, _APB1RSTR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1RSTR2;
    ///`read()` method returns [apb1rstr2::R](apb1rstr2::R) reader structure
    impl crate::Readable for APB1RSTR2 {}
    ///`write(|w| ..)` method takes [apb1rstr2::W](apb1rstr2::W) writer structure
    impl crate::Writable for APB1RSTR2 {}
    ///APB1 peripheral reset register 2
    pub mod apb1rstr2 {
        ///Reader of register APB1RSTR2
        pub type R = crate::R<u32, super::APB1RSTR2>;
        ///Writer for register APB1RSTR2
        pub type W = crate::W<u32, super::APB1RSTR2>;
        ///Register APB1RSTR2 `reset()`'s with value 0
        impl crate::ResetValue for super::APB1RSTR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LPTIM2RST`
        pub type LPTIM2RST_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM2RST`
        pub struct LPTIM2RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM2RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LPUART1RST`
        pub type LPUART1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `LPUART1RST`
        pub struct LPUART1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPUART1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 5 - Low-power timer 2 reset
            #[inline(always)]
            pub fn lptim2rst(&self) -> LPTIM2RST_R {
                LPTIM2RST_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 0 - Low-power UART 1 reset
            #[inline(always)]
            pub fn lpuart1rst(&self) -> LPUART1RST_R {
                LPUART1RST_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 5 - Low-power timer 2 reset
            #[inline(always)]
            pub fn lptim2rst(&mut self) -> LPTIM2RST_W {
                LPTIM2RST_W { w: self }
            }
            ///Bit 0 - Low-power UART 1 reset
            #[inline(always)]
            pub fn lpuart1rst(&mut self) -> LPUART1RST_W {
                LPUART1RST_W { w: self }
            }
        }
    }
    ///APB2 peripheral reset register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb2rstr](apb2rstr) module
    pub type APB2RSTR = crate::Reg<u32, _APB2RSTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB2RSTR;
    ///`read()` method returns [apb2rstr::R](apb2rstr::R) reader structure
    impl crate::Readable for APB2RSTR {}
    ///`write(|w| ..)` method takes [apb2rstr::W](apb2rstr::W) writer structure
    impl crate::Writable for APB2RSTR {}
    ///APB2 peripheral reset register
    pub mod apb2rstr {
        ///Reader of register APB2RSTR
        pub type R = crate::R<u32, super::APB2RSTR>;
        ///Writer for register APB2RSTR
        pub type W = crate::W<u32, super::APB2RSTR>;
        ///Register APB2RSTR `reset()`'s with value 0
        impl crate::ResetValue for super::APB2RSTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SAI1RST`
        pub type SAI1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `SAI1RST`
        pub struct SAI1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAI1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `TIM17RST`
        pub type TIM17RST_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM17RST`
        pub struct TIM17RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM17RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TIM16RST`
        pub type TIM16RST_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM16RST`
        pub struct TIM16RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM16RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `USART1RST`
        pub type USART1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `USART1RST`
        pub struct USART1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USART1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `SPI1RST`
        pub type SPI1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI1RST`
        pub struct SPI1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TIM1RST`
        pub type TIM1RST_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM1RST`
        pub struct TIM1RST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM1RST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 21 - Serial audio interface 1 (SAI1) reset
            #[inline(always)]
            pub fn sai1rst(&self) -> SAI1RST_R {
                SAI1RST_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 18 - TIM17 timer reset
            #[inline(always)]
            pub fn tim17rst(&self) -> TIM17RST_R {
                TIM17RST_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - TIM16 timer reset
            #[inline(always)]
            pub fn tim16rst(&self) -> TIM16RST_R {
                TIM16RST_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 14 - USART1 reset
            #[inline(always)]
            pub fn usart1rst(&self) -> USART1RST_R {
                USART1RST_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 12 - SPI1 reset
            #[inline(always)]
            pub fn spi1rst(&self) -> SPI1RST_R {
                SPI1RST_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - TIM1 timer reset
            #[inline(always)]
            pub fn tim1rst(&self) -> TIM1RST_R {
                TIM1RST_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 21 - Serial audio interface 1 (SAI1) reset
            #[inline(always)]
            pub fn sai1rst(&mut self) -> SAI1RST_W {
                SAI1RST_W { w: self }
            }
            ///Bit 18 - TIM17 timer reset
            #[inline(always)]
            pub fn tim17rst(&mut self) -> TIM17RST_W {
                TIM17RST_W { w: self }
            }
            ///Bit 17 - TIM16 timer reset
            #[inline(always)]
            pub fn tim16rst(&mut self) -> TIM16RST_W {
                TIM16RST_W { w: self }
            }
            ///Bit 14 - USART1 reset
            #[inline(always)]
            pub fn usart1rst(&mut self) -> USART1RST_W {
                USART1RST_W { w: self }
            }
            ///Bit 12 - SPI1 reset
            #[inline(always)]
            pub fn spi1rst(&mut self) -> SPI1RST_W {
                SPI1RST_W { w: self }
            }
            ///Bit 11 - TIM1 timer reset
            #[inline(always)]
            pub fn tim1rst(&mut self) -> TIM1RST_W {
                TIM1RST_W { w: self }
            }
        }
    }
    ///APB3 peripheral reset register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb3rstr](apb3rstr) module
    pub type APB3RSTR = crate::Reg<u32, _APB3RSTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB3RSTR;
    ///`read()` method returns [apb3rstr::R](apb3rstr::R) reader structure
    impl crate::Readable for APB3RSTR {}
    ///`write(|w| ..)` method takes [apb3rstr::W](apb3rstr::W) writer structure
    impl crate::Writable for APB3RSTR {}
    ///APB3 peripheral reset register
    pub mod apb3rstr {
        ///Reader of register APB3RSTR
        pub type R = crate::R<u32, super::APB3RSTR>;
        ///Writer for register APB3RSTR
        pub type W = crate::W<u32, super::APB3RSTR>;
        ///Register APB3RSTR `reset()`'s with value 0
        impl crate::ResetValue for super::APB3RSTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RFRST`
        pub type RFRST_R = crate::R<bool, bool>;
        ///Write proxy for field `RFRST`
        pub struct RFRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RFRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Radio system BLE reset
            #[inline(always)]
            pub fn rfrst(&self) -> RFRST_R {
                RFRST_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Radio system BLE reset
            #[inline(always)]
            pub fn rfrst(&mut self) -> RFRST_W {
                RFRST_W { w: self }
            }
        }
    }
    ///AHB1 peripheral clock enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb1enr](ahb1enr) module
    pub type AHB1ENR = crate::Reg<u32, _AHB1ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB1ENR;
    ///`read()` method returns [ahb1enr::R](ahb1enr::R) reader structure
    impl crate::Readable for AHB1ENR {}
    ///`write(|w| ..)` method takes [ahb1enr::W](ahb1enr::W) writer structure
    impl crate::Writable for AHB1ENR {}
    ///AHB1 peripheral clock enable register
    pub mod ahb1enr {
        ///Reader of register AHB1ENR
        pub type R = crate::R<u32, super::AHB1ENR>;
        ///Writer for register AHB1ENR
        pub type W = crate::W<u32, super::AHB1ENR>;
        ///Register AHB1ENR `reset()`'s with value 0x0100
        impl crate::ResetValue for super::AHB1ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0100
            }
        }
        ///Reader of field `TSCEN`
        pub type TSCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TSCEN`
        pub struct TSCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CRCEN`
        pub type CRCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCEN`
        pub struct CRCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DMAMUXEN`
        pub type DMAMUXEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAMUXEN`
        pub struct DMAMUXEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAMUXEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DMA2EN`
        pub type DMA2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2EN`
        pub struct DMA2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DMA1EN`
        pub type DMA1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1EN`
        pub struct DMA1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Touch Sensing Controller clock enable
            #[inline(always)]
            pub fn tscen(&self) -> TSCEN_R {
                TSCEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 12 - CPU1 CRC clock enable
            #[inline(always)]
            pub fn crcen(&self) -> CRCEN_R {
                CRCEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 2 - DMAMUX clock enable
            #[inline(always)]
            pub fn dmamuxen(&self) -> DMAMUXEN_R {
                DMAMUXEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - DMA2 clock enable
            #[inline(always)]
            pub fn dma2en(&self) -> DMA2EN_R {
                DMA2EN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - DMA1 clock enable
            #[inline(always)]
            pub fn dma1en(&self) -> DMA1EN_R {
                DMA1EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - Touch Sensing Controller clock enable
            #[inline(always)]
            pub fn tscen(&mut self) -> TSCEN_W {
                TSCEN_W { w: self }
            }
            ///Bit 12 - CPU1 CRC clock enable
            #[inline(always)]
            pub fn crcen(&mut self) -> CRCEN_W {
                CRCEN_W { w: self }
            }
            ///Bit 2 - DMAMUX clock enable
            #[inline(always)]
            pub fn dmamuxen(&mut self) -> DMAMUXEN_W {
                DMAMUXEN_W { w: self }
            }
            ///Bit 1 - DMA2 clock enable
            #[inline(always)]
            pub fn dma2en(&mut self) -> DMA2EN_W {
                DMA2EN_W { w: self }
            }
            ///Bit 0 - DMA1 clock enable
            #[inline(always)]
            pub fn dma1en(&mut self) -> DMA1EN_W {
                DMA1EN_W { w: self }
            }
        }
    }
    ///AHB2 peripheral clock enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb2enr](ahb2enr) module
    pub type AHB2ENR = crate::Reg<u32, _AHB2ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB2ENR;
    ///`read()` method returns [ahb2enr::R](ahb2enr::R) reader structure
    impl crate::Readable for AHB2ENR {}
    ///`write(|w| ..)` method takes [ahb2enr::W](ahb2enr::W) writer structure
    impl crate::Writable for AHB2ENR {}
    ///AHB2 peripheral clock enable register
    pub mod ahb2enr {
        ///Reader of register AHB2ENR
        pub type R = crate::R<u32, super::AHB2ENR>;
        ///Writer for register AHB2ENR
        pub type W = crate::W<u32, super::AHB2ENR>;
        ///Register AHB2ENR `reset()`'s with value 0
        impl crate::ResetValue for super::AHB2ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES1EN`
        pub type AES1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES1EN`
        pub struct AES1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `ADCEN`
        pub type ADCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ADCEN`
        pub struct ADCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `GPIOHEN`
        pub type GPIOHEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOHEN`
        pub struct GPIOHEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOHEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `GPIOEEN`
        pub type GPIOEEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOEEN`
        pub struct GPIOEEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOEEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `GPIODEN`
        pub type GPIODEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIODEN`
        pub struct GPIODEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIODEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `GPIOCEN`
        pub type GPIOCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOCEN`
        pub struct GPIOCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `GPIOBEN`
        pub type GPIOBEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOBEN`
        pub struct GPIOBEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOBEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `GPIOAEN`
        pub type GPIOAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOAEN`
        pub struct GPIOAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - AES1 accelerator clock enable
            #[inline(always)]
            pub fn aes1en(&self) -> AES1EN_R {
                AES1EN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 13 - ADC clock enable
            #[inline(always)]
            pub fn adcen(&self) -> ADCEN_R {
                ADCEN_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 7 - IO port H clock enable
            #[inline(always)]
            pub fn gpiohen(&self) -> GPIOHEN_R {
                GPIOHEN_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 4 - IO port E clock enable
            #[inline(always)]
            pub fn gpioeen(&self) -> GPIOEEN_R {
                GPIOEEN_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - IO port D clock enable
            #[inline(always)]
            pub fn gpioden(&self) -> GPIODEN_R {
                GPIODEN_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - IO port C clock enable
            #[inline(always)]
            pub fn gpiocen(&self) -> GPIOCEN_R {
                GPIOCEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - IO port B clock enable
            #[inline(always)]
            pub fn gpioben(&self) -> GPIOBEN_R {
                GPIOBEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - IO port A clock enable
            #[inline(always)]
            pub fn gpioaen(&self) -> GPIOAEN_R {
                GPIOAEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - AES1 accelerator clock enable
            #[inline(always)]
            pub fn aes1en(&mut self) -> AES1EN_W {
                AES1EN_W { w: self }
            }
            ///Bit 13 - ADC clock enable
            #[inline(always)]
            pub fn adcen(&mut self) -> ADCEN_W {
                ADCEN_W { w: self }
            }
            ///Bit 7 - IO port H clock enable
            #[inline(always)]
            pub fn gpiohen(&mut self) -> GPIOHEN_W {
                GPIOHEN_W { w: self }
            }
            ///Bit 4 - IO port E clock enable
            #[inline(always)]
            pub fn gpioeen(&mut self) -> GPIOEEN_W {
                GPIOEEN_W { w: self }
            }
            ///Bit 3 - IO port D clock enable
            #[inline(always)]
            pub fn gpioden(&mut self) -> GPIODEN_W {
                GPIODEN_W { w: self }
            }
            ///Bit 2 - IO port C clock enable
            #[inline(always)]
            pub fn gpiocen(&mut self) -> GPIOCEN_W {
                GPIOCEN_W { w: self }
            }
            ///Bit 1 - IO port B clock enable
            #[inline(always)]
            pub fn gpioben(&mut self) -> GPIOBEN_W {
                GPIOBEN_W { w: self }
            }
            ///Bit 0 - IO port A clock enable
            #[inline(always)]
            pub fn gpioaen(&mut self) -> GPIOAEN_W {
                GPIOAEN_W { w: self }
            }
        }
    }
    ///AHB3 peripheral clock enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb3enr](ahb3enr) module
    pub type AHB3ENR = crate::Reg<u32, _AHB3ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB3ENR;
    ///`read()` method returns [ahb3enr::R](ahb3enr::R) reader structure
    impl crate::Readable for AHB3ENR {}
    ///`write(|w| ..)` method takes [ahb3enr::W](ahb3enr::W) writer structure
    impl crate::Writable for AHB3ENR {}
    ///AHB3 peripheral clock enable register
    pub mod ahb3enr {
        ///Reader of register AHB3ENR
        pub type R = crate::R<u32, super::AHB3ENR>;
        ///Writer for register AHB3ENR
        pub type W = crate::W<u32, super::AHB3ENR>;
        ///Register AHB3ENR `reset()`'s with value 0x0208_0000
        impl crate::ResetValue for super::AHB3ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0208_0000
            }
        }
        ///Reader of field `FLASHEN`
        pub type FLASHEN_R = crate::R<bool, bool>;
        ///Write proxy for field `FLASHEN`
        pub struct FLASHEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FLASHEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `IPCCEN`
        pub type IPCCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `IPCCEN`
        pub struct IPCCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IPCCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `HSEMEN`
        pub type HSEMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `HSEMEN`
        pub struct HSEMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSEMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `RNGEN`
        pub type RNGEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RNGEN`
        pub struct RNGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNGEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `AES2EN`
        pub type AES2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES2EN`
        pub struct AES2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `PKAEN`
        pub type PKAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PKAEN`
        pub struct PKAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PKAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `QSPIEN`
        pub type QSPIEN_R = crate::R<bool, bool>;
        ///Write proxy for field `QSPIEN`
        pub struct QSPIEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> QSPIEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 25 - FLASHEN
            #[inline(always)]
            pub fn flashen(&self) -> FLASHEN_R {
                FLASHEN_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 20 - IPCCEN
            #[inline(always)]
            pub fn ipccen(&self) -> IPCCEN_R {
                IPCCEN_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - HSEMEN
            #[inline(always)]
            pub fn hsemen(&self) -> HSEMEN_R {
                HSEMEN_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - RNGEN
            #[inline(always)]
            pub fn rngen(&self) -> RNGEN_R {
                RNGEN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - AES2EN
            #[inline(always)]
            pub fn aes2en(&self) -> AES2EN_R {
                AES2EN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - PKAEN
            #[inline(always)]
            pub fn pkaen(&self) -> PKAEN_R {
                PKAEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - QSPIEN
            #[inline(always)]
            pub fn qspien(&self) -> QSPIEN_R {
                QSPIEN_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 25 - FLASHEN
            #[inline(always)]
            pub fn flashen(&mut self) -> FLASHEN_W {
                FLASHEN_W { w: self }
            }
            ///Bit 20 - IPCCEN
            #[inline(always)]
            pub fn ipccen(&mut self) -> IPCCEN_W {
                IPCCEN_W { w: self }
            }
            ///Bit 19 - HSEMEN
            #[inline(always)]
            pub fn hsemen(&mut self) -> HSEMEN_W {
                HSEMEN_W { w: self }
            }
            ///Bit 18 - RNGEN
            #[inline(always)]
            pub fn rngen(&mut self) -> RNGEN_W {
                RNGEN_W { w: self }
            }
            ///Bit 17 - AES2EN
            #[inline(always)]
            pub fn aes2en(&mut self) -> AES2EN_W {
                AES2EN_W { w: self }
            }
            ///Bit 16 - PKAEN
            #[inline(always)]
            pub fn pkaen(&mut self) -> PKAEN_W {
                PKAEN_W { w: self }
            }
            ///Bit 8 - QSPIEN
            #[inline(always)]
            pub fn qspien(&mut self) -> QSPIEN_W {
                QSPIEN_W { w: self }
            }
        }
    }
    ///APB1ENR1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1enr1](apb1enr1) module
    pub type APB1ENR1 = crate::Reg<u32, _APB1ENR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1ENR1;
    ///`read()` method returns [apb1enr1::R](apb1enr1::R) reader structure
    impl crate::Readable for APB1ENR1 {}
    ///`write(|w| ..)` method takes [apb1enr1::W](apb1enr1::W) writer structure
    impl crate::Writable for APB1ENR1 {}
    ///APB1ENR1
    pub mod apb1enr1 {
        ///Reader of register APB1ENR1
        pub type R = crate::R<u32, super::APB1ENR1>;
        ///Writer for register APB1ENR1
        pub type W = crate::W<u32, super::APB1ENR1>;
        ///Register APB1ENR1 `reset()`'s with value 0x0400
        impl crate::ResetValue for super::APB1ENR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0400
            }
        }
        ///Reader of field `LPTIM1EN`
        pub type LPTIM1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM1EN`
        pub struct LPTIM1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `USBEN`
        pub type USBEN_R = crate::R<bool, bool>;
        ///Write proxy for field `USBEN`
        pub struct USBEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USBEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `CRSEN`
        pub type CRSEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRSEN`
        pub struct CRSEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRSEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `I2C3EN`
        pub type I2C3EN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C3EN`
        pub struct I2C3EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C3EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `I2C1EN`
        pub type I2C1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C1EN`
        pub struct I2C1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `SPI2EN`
        pub type SPI2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI2EN`
        pub struct SPI2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `WWDGEN`
        pub type WWDGEN_R = crate::R<bool, bool>;
        ///Write proxy for field `WWDGEN`
        pub struct WWDGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WWDGEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `RTCAPBEN`
        pub type RTCAPBEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCAPBEN`
        pub struct RTCAPBEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCAPBEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LCDEN`
        pub type LCDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LCDEN`
        pub struct LCDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `TIM2EN`
        pub type TIM2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM2EN`
        pub struct TIM2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - CPU1 Low power timer 1 clock enable
            #[inline(always)]
            pub fn lptim1en(&self) -> LPTIM1EN_R {
                LPTIM1EN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 26 - CPU1 USB clock enable
            #[inline(always)]
            pub fn usben(&self) -> USBEN_R {
                USBEN_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 24 - CPU1 CRS clock enable
            #[inline(always)]
            pub fn crsen(&self) -> CRSEN_R {
                CRSEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - CPU1 I2C3 clock enable
            #[inline(always)]
            pub fn i2c3en(&self) -> I2C3EN_R {
                I2C3EN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 21 - CPU1 I2C1 clock enable
            #[inline(always)]
            pub fn i2c1en(&self) -> I2C1EN_R {
                I2C1EN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 14 - CPU1 SPI2 clock enable
            #[inline(always)]
            pub fn spi2en(&self) -> SPI2EN_R {
                SPI2EN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 11 - CPU1 Window watchdog clock enable
            #[inline(always)]
            pub fn wwdgen(&self) -> WWDGEN_R {
                WWDGEN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - CPU1 RTC APB clock enable
            #[inline(always)]
            pub fn rtcapben(&self) -> RTCAPBEN_R {
                RTCAPBEN_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - CPU1 LCD clock enable
            #[inline(always)]
            pub fn lcden(&self) -> LCDEN_R {
                LCDEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 0 - CPU1 TIM2 timer clock enable
            #[inline(always)]
            pub fn tim2en(&self) -> TIM2EN_R {
                TIM2EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - CPU1 Low power timer 1 clock enable
            #[inline(always)]
            pub fn lptim1en(&mut self) -> LPTIM1EN_W {
                LPTIM1EN_W { w: self }
            }
            ///Bit 26 - CPU1 USB clock enable
            #[inline(always)]
            pub fn usben(&mut self) -> USBEN_W {
                USBEN_W { w: self }
            }
            ///Bit 24 - CPU1 CRS clock enable
            #[inline(always)]
            pub fn crsen(&mut self) -> CRSEN_W {
                CRSEN_W { w: self }
            }
            ///Bit 23 - CPU1 I2C3 clock enable
            #[inline(always)]
            pub fn i2c3en(&mut self) -> I2C3EN_W {
                I2C3EN_W { w: self }
            }
            ///Bit 21 - CPU1 I2C1 clock enable
            #[inline(always)]
            pub fn i2c1en(&mut self) -> I2C1EN_W {
                I2C1EN_W { w: self }
            }
            ///Bit 14 - CPU1 SPI2 clock enable
            #[inline(always)]
            pub fn spi2en(&mut self) -> SPI2EN_W {
                SPI2EN_W { w: self }
            }
            ///Bit 11 - CPU1 Window watchdog clock enable
            #[inline(always)]
            pub fn wwdgen(&mut self) -> WWDGEN_W {
                WWDGEN_W { w: self }
            }
            ///Bit 10 - CPU1 RTC APB clock enable
            #[inline(always)]
            pub fn rtcapben(&mut self) -> RTCAPBEN_W {
                RTCAPBEN_W { w: self }
            }
            ///Bit 9 - CPU1 LCD clock enable
            #[inline(always)]
            pub fn lcden(&mut self) -> LCDEN_W {
                LCDEN_W { w: self }
            }
            ///Bit 0 - CPU1 TIM2 timer clock enable
            #[inline(always)]
            pub fn tim2en(&mut self) -> TIM2EN_W {
                TIM2EN_W { w: self }
            }
        }
    }
    ///APB1 peripheral clock enable register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1enr2](apb1enr2) module
    pub type APB1ENR2 = crate::Reg<u32, _APB1ENR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1ENR2;
    ///`read()` method returns [apb1enr2::R](apb1enr2::R) reader structure
    impl crate::Readable for APB1ENR2 {}
    ///`write(|w| ..)` method takes [apb1enr2::W](apb1enr2::W) writer structure
    impl crate::Writable for APB1ENR2 {}
    ///APB1 peripheral clock enable register 2
    pub mod apb1enr2 {
        ///Reader of register APB1ENR2
        pub type R = crate::R<u32, super::APB1ENR2>;
        ///Writer for register APB1ENR2
        pub type W = crate::W<u32, super::APB1ENR2>;
        ///Register APB1ENR2 `reset()`'s with value 0
        impl crate::ResetValue for super::APB1ENR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LPTIM2EN`
        pub type LPTIM2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM2EN`
        pub struct LPTIM2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LPUART1EN`
        pub type LPUART1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPUART1EN`
        pub struct LPUART1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPUART1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 5 - CPU1 LPTIM2EN
            #[inline(always)]
            pub fn lptim2en(&self) -> LPTIM2EN_R {
                LPTIM2EN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 0 - CPU1 Low power UART 1 clock enable
            #[inline(always)]
            pub fn lpuart1en(&self) -> LPUART1EN_R {
                LPUART1EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 5 - CPU1 LPTIM2EN
            #[inline(always)]
            pub fn lptim2en(&mut self) -> LPTIM2EN_W {
                LPTIM2EN_W { w: self }
            }
            ///Bit 0 - CPU1 Low power UART 1 clock enable
            #[inline(always)]
            pub fn lpuart1en(&mut self) -> LPUART1EN_W {
                LPUART1EN_W { w: self }
            }
        }
    }
    ///APB2ENR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb2enr](apb2enr) module
    pub type APB2ENR = crate::Reg<u32, _APB2ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB2ENR;
    ///`read()` method returns [apb2enr::R](apb2enr::R) reader structure
    impl crate::Readable for APB2ENR {}
    ///`write(|w| ..)` method takes [apb2enr::W](apb2enr::W) writer structure
    impl crate::Writable for APB2ENR {}
    ///APB2ENR
    pub mod apb2enr {
        ///Reader of register APB2ENR
        pub type R = crate::R<u32, super::APB2ENR>;
        ///Writer for register APB2ENR
        pub type W = crate::W<u32, super::APB2ENR>;
        ///Register APB2ENR `reset()`'s with value 0
        impl crate::ResetValue for super::APB2ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SAI1EN`
        pub type SAI1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `SAI1EN`
        pub struct SAI1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAI1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `TIM17EN`
        pub type TIM17EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM17EN`
        pub struct TIM17EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM17EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TIM16EN`
        pub type TIM16EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM16EN`
        pub struct TIM16EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM16EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `USART1EN`
        pub type USART1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `USART1EN`
        pub struct USART1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USART1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `SPI1EN`
        pub type SPI1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI1EN`
        pub struct SPI1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TIM1EN`
        pub type TIM1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM1EN`
        pub struct TIM1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 21 - CPU1 SAI1 clock enable
            #[inline(always)]
            pub fn sai1en(&self) -> SAI1EN_R {
                SAI1EN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 18 - CPU1 TIM17 timer clock enable
            #[inline(always)]
            pub fn tim17en(&self) -> TIM17EN_R {
                TIM17EN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - CPU1 TIM16 timer clock enable
            #[inline(always)]
            pub fn tim16en(&self) -> TIM16EN_R {
                TIM16EN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 14 - CPU1 USART1clock enable
            #[inline(always)]
            pub fn usart1en(&self) -> USART1EN_R {
                USART1EN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 12 - CPU1 SPI1 clock enable
            #[inline(always)]
            pub fn spi1en(&self) -> SPI1EN_R {
                SPI1EN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - CPU1 TIM1 timer clock enable
            #[inline(always)]
            pub fn tim1en(&self) -> TIM1EN_R {
                TIM1EN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 21 - CPU1 SAI1 clock enable
            #[inline(always)]
            pub fn sai1en(&mut self) -> SAI1EN_W {
                SAI1EN_W { w: self }
            }
            ///Bit 18 - CPU1 TIM17 timer clock enable
            #[inline(always)]
            pub fn tim17en(&mut self) -> TIM17EN_W {
                TIM17EN_W { w: self }
            }
            ///Bit 17 - CPU1 TIM16 timer clock enable
            #[inline(always)]
            pub fn tim16en(&mut self) -> TIM16EN_W {
                TIM16EN_W { w: self }
            }
            ///Bit 14 - CPU1 USART1clock enable
            #[inline(always)]
            pub fn usart1en(&mut self) -> USART1EN_W {
                USART1EN_W { w: self }
            }
            ///Bit 12 - CPU1 SPI1 clock enable
            #[inline(always)]
            pub fn spi1en(&mut self) -> SPI1EN_W {
                SPI1EN_W { w: self }
            }
            ///Bit 11 - CPU1 TIM1 timer clock enable
            #[inline(always)]
            pub fn tim1en(&mut self) -> TIM1EN_W {
                TIM1EN_W { w: self }
            }
        }
    }
    ///AHB1 peripheral clocks enable in Sleep and Stop modes register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb1smenr](ahb1smenr) module
    pub type AHB1SMENR = crate::Reg<u32, _AHB1SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB1SMENR;
    ///`read()` method returns [ahb1smenr::R](ahb1smenr::R) reader structure
    impl crate::Readable for AHB1SMENR {}
    ///`write(|w| ..)` method takes [ahb1smenr::W](ahb1smenr::W) writer structure
    impl crate::Writable for AHB1SMENR {}
    ///AHB1 peripheral clocks enable in Sleep and Stop modes register
    pub mod ahb1smenr {
        ///Reader of register AHB1SMENR
        pub type R = crate::R<u32, super::AHB1SMENR>;
        ///Writer for register AHB1SMENR
        pub type W = crate::W<u32, super::AHB1SMENR>;
        ///Register AHB1SMENR `reset()`'s with value 0x0001_1207
        impl crate::ResetValue for super::AHB1SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0001_1207
            }
        }
        ///Reader of field `TSCSMEN`
        pub type TSCSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TSCSMEN`
        pub struct TSCSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSCSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CRCSMEN`
        pub type CRCSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCSMEN`
        pub struct CRCSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `SRAM1SMEN`
        pub type SRAM1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM1SMEN`
        pub struct SRAM1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `DMAMUXSMEN`
        pub type DMAMUXSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAMUXSMEN`
        pub struct DMAMUXSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAMUXSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DMA2SMEN`
        pub type DMA2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2SMEN`
        pub struct DMA2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DMA1SMEN`
        pub type DMA1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1SMEN`
        pub struct DMA1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn tscsmen(&self) -> TSCSMEN_R {
                TSCSMEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 12 - CPU1 CRCSMEN
            #[inline(always)]
            pub fn crcsmen(&self) -> CRCSMEN_R {
                CRCSMEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 9 - CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn sram1smen(&self) -> SRAM1SMEN_R {
                SRAM1SMEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 2 - CPU1 DMAMUX clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dmamuxsmen(&self) -> DMAMUXSMEN_R {
                DMAMUXSMEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - CPU1 DMA2 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma2smen(&self) -> DMA2SMEN_R {
                DMA2SMEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - CPU1 DMA1 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma1smen(&self) -> DMA1SMEN_R {
                DMA1SMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn tscsmen(&mut self) -> TSCSMEN_W {
                TSCSMEN_W { w: self }
            }
            ///Bit 12 - CPU1 CRCSMEN
            #[inline(always)]
            pub fn crcsmen(&mut self) -> CRCSMEN_W {
                CRCSMEN_W { w: self }
            }
            ///Bit 9 - CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn sram1smen(&mut self) -> SRAM1SMEN_W {
                SRAM1SMEN_W { w: self }
            }
            ///Bit 2 - CPU1 DMAMUX clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dmamuxsmen(&mut self) -> DMAMUXSMEN_W {
                DMAMUXSMEN_W { w: self }
            }
            ///Bit 1 - CPU1 DMA2 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma2smen(&mut self) -> DMA2SMEN_W {
                DMA2SMEN_W { w: self }
            }
            ///Bit 0 - CPU1 DMA1 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma1smen(&mut self) -> DMA1SMEN_W {
                DMA1SMEN_W { w: self }
            }
        }
    }
    ///AHB2 peripheral clocks enable in Sleep and Stop modes register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb2smenr](ahb2smenr) module
    pub type AHB2SMENR = crate::Reg<u32, _AHB2SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB2SMENR;
    ///`read()` method returns [ahb2smenr::R](ahb2smenr::R) reader structure
    impl crate::Readable for AHB2SMENR {}
    ///`write(|w| ..)` method takes [ahb2smenr::W](ahb2smenr::W) writer structure
    impl crate::Writable for AHB2SMENR {}
    ///AHB2 peripheral clocks enable in Sleep and Stop modes register
    pub mod ahb2smenr {
        ///Reader of register AHB2SMENR
        pub type R = crate::R<u32, super::AHB2SMENR>;
        ///Writer for register AHB2SMENR
        pub type W = crate::W<u32, super::AHB2SMENR>;
        ///Register AHB2SMENR `reset()`'s with value 0x0001_209f
        impl crate::ResetValue for super::AHB2SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0001_209f
            }
        }
        ///Reader of field `AES1SMEN`
        pub type AES1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES1SMEN`
        pub struct AES1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `ADCFSSMEN`
        pub type ADCFSSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ADCFSSMEN`
        pub struct ADCFSSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCFSSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `GPIOHSMEN`
        pub type GPIOHSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOHSMEN`
        pub struct GPIOHSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOHSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `GPIOESMEN`
        pub type GPIOESMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOESMEN`
        pub struct GPIOESMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOESMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `GPIODSMEN`
        pub type GPIODSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIODSMEN`
        pub struct GPIODSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIODSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `GPIOCSMEN`
        pub type GPIOCSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOCSMEN`
        pub struct GPIOCSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOCSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `GPIOBSMEN`
        pub type GPIOBSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOBSMEN`
        pub struct GPIOBSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOBSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `GPIOASMEN`
        pub type GPIOASMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOASMEN`
        pub struct GPIOASMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOASMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn aes1smen(&self) -> AES1SMEN_R {
                AES1SMEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 13 - CPU1 ADC clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn adcfssmen(&self) -> ADCFSSMEN_R {
                ADCFSSMEN_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 7 - CPU1 IO port H clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiohsmen(&self) -> GPIOHSMEN_R {
                GPIOHSMEN_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 4 - CPU1 IO port E clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioesmen(&self) -> GPIOESMEN_R {
                GPIOESMEN_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - CPU1 IO port D clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiodsmen(&self) -> GPIODSMEN_R {
                GPIODSMEN_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - CPU1 IO port C clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiocsmen(&self) -> GPIOCSMEN_R {
                GPIOCSMEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - CPU1 IO port B clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiobsmen(&self) -> GPIOBSMEN_R {
                GPIOBSMEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - CPU1 IO port A clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioasmen(&self) -> GPIOASMEN_R {
                GPIOASMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn aes1smen(&mut self) -> AES1SMEN_W {
                AES1SMEN_W { w: self }
            }
            ///Bit 13 - CPU1 ADC clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn adcfssmen(&mut self) -> ADCFSSMEN_W {
                ADCFSSMEN_W { w: self }
            }
            ///Bit 7 - CPU1 IO port H clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiohsmen(&mut self) -> GPIOHSMEN_W {
                GPIOHSMEN_W { w: self }
            }
            ///Bit 4 - CPU1 IO port E clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioesmen(&mut self) -> GPIOESMEN_W {
                GPIOESMEN_W { w: self }
            }
            ///Bit 3 - CPU1 IO port D clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiodsmen(&mut self) -> GPIODSMEN_W {
                GPIODSMEN_W { w: self }
            }
            ///Bit 2 - CPU1 IO port C clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiocsmen(&mut self) -> GPIOCSMEN_W {
                GPIOCSMEN_W { w: self }
            }
            ///Bit 1 - CPU1 IO port B clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiobsmen(&mut self) -> GPIOBSMEN_W {
                GPIOBSMEN_W { w: self }
            }
            ///Bit 0 - CPU1 IO port A clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioasmen(&mut self) -> GPIOASMEN_W {
                GPIOASMEN_W { w: self }
            }
        }
    }
    ///AHB3 peripheral clocks enable in Sleep and Stop modes register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ahb3smenr](ahb3smenr) module
    pub type AHB3SMENR = crate::Reg<u32, _AHB3SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AHB3SMENR;
    ///`read()` method returns [ahb3smenr::R](ahb3smenr::R) reader structure
    impl crate::Readable for AHB3SMENR {}
    ///`write(|w| ..)` method takes [ahb3smenr::W](ahb3smenr::W) writer structure
    impl crate::Writable for AHB3SMENR {}
    ///AHB3 peripheral clocks enable in Sleep and Stop modes register
    pub mod ahb3smenr {
        ///Reader of register AHB3SMENR
        pub type R = crate::R<u32, super::AHB3SMENR>;
        ///Writer for register AHB3SMENR
        pub type W = crate::W<u32, super::AHB3SMENR>;
        ///Register AHB3SMENR `reset()`'s with value 0x0307_0100
        impl crate::ResetValue for super::AHB3SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0307_0100
            }
        }
        ///Reader of field `FLASHSMEN`
        pub type FLASHSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `FLASHSMEN`
        pub struct FLASHSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FLASHSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `SRAM2SMEN`
        pub type SRAM2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM2SMEN`
        pub struct SRAM2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `RNGSMEN`
        pub type RNGSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RNGSMEN`
        pub struct RNGSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNGSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `AES2SMEN`
        pub type AES2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES2SMEN`
        pub struct AES2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `PKASMEN`
        pub type PKASMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PKASMEN`
        pub struct PKASMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PKASMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `QSPISMEN`
        pub type QSPISMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `QSPISMEN`
        pub struct QSPISMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> QSPISMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 25 - Flash interface clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn flashsmen(&self) -> FLASHSMEN_R {
                FLASHSMEN_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn sram2smen(&self) -> SRAM2SMEN_R {
                SRAM2SMEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 18 - True RNG clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn rngsmen(&self) -> RNGSMEN_R {
                RNGSMEN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - AES2 accelerator clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn aes2smen(&self) -> AES2SMEN_R {
                AES2SMEN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - PKA accelerator clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn pkasmen(&self) -> PKASMEN_R {
                PKASMEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - QSPISMEN
            #[inline(always)]
            pub fn qspismen(&self) -> QSPISMEN_R {
                QSPISMEN_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 25 - Flash interface clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn flashsmen(&mut self) -> FLASHSMEN_W {
                FLASHSMEN_W { w: self }
            }
            ///Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn sram2smen(&mut self) -> SRAM2SMEN_W {
                SRAM2SMEN_W { w: self }
            }
            ///Bit 18 - True RNG clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn rngsmen(&mut self) -> RNGSMEN_W {
                RNGSMEN_W { w: self }
            }
            ///Bit 17 - AES2 accelerator clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn aes2smen(&mut self) -> AES2SMEN_W {
                AES2SMEN_W { w: self }
            }
            ///Bit 16 - PKA accelerator clocks enable during CPU1 sleep mode
            #[inline(always)]
            pub fn pkasmen(&mut self) -> PKASMEN_W {
                PKASMEN_W { w: self }
            }
            ///Bit 8 - QSPISMEN
            #[inline(always)]
            pub fn qspismen(&mut self) -> QSPISMEN_W {
                QSPISMEN_W { w: self }
            }
        }
    }
    ///APB1SMENR1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1smenr1](apb1smenr1) module
    pub type APB1SMENR1 = crate::Reg<u32, _APB1SMENR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1SMENR1;
    ///`read()` method returns [apb1smenr1::R](apb1smenr1::R) reader structure
    impl crate::Readable for APB1SMENR1 {}
    ///`write(|w| ..)` method takes [apb1smenr1::W](apb1smenr1::W) writer structure
    impl crate::Writable for APB1SMENR1 {}
    ///APB1SMENR1
    pub mod apb1smenr1 {
        ///Reader of register APB1SMENR1
        pub type R = crate::R<u32, super::APB1SMENR1>;
        ///Writer for register APB1SMENR1
        pub type W = crate::W<u32, super::APB1SMENR1>;
        ///Register APB1SMENR1 `reset()`'s with value 0x85a0_4e01
        impl crate::ResetValue for super::APB1SMENR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x85a0_4e01
            }
        }
        ///Reader of field `LPTIM1SMEN`
        pub type LPTIM1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM1SMEN`
        pub struct LPTIM1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `USBSMEN`
        pub type USBSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `USBSMEN`
        pub struct USBSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USBSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `CRSMEN`
        pub type CRSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRSMEN`
        pub struct CRSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `I2C3SMEN`
        pub type I2C3SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C3SMEN`
        pub struct I2C3SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C3SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `I2C1SMEN`
        pub type I2C1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C1SMEN`
        pub struct I2C1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `SPI2SMEN`
        pub type SPI2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI2SMEN`
        pub struct SPI2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `WWDGSMEN`
        pub type WWDGSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `WWDGSMEN`
        pub struct WWDGSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WWDGSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `RTCAPBSMEN`
        pub type RTCAPBSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCAPBSMEN`
        pub struct RTCAPBSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCAPBSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LCDSMEN`
        pub type LCDSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LCDSMEN`
        pub struct LCDSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCDSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `TIM2SMEN`
        pub type TIM2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM2SMEN`
        pub struct TIM2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - Low power timer 1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lptim1smen(&self) -> LPTIM1SMEN_R {
                LPTIM1SMEN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 26 - USB FS clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn usbsmen(&self) -> USBSMEN_R {
                USBSMEN_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 24 - CRS clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn crsmen(&self) -> CRSMEN_R {
                CRSMEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - I2C3 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn i2c3smen(&self) -> I2C3SMEN_R {
                I2C3SMEN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 21 - I2C1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn i2c1smen(&self) -> I2C1SMEN_R {
                I2C1SMEN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 14 - SPI2 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn spi2smen(&self) -> SPI2SMEN_R {
                SPI2SMEN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 11 - Window watchdog clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn wwdgsmen(&self) -> WWDGSMEN_R {
                WWDGSMEN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - RTC APB clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R {
                RTCAPBSMEN_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - LCD clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lcdsmen(&self) -> LCDSMEN_R {
                LCDSMEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 0 - TIM2 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim2smen(&self) -> TIM2SMEN_R {
                TIM2SMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - Low power timer 1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W {
                LPTIM1SMEN_W { w: self }
            }
            ///Bit 26 - USB FS clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn usbsmen(&mut self) -> USBSMEN_W {
                USBSMEN_W { w: self }
            }
            ///Bit 24 - CRS clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn crsmen(&mut self) -> CRSMEN_W {
                CRSMEN_W { w: self }
            }
            ///Bit 23 - I2C3 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn i2c3smen(&mut self) -> I2C3SMEN_W {
                I2C3SMEN_W { w: self }
            }
            ///Bit 21 - I2C1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn i2c1smen(&mut self) -> I2C1SMEN_W {
                I2C1SMEN_W { w: self }
            }
            ///Bit 14 - SPI2 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn spi2smen(&mut self) -> SPI2SMEN_W {
                SPI2SMEN_W { w: self }
            }
            ///Bit 11 - Window watchdog clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn wwdgsmen(&mut self) -> WWDGSMEN_W {
                WWDGSMEN_W { w: self }
            }
            ///Bit 10 - RTC APB clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W {
                RTCAPBSMEN_W { w: self }
            }
            ///Bit 9 - LCD clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lcdsmen(&mut self) -> LCDSMEN_W {
                LCDSMEN_W { w: self }
            }
            ///Bit 0 - TIM2 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim2smen(&mut self) -> TIM2SMEN_W {
                TIM2SMEN_W { w: self }
            }
        }
    }
    ///APB1 peripheral clocks enable in Sleep and Stop modes register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1smenr2](apb1smenr2) module
    pub type APB1SMENR2 = crate::Reg<u32, _APB1SMENR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1SMENR2;
    ///`read()` method returns [apb1smenr2::R](apb1smenr2::R) reader structure
    impl crate::Readable for APB1SMENR2 {}
    ///`write(|w| ..)` method takes [apb1smenr2::W](apb1smenr2::W) writer structure
    impl crate::Writable for APB1SMENR2 {}
    ///APB1 peripheral clocks enable in Sleep and Stop modes register 2
    pub mod apb1smenr2 {
        ///Reader of register APB1SMENR2
        pub type R = crate::R<u32, super::APB1SMENR2>;
        ///Writer for register APB1SMENR2
        pub type W = crate::W<u32, super::APB1SMENR2>;
        ///Register APB1SMENR2 `reset()`'s with value 0x21
        impl crate::ResetValue for super::APB1SMENR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x21
            }
        }
        ///Reader of field `LPTIM2SMEN`
        pub type LPTIM2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM2SMEN`
        pub struct LPTIM2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LPUART1SMEN`
        pub type LPUART1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPUART1SMEN`
        pub struct LPUART1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPUART1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 5 - Low power timer 2 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lptim2smen(&self) -> LPTIM2SMEN_R {
                LPTIM2SMEN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 0 - Low power UART 1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lpuart1smen(&self) -> LPUART1SMEN_R {
                LPUART1SMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 5 - Low power timer 2 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W {
                LPTIM2SMEN_W { w: self }
            }
            ///Bit 0 - Low power UART 1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W {
                LPUART1SMEN_W { w: self }
            }
        }
    }
    ///APB2SMENR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb2smenr](apb2smenr) module
    pub type APB2SMENR = crate::Reg<u32, _APB2SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB2SMENR;
    ///`read()` method returns [apb2smenr::R](apb2smenr::R) reader structure
    impl crate::Readable for APB2SMENR {}
    ///`write(|w| ..)` method takes [apb2smenr::W](apb2smenr::W) writer structure
    impl crate::Writable for APB2SMENR {}
    ///APB2SMENR
    pub mod apb2smenr {
        ///Reader of register APB2SMENR
        pub type R = crate::R<u32, super::APB2SMENR>;
        ///Writer for register APB2SMENR
        pub type W = crate::W<u32, super::APB2SMENR>;
        ///Register APB2SMENR `reset()`'s with value 0x0026_5800
        impl crate::ResetValue for super::APB2SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0026_5800
            }
        }
        ///Reader of field `SAI1SMEN`
        pub type SAI1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SAI1SMEN`
        pub struct SAI1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAI1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `TIM17SMEN`
        pub type TIM17SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM17SMEN`
        pub struct TIM17SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM17SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TIM16SMEN`
        pub type TIM16SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM16SMEN`
        pub struct TIM16SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM16SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `USART1SMEN`
        pub type USART1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `USART1SMEN`
        pub struct USART1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USART1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `SPI1SMEN`
        pub type SPI1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI1SMEN`
        pub struct SPI1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TIM1SMEN`
        pub type TIM1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM1SMEN`
        pub struct TIM1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 21 - SAI1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn sai1smen(&self) -> SAI1SMEN_R {
                SAI1SMEN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 18 - TIM17 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim17smen(&self) -> TIM17SMEN_R {
                TIM17SMEN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - TIM16 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim16smen(&self) -> TIM16SMEN_R {
                TIM16SMEN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 14 - USART1clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn usart1smen(&self) -> USART1SMEN_R {
                USART1SMEN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 12 - SPI1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn spi1smen(&self) -> SPI1SMEN_R {
                SPI1SMEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - TIM1 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim1smen(&self) -> TIM1SMEN_R {
                TIM1SMEN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 21 - SAI1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn sai1smen(&mut self) -> SAI1SMEN_W {
                SAI1SMEN_W { w: self }
            }
            ///Bit 18 - TIM17 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim17smen(&mut self) -> TIM17SMEN_W {
                TIM17SMEN_W { w: self }
            }
            ///Bit 17 - TIM16 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim16smen(&mut self) -> TIM16SMEN_W {
                TIM16SMEN_W { w: self }
            }
            ///Bit 14 - USART1clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn usart1smen(&mut self) -> USART1SMEN_W {
                USART1SMEN_W { w: self }
            }
            ///Bit 12 - SPI1 clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn spi1smen(&mut self) -> SPI1SMEN_W {
                SPI1SMEN_W { w: self }
            }
            ///Bit 11 - TIM1 timer clocks enable during CPU1 Sleep mode
            #[inline(always)]
            pub fn tim1smen(&mut self) -> TIM1SMEN_W {
                TIM1SMEN_W { w: self }
            }
        }
    }
    ///CCIPR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccipr](ccipr) module
    pub type CCIPR = crate::Reg<u32, _CCIPR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCIPR;
    ///`read()` method returns [ccipr::R](ccipr::R) reader structure
    impl crate::Readable for CCIPR {}
    ///`write(|w| ..)` method takes [ccipr::W](ccipr::W) writer structure
    impl crate::Writable for CCIPR {}
    ///CCIPR
    pub mod ccipr {
        ///Reader of register CCIPR
        pub type R = crate::R<u32, super::CCIPR>;
        ///Writer for register CCIPR
        pub type W = crate::W<u32, super::CCIPR>;
        ///Register CCIPR `reset()`'s with value 0
        impl crate::ResetValue for super::CCIPR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RNGSEL`
        pub type RNGSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `RNGSEL`
        pub struct RNGSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNGSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `ADCSEL`
        pub type ADCSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `ADCSEL`
        pub struct ADCSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `CLK48SEL`
        pub type CLK48SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `CLK48SEL`
        pub struct CLK48SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CLK48SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `SAI1SEL`
        pub type SAI1SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `SAI1SEL`
        pub struct SAI1SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAI1SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `LPTIM2SEL`
        pub type LPTIM2SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `LPTIM2SEL`
        pub struct LPTIM2SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM2SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `LPTIM1SEL`
        pub type LPTIM1SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `LPTIM1SEL`
        pub struct LPTIM1SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM1SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `I2C3SEL`
        pub type I2C3SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `I2C3SEL`
        pub struct I2C3SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C3SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `I2C1SEL`
        pub type I2C1SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `I2C1SEL`
        pub struct I2C1SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C1SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `LPUART1SEL`
        pub type LPUART1SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `LPUART1SEL`
        pub struct LPUART1SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPUART1SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `USART1SEL`
        pub type USART1SEL_R = crate::R<u8, u8>;
        ///Write proxy for field `USART1SEL`
        pub struct USART1SEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USART1SEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - RNG clock source selection
            #[inline(always)]
            pub fn rngsel(&self) -> RNGSEL_R {
                RNGSEL_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - ADCs clock source selection
            #[inline(always)]
            pub fn adcsel(&self) -> ADCSEL_R {
                ADCSEL_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - 48 MHz clock source selection
            #[inline(always)]
            pub fn clk48sel(&self) -> CLK48SEL_R {
                CLK48SEL_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 22:23 - SAI1 clock source selection
            #[inline(always)]
            pub fn sai1sel(&self) -> SAI1SEL_R {
                SAI1SEL_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Low power timer 2 clock source selection
            #[inline(always)]
            pub fn lptim2sel(&self) -> LPTIM2SEL_R {
                LPTIM2SEL_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Low power timer 1 clock source selection
            #[inline(always)]
            pub fn lptim1sel(&self) -> LPTIM1SEL_R {
                LPTIM1SEL_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - I2C3 clock source selection
            #[inline(always)]
            pub fn i2c3sel(&self) -> I2C3SEL_R {
                I2C3SEL_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 12:13 - I2C1 clock source selection
            #[inline(always)]
            pub fn i2c1sel(&self) -> I2C1SEL_R {
                I2C1SEL_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - LPUART1 clock source selection
            #[inline(always)]
            pub fn lpuart1sel(&self) -> LPUART1SEL_R {
                LPUART1SEL_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 0:1 - USART1 clock source selection
            #[inline(always)]
            pub fn usart1sel(&self) -> USART1SEL_R {
                USART1SEL_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - RNG clock source selection
            #[inline(always)]
            pub fn rngsel(&mut self) -> RNGSEL_W {
                RNGSEL_W { w: self }
            }
            ///Bits 28:29 - ADCs clock source selection
            #[inline(always)]
            pub fn adcsel(&mut self) -> ADCSEL_W {
                ADCSEL_W { w: self }
            }
            ///Bits 26:27 - 48 MHz clock source selection
            #[inline(always)]
            pub fn clk48sel(&mut self) -> CLK48SEL_W {
                CLK48SEL_W { w: self }
            }
            ///Bits 22:23 - SAI1 clock source selection
            #[inline(always)]
            pub fn sai1sel(&mut self) -> SAI1SEL_W {
                SAI1SEL_W { w: self }
            }
            ///Bits 20:21 - Low power timer 2 clock source selection
            #[inline(always)]
            pub fn lptim2sel(&mut self) -> LPTIM2SEL_W {
                LPTIM2SEL_W { w: self }
            }
            ///Bits 18:19 - Low power timer 1 clock source selection
            #[inline(always)]
            pub fn lptim1sel(&mut self) -> LPTIM1SEL_W {
                LPTIM1SEL_W { w: self }
            }
            ///Bits 16:17 - I2C3 clock source selection
            #[inline(always)]
            pub fn i2c3sel(&mut self) -> I2C3SEL_W {
                I2C3SEL_W { w: self }
            }
            ///Bits 12:13 - I2C1 clock source selection
            #[inline(always)]
            pub fn i2c1sel(&mut self) -> I2C1SEL_W {
                I2C1SEL_W { w: self }
            }
            ///Bits 10:11 - LPUART1 clock source selection
            #[inline(always)]
            pub fn lpuart1sel(&mut self) -> LPUART1SEL_W {
                LPUART1SEL_W { w: self }
            }
            ///Bits 0:1 - USART1 clock source selection
            #[inline(always)]
            pub fn usart1sel(&mut self) -> USART1SEL_W {
                USART1SEL_W { w: self }
            }
        }
    }
    ///BDCR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bdcr](bdcr) module
    pub type BDCR = crate::Reg<u32, _BDCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BDCR;
    ///`read()` method returns [bdcr::R](bdcr::R) reader structure
    impl crate::Readable for BDCR {}
    ///`write(|w| ..)` method takes [bdcr::W](bdcr::W) writer structure
    impl crate::Writable for BDCR {}
    ///BDCR
    pub mod bdcr {
        ///Reader of register BDCR
        pub type R = crate::R<u32, super::BDCR>;
        ///Writer for register BDCR
        pub type W = crate::W<u32, super::BDCR>;
        ///Register BDCR `reset()`'s with value 0
        impl crate::ResetValue for super::BDCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LSCOSEL`
        pub type LSCOSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `LSCOSEL`
        pub struct LSCOSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSCOSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 25)) | (((value as u32) & 0x03) << 25);
                self.w
            }
        }
        ///Reader of field `LSCOEN`
        pub type LSCOEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LSCOEN`
        pub struct LSCOEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSCOEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `BDRST`
        pub type BDRST_R = crate::R<bool, bool>;
        ///Write proxy for field `BDRST`
        pub struct BDRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BDRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `RTCEN`
        pub type RTCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCEN`
        pub struct RTCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `RTCSEL`
        pub type RTCSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `RTCSEL`
        pub struct RTCSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `LSECSSD_`
        pub type LSECSSD__R = crate::R<bool, bool>;
        ///Reader of field `LSECSSON`
        pub type LSECSSON_R = crate::R<bool, bool>;
        ///Write proxy for field `LSECSSON`
        pub struct LSECSSON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSECSSON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LSEDRV`
        pub type LSEDRV_R = crate::R<u8, u8>;
        ///Write proxy for field `LSEDRV`
        pub struct LSEDRV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSEDRV_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
                self.w
            }
        }
        ///Reader of field `LSEBYP`
        pub type LSEBYP_R = crate::R<bool, bool>;
        ///Write proxy for field `LSEBYP`
        pub struct LSEBYP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSEBYP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `LSERDY`
        pub type LSERDY_R = crate::R<bool, bool>;
        ///Reader of field `LSEON`
        pub type LSEON_R = crate::R<bool, bool>;
        ///Write proxy for field `LSEON`
        pub struct LSEON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSEON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 25:26 - Low speed clock output selection
            #[inline(always)]
            pub fn lscosel(&self) -> LSCOSEL_R {
                LSCOSEL_R::new(((self.bits >> 25) & 0x03) as u8)
            }
            ///Bit 24 - Low speed clock output enable
            #[inline(always)]
            pub fn lscoen(&self) -> LSCOEN_R {
                LSCOEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 16 - Backup domain software reset
            #[inline(always)]
            pub fn bdrst(&self) -> BDRST_R {
                BDRST_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - RTC clock enable
            #[inline(always)]
            pub fn rtcen(&self) -> RTCEN_R {
                RTCEN_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 8:9 - RTC clock source selection
            #[inline(always)]
            pub fn rtcsel(&self) -> RTCSEL_R {
                RTCSEL_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 6 - CSS on LSE failure detection
            #[inline(always)]
            pub fn lsecssd_(&self) -> LSECSSD__R {
                LSECSSD__R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - LSECSSON
            #[inline(always)]
            pub fn lsecsson(&self) -> LSECSSON_R {
                LSECSSON_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bits 3:4 - SE oscillator drive capability
            #[inline(always)]
            pub fn lsedrv(&self) -> LSEDRV_R {
                LSEDRV_R::new(((self.bits >> 3) & 0x03) as u8)
            }
            ///Bit 2 - LSE oscillator bypass
            #[inline(always)]
            pub fn lsebyp(&self) -> LSEBYP_R {
                LSEBYP_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - LSE oscillator ready
            #[inline(always)]
            pub fn lserdy(&self) -> LSERDY_R {
                LSERDY_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - LSE oscillator enable
            #[inline(always)]
            pub fn lseon(&self) -> LSEON_R {
                LSEON_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 25:26 - Low speed clock output selection
            #[inline(always)]
            pub fn lscosel(&mut self) -> LSCOSEL_W {
                LSCOSEL_W { w: self }
            }
            ///Bit 24 - Low speed clock output enable
            #[inline(always)]
            pub fn lscoen(&mut self) -> LSCOEN_W {
                LSCOEN_W { w: self }
            }
            ///Bit 16 - Backup domain software reset
            #[inline(always)]
            pub fn bdrst(&mut self) -> BDRST_W {
                BDRST_W { w: self }
            }
            ///Bit 15 - RTC clock enable
            #[inline(always)]
            pub fn rtcen(&mut self) -> RTCEN_W {
                RTCEN_W { w: self }
            }
            ///Bits 8:9 - RTC clock source selection
            #[inline(always)]
            pub fn rtcsel(&mut self) -> RTCSEL_W {
                RTCSEL_W { w: self }
            }
            ///Bit 5 - LSECSSON
            #[inline(always)]
            pub fn lsecsson(&mut self) -> LSECSSON_W {
                LSECSSON_W { w: self }
            }
            ///Bits 3:4 - SE oscillator drive capability
            #[inline(always)]
            pub fn lsedrv(&mut self) -> LSEDRV_W {
                LSEDRV_W { w: self }
            }
            ///Bit 2 - LSE oscillator bypass
            #[inline(always)]
            pub fn lsebyp(&mut self) -> LSEBYP_W {
                LSEBYP_W { w: self }
            }
            ///Bit 0 - LSE oscillator enable
            #[inline(always)]
            pub fn lseon(&mut self) -> LSEON_W {
                LSEON_W { w: self }
            }
        }
    }
    ///CSR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [csr](csr) module
    pub type CSR = crate::Reg<u32, _CSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CSR;
    ///`read()` method returns [csr::R](csr::R) reader structure
    impl crate::Readable for CSR {}
    ///`write(|w| ..)` method takes [csr::W](csr::W) writer structure
    impl crate::Writable for CSR {}
    ///CSR
    pub mod csr {
        ///Reader of register CSR
        pub type R = crate::R<u32, super::CSR>;
        ///Writer for register CSR
        pub type W = crate::W<u32, super::CSR>;
        ///Register CSR `reset()`'s with value 0x0c00_0000
        impl crate::ResetValue for super::CSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0c00_0000
            }
        }
        ///Reader of field `LPWRRSTF`
        pub type LPWRRSTF_R = crate::R<bool, bool>;
        ///Reader of field `WWDGRSTF`
        pub type WWDGRSTF_R = crate::R<bool, bool>;
        ///Reader of field `IWDGRSTF`
        pub type IWDGRSTF_R = crate::R<bool, bool>;
        ///Reader of field `SFTRSTF`
        pub type SFTRSTF_R = crate::R<bool, bool>;
        ///Reader of field `BORRSTF`
        pub type BORRSTF_R = crate::R<bool, bool>;
        ///Reader of field `PINRSTF`
        pub type PINRSTF_R = crate::R<bool, bool>;
        ///Reader of field `OBLRSTF`
        pub type OBLRSTF_R = crate::R<bool, bool>;
        ///Reader of field `RMVF`
        pub type RMVF_R = crate::R<bool, bool>;
        ///Write proxy for field `RMVF`
        pub struct RMVF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RMVF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `RFWKPSEL`
        pub type RFWKPSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `RFWKPSEL`
        pub struct RFWKPSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RFWKPSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `LSI2BW`
        pub type LSI2BW_R = crate::R<u8, u8>;
        ///Write proxy for field `LSI2BW`
        pub struct LSI2BW_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI2BW_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `LSI2TRIMOK`
        pub type LSI2TRIMOK_R = crate::R<bool, bool>;
        ///Reader of field `LSI2TRIMEN`
        pub type LSI2TRIMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LSI2TRIMEN`
        pub struct LSI2TRIMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI2TRIMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `LSI2RDY`
        pub type LSI2RDY_R = crate::R<bool, bool>;
        ///Reader of field `LSI2ON`
        pub type LSI2ON_R = crate::R<bool, bool>;
        ///Write proxy for field `LSI2ON`
        pub struct LSI2ON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI2ON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `LSI1RDY`
        pub type LSI1RDY_R = crate::R<bool, bool>;
        ///Reader of field `LSI1ON`
        pub type LSI1ON_R = crate::R<bool, bool>;
        ///Write proxy for field `LSI1ON`
        pub struct LSI1ON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSI1ON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `RFRSTS`
        pub type RFRSTS_R = crate::R<bool, bool>;
        impl R {
            ///Bit 31 - Low-power reset flag
            #[inline(always)]
            pub fn lpwrrstf(&self) -> LPWRRSTF_R {
                LPWRRSTF_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - Window watchdog reset flag
            #[inline(always)]
            pub fn wwdgrstf(&self) -> WWDGRSTF_R {
                WWDGRSTF_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - Independent window watchdog reset flag
            #[inline(always)]
            pub fn iwdgrstf(&self) -> IWDGRSTF_R {
                IWDGRSTF_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - Software reset flag
            #[inline(always)]
            pub fn sftrstf(&self) -> SFTRSTF_R {
                SFTRSTF_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - BOR flag
            #[inline(always)]
            pub fn borrstf(&self) -> BORRSTF_R {
                BORRSTF_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - Pin reset flag
            #[inline(always)]
            pub fn pinrstf(&self) -> PINRSTF_R {
                PINRSTF_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - Option byte loader reset flag
            #[inline(always)]
            pub fn oblrstf(&self) -> OBLRSTF_R {
                OBLRSTF_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 23 - Remove reset flag
            #[inline(always)]
            pub fn rmvf(&self) -> RMVF_R {
                RMVF_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bits 14:15 - RF system wakeup clock source selection
            #[inline(always)]
            pub fn rfwkpsel(&self) -> RFWKPSEL_R {
                RFWKPSEL_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 8:11 - LSI2 oscillator bias configuration
            #[inline(always)]
            pub fn lsi2bw(&self) -> LSI2BW_R {
                LSI2BW_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bit 5 - LSI2 oscillator trim OK
            #[inline(always)]
            pub fn lsi2trimok(&self) -> LSI2TRIMOK_R {
                LSI2TRIMOK_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - LSI2 oscillator trimming enable
            #[inline(always)]
            pub fn lsi2trimen(&self) -> LSI2TRIMEN_R {
                LSI2TRIMEN_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - LSI2 oscillator ready
            #[inline(always)]
            pub fn lsi2rdy(&self) -> LSI2RDY_R {
                LSI2RDY_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - LSI2 oscillator enabled
            #[inline(always)]
            pub fn lsi2on(&self) -> LSI2ON_R {
                LSI2ON_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - LSI1 oscillator ready
            #[inline(always)]
            pub fn lsi1rdy(&self) -> LSI1RDY_R {
                LSI1RDY_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - LSI1 oscillator enabled
            #[inline(always)]
            pub fn lsi1on(&self) -> LSI1ON_R {
                LSI1ON_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 16 - Radio system BLE and 802.15.4 reset status
            #[inline(always)]
            pub fn rfrsts(&self) -> RFRSTS_R {
                RFRSTS_R::new(((self.bits >> 16) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 23 - Remove reset flag
            #[inline(always)]
            pub fn rmvf(&mut self) -> RMVF_W {
                RMVF_W { w: self }
            }
            ///Bits 14:15 - RF system wakeup clock source selection
            #[inline(always)]
            pub fn rfwkpsel(&mut self) -> RFWKPSEL_W {
                RFWKPSEL_W { w: self }
            }
            ///Bits 8:11 - LSI2 oscillator bias configuration
            #[inline(always)]
            pub fn lsi2bw(&mut self) -> LSI2BW_W {
                LSI2BW_W { w: self }
            }
            ///Bit 4 - LSI2 oscillator trimming enable
            #[inline(always)]
            pub fn lsi2trimen(&mut self) -> LSI2TRIMEN_W {
                LSI2TRIMEN_W { w: self }
            }
            ///Bit 2 - LSI2 oscillator enabled
            #[inline(always)]
            pub fn lsi2on(&mut self) -> LSI2ON_W {
                LSI2ON_W { w: self }
            }
            ///Bit 0 - LSI1 oscillator enabled
            #[inline(always)]
            pub fn lsi1on(&mut self) -> LSI1ON_W {
                LSI1ON_W { w: self }
            }
        }
    }
    ///Clock recovery RC register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [crrcr](crrcr) module
    pub type CRRCR = crate::Reg<u32, _CRRCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CRRCR;
    ///`read()` method returns [crrcr::R](crrcr::R) reader structure
    impl crate::Readable for CRRCR {}
    ///`write(|w| ..)` method takes [crrcr::W](crrcr::W) writer structure
    impl crate::Writable for CRRCR {}
    ///Clock recovery RC register
    pub mod crrcr {
        ///Reader of register CRRCR
        pub type R = crate::R<u32, super::CRRCR>;
        ///Writer for register CRRCR
        pub type W = crate::W<u32, super::CRRCR>;
        ///Register CRRCR `reset()`'s with value 0
        impl crate::ResetValue for super::CRRCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `HSI48CAL`
        pub type HSI48CAL_R = crate::R<u16, u16>;
        ///Reader of field `HSI48RDY`
        pub type HSI48RDY_R = crate::R<bool, bool>;
        ///Reader of field `HSI48ON`
        pub type HSI48ON_R = crate::R<bool, bool>;
        ///Write proxy for field `HSI48ON`
        pub struct HSI48ON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSI48ON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 7:15 - HSI48 clock calibration
            #[inline(always)]
            pub fn hsi48cal(&self) -> HSI48CAL_R {
                HSI48CAL_R::new(((self.bits >> 7) & 0x01ff) as u16)
            }
            ///Bit 1 - HSI48 clock ready
            #[inline(always)]
            pub fn hsi48rdy(&self) -> HSI48RDY_R {
                HSI48RDY_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - HSI48 oscillator enabled
            #[inline(always)]
            pub fn hsi48on(&self) -> HSI48ON_R {
                HSI48ON_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - HSI48 oscillator enabled
            #[inline(always)]
            pub fn hsi48on(&mut self) -> HSI48ON_W {
                HSI48ON_W { w: self }
            }
        }
    }
    ///Clock HSE register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hsecr](hsecr) module
    pub type HSECR = crate::Reg<u32, _HSECR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HSECR;
    ///`read()` method returns [hsecr::R](hsecr::R) reader structure
    impl crate::Readable for HSECR {}
    ///`write(|w| ..)` method takes [hsecr::W](hsecr::W) writer structure
    impl crate::Writable for HSECR {}
    ///Clock HSE register
    pub mod hsecr {
        ///Reader of register HSECR
        pub type R = crate::R<u32, super::HSECR>;
        ///Writer for register HSECR
        pub type W = crate::W<u32, super::HSECR>;
        ///Register HSECR `reset()`'s with value 0x30
        impl crate::ResetValue for super::HSECR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x30
            }
        }
        ///Reader of field `HSETUNE`
        pub type HSETUNE_R = crate::R<u8, u8>;
        ///Reader of field `HSEGMC`
        pub type HSEGMC_R = crate::R<u8, u8>;
        ///Write proxy for field `HSEGMC`
        pub struct HSEGMC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSEGMC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `HSES`
        pub type HSES_R = crate::R<bool, bool>;
        ///Write proxy for field `HSES`
        pub struct HSES_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSES_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `UNLOCKED`
        pub type UNLOCKED_R = crate::R<bool, bool>;
        ///Write proxy for field `UNLOCKED`
        pub struct UNLOCKED_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UNLOCKED_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 8:13 - HSE capacitor tuning
            #[inline(always)]
            pub fn hsetune(&self) -> HSETUNE_R {
                HSETUNE_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
            ///Bits 4:6 - HSE current control
            #[inline(always)]
            pub fn hsegmc(&self) -> HSEGMC_R {
                HSEGMC_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - HSE Sense amplifier threshold
            #[inline(always)]
            pub fn hses(&self) -> HSES_R {
                HSES_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 0 - Register lock system
            #[inline(always)]
            pub fn unlocked(&self) -> UNLOCKED_R {
                UNLOCKED_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 4:6 - HSE current control
            #[inline(always)]
            pub fn hsegmc(&mut self) -> HSEGMC_W {
                HSEGMC_W { w: self }
            }
            ///Bit 3 - HSE Sense amplifier threshold
            #[inline(always)]
            pub fn hses(&mut self) -> HSES_W {
                HSES_W { w: self }
            }
            ///Bit 0 - Register lock system
            #[inline(always)]
            pub fn unlocked(&mut self) -> UNLOCKED_W {
                UNLOCKED_W { w: self }
            }
        }
    }
    ///Extended clock recovery register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [extcfgr](extcfgr) module
    pub type EXTCFGR = crate::Reg<u32, _EXTCFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EXTCFGR;
    ///`read()` method returns [extcfgr::R](extcfgr::R) reader structure
    impl crate::Readable for EXTCFGR {}
    ///`write(|w| ..)` method takes [extcfgr::W](extcfgr::W) writer structure
    impl crate::Writable for EXTCFGR {}
    ///Extended clock recovery register
    pub mod extcfgr {
        ///Reader of register EXTCFGR
        pub type R = crate::R<u32, super::EXTCFGR>;
        ///Writer for register EXTCFGR
        pub type W = crate::W<u32, super::EXTCFGR>;
        ///Register EXTCFGR `reset()`'s with value 0x0003_0000
        impl crate::ResetValue for super::EXTCFGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0003_0000
            }
        }
        ///Reader of field `RFCSS`
        pub type RFCSS_R = crate::R<bool, bool>;
        ///Reader of field `C2HPREF`
        pub type C2HPREF_R = crate::R<bool, bool>;
        ///Reader of field `SHDHPREF`
        pub type SHDHPREF_R = crate::R<bool, bool>;
        ///Reader of field `C2HPRE`
        pub type C2HPRE_R = crate::R<u8, u8>;
        ///Write proxy for field `C2HPRE`
        pub struct C2HPRE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C2HPRE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `SHDHPRE`
        pub type SHDHPRE_R = crate::R<u8, u8>;
        ///Write proxy for field `SHDHPRE`
        pub struct SHDHPRE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SHDHPRE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bit 20 - RF clock source selected
            #[inline(always)]
            pub fn rfcss(&self) -> RFCSS_R {
                RFCSS_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 17 - CPU2 AHB prescaler flag
            #[inline(always)]
            pub fn c2hpref(&self) -> C2HPREF_R {
                C2HPREF_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - Shared AHB prescaler flag
            #[inline(always)]
            pub fn shdhpref(&self) -> SHDHPREF_R {
                SHDHPREF_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 4:7 - CPU2 AHB prescaler
            #[inline(always)]
            pub fn c2hpre(&self) -> C2HPRE_R {
                C2HPRE_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Shared AHB prescaler
            #[inline(always)]
            pub fn shdhpre(&self) -> SHDHPRE_R {
                SHDHPRE_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 4:7 - CPU2 AHB prescaler
            #[inline(always)]
            pub fn c2hpre(&mut self) -> C2HPRE_W {
                C2HPRE_W { w: self }
            }
            ///Bits 0:3 - Shared AHB prescaler
            #[inline(always)]
            pub fn shdhpre(&mut self) -> SHDHPRE_W {
                SHDHPRE_W { w: self }
            }
        }
    }
    ///CPU2 AHB1 peripheral clock enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ahb1enr](c2ahb1enr) module
    pub type C2AHB1ENR = crate::Reg<u32, _C2AHB1ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2AHB1ENR;
    ///`read()` method returns [c2ahb1enr::R](c2ahb1enr::R) reader structure
    impl crate::Readable for C2AHB1ENR {}
    ///`write(|w| ..)` method takes [c2ahb1enr::W](c2ahb1enr::W) writer structure
    impl crate::Writable for C2AHB1ENR {}
    ///CPU2 AHB1 peripheral clock enable register
    pub mod c2ahb1enr {
        ///Reader of register C2AHB1ENR
        pub type R = crate::R<u32, super::C2AHB1ENR>;
        ///Writer for register C2AHB1ENR
        pub type W = crate::W<u32, super::C2AHB1ENR>;
        ///Register C2AHB1ENR `reset()`'s with value 0
        impl crate::ResetValue for super::C2AHB1ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TSCEN`
        pub type TSCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TSCEN`
        pub struct TSCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CRCEN`
        pub type CRCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCEN`
        pub struct CRCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `SRAM1EN`
        pub type SRAM1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM1EN`
        pub struct SRAM1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `DMAMUXEN`
        pub type DMAMUXEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAMUXEN`
        pub struct DMAMUXEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAMUXEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DMA2EN`
        pub type DMA2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2EN`
        pub struct DMA2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DMA1EN`
        pub type DMA1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1EN`
        pub struct DMA1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - CPU2 Touch Sensing Controller clock enable
            #[inline(always)]
            pub fn tscen(&self) -> TSCEN_R {
                TSCEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 12 - CPU2 CRC clock enable
            #[inline(always)]
            pub fn crcen(&self) -> CRCEN_R {
                CRCEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 9 - CPU2 SRAM1 clock enable
            #[inline(always)]
            pub fn sram1en(&self) -> SRAM1EN_R {
                SRAM1EN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 2 - CPU2 DMAMUX clock enable
            #[inline(always)]
            pub fn dmamuxen(&self) -> DMAMUXEN_R {
                DMAMUXEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - CPU2 DMA2 clock enable
            #[inline(always)]
            pub fn dma2en(&self) -> DMA2EN_R {
                DMA2EN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - CPU2 DMA1 clock enable
            #[inline(always)]
            pub fn dma1en(&self) -> DMA1EN_R {
                DMA1EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - CPU2 Touch Sensing Controller clock enable
            #[inline(always)]
            pub fn tscen(&mut self) -> TSCEN_W {
                TSCEN_W { w: self }
            }
            ///Bit 12 - CPU2 CRC clock enable
            #[inline(always)]
            pub fn crcen(&mut self) -> CRCEN_W {
                CRCEN_W { w: self }
            }
            ///Bit 9 - CPU2 SRAM1 clock enable
            #[inline(always)]
            pub fn sram1en(&mut self) -> SRAM1EN_W {
                SRAM1EN_W { w: self }
            }
            ///Bit 2 - CPU2 DMAMUX clock enable
            #[inline(always)]
            pub fn dmamuxen(&mut self) -> DMAMUXEN_W {
                DMAMUXEN_W { w: self }
            }
            ///Bit 1 - CPU2 DMA2 clock enable
            #[inline(always)]
            pub fn dma2en(&mut self) -> DMA2EN_W {
                DMA2EN_W { w: self }
            }
            ///Bit 0 - CPU2 DMA1 clock enable
            #[inline(always)]
            pub fn dma1en(&mut self) -> DMA1EN_W {
                DMA1EN_W { w: self }
            }
        }
    }
    ///CPU2 AHB2 peripheral clock enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ahb2enr](c2ahb2enr) module
    pub type C2AHB2ENR = crate::Reg<u32, _C2AHB2ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2AHB2ENR;
    ///`read()` method returns [c2ahb2enr::R](c2ahb2enr::R) reader structure
    impl crate::Readable for C2AHB2ENR {}
    ///`write(|w| ..)` method takes [c2ahb2enr::W](c2ahb2enr::W) writer structure
    impl crate::Writable for C2AHB2ENR {}
    ///CPU2 AHB2 peripheral clock enable register
    pub mod c2ahb2enr {
        ///Reader of register C2AHB2ENR
        pub type R = crate::R<u32, super::C2AHB2ENR>;
        ///Writer for register C2AHB2ENR
        pub type W = crate::W<u32, super::C2AHB2ENR>;
        ///Register C2AHB2ENR `reset()`'s with value 0
        impl crate::ResetValue for super::C2AHB2ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES1EN`
        pub type AES1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES1EN`
        pub struct AES1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `ADCEN`
        pub type ADCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ADCEN`
        pub struct ADCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `GPIOHEN`
        pub type GPIOHEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOHEN`
        pub struct GPIOHEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOHEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `GPIOEEN`
        pub type GPIOEEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOEEN`
        pub struct GPIOEEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOEEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `GPIODEN`
        pub type GPIODEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIODEN`
        pub struct GPIODEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIODEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `GPIOCEN`
        pub type GPIOCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOCEN`
        pub struct GPIOCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `GPIOBEN`
        pub type GPIOBEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOBEN`
        pub struct GPIOBEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOBEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `GPIOAEN`
        pub type GPIOAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOAEN`
        pub struct GPIOAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - CPU2 AES1 accelerator clock enable
            #[inline(always)]
            pub fn aes1en(&self) -> AES1EN_R {
                AES1EN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 13 - CPU2 ADC clock enable
            #[inline(always)]
            pub fn adcen(&self) -> ADCEN_R {
                ADCEN_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 7 - CPU2 IO port H clock enable
            #[inline(always)]
            pub fn gpiohen(&self) -> GPIOHEN_R {
                GPIOHEN_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 4 - CPU2 IO port E clock enable
            #[inline(always)]
            pub fn gpioeen(&self) -> GPIOEEN_R {
                GPIOEEN_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - CPU2 IO port D clock enable
            #[inline(always)]
            pub fn gpioden(&self) -> GPIODEN_R {
                GPIODEN_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - CPU2 IO port C clock enable
            #[inline(always)]
            pub fn gpiocen(&self) -> GPIOCEN_R {
                GPIOCEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - CPU2 IO port B clock enable
            #[inline(always)]
            pub fn gpioben(&self) -> GPIOBEN_R {
                GPIOBEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - CPU2 IO port A clock enable
            #[inline(always)]
            pub fn gpioaen(&self) -> GPIOAEN_R {
                GPIOAEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - CPU2 AES1 accelerator clock enable
            #[inline(always)]
            pub fn aes1en(&mut self) -> AES1EN_W {
                AES1EN_W { w: self }
            }
            ///Bit 13 - CPU2 ADC clock enable
            #[inline(always)]
            pub fn adcen(&mut self) -> ADCEN_W {
                ADCEN_W { w: self }
            }
            ///Bit 7 - CPU2 IO port H clock enable
            #[inline(always)]
            pub fn gpiohen(&mut self) -> GPIOHEN_W {
                GPIOHEN_W { w: self }
            }
            ///Bit 4 - CPU2 IO port E clock enable
            #[inline(always)]
            pub fn gpioeen(&mut self) -> GPIOEEN_W {
                GPIOEEN_W { w: self }
            }
            ///Bit 3 - CPU2 IO port D clock enable
            #[inline(always)]
            pub fn gpioden(&mut self) -> GPIODEN_W {
                GPIODEN_W { w: self }
            }
            ///Bit 2 - CPU2 IO port C clock enable
            #[inline(always)]
            pub fn gpiocen(&mut self) -> GPIOCEN_W {
                GPIOCEN_W { w: self }
            }
            ///Bit 1 - CPU2 IO port B clock enable
            #[inline(always)]
            pub fn gpioben(&mut self) -> GPIOBEN_W {
                GPIOBEN_W { w: self }
            }
            ///Bit 0 - CPU2 IO port A clock enable
            #[inline(always)]
            pub fn gpioaen(&mut self) -> GPIOAEN_W {
                GPIOAEN_W { w: self }
            }
        }
    }
    ///CPU2 AHB3 peripheral clock enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ahb3enr](c2ahb3enr) module
    pub type C2AHB3ENR = crate::Reg<u32, _C2AHB3ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2AHB3ENR;
    ///`read()` method returns [c2ahb3enr::R](c2ahb3enr::R) reader structure
    impl crate::Readable for C2AHB3ENR {}
    ///`write(|w| ..)` method takes [c2ahb3enr::W](c2ahb3enr::W) writer structure
    impl crate::Writable for C2AHB3ENR {}
    ///CPU2 AHB3 peripheral clock enable register
    pub mod c2ahb3enr {
        ///Reader of register C2AHB3ENR
        pub type R = crate::R<u32, super::C2AHB3ENR>;
        ///Writer for register C2AHB3ENR
        pub type W = crate::W<u32, super::C2AHB3ENR>;
        ///Register C2AHB3ENR `reset()`'s with value 0x0208_0000
        impl crate::ResetValue for super::C2AHB3ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0208_0000
            }
        }
        ///Reader of field `FLASHEN`
        pub type FLASHEN_R = crate::R<bool, bool>;
        ///Write proxy for field `FLASHEN`
        pub struct FLASHEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FLASHEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `IPCCEN`
        pub type IPCCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `IPCCEN`
        pub struct IPCCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IPCCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `HSEMEN`
        pub type HSEMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `HSEMEN`
        pub struct HSEMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HSEMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `RNGEN`
        pub type RNGEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RNGEN`
        pub struct RNGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNGEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `AES2EN`
        pub type AES2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES2EN`
        pub struct AES2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `PKAEN`
        pub type PKAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PKAEN`
        pub struct PKAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PKAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        impl R {
            ///Bit 25 - CPU2 FLASHEN
            #[inline(always)]
            pub fn flashen(&self) -> FLASHEN_R {
                FLASHEN_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 20 - CPU2 IPCCEN
            #[inline(always)]
            pub fn ipccen(&self) -> IPCCEN_R {
                IPCCEN_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - CPU2 HSEMEN
            #[inline(always)]
            pub fn hsemen(&self) -> HSEMEN_R {
                HSEMEN_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - CPU2 RNGEN
            #[inline(always)]
            pub fn rngen(&self) -> RNGEN_R {
                RNGEN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - CPU2 AES2EN
            #[inline(always)]
            pub fn aes2en(&self) -> AES2EN_R {
                AES2EN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - CPU2 PKAEN
            #[inline(always)]
            pub fn pkaen(&self) -> PKAEN_R {
                PKAEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 25 - CPU2 FLASHEN
            #[inline(always)]
            pub fn flashen(&mut self) -> FLASHEN_W {
                FLASHEN_W { w: self }
            }
            ///Bit 20 - CPU2 IPCCEN
            #[inline(always)]
            pub fn ipccen(&mut self) -> IPCCEN_W {
                IPCCEN_W { w: self }
            }
            ///Bit 19 - CPU2 HSEMEN
            #[inline(always)]
            pub fn hsemen(&mut self) -> HSEMEN_W {
                HSEMEN_W { w: self }
            }
            ///Bit 18 - CPU2 RNGEN
            #[inline(always)]
            pub fn rngen(&mut self) -> RNGEN_W {
                RNGEN_W { w: self }
            }
            ///Bit 17 - CPU2 AES2EN
            #[inline(always)]
            pub fn aes2en(&mut self) -> AES2EN_W {
                AES2EN_W { w: self }
            }
            ///Bit 16 - CPU2 PKAEN
            #[inline(always)]
            pub fn pkaen(&mut self) -> PKAEN_W {
                PKAEN_W { w: self }
            }
        }
    }
    ///CPU2 APB1ENR1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb1enr1](c2apb1enr1) module
    pub type C2APB1ENR1 = crate::Reg<u32, _C2APB1ENR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB1ENR1;
    ///`read()` method returns [c2apb1enr1::R](c2apb1enr1::R) reader structure
    impl crate::Readable for C2APB1ENR1 {}
    ///`write(|w| ..)` method takes [c2apb1enr1::W](c2apb1enr1::W) writer structure
    impl crate::Writable for C2APB1ENR1 {}
    ///CPU2 APB1ENR1
    pub mod c2apb1enr1 {
        ///Reader of register C2APB1ENR1
        pub type R = crate::R<u32, super::C2APB1ENR1>;
        ///Writer for register C2APB1ENR1
        pub type W = crate::W<u32, super::C2APB1ENR1>;
        ///Register C2APB1ENR1 `reset()`'s with value 0x0400
        impl crate::ResetValue for super::C2APB1ENR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0400
            }
        }
        ///Reader of field `LPTIM1EN`
        pub type LPTIM1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM1EN`
        pub struct LPTIM1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `USBEN`
        pub type USBEN_R = crate::R<bool, bool>;
        ///Write proxy for field `USBEN`
        pub struct USBEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USBEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `CRSEN`
        pub type CRSEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRSEN`
        pub struct CRSEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRSEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `I2C3EN`
        pub type I2C3EN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C3EN`
        pub struct I2C3EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C3EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `I2C1EN`
        pub type I2C1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C1EN`
        pub struct I2C1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `SPI2EN`
        pub type SPI2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI2EN`
        pub struct SPI2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `RTCAPBEN`
        pub type RTCAPBEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCAPBEN`
        pub struct RTCAPBEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCAPBEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LCDEN`
        pub type LCDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LCDEN`
        pub struct LCDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `TIM2EN`
        pub type TIM2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM2EN`
        pub struct TIM2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - CPU2 Low power timer 1 clock enable
            #[inline(always)]
            pub fn lptim1en(&self) -> LPTIM1EN_R {
                LPTIM1EN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 26 - CPU2 USB clock enable
            #[inline(always)]
            pub fn usben(&self) -> USBEN_R {
                USBEN_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 24 - CPU2 CRS clock enable
            #[inline(always)]
            pub fn crsen(&self) -> CRSEN_R {
                CRSEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - CPU2 I2C3 clock enable
            #[inline(always)]
            pub fn i2c3en(&self) -> I2C3EN_R {
                I2C3EN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 21 - CPU2 I2C1 clock enable
            #[inline(always)]
            pub fn i2c1en(&self) -> I2C1EN_R {
                I2C1EN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 14 - CPU2 SPI2 clock enable
            #[inline(always)]
            pub fn spi2en(&self) -> SPI2EN_R {
                SPI2EN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 10 - CPU2 RTC APB clock enable
            #[inline(always)]
            pub fn rtcapben(&self) -> RTCAPBEN_R {
                RTCAPBEN_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - CPU2 LCD clock enable
            #[inline(always)]
            pub fn lcden(&self) -> LCDEN_R {
                LCDEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 0 - CPU2 TIM2 timer clock enable
            #[inline(always)]
            pub fn tim2en(&self) -> TIM2EN_R {
                TIM2EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - CPU2 Low power timer 1 clock enable
            #[inline(always)]
            pub fn lptim1en(&mut self) -> LPTIM1EN_W {
                LPTIM1EN_W { w: self }
            }
            ///Bit 26 - CPU2 USB clock enable
            #[inline(always)]
            pub fn usben(&mut self) -> USBEN_W {
                USBEN_W { w: self }
            }
            ///Bit 24 - CPU2 CRS clock enable
            #[inline(always)]
            pub fn crsen(&mut self) -> CRSEN_W {
                CRSEN_W { w: self }
            }
            ///Bit 23 - CPU2 I2C3 clock enable
            #[inline(always)]
            pub fn i2c3en(&mut self) -> I2C3EN_W {
                I2C3EN_W { w: self }
            }
            ///Bit 21 - CPU2 I2C1 clock enable
            #[inline(always)]
            pub fn i2c1en(&mut self) -> I2C1EN_W {
                I2C1EN_W { w: self }
            }
            ///Bit 14 - CPU2 SPI2 clock enable
            #[inline(always)]
            pub fn spi2en(&mut self) -> SPI2EN_W {
                SPI2EN_W { w: self }
            }
            ///Bit 10 - CPU2 RTC APB clock enable
            #[inline(always)]
            pub fn rtcapben(&mut self) -> RTCAPBEN_W {
                RTCAPBEN_W { w: self }
            }
            ///Bit 9 - CPU2 LCD clock enable
            #[inline(always)]
            pub fn lcden(&mut self) -> LCDEN_W {
                LCDEN_W { w: self }
            }
            ///Bit 0 - CPU2 TIM2 timer clock enable
            #[inline(always)]
            pub fn tim2en(&mut self) -> TIM2EN_W {
                TIM2EN_W { w: self }
            }
        }
    }
    ///CPU2 APB1 peripheral clock enable register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb1enr2](c2apb1enr2) module
    pub type C2APB1ENR2 = crate::Reg<u32, _C2APB1ENR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB1ENR2;
    ///`read()` method returns [c2apb1enr2::R](c2apb1enr2::R) reader structure
    impl crate::Readable for C2APB1ENR2 {}
    ///`write(|w| ..)` method takes [c2apb1enr2::W](c2apb1enr2::W) writer structure
    impl crate::Writable for C2APB1ENR2 {}
    ///CPU2 APB1 peripheral clock enable register 2
    pub mod c2apb1enr2 {
        ///Reader of register C2APB1ENR2
        pub type R = crate::R<u32, super::C2APB1ENR2>;
        ///Writer for register C2APB1ENR2
        pub type W = crate::W<u32, super::C2APB1ENR2>;
        ///Register C2APB1ENR2 `reset()`'s with value 0
        impl crate::ResetValue for super::C2APB1ENR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LPTIM2EN`
        pub type LPTIM2EN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM2EN`
        pub struct LPTIM2EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM2EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LPUART1EN`
        pub type LPUART1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPUART1EN`
        pub struct LPUART1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPUART1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 5 - CPU2 LPTIM2EN
            #[inline(always)]
            pub fn lptim2en(&self) -> LPTIM2EN_R {
                LPTIM2EN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 0 - CPU2 Low power UART 1 clock enable
            #[inline(always)]
            pub fn lpuart1en(&self) -> LPUART1EN_R {
                LPUART1EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 5 - CPU2 LPTIM2EN
            #[inline(always)]
            pub fn lptim2en(&mut self) -> LPTIM2EN_W {
                LPTIM2EN_W { w: self }
            }
            ///Bit 0 - CPU2 Low power UART 1 clock enable
            #[inline(always)]
            pub fn lpuart1en(&mut self) -> LPUART1EN_W {
                LPUART1EN_W { w: self }
            }
        }
    }
    ///CPU2 APB2ENR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb2enr](c2apb2enr) module
    pub type C2APB2ENR = crate::Reg<u32, _C2APB2ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB2ENR;
    ///`read()` method returns [c2apb2enr::R](c2apb2enr::R) reader structure
    impl crate::Readable for C2APB2ENR {}
    ///`write(|w| ..)` method takes [c2apb2enr::W](c2apb2enr::W) writer structure
    impl crate::Writable for C2APB2ENR {}
    ///CPU2 APB2ENR
    pub mod c2apb2enr {
        ///Reader of register C2APB2ENR
        pub type R = crate::R<u32, super::C2APB2ENR>;
        ///Writer for register C2APB2ENR
        pub type W = crate::W<u32, super::C2APB2ENR>;
        ///Register C2APB2ENR `reset()`'s with value 0
        impl crate::ResetValue for super::C2APB2ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SAI1EN`
        pub type SAI1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `SAI1EN`
        pub struct SAI1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAI1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `TIM17EN`
        pub type TIM17EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM17EN`
        pub struct TIM17EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM17EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TIM16EN`
        pub type TIM16EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM16EN`
        pub struct TIM16EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM16EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `USART1EN`
        pub type USART1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `USART1EN`
        pub struct USART1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USART1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `SPI1EN`
        pub type SPI1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI1EN`
        pub struct SPI1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TIM1EN`
        pub type TIM1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM1EN`
        pub struct TIM1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 21 - CPU2 SAI1 clock enable
            #[inline(always)]
            pub fn sai1en(&self) -> SAI1EN_R {
                SAI1EN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 18 - CPU2 TIM17 timer clock enable
            #[inline(always)]
            pub fn tim17en(&self) -> TIM17EN_R {
                TIM17EN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - CPU2 TIM16 timer clock enable
            #[inline(always)]
            pub fn tim16en(&self) -> TIM16EN_R {
                TIM16EN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 14 - CPU2 USART1clock enable
            #[inline(always)]
            pub fn usart1en(&self) -> USART1EN_R {
                USART1EN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 12 - CPU2 SPI1 clock enable
            #[inline(always)]
            pub fn spi1en(&self) -> SPI1EN_R {
                SPI1EN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - CPU2 TIM1 timer clock enable
            #[inline(always)]
            pub fn tim1en(&self) -> TIM1EN_R {
                TIM1EN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 21 - CPU2 SAI1 clock enable
            #[inline(always)]
            pub fn sai1en(&mut self) -> SAI1EN_W {
                SAI1EN_W { w: self }
            }
            ///Bit 18 - CPU2 TIM17 timer clock enable
            #[inline(always)]
            pub fn tim17en(&mut self) -> TIM17EN_W {
                TIM17EN_W { w: self }
            }
            ///Bit 17 - CPU2 TIM16 timer clock enable
            #[inline(always)]
            pub fn tim16en(&mut self) -> TIM16EN_W {
                TIM16EN_W { w: self }
            }
            ///Bit 14 - CPU2 USART1clock enable
            #[inline(always)]
            pub fn usart1en(&mut self) -> USART1EN_W {
                USART1EN_W { w: self }
            }
            ///Bit 12 - CPU2 SPI1 clock enable
            #[inline(always)]
            pub fn spi1en(&mut self) -> SPI1EN_W {
                SPI1EN_W { w: self }
            }
            ///Bit 11 - CPU2 TIM1 timer clock enable
            #[inline(always)]
            pub fn tim1en(&mut self) -> TIM1EN_W {
                TIM1EN_W { w: self }
            }
        }
    }
    ///CPU2 APB3ENR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb3enr](c2apb3enr) module
    pub type C2APB3ENR = crate::Reg<u32, _C2APB3ENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB3ENR;
    ///`read()` method returns [c2apb3enr::R](c2apb3enr::R) reader structure
    impl crate::Readable for C2APB3ENR {}
    ///`write(|w| ..)` method takes [c2apb3enr::W](c2apb3enr::W) writer structure
    impl crate::Writable for C2APB3ENR {}
    ///CPU2 APB3ENR
    pub mod c2apb3enr {
        ///Reader of register C2APB3ENR
        pub type R = crate::R<u32, super::C2APB3ENR>;
        ///Writer for register C2APB3ENR
        pub type W = crate::W<u32, super::C2APB3ENR>;
        ///Register C2APB3ENR `reset()`'s with value 0
        impl crate::ResetValue for super::C2APB3ENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EN802`
        pub type EN802_R = crate::R<bool, bool>;
        ///Write proxy for field `EN802`
        pub struct EN802_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN802_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `BLEEN`
        pub type BLEEN_R = crate::R<bool, bool>;
        ///Write proxy for field `BLEEN`
        pub struct BLEEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BLEEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 1 - CPU2 802.15.4 interface clock enable
            #[inline(always)]
            pub fn en802(&self) -> EN802_R {
                EN802_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - CPU2 BLE interface clock enable
            #[inline(always)]
            pub fn bleen(&self) -> BLEEN_R {
                BLEEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 1 - CPU2 802.15.4 interface clock enable
            #[inline(always)]
            pub fn en802(&mut self) -> EN802_W {
                EN802_W { w: self }
            }
            ///Bit 0 - CPU2 BLE interface clock enable
            #[inline(always)]
            pub fn bleen(&mut self) -> BLEEN_W {
                BLEEN_W { w: self }
            }
        }
    }
    ///CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ahb1smenr](c2ahb1smenr) module
    pub type C2AHB1SMENR = crate::Reg<u32, _C2AHB1SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2AHB1SMENR;
    ///`read()` method returns [c2ahb1smenr::R](c2ahb1smenr::R) reader structure
    impl crate::Readable for C2AHB1SMENR {}
    ///`write(|w| ..)` method takes [c2ahb1smenr::W](c2ahb1smenr::W) writer structure
    impl crate::Writable for C2AHB1SMENR {}
    ///CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
    pub mod c2ahb1smenr {
        ///Reader of register C2AHB1SMENR
        pub type R = crate::R<u32, super::C2AHB1SMENR>;
        ///Writer for register C2AHB1SMENR
        pub type W = crate::W<u32, super::C2AHB1SMENR>;
        ///Register C2AHB1SMENR `reset()`'s with value 0x0001_1207
        impl crate::ResetValue for super::C2AHB1SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0001_1207
            }
        }
        ///Reader of field `TSCSMEN`
        pub type TSCSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TSCSMEN`
        pub struct TSCSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSCSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CRCSMEN`
        pub type CRCSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCSMEN`
        pub struct CRCSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `SRAM1SMEN`
        pub type SRAM1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM1SMEN`
        pub struct SRAM1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `DMAMUXSMEN`
        pub type DMAMUXSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAMUXSMEN`
        pub struct DMAMUXSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAMUXSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DMA2SMEN`
        pub type DMA2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2SMEN`
        pub struct DMA2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DMA1SMEN`
        pub type DMA1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1SMEN`
        pub struct DMA1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn tscsmen(&self) -> TSCSMEN_R {
                TSCSMEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 12 - CPU2 CRCSMEN
            #[inline(always)]
            pub fn crcsmen(&self) -> CRCSMEN_R {
                CRCSMEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 9 - SRAM1 interface clock enable during CPU1 CSleep mode
            #[inline(always)]
            pub fn sram1smen(&self) -> SRAM1SMEN_R {
                SRAM1SMEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 2 - CPU2 DMAMUX clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dmamuxsmen(&self) -> DMAMUXSMEN_R {
                DMAMUXSMEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - CPU2 DMA2 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma2smen(&self) -> DMA2SMEN_R {
                DMA2SMEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - CPU2 DMA1 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma1smen(&self) -> DMA1SMEN_R {
                DMA1SMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn tscsmen(&mut self) -> TSCSMEN_W {
                TSCSMEN_W { w: self }
            }
            ///Bit 12 - CPU2 CRCSMEN
            #[inline(always)]
            pub fn crcsmen(&mut self) -> CRCSMEN_W {
                CRCSMEN_W { w: self }
            }
            ///Bit 9 - SRAM1 interface clock enable during CPU1 CSleep mode
            #[inline(always)]
            pub fn sram1smen(&mut self) -> SRAM1SMEN_W {
                SRAM1SMEN_W { w: self }
            }
            ///Bit 2 - CPU2 DMAMUX clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dmamuxsmen(&mut self) -> DMAMUXSMEN_W {
                DMAMUXSMEN_W { w: self }
            }
            ///Bit 1 - CPU2 DMA2 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma2smen(&mut self) -> DMA2SMEN_W {
                DMA2SMEN_W { w: self }
            }
            ///Bit 0 - CPU2 DMA1 clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn dma1smen(&mut self) -> DMA1SMEN_W {
                DMA1SMEN_W { w: self }
            }
        }
    }
    ///CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ahb2smenr](c2ahb2smenr) module
    pub type C2AHB2SMENR = crate::Reg<u32, _C2AHB2SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2AHB2SMENR;
    ///`read()` method returns [c2ahb2smenr::R](c2ahb2smenr::R) reader structure
    impl crate::Readable for C2AHB2SMENR {}
    ///`write(|w| ..)` method takes [c2ahb2smenr::W](c2ahb2smenr::W) writer structure
    impl crate::Writable for C2AHB2SMENR {}
    ///CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
    pub mod c2ahb2smenr {
        ///Reader of register C2AHB2SMENR
        pub type R = crate::R<u32, super::C2AHB2SMENR>;
        ///Writer for register C2AHB2SMENR
        pub type W = crate::W<u32, super::C2AHB2SMENR>;
        ///Register C2AHB2SMENR `reset()`'s with value 0x0001_209f
        impl crate::ResetValue for super::C2AHB2SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0001_209f
            }
        }
        ///Reader of field `AES1SMEN`
        pub type AES1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES1SMEN`
        pub struct AES1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `ADCFSSMEN`
        pub type ADCFSSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ADCFSSMEN`
        pub struct ADCFSSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCFSSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `GPIOHSMEN`
        pub type GPIOHSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOHSMEN`
        pub struct GPIOHSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOHSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `GPIOESMEN`
        pub type GPIOESMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOESMEN`
        pub struct GPIOESMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOESMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `GPIODSMEN`
        pub type GPIODSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIODSMEN`
        pub struct GPIODSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIODSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `GPIOCSMEN`
        pub type GPIOCSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOCSMEN`
        pub struct GPIOCSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOCSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `GPIOBSMEN`
        pub type GPIOBSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOBSMEN`
        pub struct GPIOBSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOBSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `GPIOASMEN`
        pub type GPIOASMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `GPIOASMEN`
        pub struct GPIOASMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GPIOASMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - CPU2 AES1 accelerator clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn aes1smen(&self) -> AES1SMEN_R {
                AES1SMEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 13 - CPU2 ADC clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn adcfssmen(&self) -> ADCFSSMEN_R {
                ADCFSSMEN_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 7 - CPU2 IO port H clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiohsmen(&self) -> GPIOHSMEN_R {
                GPIOHSMEN_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 4 - CPU2 IO port E clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioesmen(&self) -> GPIOESMEN_R {
                GPIOESMEN_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - CPU2 IO port D clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiodsmen(&self) -> GPIODSMEN_R {
                GPIODSMEN_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - CPU2 IO port C clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiocsmen(&self) -> GPIOCSMEN_R {
                GPIOCSMEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - CPU2 IO port B clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiobsmen(&self) -> GPIOBSMEN_R {
                GPIOBSMEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - CPU2 IO port A clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioasmen(&self) -> GPIOASMEN_R {
                GPIOASMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - CPU2 AES1 accelerator clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn aes1smen(&mut self) -> AES1SMEN_W {
                AES1SMEN_W { w: self }
            }
            ///Bit 13 - CPU2 ADC clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn adcfssmen(&mut self) -> ADCFSSMEN_W {
                ADCFSSMEN_W { w: self }
            }
            ///Bit 7 - CPU2 IO port H clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiohsmen(&mut self) -> GPIOHSMEN_W {
                GPIOHSMEN_W { w: self }
            }
            ///Bit 4 - CPU2 IO port E clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioesmen(&mut self) -> GPIOESMEN_W {
                GPIOESMEN_W { w: self }
            }
            ///Bit 3 - CPU2 IO port D clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiodsmen(&mut self) -> GPIODSMEN_W {
                GPIODSMEN_W { w: self }
            }
            ///Bit 2 - CPU2 IO port C clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiocsmen(&mut self) -> GPIOCSMEN_W {
                GPIOCSMEN_W { w: self }
            }
            ///Bit 1 - CPU2 IO port B clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpiobsmen(&mut self) -> GPIOBSMEN_W {
                GPIOBSMEN_W { w: self }
            }
            ///Bit 0 - CPU2 IO port A clocks enable during Sleep and Stop modes
            #[inline(always)]
            pub fn gpioasmen(&mut self) -> GPIOASMEN_W {
                GPIOASMEN_W { w: self }
            }
        }
    }
    ///CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ahb3smenr](c2ahb3smenr) module
    pub type C2AHB3SMENR = crate::Reg<u32, _C2AHB3SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2AHB3SMENR;
    ///`read()` method returns [c2ahb3smenr::R](c2ahb3smenr::R) reader structure
    impl crate::Readable for C2AHB3SMENR {}
    ///`write(|w| ..)` method takes [c2ahb3smenr::W](c2ahb3smenr::W) writer structure
    impl crate::Writable for C2AHB3SMENR {}
    ///CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
    pub mod c2ahb3smenr {
        ///Reader of register C2AHB3SMENR
        pub type R = crate::R<u32, super::C2AHB3SMENR>;
        ///Writer for register C2AHB3SMENR
        pub type W = crate::W<u32, super::C2AHB3SMENR>;
        ///Register C2AHB3SMENR `reset()`'s with value 0x0307_0000
        impl crate::ResetValue for super::C2AHB3SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0307_0000
            }
        }
        ///Reader of field `FLASHSMEN`
        pub type FLASHSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `FLASHSMEN`
        pub struct FLASHSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FLASHSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `SRAM2SMEN`
        pub type SRAM2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM2SMEN`
        pub struct SRAM2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `RNGSMEN`
        pub type RNGSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RNGSMEN`
        pub struct RNGSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNGSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `AES2SMEN`
        pub type AES2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `AES2SMEN`
        pub struct AES2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `PKASMEN`
        pub type PKASMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PKASMEN`
        pub struct PKASMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PKASMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        impl R {
            ///Bit 25 - Flash interface clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn flashsmen(&self) -> FLASHSMEN_R {
                FLASHSMEN_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn sram2smen(&self) -> SRAM2SMEN_R {
                SRAM2SMEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 18 - True RNG clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn rngsmen(&self) -> RNGSMEN_R {
                RNGSMEN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - AES2 accelerator clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn aes2smen(&self) -> AES2SMEN_R {
                AES2SMEN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - PKA accelerator clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn pkasmen(&self) -> PKASMEN_R {
                PKASMEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 25 - Flash interface clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn flashsmen(&mut self) -> FLASHSMEN_W {
                FLASHSMEN_W { w: self }
            }
            ///Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn sram2smen(&mut self) -> SRAM2SMEN_W {
                SRAM2SMEN_W { w: self }
            }
            ///Bit 18 - True RNG clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn rngsmen(&mut self) -> RNGSMEN_W {
                RNGSMEN_W { w: self }
            }
            ///Bit 17 - AES2 accelerator clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn aes2smen(&mut self) -> AES2SMEN_W {
                AES2SMEN_W { w: self }
            }
            ///Bit 16 - PKA accelerator clocks enable during CPU2 sleep modes
            #[inline(always)]
            pub fn pkasmen(&mut self) -> PKASMEN_W {
                PKASMEN_W { w: self }
            }
        }
    }
    ///CPU2 APB1SMENR1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb1smenr1](c2apb1smenr1) module
    pub type C2APB1SMENR1 = crate::Reg<u32, _C2APB1SMENR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB1SMENR1;
    ///`read()` method returns [c2apb1smenr1::R](c2apb1smenr1::R) reader structure
    impl crate::Readable for C2APB1SMENR1 {}
    ///`write(|w| ..)` method takes [c2apb1smenr1::W](c2apb1smenr1::W) writer structure
    impl crate::Writable for C2APB1SMENR1 {}
    ///CPU2 APB1SMENR1
    pub mod c2apb1smenr1 {
        ///Reader of register C2APB1SMENR1
        pub type R = crate::R<u32, super::C2APB1SMENR1>;
        ///Writer for register C2APB1SMENR1
        pub type W = crate::W<u32, super::C2APB1SMENR1>;
        ///Register C2APB1SMENR1 `reset()`'s with value 0x85a0_4601
        impl crate::ResetValue for super::C2APB1SMENR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x85a0_4601
            }
        }
        ///Reader of field `LPTIM1SMEN`
        pub type LPTIM1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM1SMEN`
        pub struct LPTIM1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `USBSMEN`
        pub type USBSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `USBSMEN`
        pub struct USBSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USBSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `CRSMEN`
        pub type CRSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRSMEN`
        pub struct CRSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `I2C3SMEN`
        pub type I2C3SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C3SMEN`
        pub struct I2C3SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C3SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `I2C1SMEN`
        pub type I2C1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C1SMEN`
        pub struct I2C1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `SPI2SMEN`
        pub type SPI2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI2SMEN`
        pub struct SPI2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `RTCAPBSMEN`
        pub type RTCAPBSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCAPBSMEN`
        pub struct RTCAPBSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCAPBSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LCDSMEN`
        pub type LCDSMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LCDSMEN`
        pub struct LCDSMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCDSMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `TIM2SMEN`
        pub type TIM2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM2SMEN`
        pub struct TIM2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - Low power timer 1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lptim1smen(&self) -> LPTIM1SMEN_R {
                LPTIM1SMEN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 26 - USB FS clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn usbsmen(&self) -> USBSMEN_R {
                USBSMEN_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 24 - CRS clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn crsmen(&self) -> CRSMEN_R {
                CRSMEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - I2C3 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn i2c3smen(&self) -> I2C3SMEN_R {
                I2C3SMEN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 21 - I2C1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn i2c1smen(&self) -> I2C1SMEN_R {
                I2C1SMEN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 14 - SPI2 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn spi2smen(&self) -> SPI2SMEN_R {
                SPI2SMEN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 10 - RTC APB clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R {
                RTCAPBSMEN_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - LCD clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lcdsmen(&self) -> LCDSMEN_R {
                LCDSMEN_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 0 - TIM2 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim2smen(&self) -> TIM2SMEN_R {
                TIM2SMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - Low power timer 1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W {
                LPTIM1SMEN_W { w: self }
            }
            ///Bit 26 - USB FS clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn usbsmen(&mut self) -> USBSMEN_W {
                USBSMEN_W { w: self }
            }
            ///Bit 24 - CRS clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn crsmen(&mut self) -> CRSMEN_W {
                CRSMEN_W { w: self }
            }
            ///Bit 23 - I2C3 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn i2c3smen(&mut self) -> I2C3SMEN_W {
                I2C3SMEN_W { w: self }
            }
            ///Bit 21 - I2C1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn i2c1smen(&mut self) -> I2C1SMEN_W {
                I2C1SMEN_W { w: self }
            }
            ///Bit 14 - SPI2 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn spi2smen(&mut self) -> SPI2SMEN_W {
                SPI2SMEN_W { w: self }
            }
            ///Bit 10 - RTC APB clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W {
                RTCAPBSMEN_W { w: self }
            }
            ///Bit 9 - LCD clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lcdsmen(&mut self) -> LCDSMEN_W {
                LCDSMEN_W { w: self }
            }
            ///Bit 0 - TIM2 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim2smen(&mut self) -> TIM2SMEN_W {
                TIM2SMEN_W { w: self }
            }
        }
    }
    ///CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb1smenr2](c2apb1smenr2) module
    pub type C2APB1SMENR2 = crate::Reg<u32, _C2APB1SMENR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB1SMENR2;
    ///`read()` method returns [c2apb1smenr2::R](c2apb1smenr2::R) reader structure
    impl crate::Readable for C2APB1SMENR2 {}
    ///`write(|w| ..)` method takes [c2apb1smenr2::W](c2apb1smenr2::W) writer structure
    impl crate::Writable for C2APB1SMENR2 {}
    ///CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
    pub mod c2apb1smenr2 {
        ///Reader of register C2APB1SMENR2
        pub type R = crate::R<u32, super::C2APB1SMENR2>;
        ///Writer for register C2APB1SMENR2
        pub type W = crate::W<u32, super::C2APB1SMENR2>;
        ///Register C2APB1SMENR2 `reset()`'s with value 0x21
        impl crate::ResetValue for super::C2APB1SMENR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x21
            }
        }
        ///Reader of field `LPTIM2SMEN`
        pub type LPTIM2SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPTIM2SMEN`
        pub struct LPTIM2SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPTIM2SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LPUART1SMEN`
        pub type LPUART1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPUART1SMEN`
        pub struct LPUART1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPUART1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 5 - Low power timer 2 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lptim2smen(&self) -> LPTIM2SMEN_R {
                LPTIM2SMEN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 0 - Low power UART 1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lpuart1smen(&self) -> LPUART1SMEN_R {
                LPUART1SMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 5 - Low power timer 2 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W {
                LPTIM2SMEN_W { w: self }
            }
            ///Bit 0 - Low power UART 1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W {
                LPUART1SMEN_W { w: self }
            }
        }
    }
    ///CPU2 APB2SMENR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb2smenr](c2apb2smenr) module
    pub type C2APB2SMENR = crate::Reg<u32, _C2APB2SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB2SMENR;
    ///`read()` method returns [c2apb2smenr::R](c2apb2smenr::R) reader structure
    impl crate::Readable for C2APB2SMENR {}
    ///`write(|w| ..)` method takes [c2apb2smenr::W](c2apb2smenr::W) writer structure
    impl crate::Writable for C2APB2SMENR {}
    ///CPU2 APB2SMENR
    pub mod c2apb2smenr {
        ///Reader of register C2APB2SMENR
        pub type R = crate::R<u32, super::C2APB2SMENR>;
        ///Writer for register C2APB2SMENR
        pub type W = crate::W<u32, super::C2APB2SMENR>;
        ///Register C2APB2SMENR `reset()`'s with value 0x0026_5800
        impl crate::ResetValue for super::C2APB2SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0026_5800
            }
        }
        ///Reader of field `SAI1SMEN`
        pub type SAI1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SAI1SMEN`
        pub struct SAI1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAI1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `TIM17SMEN`
        pub type TIM17SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM17SMEN`
        pub struct TIM17SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM17SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TIM16SMEN`
        pub type TIM16SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM16SMEN`
        pub struct TIM16SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM16SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `USART1SMEN`
        pub type USART1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `USART1SMEN`
        pub struct USART1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USART1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `SPI1SMEN`
        pub type SPI1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SPI1SMEN`
        pub struct SPI1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPI1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TIM1SMEN`
        pub type TIM1SMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM1SMEN`
        pub struct TIM1SMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM1SMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 21 - SAI1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn sai1smen(&self) -> SAI1SMEN_R {
                SAI1SMEN_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 18 - TIM17 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim17smen(&self) -> TIM17SMEN_R {
                TIM17SMEN_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - TIM16 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim16smen(&self) -> TIM16SMEN_R {
                TIM16SMEN_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 14 - USART1clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn usart1smen(&self) -> USART1SMEN_R {
                USART1SMEN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 12 - SPI1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn spi1smen(&self) -> SPI1SMEN_R {
                SPI1SMEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - TIM1 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim1smen(&self) -> TIM1SMEN_R {
                TIM1SMEN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 21 - SAI1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn sai1smen(&mut self) -> SAI1SMEN_W {
                SAI1SMEN_W { w: self }
            }
            ///Bit 18 - TIM17 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim17smen(&mut self) -> TIM17SMEN_W {
                TIM17SMEN_W { w: self }
            }
            ///Bit 17 - TIM16 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim16smen(&mut self) -> TIM16SMEN_W {
                TIM16SMEN_W { w: self }
            }
            ///Bit 14 - USART1clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn usart1smen(&mut self) -> USART1SMEN_W {
                USART1SMEN_W { w: self }
            }
            ///Bit 12 - SPI1 clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn spi1smen(&mut self) -> SPI1SMEN_W {
                SPI1SMEN_W { w: self }
            }
            ///Bit 11 - TIM1 timer clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn tim1smen(&mut self) -> TIM1SMEN_W {
                TIM1SMEN_W { w: self }
            }
        }
    }
    ///CPU2 APB3SMENR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb3smenr](c2apb3smenr) module
    pub type C2APB3SMENR = crate::Reg<u32, _C2APB3SMENR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB3SMENR;
    ///`read()` method returns [c2apb3smenr::R](c2apb3smenr::R) reader structure
    impl crate::Readable for C2APB3SMENR {}
    ///`write(|w| ..)` method takes [c2apb3smenr::W](c2apb3smenr::W) writer structure
    impl crate::Writable for C2APB3SMENR {}
    ///CPU2 APB3SMENR
    pub mod c2apb3smenr {
        ///Reader of register C2APB3SMENR
        pub type R = crate::R<u32, super::C2APB3SMENR>;
        ///Writer for register C2APB3SMENR
        pub type W = crate::W<u32, super::C2APB3SMENR>;
        ///Register C2APB3SMENR `reset()`'s with value 0x03
        impl crate::ResetValue for super::C2APB3SMENR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x03
            }
        }
        ///Reader of field `SMEN802`
        pub type SMEN802_R = crate::R<bool, bool>;
        ///Write proxy for field `SMEN802`
        pub struct SMEN802_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMEN802_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `BLESMEN`
        pub type BLESMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `BLESMEN`
        pub struct BLESMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BLESMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 1 - 802.15.4 interface clocks enable during CPU2 Sleep modes
            #[inline(always)]
            pub fn smen802(&self) -> SMEN802_R {
                SMEN802_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - BLE interface clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn blesmen(&self) -> BLESMEN_R {
                BLESMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 1 - 802.15.4 interface clocks enable during CPU2 Sleep modes
            #[inline(always)]
            pub fn smen802(&mut self) -> SMEN802_W {
                SMEN802_W { w: self }
            }
            ///Bit 0 - BLE interface clocks enable during CPU2 Sleep mode
            #[inline(always)]
            pub fn blesmen(&mut self) -> BLESMEN_W {
                BLESMEN_W { w: self }
            }
        }
    }
}
///Power control
pub struct PWR {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PWR {}
impl PWR {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const pwr::RegisterBlock {
        0x5800_0400 as *const _
    }
}
impl Deref for PWR {
    type Target = pwr::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*PWR::ptr() }
    }
}
///Power control
pub mod pwr {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Power control register 1
        pub cr1: CR1,
        ///0x04 - Power control register 2
        pub cr2: CR2,
        ///0x08 - Power control register 3
        pub cr3: CR3,
        ///0x0c - Power control register 4
        pub cr4: CR4,
        ///0x10 - Power status register 1
        pub sr1: SR1,
        ///0x14 - Power status register 2
        pub sr2: SR2,
        ///0x18 - Power status clear register
        pub scr: SCR,
        ///0x1c - Power control register 5
        pub cr5: CR5,
        ///0x20 - Power Port A pull-up control register
        pub pucra: PUCRA,
        ///0x24 - Power Port A pull-down control register
        pub pdcra: PDCRA,
        ///0x28 - Power Port B pull-up control register
        pub pucrb: PUCRB,
        ///0x2c - Power Port B pull-down control register
        pub pdcrb: PDCRB,
        ///0x30 - Power Port C pull-up control register
        pub pucrc: PUCRC,
        ///0x34 - Power Port C pull-down control register
        pub pdcrc: PDCRC,
        ///0x38 - Power Port D pull-up control register
        pub pucrd: PUCRD,
        ///0x3c - Power Port D pull-down control register
        pub pdcrd: PDCRD,
        ///0x40 - Power Port E pull-up control register
        pub pucre: PUCRE,
        ///0x44 - Power Port E pull-down control register
        pub pdcre: PDCRE,
        _reserved18: [u8; 16usize],
        ///0x58 - Power Port H pull-up control register
        pub pucrh: PUCRH,
        ///0x5c - Power Port H pull-down control register
        pub pdcrh: PDCRH,
        _reserved20: [u8; 32usize],
        ///0x80 - CPU2 Power control register 1
        pub c2cr1: C2CR1,
        ///0x84 - CPU2 Power control register 3
        pub c2cr3: C2CR3,
        ///0x88 - Power status clear register
        pub extscr: EXTSCR,
    }
    ///Power control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///Power control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0x0200
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0200
            }
        }
        ///Reader of field `LPR`
        pub type LPR_R = crate::R<bool, bool>;
        ///Write proxy for field `LPR`
        pub struct LPR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `VOS`
        pub type VOS_R = crate::R<u8, u8>;
        ///Write proxy for field `VOS`
        pub struct VOS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> VOS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u32) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `DBP`
        pub type DBP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBP`
        pub struct DBP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `FPDS`
        pub type FPDS_R = crate::R<bool, bool>;
        ///Write proxy for field `FPDS`
        pub struct FPDS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FPDS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `FPDR`
        pub type FPDR_R = crate::R<bool, bool>;
        ///Write proxy for field `FPDR`
        pub struct FPDR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FPDR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `LPMS`
        pub type LPMS_R = crate::R<u8, u8>;
        ///Write proxy for field `LPMS`
        pub struct LPMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Low-power run
            #[inline(always)]
            pub fn lpr(&self) -> LPR_R {
                LPR_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 9:10 - Voltage scaling range selection
            #[inline(always)]
            pub fn vos(&self) -> VOS_R {
                VOS_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 8 - Disable backup domain write protection
            #[inline(always)]
            pub fn dbp(&self) -> DBP_R {
                DBP_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 5 - Flash power down mode during LPsSleep for CPU1
            #[inline(always)]
            pub fn fpds(&self) -> FPDS_R {
                FPDS_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Flash power down mode during LPRun for CPU1
            #[inline(always)]
            pub fn fpdr(&self) -> FPDR_R {
                FPDR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bits 0:2 - Low-power mode selection for CPU1
            #[inline(always)]
            pub fn lpms(&self) -> LPMS_R {
                LPMS_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bit 14 - Low-power run
            #[inline(always)]
            pub fn lpr(&mut self) -> LPR_W {
                LPR_W { w: self }
            }
            ///Bits 9:10 - Voltage scaling range selection
            #[inline(always)]
            pub fn vos(&mut self) -> VOS_W {
                VOS_W { w: self }
            }
            ///Bit 8 - Disable backup domain write protection
            #[inline(always)]
            pub fn dbp(&mut self) -> DBP_W {
                DBP_W { w: self }
            }
            ///Bit 5 - Flash power down mode during LPsSleep for CPU1
            #[inline(always)]
            pub fn fpds(&mut self) -> FPDS_W {
                FPDS_W { w: self }
            }
            ///Bit 4 - Flash power down mode during LPRun for CPU1
            #[inline(always)]
            pub fn fpdr(&mut self) -> FPDR_W {
                FPDR_W { w: self }
            }
            ///Bits 0:2 - Low-power mode selection for CPU1
            #[inline(always)]
            pub fn lpms(&mut self) -> LPMS_W {
                LPMS_W { w: self }
            }
        }
    }
    ///Power control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///Power control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `USV`
        pub type USV_R = crate::R<bool, bool>;
        ///Write proxy for field `USV`
        pub struct USV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> USV_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PVME3`
        pub type PVME3_R = crate::R<bool, bool>;
        ///Write proxy for field `PVME3`
        pub struct PVME3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVME3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PVME1`
        pub type PVME1_R = crate::R<bool, bool>;
        ///Write proxy for field `PVME1`
        pub struct PVME1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVME1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PLS`
        pub type PLS_R = crate::R<u8, u8>;
        ///Write proxy for field `PLS`
        pub struct PLS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PLS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 1)) | (((value as u32) & 0x07) << 1);
                self.w
            }
        }
        ///Reader of field `PVDE`
        pub type PVDE_R = crate::R<bool, bool>;
        ///Write proxy for field `PVDE`
        pub struct PVDE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVDE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 10 - VDDUSB USB supply valid
            #[inline(always)]
            pub fn usv(&self) -> USV_R {
                USV_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
            #[inline(always)]
            pub fn pvme3(&self) -> PVME3_R {
                PVME3_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
            #[inline(always)]
            pub fn pvme1(&self) -> PVME1_R {
                PVME1_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bits 1:3 - Power voltage detector level selection
            #[inline(always)]
            pub fn pls(&self) -> PLS_R {
                PLS_R::new(((self.bits >> 1) & 0x07) as u8)
            }
            ///Bit 0 - Power voltage detector enable
            #[inline(always)]
            pub fn pvde(&self) -> PVDE_R {
                PVDE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 10 - VDDUSB USB supply valid
            #[inline(always)]
            pub fn usv(&mut self) -> USV_W {
                USV_W { w: self }
            }
            ///Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
            #[inline(always)]
            pub fn pvme3(&mut self) -> PVME3_W {
                PVME3_W { w: self }
            }
            ///Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
            #[inline(always)]
            pub fn pvme1(&mut self) -> PVME1_W {
                PVME1_W { w: self }
            }
            ///Bits 1:3 - Power voltage detector level selection
            #[inline(always)]
            pub fn pls(&mut self) -> PLS_W {
                PLS_W { w: self }
            }
            ///Bit 0 - Power voltage detector enable
            #[inline(always)]
            pub fn pvde(&mut self) -> PVDE_W {
                PVDE_W { w: self }
            }
        }
    }
    ///Power control register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr3](cr3) module
    pub type CR3 = crate::Reg<u32, _CR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR3;
    ///`read()` method returns [cr3::R](cr3::R) reader structure
    impl crate::Readable for CR3 {}
    ///`write(|w| ..)` method takes [cr3::W](cr3::W) writer structure
    impl crate::Writable for CR3 {}
    ///Power control register 3
    pub mod cr3 {
        ///Reader of register CR3
        pub type R = crate::R<u32, super::CR3>;
        ///Writer for register CR3
        pub type W = crate::W<u32, super::CR3>;
        ///Register CR3 `reset()`'s with value 0x8000
        impl crate::ResetValue for super::CR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x8000
            }
        }
        ///Reader of field `EIWUL`
        pub type EIWUL_R = crate::R<bool, bool>;
        ///Write proxy for field `EIWUL`
        pub struct EIWUL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EIWUL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `EC2H`
        pub type EC2H_R = crate::R<bool, bool>;
        ///Write proxy for field `EC2H`
        pub struct EC2H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EC2H_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `E802A`
        pub type E802A_R = crate::R<bool, bool>;
        ///Write proxy for field `E802A`
        pub struct E802A_W<'a> {
            w: &'a mut W,
        }
        impl<'a> E802A_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `EBLEA`
        pub type EBLEA_R = crate::R<bool, bool>;
        ///Write proxy for field `EBLEA`
        pub struct EBLEA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EBLEA_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ECRPE`
        pub type ECRPE_R = crate::R<bool, bool>;
        ///Write proxy for field `ECRPE`
        pub struct ECRPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ECRPE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `APC`
        pub type APC_R = crate::R<bool, bool>;
        ///Write proxy for field `APC`
        pub struct APC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> APC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `RRS`
        pub type RRS_R = crate::R<bool, bool>;
        ///Write proxy for field `RRS`
        pub struct RRS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RRS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `EBORHSDFB`
        pub type EBORHSDFB_R = crate::R<bool, bool>;
        ///Write proxy for field `EBORHSDFB`
        pub struct EBORHSDFB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EBORHSDFB_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EWUP5`
        pub type EWUP5_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP5`
        pub struct EWUP5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `EWUP4`
        pub type EWUP4_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP4`
        pub struct EWUP4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `EWUP3`
        pub type EWUP3_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP3`
        pub struct EWUP3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `EWUP2`
        pub type EWUP2_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP2`
        pub struct EWUP2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EWUP1`
        pub type EWUP1_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP1`
        pub struct EWUP1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Enable internal wakeup line for CPU1
            #[inline(always)]
            pub fn eiwul(&self) -> EIWUL_R {
                EIWUL_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Enable CPU2 Hold interrupt for CPU1
            #[inline(always)]
            pub fn ec2h(&self) -> EC2H_R {
                EC2H_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Enable end of activity interrupt for CPU1
            #[inline(always)]
            pub fn e802a(&self) -> E802A_R {
                E802A_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 11 - Enable BLE end of activity interrupt for CPU1
            #[inline(always)]
            pub fn eblea(&self) -> EBLEA_R {
                EBLEA_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Enable critical radio phase end of activity interrupt for CPU1
            #[inline(always)]
            pub fn ecrpe(&self) -> ECRPE_R {
                ECRPE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 10 - Apply pull-up and pull-down configuration
            #[inline(always)]
            pub fn apc(&self) -> APC_R {
                APC_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - SRAM2a retention in Standby mode
            #[inline(always)]
            pub fn rrs(&self) -> RRS_R {
                RRS_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Enable BORH and Step Down counverter forced in Bypass interrups for CPU1
            #[inline(always)]
            pub fn eborhsdfb(&self) -> EBORHSDFB_R {
                EBORHSDFB_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 4 - Enable Wakeup pin WKUP5
            #[inline(always)]
            pub fn ewup5(&self) -> EWUP5_R {
                EWUP5_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Enable Wakeup pin WKUP4
            #[inline(always)]
            pub fn ewup4(&self) -> EWUP4_R {
                EWUP4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Enable Wakeup pin WKUP3
            #[inline(always)]
            pub fn ewup3(&self) -> EWUP3_R {
                EWUP3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Enable Wakeup pin WKUP2
            #[inline(always)]
            pub fn ewup2(&self) -> EWUP2_R {
                EWUP2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Enable Wakeup pin WKUP1
            #[inline(always)]
            pub fn ewup1(&self) -> EWUP1_R {
                EWUP1_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Enable internal wakeup line for CPU1
            #[inline(always)]
            pub fn eiwul(&mut self) -> EIWUL_W {
                EIWUL_W { w: self }
            }
            ///Bit 14 - Enable CPU2 Hold interrupt for CPU1
            #[inline(always)]
            pub fn ec2h(&mut self) -> EC2H_W {
                EC2H_W { w: self }
            }
            ///Bit 13 - Enable end of activity interrupt for CPU1
            #[inline(always)]
            pub fn e802a(&mut self) -> E802A_W {
                E802A_W { w: self }
            }
            ///Bit 11 - Enable BLE end of activity interrupt for CPU1
            #[inline(always)]
            pub fn eblea(&mut self) -> EBLEA_W {
                EBLEA_W { w: self }
            }
            ///Bit 12 - Enable critical radio phase end of activity interrupt for CPU1
            #[inline(always)]
            pub fn ecrpe(&mut self) -> ECRPE_W {
                ECRPE_W { w: self }
            }
            ///Bit 10 - Apply pull-up and pull-down configuration
            #[inline(always)]
            pub fn apc(&mut self) -> APC_W {
                APC_W { w: self }
            }
            ///Bit 9 - SRAM2a retention in Standby mode
            #[inline(always)]
            pub fn rrs(&mut self) -> RRS_W {
                RRS_W { w: self }
            }
            ///Bit 8 - Enable BORH and Step Down counverter forced in Bypass interrups for CPU1
            #[inline(always)]
            pub fn eborhsdfb(&mut self) -> EBORHSDFB_W {
                EBORHSDFB_W { w: self }
            }
            ///Bit 4 - Enable Wakeup pin WKUP5
            #[inline(always)]
            pub fn ewup5(&mut self) -> EWUP5_W {
                EWUP5_W { w: self }
            }
            ///Bit 3 - Enable Wakeup pin WKUP4
            #[inline(always)]
            pub fn ewup4(&mut self) -> EWUP4_W {
                EWUP4_W { w: self }
            }
            ///Bit 2 - Enable Wakeup pin WKUP3
            #[inline(always)]
            pub fn ewup3(&mut self) -> EWUP3_W {
                EWUP3_W { w: self }
            }
            ///Bit 1 - Enable Wakeup pin WKUP2
            #[inline(always)]
            pub fn ewup2(&mut self) -> EWUP2_W {
                EWUP2_W { w: self }
            }
            ///Bit 0 - Enable Wakeup pin WKUP1
            #[inline(always)]
            pub fn ewup1(&mut self) -> EWUP1_W {
                EWUP1_W { w: self }
            }
        }
    }
    ///Power control register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr4](cr4) module
    pub type CR4 = crate::Reg<u32, _CR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR4;
    ///`read()` method returns [cr4::R](cr4::R) reader structure
    impl crate::Readable for CR4 {}
    ///`write(|w| ..)` method takes [cr4::W](cr4::W) writer structure
    impl crate::Writable for CR4 {}
    ///Power control register 4
    pub mod cr4 {
        ///Reader of register CR4
        pub type R = crate::R<u32, super::CR4>;
        ///Writer for register CR4
        pub type W = crate::W<u32, super::CR4>;
        ///Register CR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `C2BOOT`
        pub type C2BOOT_R = crate::R<bool, bool>;
        ///Write proxy for field `C2BOOT`
        pub struct C2BOOT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C2BOOT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `VBRS`
        pub type VBRS_R = crate::R<bool, bool>;
        ///Write proxy for field `VBRS`
        pub struct VBRS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> VBRS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `VBE`
        pub type VBE_R = crate::R<bool, bool>;
        ///Write proxy for field `VBE`
        pub struct VBE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> VBE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `WP5`
        pub type WP5_R = crate::R<bool, bool>;
        ///Write proxy for field `WP5`
        pub struct WP5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WP5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `WP4`
        pub type WP4_R = crate::R<bool, bool>;
        ///Write proxy for field `WP4`
        pub struct WP4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WP4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `WP3`
        pub type WP3_R = crate::R<bool, bool>;
        ///Write proxy for field `WP3`
        pub struct WP3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WP3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `WP2`
        pub type WP2_R = crate::R<bool, bool>;
        ///Write proxy for field `WP2`
        pub struct WP2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WP2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `WP1`
        pub type WP1_R = crate::R<bool, bool>;
        ///Write proxy for field `WP1`
        pub struct WP1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WP1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - BOOT CPU2 after reset or wakeup from Stop or Standby modes
            #[inline(always)]
            pub fn c2boot(&self) -> C2BOOT_R {
                C2BOOT_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 9 - VBAT battery charging resistor selection
            #[inline(always)]
            pub fn vbrs(&self) -> VBRS_R {
                VBRS_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - VBAT battery charging enable
            #[inline(always)]
            pub fn vbe(&self) -> VBE_R {
                VBE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 4 - Wakeup pin WKUP5 polarity
            #[inline(always)]
            pub fn wp5(&self) -> WP5_R {
                WP5_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Wakeup pin WKUP4 polarity
            #[inline(always)]
            pub fn wp4(&self) -> WP4_R {
                WP4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Wakeup pin WKUP3 polarity
            #[inline(always)]
            pub fn wp3(&self) -> WP3_R {
                WP3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Wakeup pin WKUP2 polarity
            #[inline(always)]
            pub fn wp2(&self) -> WP2_R {
                WP2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Wakeup pin WKUP1 polarity
            #[inline(always)]
            pub fn wp1(&self) -> WP1_R {
                WP1_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - BOOT CPU2 after reset or wakeup from Stop or Standby modes
            #[inline(always)]
            pub fn c2boot(&mut self) -> C2BOOT_W {
                C2BOOT_W { w: self }
            }
            ///Bit 9 - VBAT battery charging resistor selection
            #[inline(always)]
            pub fn vbrs(&mut self) -> VBRS_W {
                VBRS_W { w: self }
            }
            ///Bit 8 - VBAT battery charging enable
            #[inline(always)]
            pub fn vbe(&mut self) -> VBE_W {
                VBE_W { w: self }
            }
            ///Bit 4 - Wakeup pin WKUP5 polarity
            #[inline(always)]
            pub fn wp5(&mut self) -> WP5_W {
                WP5_W { w: self }
            }
            ///Bit 3 - Wakeup pin WKUP4 polarity
            #[inline(always)]
            pub fn wp4(&mut self) -> WP4_W {
                WP4_W { w: self }
            }
            ///Bit 2 - Wakeup pin WKUP3 polarity
            #[inline(always)]
            pub fn wp3(&mut self) -> WP3_W {
                WP3_W { w: self }
            }
            ///Bit 1 - Wakeup pin WKUP2 polarity
            #[inline(always)]
            pub fn wp2(&mut self) -> WP2_W {
                WP2_W { w: self }
            }
            ///Bit 0 - Wakeup pin WKUP1 polarity
            #[inline(always)]
            pub fn wp1(&mut self) -> WP1_W {
                WP1_W { w: self }
            }
        }
    }
    ///Power status register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr1](sr1) module
    pub type SR1 = crate::Reg<u32, _SR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR1;
    ///`read()` method returns [sr1::R](sr1::R) reader structure
    impl crate::Readable for SR1 {}
    ///Power status register 1
    pub mod sr1 {
        ///Reader of register SR1
        pub type R = crate::R<u32, super::SR1>;
        ///Reader of field `WUFI`
        pub type WUFI_R = crate::R<bool, bool>;
        ///Reader of field `C2HF`
        pub type C2HF_R = crate::R<bool, bool>;
        ///Reader of field `AF802`
        pub type AF802_R = crate::R<bool, bool>;
        ///Reader of field `BLEAF`
        pub type BLEAF_R = crate::R<bool, bool>;
        ///Reader of field `CRPEF`
        pub type CRPEF_R = crate::R<bool, bool>;
        ///Reader of field `_802WUF`
        pub type _802WUF_R = crate::R<bool, bool>;
        ///Reader of field `BLEWUF`
        pub type BLEWUF_R = crate::R<bool, bool>;
        ///Reader of field `BORHF`
        pub type BORHF_R = crate::R<bool, bool>;
        ///Reader of field `SDFBF`
        pub type SDFBF_R = crate::R<bool, bool>;
        ///Reader of field `CWUF5`
        pub type CWUF5_R = crate::R<bool, bool>;
        ///Reader of field `CWUF4`
        pub type CWUF4_R = crate::R<bool, bool>;
        ///Reader of field `CWUF3`
        pub type CWUF3_R = crate::R<bool, bool>;
        ///Reader of field `CWUF2`
        pub type CWUF2_R = crate::R<bool, bool>;
        ///Reader of field `CWUF1`
        pub type CWUF1_R = crate::R<bool, bool>;
        impl R {
            ///Bit 15 - Internal Wakeup interrupt flag
            #[inline(always)]
            pub fn wufi(&self) -> WUFI_R {
                WUFI_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - CPU2 Hold interrupt flag
            #[inline(always)]
            pub fn c2hf(&self) -> C2HF_R {
                C2HF_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - 802.15.4 end of activity interrupt flag
            #[inline(always)]
            pub fn af802(&self) -> AF802_R {
                AF802_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - BLE end of activity interrupt flag
            #[inline(always)]
            pub fn bleaf(&self) -> BLEAF_R {
                BLEAF_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Enable critical radio phase end of activity interrupt flag
            #[inline(always)]
            pub fn crpef(&self) -> CRPEF_R {
                CRPEF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - 802.15.4 wakeup interrupt flag
            #[inline(always)]
            pub fn _802wuf(&self) -> _802WUF_R {
                _802WUF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - BLE wakeup interrupt flag
            #[inline(always)]
            pub fn blewuf(&self) -> BLEWUF_R {
                BLEWUF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - BORH interrupt flag
            #[inline(always)]
            pub fn borhf(&self) -> BORHF_R {
                BORHF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Step Down converter forced in Bypass interrupt flag
            #[inline(always)]
            pub fn sdfbf(&self) -> SDFBF_R {
                SDFBF_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 4 - Wakeup flag 5
            #[inline(always)]
            pub fn cwuf5(&self) -> CWUF5_R {
                CWUF5_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Wakeup flag 4
            #[inline(always)]
            pub fn cwuf4(&self) -> CWUF4_R {
                CWUF4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Wakeup flag 3
            #[inline(always)]
            pub fn cwuf3(&self) -> CWUF3_R {
                CWUF3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Wakeup flag 2
            #[inline(always)]
            pub fn cwuf2(&self) -> CWUF2_R {
                CWUF2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Wakeup flag 1
            #[inline(always)]
            pub fn cwuf1(&self) -> CWUF1_R {
                CWUF1_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///Power status register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr2](sr2) module
    pub type SR2 = crate::Reg<u32, _SR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR2;
    ///`read()` method returns [sr2::R](sr2::R) reader structure
    impl crate::Readable for SR2 {}
    ///Power status register 2
    pub mod sr2 {
        ///Reader of register SR2
        pub type R = crate::R<u32, super::SR2>;
        ///Reader of field `PVMO3`
        pub type PVMO3_R = crate::R<bool, bool>;
        ///Reader of field `PVMO1`
        pub type PVMO1_R = crate::R<bool, bool>;
        ///Reader of field `PVDO`
        pub type PVDO_R = crate::R<bool, bool>;
        ///Reader of field `VOSF`
        pub type VOSF_R = crate::R<bool, bool>;
        ///Reader of field `REGLPF`
        pub type REGLPF_R = crate::R<bool, bool>;
        ///Reader of field `REGLPS`
        pub type REGLPS_R = crate::R<bool, bool>;
        ///Reader of field `SDSMPSF`
        pub type SDSMPSF_R = crate::R<bool, bool>;
        ///Reader of field `SDBF`
        pub type SDBF_R = crate::R<bool, bool>;
        impl R {
            ///Bit 14 - Peripheral voltage monitoring output: VDDA vs. 1.62 V
            #[inline(always)]
            pub fn pvmo3(&self) -> PVMO3_R {
                PVMO3_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 12 - Peripheral voltage monitoring output: VDDUSB vs. 1.2 V
            #[inline(always)]
            pub fn pvmo1(&self) -> PVMO1_R {
                PVMO1_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Power voltage detector output
            #[inline(always)]
            pub fn pvdo(&self) -> PVDO_R {
                PVDO_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Voltage scaling flag
            #[inline(always)]
            pub fn vosf(&self) -> VOSF_R {
                VOSF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Low-power regulator flag
            #[inline(always)]
            pub fn reglpf(&self) -> REGLPF_R {
                REGLPF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Low-power regulator started
            #[inline(always)]
            pub fn reglps(&self) -> REGLPS_R {
                REGLPS_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 1 - Step Down converter SMPS mode flag
            #[inline(always)]
            pub fn sdsmpsf(&self) -> SDSMPSF_R {
                SDSMPSF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Step Down converter Bypass mode flag
            #[inline(always)]
            pub fn sdbf(&self) -> SDBF_R {
                SDBF_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///Power status clear register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [scr](scr) module
    pub type SCR = crate::Reg<u32, _SCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SCR;
    ///`write(|w| ..)` method takes [scr::W](scr::W) writer structure
    impl crate::Writable for SCR {}
    ///Power status clear register
    pub mod scr {
        ///Writer for register SCR
        pub type W = crate::W<u32, super::SCR>;
        ///Register SCR `reset()`'s with value 0
        impl crate::ResetValue for super::SCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `CC2HF`
        pub struct CC2HF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2HF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `C802AF`
        pub struct C802AF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C802AF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `CBLEAF`
        pub struct CBLEAF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CBLEAF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `CCRPEF`
        pub struct CCRPEF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCRPEF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `C802WUF`
        pub struct C802WUF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C802WUF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `CBLEWUF`
        pub struct CBLEWUF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CBLEWUF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `CBORHF`
        pub struct CBORHF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CBORHF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `CSMPSFBF`
        pub struct CSMPSFBF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CSMPSFBF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `CWUF5`
        pub struct CWUF5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CWUF5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CWUF4`
        pub struct CWUF4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CWUF4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CWUF3`
        pub struct CWUF3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CWUF3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CWUF2`
        pub struct CWUF2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CWUF2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CWUF1`
        pub struct CWUF1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CWUF1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 14 - Clear CPU2 Hold interrupt flag
            #[inline(always)]
            pub fn cc2hf(&mut self) -> CC2HF_W {
                CC2HF_W { w: self }
            }
            ///Bit 13 - Clear 802.15.4 end of activity interrupt flag
            #[inline(always)]
            pub fn c802af(&mut self) -> C802AF_W {
                C802AF_W { w: self }
            }
            ///Bit 12 - Clear BLE end of activity interrupt flag
            #[inline(always)]
            pub fn cbleaf(&mut self) -> CBLEAF_W {
                CBLEAF_W { w: self }
            }
            ///Bit 11 - Clear critical radio phase end of activity interrupt flag
            #[inline(always)]
            pub fn ccrpef(&mut self) -> CCRPEF_W {
                CCRPEF_W { w: self }
            }
            ///Bit 10 - Clear 802.15.4 wakeup interrupt flag
            #[inline(always)]
            pub fn c802wuf(&mut self) -> C802WUF_W {
                C802WUF_W { w: self }
            }
            ///Bit 9 - Clear BLE wakeup interrupt flag
            #[inline(always)]
            pub fn cblewuf(&mut self) -> CBLEWUF_W {
                CBLEWUF_W { w: self }
            }
            ///Bit 8 - Clear BORH interrupt flag
            #[inline(always)]
            pub fn cborhf(&mut self) -> CBORHF_W {
                CBORHF_W { w: self }
            }
            ///Bit 7 - Clear SMPS Step Down converter forced in Bypass interrupt flag
            #[inline(always)]
            pub fn csmpsfbf(&mut self) -> CSMPSFBF_W {
                CSMPSFBF_W { w: self }
            }
            ///Bit 4 - Clear wakeup flag 5
            #[inline(always)]
            pub fn cwuf5(&mut self) -> CWUF5_W {
                CWUF5_W { w: self }
            }
            ///Bit 3 - Clear wakeup flag 4
            #[inline(always)]
            pub fn cwuf4(&mut self) -> CWUF4_W {
                CWUF4_W { w: self }
            }
            ///Bit 2 - Clear wakeup flag 3
            #[inline(always)]
            pub fn cwuf3(&mut self) -> CWUF3_W {
                CWUF3_W { w: self }
            }
            ///Bit 1 - Clear wakeup flag 2
            #[inline(always)]
            pub fn cwuf2(&mut self) -> CWUF2_W {
                CWUF2_W { w: self }
            }
            ///Bit 0 - Clear wakeup flag 1
            #[inline(always)]
            pub fn cwuf1(&mut self) -> CWUF1_W {
                CWUF1_W { w: self }
            }
        }
    }
    ///Power control register 5
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr5](cr5) module
    pub type CR5 = crate::Reg<u32, _CR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR5;
    ///`read()` method returns [cr5::R](cr5::R) reader structure
    impl crate::Readable for CR5 {}
    ///`write(|w| ..)` method takes [cr5::W](cr5::W) writer structure
    impl crate::Writable for CR5 {}
    ///Power control register 5
    pub mod cr5 {
        ///Reader of register CR5
        pub type R = crate::R<u32, super::CR5>;
        ///Writer for register CR5
        pub type W = crate::W<u32, super::CR5>;
        ///Register CR5 `reset()`'s with value 0x4270
        impl crate::ResetValue for super::CR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x4270
            }
        }
        ///Reader of field `SDEB`
        pub type SDEB_R = crate::R<bool, bool>;
        ///Write proxy for field `SDEB`
        pub struct SDEB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SDEB_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `SDBEN`
        pub type SDBEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SDBEN`
        pub struct SDBEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SDBEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `SMPSCFG`
        pub type SMPSCFG_R = crate::R<bool, bool>;
        ///Write proxy for field `SMPSCFG`
        pub struct SMPSCFG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMPSCFG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `BORHC`
        pub type BORHC_R = crate::R<bool, bool>;
        ///Write proxy for field `BORHC`
        pub struct BORHC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BORHC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `SDSC`
        pub type SDSC_R = crate::R<u8, u8>;
        ///Write proxy for field `SDSC`
        pub struct SDSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SDSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `SDVOS`
        pub type SDVOS_R = crate::R<u8, u8>;
        ///Write proxy for field `SDVOS`
        pub struct SDVOS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SDVOS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Enable Step Down converter SMPS mode enabled
            #[inline(always)]
            pub fn sdeb(&self) -> SDEB_R {
                SDEB_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Enable Step Down converter Bypass mode enabled
            #[inline(always)]
            pub fn sdben(&self) -> SDBEN_R {
                SDBEN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 9 - VOS configuration selection (non user)
            #[inline(always)]
            pub fn smpscfg(&self) -> SMPSCFG_R {
                SMPSCFG_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - BORH configuration selection
            #[inline(always)]
            pub fn borhc(&self) -> BORHC_R {
                BORHC_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 4:6 - Step Down converter supplt startup current selection
            #[inline(always)]
            pub fn sdsc(&self) -> SDSC_R {
                SDSC_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:3 - Step Down converter voltage output scaling
            #[inline(always)]
            pub fn sdvos(&self) -> SDVOS_R {
                SDVOS_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bit 15 - Enable Step Down converter SMPS mode enabled
            #[inline(always)]
            pub fn sdeb(&mut self) -> SDEB_W {
                SDEB_W { w: self }
            }
            ///Bit 14 - Enable Step Down converter Bypass mode enabled
            #[inline(always)]
            pub fn sdben(&mut self) -> SDBEN_W {
                SDBEN_W { w: self }
            }
            ///Bit 9 - VOS configuration selection (non user)
            #[inline(always)]
            pub fn smpscfg(&mut self) -> SMPSCFG_W {
                SMPSCFG_W { w: self }
            }
            ///Bit 8 - BORH configuration selection
            #[inline(always)]
            pub fn borhc(&mut self) -> BORHC_W {
                BORHC_W { w: self }
            }
            ///Bits 4:6 - Step Down converter supplt startup current selection
            #[inline(always)]
            pub fn sdsc(&mut self) -> SDSC_W {
                SDSC_W { w: self }
            }
            ///Bits 0:3 - Step Down converter voltage output scaling
            #[inline(always)]
            pub fn sdvos(&mut self) -> SDVOS_W {
                SDVOS_W { w: self }
            }
        }
    }
    ///Power Port A pull-up control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pucra](pucra) module
    pub type PUCRA = crate::Reg<u32, _PUCRA>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUCRA;
    ///`read()` method returns [pucra::R](pucra::R) reader structure
    impl crate::Readable for PUCRA {}
    ///`write(|w| ..)` method takes [pucra::W](pucra::W) writer structure
    impl crate::Writable for PUCRA {}
    ///Power Port A pull-up control register
    pub mod pucra {
        ///Reader of register PUCRA
        pub type R = crate::R<u32, super::PUCRA>;
        ///Writer for register PUCRA
        pub type W = crate::W<u32, super::PUCRA>;
        ///Register PUCRA `reset()`'s with value 0
        impl crate::ResetValue for super::PUCRA {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PU15`
        pub type PU15_R = crate::R<bool, bool>;
        ///Write proxy for field `PU15`
        pub struct PU15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PU13`
        pub type PU13_R = crate::R<bool, bool>;
        ///Write proxy for field `PU13`
        pub struct PU13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PU12`
        pub type PU12_R = crate::R<bool, bool>;
        ///Write proxy for field `PU12`
        pub struct PU12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PU11`
        pub type PU11_R = crate::R<bool, bool>;
        ///Write proxy for field `PU11`
        pub struct PU11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PU10`
        pub type PU10_R = crate::R<bool, bool>;
        ///Write proxy for field `PU10`
        pub struct PU10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PU9`
        pub type PU9_R = crate::R<bool, bool>;
        ///Write proxy for field `PU9`
        pub struct PU9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PU8`
        pub type PU8_R = crate::R<bool, bool>;
        ///Write proxy for field `PU8`
        pub struct PU8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PU7`
        pub type PU7_R = crate::R<bool, bool>;
        ///Write proxy for field `PU7`
        pub struct PU7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PU6`
        pub type PU6_R = crate::R<bool, bool>;
        ///Write proxy for field `PU6`
        pub struct PU6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PU5`
        pub type PU5_R = crate::R<bool, bool>;
        ///Write proxy for field `PU5`
        pub struct PU5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PU4`
        pub type PU4_R = crate::R<bool, bool>;
        ///Write proxy for field `PU4`
        pub struct PU4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PU3`
        pub type PU3_R = crate::R<bool, bool>;
        ///Write proxy for field `PU3`
        pub struct PU3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PU2`
        pub type PU2_R = crate::R<bool, bool>;
        ///Write proxy for field `PU2`
        pub struct PU2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PU1`
        pub type PU1_R = crate::R<bool, bool>;
        ///Write proxy for field `PU1`
        pub struct PU1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PU0`
        pub type PU0_R = crate::R<bool, bool>;
        ///Write proxy for field `PU0`
        pub struct PU0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&self) -> PU15_R {
                PU15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 13 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&self) -> PU13_R {
                PU13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&self) -> PU12_R {
                PU12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&self) -> PU11_R {
                PU11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&self) -> PU10_R {
                PU10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&self) -> PU9_R {
                PU9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&self) -> PU8_R {
                PU8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&self) -> PU7_R {
                PU7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&self) -> PU6_R {
                PU6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&self) -> PU5_R {
                PU5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&self) -> PU4_R {
                PU4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&self) -> PU3_R {
                PU3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&self) -> PU2_R {
                PU2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&self) -> PU1_R {
                PU1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&self) -> PU0_R {
                PU0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&mut self) -> PU15_W {
                PU15_W { w: self }
            }
            ///Bit 13 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&mut self) -> PU13_W {
                PU13_W { w: self }
            }
            ///Bit 12 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&mut self) -> PU12_W {
                PU12_W { w: self }
            }
            ///Bit 11 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&mut self) -> PU11_W {
                PU11_W { w: self }
            }
            ///Bit 10 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&mut self) -> PU10_W {
                PU10_W { w: self }
            }
            ///Bit 9 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&mut self) -> PU9_W {
                PU9_W { w: self }
            }
            ///Bit 8 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&mut self) -> PU8_W {
                PU8_W { w: self }
            }
            ///Bit 7 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&mut self) -> PU7_W {
                PU7_W { w: self }
            }
            ///Bit 6 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&mut self) -> PU6_W {
                PU6_W { w: self }
            }
            ///Bit 5 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&mut self) -> PU5_W {
                PU5_W { w: self }
            }
            ///Bit 4 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&mut self) -> PU4_W {
                PU4_W { w: self }
            }
            ///Bit 3 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&mut self) -> PU3_W {
                PU3_W { w: self }
            }
            ///Bit 2 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&mut self) -> PU2_W {
                PU2_W { w: self }
            }
            ///Bit 1 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&mut self) -> PU1_W {
                PU1_W { w: self }
            }
            ///Bit 0 - Port A pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&mut self) -> PU0_W {
                PU0_W { w: self }
            }
        }
    }
    ///Power Port A pull-down control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdcra](pdcra) module
    pub type PDCRA = crate::Reg<u32, _PDCRA>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDCRA;
    ///`read()` method returns [pdcra::R](pdcra::R) reader structure
    impl crate::Readable for PDCRA {}
    ///`write(|w| ..)` method takes [pdcra::W](pdcra::W) writer structure
    impl crate::Writable for PDCRA {}
    ///Power Port A pull-down control register
    pub mod pdcra {
        ///Reader of register PDCRA
        pub type R = crate::R<u32, super::PDCRA>;
        ///Writer for register PDCRA
        pub type W = crate::W<u32, super::PDCRA>;
        ///Register PDCRA `reset()`'s with value 0
        impl crate::ResetValue for super::PDCRA {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PD14`
        pub type PD14_R = crate::R<bool, bool>;
        ///Write proxy for field `PD14`
        pub struct PD14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PD12`
        pub type PD12_R = crate::R<bool, bool>;
        ///Write proxy for field `PD12`
        pub struct PD12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PD11`
        pub type PD11_R = crate::R<bool, bool>;
        ///Write proxy for field `PD11`
        pub struct PD11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PD10`
        pub type PD10_R = crate::R<bool, bool>;
        ///Write proxy for field `PD10`
        pub struct PD10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PD9`
        pub type PD9_R = crate::R<bool, bool>;
        ///Write proxy for field `PD9`
        pub struct PD9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PD8`
        pub type PD8_R = crate::R<bool, bool>;
        ///Write proxy for field `PD8`
        pub struct PD8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PD7`
        pub type PD7_R = crate::R<bool, bool>;
        ///Write proxy for field `PD7`
        pub struct PD7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PD6`
        pub type PD6_R = crate::R<bool, bool>;
        ///Write proxy for field `PD6`
        pub struct PD6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PD5`
        pub type PD5_R = crate::R<bool, bool>;
        ///Write proxy for field `PD5`
        pub struct PD5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PD4`
        pub type PD4_R = crate::R<bool, bool>;
        ///Write proxy for field `PD4`
        pub struct PD4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PD3`
        pub type PD3_R = crate::R<bool, bool>;
        ///Write proxy for field `PD3`
        pub struct PD3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PD2`
        pub type PD2_R = crate::R<bool, bool>;
        ///Write proxy for field `PD2`
        pub struct PD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PD1`
        pub type PD1_R = crate::R<bool, bool>;
        ///Write proxy for field `PD1`
        pub struct PD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PD0`
        pub type PD0_R = crate::R<bool, bool>;
        ///Write proxy for field `PD0`
        pub struct PD0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 14 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&self) -> PD14_R {
                PD14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 12 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&self) -> PD12_R {
                PD12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&self) -> PD11_R {
                PD11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&self) -> PD10_R {
                PD10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&self) -> PD9_R {
                PD9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&self) -> PD8_R {
                PD8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&self) -> PD7_R {
                PD7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&self) -> PD6_R {
                PD6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&self) -> PD5_R {
                PD5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&self) -> PD4_R {
                PD4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&self) -> PD3_R {
                PD3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&self) -> PD2_R {
                PD2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&self) -> PD1_R {
                PD1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&self) -> PD0_R {
                PD0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 14 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&mut self) -> PD14_W {
                PD14_W { w: self }
            }
            ///Bit 12 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&mut self) -> PD12_W {
                PD12_W { w: self }
            }
            ///Bit 11 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&mut self) -> PD11_W {
                PD11_W { w: self }
            }
            ///Bit 10 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&mut self) -> PD10_W {
                PD10_W { w: self }
            }
            ///Bit 9 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&mut self) -> PD9_W {
                PD9_W { w: self }
            }
            ///Bit 8 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&mut self) -> PD8_W {
                PD8_W { w: self }
            }
            ///Bit 7 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&mut self) -> PD7_W {
                PD7_W { w: self }
            }
            ///Bit 6 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&mut self) -> PD6_W {
                PD6_W { w: self }
            }
            ///Bit 5 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&mut self) -> PD5_W {
                PD5_W { w: self }
            }
            ///Bit 4 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&mut self) -> PD4_W {
                PD4_W { w: self }
            }
            ///Bit 3 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&mut self) -> PD3_W {
                PD3_W { w: self }
            }
            ///Bit 2 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&mut self) -> PD2_W {
                PD2_W { w: self }
            }
            ///Bit 1 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&mut self) -> PD1_W {
                PD1_W { w: self }
            }
            ///Bit 0 - Port A pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&mut self) -> PD0_W {
                PD0_W { w: self }
            }
        }
    }
    ///Power Port B pull-up control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pucrb](pucrb) module
    pub type PUCRB = crate::Reg<u32, _PUCRB>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUCRB;
    ///`read()` method returns [pucrb::R](pucrb::R) reader structure
    impl crate::Readable for PUCRB {}
    ///`write(|w| ..)` method takes [pucrb::W](pucrb::W) writer structure
    impl crate::Writable for PUCRB {}
    ///Power Port B pull-up control register
    pub mod pucrb {
        ///Reader of register PUCRB
        pub type R = crate::R<u32, super::PUCRB>;
        ///Writer for register PUCRB
        pub type W = crate::W<u32, super::PUCRB>;
        ///Register PUCRB `reset()`'s with value 0
        impl crate::ResetValue for super::PUCRB {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PU15`
        pub type PU15_R = crate::R<bool, bool>;
        ///Write proxy for field `PU15`
        pub struct PU15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PU14`
        pub type PU14_R = crate::R<bool, bool>;
        ///Write proxy for field `PU14`
        pub struct PU14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PU13`
        pub type PU13_R = crate::R<bool, bool>;
        ///Write proxy for field `PU13`
        pub struct PU13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PU12`
        pub type PU12_R = crate::R<bool, bool>;
        ///Write proxy for field `PU12`
        pub struct PU12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PU11`
        pub type PU11_R = crate::R<bool, bool>;
        ///Write proxy for field `PU11`
        pub struct PU11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PU10`
        pub type PU10_R = crate::R<bool, bool>;
        ///Write proxy for field `PU10`
        pub struct PU10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PU9`
        pub type PU9_R = crate::R<bool, bool>;
        ///Write proxy for field `PU9`
        pub struct PU9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PU8`
        pub type PU8_R = crate::R<bool, bool>;
        ///Write proxy for field `PU8`
        pub struct PU8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PU7`
        pub type PU7_R = crate::R<bool, bool>;
        ///Write proxy for field `PU7`
        pub struct PU7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PU6`
        pub type PU6_R = crate::R<bool, bool>;
        ///Write proxy for field `PU6`
        pub struct PU6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PU5`
        pub type PU5_R = crate::R<bool, bool>;
        ///Write proxy for field `PU5`
        pub struct PU5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PU4`
        pub type PU4_R = crate::R<bool, bool>;
        ///Write proxy for field `PU4`
        pub struct PU4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PU3`
        pub type PU3_R = crate::R<bool, bool>;
        ///Write proxy for field `PU3`
        pub struct PU3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PU2`
        pub type PU2_R = crate::R<bool, bool>;
        ///Write proxy for field `PU2`
        pub struct PU2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PU1`
        pub type PU1_R = crate::R<bool, bool>;
        ///Write proxy for field `PU1`
        pub struct PU1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PU0`
        pub type PU0_R = crate::R<bool, bool>;
        ///Write proxy for field `PU0`
        pub struct PU0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&self) -> PU15_R {
                PU15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu14(&self) -> PU14_R {
                PU14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&self) -> PU13_R {
                PU13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&self) -> PU12_R {
                PU12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&self) -> PU11_R {
                PU11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&self) -> PU10_R {
                PU10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&self) -> PU9_R {
                PU9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&self) -> PU8_R {
                PU8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&self) -> PU7_R {
                PU7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&self) -> PU6_R {
                PU6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&self) -> PU5_R {
                PU5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&self) -> PU4_R {
                PU4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&self) -> PU3_R {
                PU3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&self) -> PU2_R {
                PU2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&self) -> PU1_R {
                PU1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&self) -> PU0_R {
                PU0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&mut self) -> PU15_W {
                PU15_W { w: self }
            }
            ///Bit 14 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu14(&mut self) -> PU14_W {
                PU14_W { w: self }
            }
            ///Bit 13 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&mut self) -> PU13_W {
                PU13_W { w: self }
            }
            ///Bit 12 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&mut self) -> PU12_W {
                PU12_W { w: self }
            }
            ///Bit 11 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&mut self) -> PU11_W {
                PU11_W { w: self }
            }
            ///Bit 10 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&mut self) -> PU10_W {
                PU10_W { w: self }
            }
            ///Bit 9 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&mut self) -> PU9_W {
                PU9_W { w: self }
            }
            ///Bit 8 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&mut self) -> PU8_W {
                PU8_W { w: self }
            }
            ///Bit 7 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&mut self) -> PU7_W {
                PU7_W { w: self }
            }
            ///Bit 6 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&mut self) -> PU6_W {
                PU6_W { w: self }
            }
            ///Bit 5 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&mut self) -> PU5_W {
                PU5_W { w: self }
            }
            ///Bit 4 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&mut self) -> PU4_W {
                PU4_W { w: self }
            }
            ///Bit 3 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&mut self) -> PU3_W {
                PU3_W { w: self }
            }
            ///Bit 2 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&mut self) -> PU2_W {
                PU2_W { w: self }
            }
            ///Bit 1 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&mut self) -> PU1_W {
                PU1_W { w: self }
            }
            ///Bit 0 - Port B pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&mut self) -> PU0_W {
                PU0_W { w: self }
            }
        }
    }
    ///Power Port B pull-down control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdcrb](pdcrb) module
    pub type PDCRB = crate::Reg<u32, _PDCRB>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDCRB;
    ///`read()` method returns [pdcrb::R](pdcrb::R) reader structure
    impl crate::Readable for PDCRB {}
    ///`write(|w| ..)` method takes [pdcrb::W](pdcrb::W) writer structure
    impl crate::Writable for PDCRB {}
    ///Power Port B pull-down control register
    pub mod pdcrb {
        ///Reader of register PDCRB
        pub type R = crate::R<u32, super::PDCRB>;
        ///Writer for register PDCRB
        pub type W = crate::W<u32, super::PDCRB>;
        ///Register PDCRB `reset()`'s with value 0
        impl crate::ResetValue for super::PDCRB {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PD15`
        pub type PD15_R = crate::R<bool, bool>;
        ///Write proxy for field `PD15`
        pub struct PD15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PD14`
        pub type PD14_R = crate::R<bool, bool>;
        ///Write proxy for field `PD14`
        pub struct PD14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PD13`
        pub type PD13_R = crate::R<bool, bool>;
        ///Write proxy for field `PD13`
        pub struct PD13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PD12`
        pub type PD12_R = crate::R<bool, bool>;
        ///Write proxy for field `PD12`
        pub struct PD12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PD11`
        pub type PD11_R = crate::R<bool, bool>;
        ///Write proxy for field `PD11`
        pub struct PD11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PD10`
        pub type PD10_R = crate::R<bool, bool>;
        ///Write proxy for field `PD10`
        pub struct PD10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PD9`
        pub type PD9_R = crate::R<bool, bool>;
        ///Write proxy for field `PD9`
        pub struct PD9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PD8`
        pub type PD8_R = crate::R<bool, bool>;
        ///Write proxy for field `PD8`
        pub struct PD8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PD7`
        pub type PD7_R = crate::R<bool, bool>;
        ///Write proxy for field `PD7`
        pub struct PD7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PD6`
        pub type PD6_R = crate::R<bool, bool>;
        ///Write proxy for field `PD6`
        pub struct PD6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PD5`
        pub type PD5_R = crate::R<bool, bool>;
        ///Write proxy for field `PD5`
        pub struct PD5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PD3`
        pub type PD3_R = crate::R<bool, bool>;
        ///Write proxy for field `PD3`
        pub struct PD3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PD2`
        pub type PD2_R = crate::R<bool, bool>;
        ///Write proxy for field `PD2`
        pub struct PD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PD1`
        pub type PD1_R = crate::R<bool, bool>;
        ///Write proxy for field `PD1`
        pub struct PD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PD0`
        pub type PD0_R = crate::R<bool, bool>;
        ///Write proxy for field `PD0`
        pub struct PD0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd15(&self) -> PD15_R {
                PD15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&self) -> PD14_R {
                PD14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd13(&self) -> PD13_R {
                PD13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&self) -> PD12_R {
                PD12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&self) -> PD11_R {
                PD11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&self) -> PD10_R {
                PD10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&self) -> PD9_R {
                PD9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&self) -> PD8_R {
                PD8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&self) -> PD7_R {
                PD7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&self) -> PD6_R {
                PD6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&self) -> PD5_R {
                PD5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 3 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&self) -> PD3_R {
                PD3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&self) -> PD2_R {
                PD2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&self) -> PD1_R {
                PD1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&self) -> PD0_R {
                PD0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd15(&mut self) -> PD15_W {
                PD15_W { w: self }
            }
            ///Bit 14 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&mut self) -> PD14_W {
                PD14_W { w: self }
            }
            ///Bit 13 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd13(&mut self) -> PD13_W {
                PD13_W { w: self }
            }
            ///Bit 12 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&mut self) -> PD12_W {
                PD12_W { w: self }
            }
            ///Bit 11 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&mut self) -> PD11_W {
                PD11_W { w: self }
            }
            ///Bit 10 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&mut self) -> PD10_W {
                PD10_W { w: self }
            }
            ///Bit 9 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&mut self) -> PD9_W {
                PD9_W { w: self }
            }
            ///Bit 8 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&mut self) -> PD8_W {
                PD8_W { w: self }
            }
            ///Bit 7 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&mut self) -> PD7_W {
                PD7_W { w: self }
            }
            ///Bit 6 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&mut self) -> PD6_W {
                PD6_W { w: self }
            }
            ///Bit 5 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&mut self) -> PD5_W {
                PD5_W { w: self }
            }
            ///Bit 3 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&mut self) -> PD3_W {
                PD3_W { w: self }
            }
            ///Bit 2 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&mut self) -> PD2_W {
                PD2_W { w: self }
            }
            ///Bit 1 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&mut self) -> PD1_W {
                PD1_W { w: self }
            }
            ///Bit 0 - Port B pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&mut self) -> PD0_W {
                PD0_W { w: self }
            }
        }
    }
    ///Power Port C pull-up control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pucrc](pucrc) module
    pub type PUCRC = crate::Reg<u32, _PUCRC>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUCRC;
    ///`read()` method returns [pucrc::R](pucrc::R) reader structure
    impl crate::Readable for PUCRC {}
    ///`write(|w| ..)` method takes [pucrc::W](pucrc::W) writer structure
    impl crate::Writable for PUCRC {}
    ///Power Port C pull-up control register
    pub mod pucrc {
        ///Reader of register PUCRC
        pub type R = crate::R<u32, super::PUCRC>;
        ///Writer for register PUCRC
        pub type W = crate::W<u32, super::PUCRC>;
        ///Register PUCRC `reset()`'s with value 0
        impl crate::ResetValue for super::PUCRC {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PU15`
        pub type PU15_R = crate::R<bool, bool>;
        ///Write proxy for field `PU15`
        pub struct PU15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PU14`
        pub type PU14_R = crate::R<bool, bool>;
        ///Write proxy for field `PU14`
        pub struct PU14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PU13`
        pub type PU13_R = crate::R<bool, bool>;
        ///Write proxy for field `PU13`
        pub struct PU13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PU12`
        pub type PU12_R = crate::R<bool, bool>;
        ///Write proxy for field `PU12`
        pub struct PU12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PU11`
        pub type PU11_R = crate::R<bool, bool>;
        ///Write proxy for field `PU11`
        pub struct PU11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PU10`
        pub type PU10_R = crate::R<bool, bool>;
        ///Write proxy for field `PU10`
        pub struct PU10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PU9`
        pub type PU9_R = crate::R<bool, bool>;
        ///Write proxy for field `PU9`
        pub struct PU9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PU8`
        pub type PU8_R = crate::R<bool, bool>;
        ///Write proxy for field `PU8`
        pub struct PU8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PU7`
        pub type PU7_R = crate::R<bool, bool>;
        ///Write proxy for field `PU7`
        pub struct PU7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PU6`
        pub type PU6_R = crate::R<bool, bool>;
        ///Write proxy for field `PU6`
        pub struct PU6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PU5`
        pub type PU5_R = crate::R<bool, bool>;
        ///Write proxy for field `PU5`
        pub struct PU5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PU4`
        pub type PU4_R = crate::R<bool, bool>;
        ///Write proxy for field `PU4`
        pub struct PU4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PU3`
        pub type PU3_R = crate::R<bool, bool>;
        ///Write proxy for field `PU3`
        pub struct PU3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PU2`
        pub type PU2_R = crate::R<bool, bool>;
        ///Write proxy for field `PU2`
        pub struct PU2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PU1`
        pub type PU1_R = crate::R<bool, bool>;
        ///Write proxy for field `PU1`
        pub struct PU1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PU0`
        pub type PU0_R = crate::R<bool, bool>;
        ///Write proxy for field `PU0`
        pub struct PU0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&self) -> PU15_R {
                PU15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu14(&self) -> PU14_R {
                PU14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&self) -> PU13_R {
                PU13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&self) -> PU12_R {
                PU12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&self) -> PU11_R {
                PU11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&self) -> PU10_R {
                PU10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&self) -> PU9_R {
                PU9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&self) -> PU8_R {
                PU8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&self) -> PU7_R {
                PU7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&self) -> PU6_R {
                PU6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&self) -> PU5_R {
                PU5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&self) -> PU4_R {
                PU4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&self) -> PU3_R {
                PU3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&self) -> PU2_R {
                PU2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&self) -> PU1_R {
                PU1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&self) -> PU0_R {
                PU0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&mut self) -> PU15_W {
                PU15_W { w: self }
            }
            ///Bit 14 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu14(&mut self) -> PU14_W {
                PU14_W { w: self }
            }
            ///Bit 13 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&mut self) -> PU13_W {
                PU13_W { w: self }
            }
            ///Bit 12 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&mut self) -> PU12_W {
                PU12_W { w: self }
            }
            ///Bit 11 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&mut self) -> PU11_W {
                PU11_W { w: self }
            }
            ///Bit 10 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&mut self) -> PU10_W {
                PU10_W { w: self }
            }
            ///Bit 9 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&mut self) -> PU9_W {
                PU9_W { w: self }
            }
            ///Bit 8 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&mut self) -> PU8_W {
                PU8_W { w: self }
            }
            ///Bit 7 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&mut self) -> PU7_W {
                PU7_W { w: self }
            }
            ///Bit 6 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&mut self) -> PU6_W {
                PU6_W { w: self }
            }
            ///Bit 5 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&mut self) -> PU5_W {
                PU5_W { w: self }
            }
            ///Bit 4 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&mut self) -> PU4_W {
                PU4_W { w: self }
            }
            ///Bit 3 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&mut self) -> PU3_W {
                PU3_W { w: self }
            }
            ///Bit 2 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&mut self) -> PU2_W {
                PU2_W { w: self }
            }
            ///Bit 1 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&mut self) -> PU1_W {
                PU1_W { w: self }
            }
            ///Bit 0 - Port C pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&mut self) -> PU0_W {
                PU0_W { w: self }
            }
        }
    }
    ///Power Port C pull-down control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdcrc](pdcrc) module
    pub type PDCRC = crate::Reg<u32, _PDCRC>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDCRC;
    ///`read()` method returns [pdcrc::R](pdcrc::R) reader structure
    impl crate::Readable for PDCRC {}
    ///`write(|w| ..)` method takes [pdcrc::W](pdcrc::W) writer structure
    impl crate::Writable for PDCRC {}
    ///Power Port C pull-down control register
    pub mod pdcrc {
        ///Reader of register PDCRC
        pub type R = crate::R<u32, super::PDCRC>;
        ///Writer for register PDCRC
        pub type W = crate::W<u32, super::PDCRC>;
        ///Register PDCRC `reset()`'s with value 0
        impl crate::ResetValue for super::PDCRC {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PD15`
        pub type PD15_R = crate::R<bool, bool>;
        ///Write proxy for field `PD15`
        pub struct PD15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PD14`
        pub type PD14_R = crate::R<bool, bool>;
        ///Write proxy for field `PD14`
        pub struct PD14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PD13`
        pub type PD13_R = crate::R<bool, bool>;
        ///Write proxy for field `PD13`
        pub struct PD13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PD12`
        pub type PD12_R = crate::R<bool, bool>;
        ///Write proxy for field `PD12`
        pub struct PD12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PD11`
        pub type PD11_R = crate::R<bool, bool>;
        ///Write proxy for field `PD11`
        pub struct PD11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PD10`
        pub type PD10_R = crate::R<bool, bool>;
        ///Write proxy for field `PD10`
        pub struct PD10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PD9`
        pub type PD9_R = crate::R<bool, bool>;
        ///Write proxy for field `PD9`
        pub struct PD9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PD8`
        pub type PD8_R = crate::R<bool, bool>;
        ///Write proxy for field `PD8`
        pub struct PD8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PD7`
        pub type PD7_R = crate::R<bool, bool>;
        ///Write proxy for field `PD7`
        pub struct PD7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PD6`
        pub type PD6_R = crate::R<bool, bool>;
        ///Write proxy for field `PD6`
        pub struct PD6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PD5`
        pub type PD5_R = crate::R<bool, bool>;
        ///Write proxy for field `PD5`
        pub struct PD5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PD4`
        pub type PD4_R = crate::R<bool, bool>;
        ///Write proxy for field `PD4`
        pub struct PD4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PD3`
        pub type PD3_R = crate::R<bool, bool>;
        ///Write proxy for field `PD3`
        pub struct PD3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PD2`
        pub type PD2_R = crate::R<bool, bool>;
        ///Write proxy for field `PD2`
        pub struct PD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PD1`
        pub type PD1_R = crate::R<bool, bool>;
        ///Write proxy for field `PD1`
        pub struct PD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PD0`
        pub type PD0_R = crate::R<bool, bool>;
        ///Write proxy for field `PD0`
        pub struct PD0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd15(&self) -> PD15_R {
                PD15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&self) -> PD14_R {
                PD14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd13(&self) -> PD13_R {
                PD13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&self) -> PD12_R {
                PD12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&self) -> PD11_R {
                PD11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&self) -> PD10_R {
                PD10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&self) -> PD9_R {
                PD9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&self) -> PD8_R {
                PD8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&self) -> PD7_R {
                PD7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&self) -> PD6_R {
                PD6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&self) -> PD5_R {
                PD5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&self) -> PD4_R {
                PD4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&self) -> PD3_R {
                PD3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&self) -> PD2_R {
                PD2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&self) -> PD1_R {
                PD1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&self) -> PD0_R {
                PD0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd15(&mut self) -> PD15_W {
                PD15_W { w: self }
            }
            ///Bit 14 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&mut self) -> PD14_W {
                PD14_W { w: self }
            }
            ///Bit 13 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd13(&mut self) -> PD13_W {
                PD13_W { w: self }
            }
            ///Bit 12 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&mut self) -> PD12_W {
                PD12_W { w: self }
            }
            ///Bit 11 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&mut self) -> PD11_W {
                PD11_W { w: self }
            }
            ///Bit 10 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&mut self) -> PD10_W {
                PD10_W { w: self }
            }
            ///Bit 9 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&mut self) -> PD9_W {
                PD9_W { w: self }
            }
            ///Bit 8 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&mut self) -> PD8_W {
                PD8_W { w: self }
            }
            ///Bit 7 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&mut self) -> PD7_W {
                PD7_W { w: self }
            }
            ///Bit 6 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&mut self) -> PD6_W {
                PD6_W { w: self }
            }
            ///Bit 5 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&mut self) -> PD5_W {
                PD5_W { w: self }
            }
            ///Bit 4 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&mut self) -> PD4_W {
                PD4_W { w: self }
            }
            ///Bit 3 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&mut self) -> PD3_W {
                PD3_W { w: self }
            }
            ///Bit 2 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&mut self) -> PD2_W {
                PD2_W { w: self }
            }
            ///Bit 1 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&mut self) -> PD1_W {
                PD1_W { w: self }
            }
            ///Bit 0 - Port C pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&mut self) -> PD0_W {
                PD0_W { w: self }
            }
        }
    }
    ///Power Port D pull-up control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pucrd](pucrd) module
    pub type PUCRD = crate::Reg<u32, _PUCRD>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUCRD;
    ///`read()` method returns [pucrd::R](pucrd::R) reader structure
    impl crate::Readable for PUCRD {}
    ///`write(|w| ..)` method takes [pucrd::W](pucrd::W) writer structure
    impl crate::Writable for PUCRD {}
    ///Power Port D pull-up control register
    pub mod pucrd {
        ///Reader of register PUCRD
        pub type R = crate::R<u32, super::PUCRD>;
        ///Writer for register PUCRD
        pub type W = crate::W<u32, super::PUCRD>;
        ///Register PUCRD `reset()`'s with value 0
        impl crate::ResetValue for super::PUCRD {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PU15`
        pub type PU15_R = crate::R<bool, bool>;
        ///Write proxy for field `PU15`
        pub struct PU15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PU14`
        pub type PU14_R = crate::R<bool, bool>;
        ///Write proxy for field `PU14`
        pub struct PU14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PU13`
        pub type PU13_R = crate::R<bool, bool>;
        ///Write proxy for field `PU13`
        pub struct PU13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PU12`
        pub type PU12_R = crate::R<bool, bool>;
        ///Write proxy for field `PU12`
        pub struct PU12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PU11`
        pub type PU11_R = crate::R<bool, bool>;
        ///Write proxy for field `PU11`
        pub struct PU11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PU10`
        pub type PU10_R = crate::R<bool, bool>;
        ///Write proxy for field `PU10`
        pub struct PU10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PU9`
        pub type PU9_R = crate::R<bool, bool>;
        ///Write proxy for field `PU9`
        pub struct PU9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PU8`
        pub type PU8_R = crate::R<bool, bool>;
        ///Write proxy for field `PU8`
        pub struct PU8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PU7`
        pub type PU7_R = crate::R<bool, bool>;
        ///Write proxy for field `PU7`
        pub struct PU7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PU6`
        pub type PU6_R = crate::R<bool, bool>;
        ///Write proxy for field `PU6`
        pub struct PU6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PU5`
        pub type PU5_R = crate::R<bool, bool>;
        ///Write proxy for field `PU5`
        pub struct PU5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PU4`
        pub type PU4_R = crate::R<bool, bool>;
        ///Write proxy for field `PU4`
        pub struct PU4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PU3`
        pub type PU3_R = crate::R<bool, bool>;
        ///Write proxy for field `PU3`
        pub struct PU3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PU2`
        pub type PU2_R = crate::R<bool, bool>;
        ///Write proxy for field `PU2`
        pub struct PU2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PU1`
        pub type PU1_R = crate::R<bool, bool>;
        ///Write proxy for field `PU1`
        pub struct PU1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PU0`
        pub type PU0_R = crate::R<bool, bool>;
        ///Write proxy for field `PU0`
        pub struct PU0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&self) -> PU15_R {
                PU15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu14(&self) -> PU14_R {
                PU14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&self) -> PU13_R {
                PU13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&self) -> PU12_R {
                PU12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&self) -> PU11_R {
                PU11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&self) -> PU10_R {
                PU10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&self) -> PU9_R {
                PU9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&self) -> PU8_R {
                PU8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&self) -> PU7_R {
                PU7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&self) -> PU6_R {
                PU6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&self) -> PU5_R {
                PU5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&self) -> PU4_R {
                PU4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&self) -> PU3_R {
                PU3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&self) -> PU2_R {
                PU2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&self) -> PU1_R {
                PU1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&self) -> PU0_R {
                PU0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu15(&mut self) -> PU15_W {
                PU15_W { w: self }
            }
            ///Bit 14 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu14(&mut self) -> PU14_W {
                PU14_W { w: self }
            }
            ///Bit 13 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu13(&mut self) -> PU13_W {
                PU13_W { w: self }
            }
            ///Bit 12 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu12(&mut self) -> PU12_W {
                PU12_W { w: self }
            }
            ///Bit 11 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu11(&mut self) -> PU11_W {
                PU11_W { w: self }
            }
            ///Bit 10 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu10(&mut self) -> PU10_W {
                PU10_W { w: self }
            }
            ///Bit 9 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu9(&mut self) -> PU9_W {
                PU9_W { w: self }
            }
            ///Bit 8 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu8(&mut self) -> PU8_W {
                PU8_W { w: self }
            }
            ///Bit 7 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu7(&mut self) -> PU7_W {
                PU7_W { w: self }
            }
            ///Bit 6 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu6(&mut self) -> PU6_W {
                PU6_W { w: self }
            }
            ///Bit 5 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu5(&mut self) -> PU5_W {
                PU5_W { w: self }
            }
            ///Bit 4 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&mut self) -> PU4_W {
                PU4_W { w: self }
            }
            ///Bit 3 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&mut self) -> PU3_W {
                PU3_W { w: self }
            }
            ///Bit 2 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&mut self) -> PU2_W {
                PU2_W { w: self }
            }
            ///Bit 1 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&mut self) -> PU1_W {
                PU1_W { w: self }
            }
            ///Bit 0 - Port D pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&mut self) -> PU0_W {
                PU0_W { w: self }
            }
        }
    }
    ///Power Port D pull-down control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdcrd](pdcrd) module
    pub type PDCRD = crate::Reg<u32, _PDCRD>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDCRD;
    ///`read()` method returns [pdcrd::R](pdcrd::R) reader structure
    impl crate::Readable for PDCRD {}
    ///`write(|w| ..)` method takes [pdcrd::W](pdcrd::W) writer structure
    impl crate::Writable for PDCRD {}
    ///Power Port D pull-down control register
    pub mod pdcrd {
        ///Reader of register PDCRD
        pub type R = crate::R<u32, super::PDCRD>;
        ///Writer for register PDCRD
        pub type W = crate::W<u32, super::PDCRD>;
        ///Register PDCRD `reset()`'s with value 0
        impl crate::ResetValue for super::PDCRD {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PD15`
        pub type PD15_R = crate::R<bool, bool>;
        ///Write proxy for field `PD15`
        pub struct PD15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PD14`
        pub type PD14_R = crate::R<bool, bool>;
        ///Write proxy for field `PD14`
        pub struct PD14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `PD13`
        pub type PD13_R = crate::R<bool, bool>;
        ///Write proxy for field `PD13`
        pub struct PD13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PD12`
        pub type PD12_R = crate::R<bool, bool>;
        ///Write proxy for field `PD12`
        pub struct PD12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `PD11`
        pub type PD11_R = crate::R<bool, bool>;
        ///Write proxy for field `PD11`
        pub struct PD11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PD10`
        pub type PD10_R = crate::R<bool, bool>;
        ///Write proxy for field `PD10`
        pub struct PD10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PD9`
        pub type PD9_R = crate::R<bool, bool>;
        ///Write proxy for field `PD9`
        pub struct PD9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PD8`
        pub type PD8_R = crate::R<bool, bool>;
        ///Write proxy for field `PD8`
        pub struct PD8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `PD7`
        pub type PD7_R = crate::R<bool, bool>;
        ///Write proxy for field `PD7`
        pub struct PD7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `PD6`
        pub type PD6_R = crate::R<bool, bool>;
        ///Write proxy for field `PD6`
        pub struct PD6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PD5`
        pub type PD5_R = crate::R<bool, bool>;
        ///Write proxy for field `PD5`
        pub struct PD5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `PD4`
        pub type PD4_R = crate::R<bool, bool>;
        ///Write proxy for field `PD4`
        pub struct PD4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PD3`
        pub type PD3_R = crate::R<bool, bool>;
        ///Write proxy for field `PD3`
        pub struct PD3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PD2`
        pub type PD2_R = crate::R<bool, bool>;
        ///Write proxy for field `PD2`
        pub struct PD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PD1`
        pub type PD1_R = crate::R<bool, bool>;
        ///Write proxy for field `PD1`
        pub struct PD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PD0`
        pub type PD0_R = crate::R<bool, bool>;
        ///Write proxy for field `PD0`
        pub struct PD0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd15(&self) -> PD15_R {
                PD15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&self) -> PD14_R {
                PD14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd13(&self) -> PD13_R {
                PD13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&self) -> PD12_R {
                PD12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&self) -> PD11_R {
                PD11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&self) -> PD10_R {
                PD10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&self) -> PD9_R {
                PD9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&self) -> PD8_R {
                PD8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&self) -> PD7_R {
                PD7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&self) -> PD6_R {
                PD6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&self) -> PD5_R {
                PD5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&self) -> PD4_R {
                PD4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&self) -> PD3_R {
                PD3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&self) -> PD2_R {
                PD2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&self) -> PD1_R {
                PD1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&self) -> PD0_R {
                PD0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd15(&mut self) -> PD15_W {
                PD15_W { w: self }
            }
            ///Bit 14 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd14(&mut self) -> PD14_W {
                PD14_W { w: self }
            }
            ///Bit 13 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd13(&mut self) -> PD13_W {
                PD13_W { w: self }
            }
            ///Bit 12 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd12(&mut self) -> PD12_W {
                PD12_W { w: self }
            }
            ///Bit 11 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd11(&mut self) -> PD11_W {
                PD11_W { w: self }
            }
            ///Bit 10 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd10(&mut self) -> PD10_W {
                PD10_W { w: self }
            }
            ///Bit 9 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd9(&mut self) -> PD9_W {
                PD9_W { w: self }
            }
            ///Bit 8 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd8(&mut self) -> PD8_W {
                PD8_W { w: self }
            }
            ///Bit 7 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd7(&mut self) -> PD7_W {
                PD7_W { w: self }
            }
            ///Bit 6 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd6(&mut self) -> PD6_W {
                PD6_W { w: self }
            }
            ///Bit 5 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd5(&mut self) -> PD5_W {
                PD5_W { w: self }
            }
            ///Bit 4 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&mut self) -> PD4_W {
                PD4_W { w: self }
            }
            ///Bit 3 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&mut self) -> PD3_W {
                PD3_W { w: self }
            }
            ///Bit 2 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&mut self) -> PD2_W {
                PD2_W { w: self }
            }
            ///Bit 1 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&mut self) -> PD1_W {
                PD1_W { w: self }
            }
            ///Bit 0 - Port D pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&mut self) -> PD0_W {
                PD0_W { w: self }
            }
        }
    }
    ///Power Port E pull-up control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pucre](pucre) module
    pub type PUCRE = crate::Reg<u32, _PUCRE>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUCRE;
    ///`read()` method returns [pucre::R](pucre::R) reader structure
    impl crate::Readable for PUCRE {}
    ///`write(|w| ..)` method takes [pucre::W](pucre::W) writer structure
    impl crate::Writable for PUCRE {}
    ///Power Port E pull-up control register
    pub mod pucre {
        ///Reader of register PUCRE
        pub type R = crate::R<u32, super::PUCRE>;
        ///Writer for register PUCRE
        pub type W = crate::W<u32, super::PUCRE>;
        ///Register PUCRE `reset()`'s with value 0
        impl crate::ResetValue for super::PUCRE {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PU4`
        pub type PU4_R = crate::R<bool, bool>;
        ///Write proxy for field `PU4`
        pub struct PU4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PU3`
        pub type PU3_R = crate::R<bool, bool>;
        ///Write proxy for field `PU3`
        pub struct PU3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PU2`
        pub type PU2_R = crate::R<bool, bool>;
        ///Write proxy for field `PU2`
        pub struct PU2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PU1`
        pub type PU1_R = crate::R<bool, bool>;
        ///Write proxy for field `PU1`
        pub struct PU1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PU0`
        pub type PU0_R = crate::R<bool, bool>;
        ///Write proxy for field `PU0`
        pub struct PU0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 4 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&self) -> PU4_R {
                PU4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&self) -> PU3_R {
                PU3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&self) -> PU2_R {
                PU2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&self) -> PU1_R {
                PU1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&self) -> PU0_R {
                PU0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 4 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu4(&mut self) -> PU4_W {
                PU4_W { w: self }
            }
            ///Bit 3 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu3(&mut self) -> PU3_W {
                PU3_W { w: self }
            }
            ///Bit 2 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu2(&mut self) -> PU2_W {
                PU2_W { w: self }
            }
            ///Bit 1 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu1(&mut self) -> PU1_W {
                PU1_W { w: self }
            }
            ///Bit 0 - Port E pull-up bit y (y=0..15)
            #[inline(always)]
            pub fn pu0(&mut self) -> PU0_W {
                PU0_W { w: self }
            }
        }
    }
    ///Power Port E pull-down control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdcre](pdcre) module
    pub type PDCRE = crate::Reg<u32, _PDCRE>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDCRE;
    ///`read()` method returns [pdcre::R](pdcre::R) reader structure
    impl crate::Readable for PDCRE {}
    ///`write(|w| ..)` method takes [pdcre::W](pdcre::W) writer structure
    impl crate::Writable for PDCRE {}
    ///Power Port E pull-down control register
    pub mod pdcre {
        ///Reader of register PDCRE
        pub type R = crate::R<u32, super::PDCRE>;
        ///Writer for register PDCRE
        pub type W = crate::W<u32, super::PDCRE>;
        ///Register PDCRE `reset()`'s with value 0
        impl crate::ResetValue for super::PDCRE {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PD4`
        pub type PD4_R = crate::R<bool, bool>;
        ///Write proxy for field `PD4`
        pub struct PD4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `PD3`
        pub type PD3_R = crate::R<bool, bool>;
        ///Write proxy for field `PD3`
        pub struct PD3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PD2`
        pub type PD2_R = crate::R<bool, bool>;
        ///Write proxy for field `PD2`
        pub struct PD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `PD1`
        pub type PD1_R = crate::R<bool, bool>;
        ///Write proxy for field `PD1`
        pub struct PD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PD0`
        pub type PD0_R = crate::R<bool, bool>;
        ///Write proxy for field `PD0`
        pub struct PD0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 4 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&self) -> PD4_R {
                PD4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&self) -> PD3_R {
                PD3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&self) -> PD2_R {
                PD2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&self) -> PD1_R {
                PD1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&self) -> PD0_R {
                PD0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 4 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd4(&mut self) -> PD4_W {
                PD4_W { w: self }
            }
            ///Bit 3 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd3(&mut self) -> PD3_W {
                PD3_W { w: self }
            }
            ///Bit 2 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd2(&mut self) -> PD2_W {
                PD2_W { w: self }
            }
            ///Bit 1 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd1(&mut self) -> PD1_W {
                PD1_W { w: self }
            }
            ///Bit 0 - Port E pull-down bit y (y=0..15)
            #[inline(always)]
            pub fn pd0(&mut self) -> PD0_W {
                PD0_W { w: self }
            }
        }
    }
    ///Power Port H pull-up control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pucrh](pucrh) module
    pub type PUCRH = crate::Reg<u32, _PUCRH>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUCRH;
    ///`read()` method returns [pucrh::R](pucrh::R) reader structure
    impl crate::Readable for PUCRH {}
    ///`write(|w| ..)` method takes [pucrh::W](pucrh::W) writer structure
    impl crate::Writable for PUCRH {}
    ///Power Port H pull-up control register
    pub mod pucrh {
        ///Reader of register PUCRH
        pub type R = crate::R<u32, super::PUCRH>;
        ///Writer for register PUCRH
        pub type W = crate::W<u32, super::PUCRH>;
        ///Register PUCRH `reset()`'s with value 0
        impl crate::ResetValue for super::PUCRH {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PU3`
        pub type PU3_R = crate::R<bool, bool>;
        ///Write proxy for field `PU3`
        pub struct PU3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PU1`
        pub type PU1_R = crate::R<bool, bool>;
        ///Write proxy for field `PU1`
        pub struct PU1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PU0`
        pub type PU0_R = crate::R<bool, bool>;
        ///Write proxy for field `PU0`
        pub struct PU0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PU0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 3 - Port H pull-up bit y (y=0..1)
            #[inline(always)]
            pub fn pu3(&self) -> PU3_R {
                PU3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Port H pull-up bit y (y=0..1)
            #[inline(always)]
            pub fn pu1(&self) -> PU1_R {
                PU1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port H pull-up bit y (y=0..1)
            #[inline(always)]
            pub fn pu0(&self) -> PU0_R {
                PU0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 3 - Port H pull-up bit y (y=0..1)
            #[inline(always)]
            pub fn pu3(&mut self) -> PU3_W {
                PU3_W { w: self }
            }
            ///Bit 1 - Port H pull-up bit y (y=0..1)
            #[inline(always)]
            pub fn pu1(&mut self) -> PU1_W {
                PU1_W { w: self }
            }
            ///Bit 0 - Port H pull-up bit y (y=0..1)
            #[inline(always)]
            pub fn pu0(&mut self) -> PU0_W {
                PU0_W { w: self }
            }
        }
    }
    ///Power Port H pull-down control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdcrh](pdcrh) module
    pub type PDCRH = crate::Reg<u32, _PDCRH>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDCRH;
    ///`read()` method returns [pdcrh::R](pdcrh::R) reader structure
    impl crate::Readable for PDCRH {}
    ///`write(|w| ..)` method takes [pdcrh::W](pdcrh::W) writer structure
    impl crate::Writable for PDCRH {}
    ///Power Port H pull-down control register
    pub mod pdcrh {
        ///Reader of register PDCRH
        pub type R = crate::R<u32, super::PDCRH>;
        ///Writer for register PDCRH
        pub type W = crate::W<u32, super::PDCRH>;
        ///Register PDCRH `reset()`'s with value 0
        impl crate::ResetValue for super::PDCRH {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PD3`
        pub type PD3_R = crate::R<bool, bool>;
        ///Write proxy for field `PD3`
        pub struct PD3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `PD1`
        pub type PD1_R = crate::R<bool, bool>;
        ///Write proxy for field `PD1`
        pub struct PD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PD0`
        pub type PD0_R = crate::R<bool, bool>;
        ///Write proxy for field `PD0`
        pub struct PD0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PD0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 3 - Port H pull-down bit y (y=0..1)
            #[inline(always)]
            pub fn pd3(&self) -> PD3_R {
                PD3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Port H pull-down bit y (y=0..1)
            #[inline(always)]
            pub fn pd1(&self) -> PD1_R {
                PD1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port H pull-down bit y (y=0..1)
            #[inline(always)]
            pub fn pd0(&self) -> PD0_R {
                PD0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 3 - Port H pull-down bit y (y=0..1)
            #[inline(always)]
            pub fn pd3(&mut self) -> PD3_W {
                PD3_W { w: self }
            }
            ///Bit 1 - Port H pull-down bit y (y=0..1)
            #[inline(always)]
            pub fn pd1(&mut self) -> PD1_W {
                PD1_W { w: self }
            }
            ///Bit 0 - Port H pull-down bit y (y=0..1)
            #[inline(always)]
            pub fn pd0(&mut self) -> PD0_W {
                PD0_W { w: self }
            }
        }
    }
    ///CPU2 Power control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2cr1](c2cr1) module
    pub type C2CR1 = crate::Reg<u32, _C2CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2CR1;
    ///`read()` method returns [c2cr1::R](c2cr1::R) reader structure
    impl crate::Readable for C2CR1 {}
    ///`write(|w| ..)` method takes [c2cr1::W](c2cr1::W) writer structure
    impl crate::Writable for C2CR1 {}
    ///CPU2 Power control register 1
    pub mod c2cr1 {
        ///Reader of register C2CR1
        pub type R = crate::R<u32, super::C2CR1>;
        ///Writer for register C2CR1
        pub type W = crate::W<u32, super::C2CR1>;
        ///Register C2CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::C2CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `_802EWKUP`
        pub type _802EWKUP_R = crate::R<bool, bool>;
        ///Write proxy for field `_802EWKUP`
        pub struct _802EWKUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> _802EWKUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `BLEEWKUP`
        pub type BLEEWKUP_R = crate::R<bool, bool>;
        ///Write proxy for field `BLEEWKUP`
        pub struct BLEEWKUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BLEEWKUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `FPDS`
        pub type FPDS_R = crate::R<bool, bool>;
        ///Write proxy for field `FPDS`
        pub struct FPDS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FPDS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `FPDR`
        pub type FPDR_R = crate::R<bool, bool>;
        ///Write proxy for field `FPDR`
        pub struct FPDR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FPDR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `LPMS`
        pub type LPMS_R = crate::R<u8, u8>;
        ///Write proxy for field `LPMS`
        pub struct LPMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bit 15 - 802.15.4 external wakeup signal
            #[inline(always)]
            pub fn _802ewkup(&self) -> _802EWKUP_R {
                _802EWKUP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - BLE external wakeup signal
            #[inline(always)]
            pub fn bleewkup(&self) -> BLEEWKUP_R {
                BLEEWKUP_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 5 - Flash power down mode during LPSleep for CPU2
            #[inline(always)]
            pub fn fpds(&self) -> FPDS_R {
                FPDS_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Flash power down mode during LPRun for CPU2
            #[inline(always)]
            pub fn fpdr(&self) -> FPDR_R {
                FPDR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bits 0:2 - Low-power mode selection for CPU2
            #[inline(always)]
            pub fn lpms(&self) -> LPMS_R {
                LPMS_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bit 15 - 802.15.4 external wakeup signal
            #[inline(always)]
            pub fn _802ewkup(&mut self) -> _802EWKUP_W {
                _802EWKUP_W { w: self }
            }
            ///Bit 14 - BLE external wakeup signal
            #[inline(always)]
            pub fn bleewkup(&mut self) -> BLEEWKUP_W {
                BLEEWKUP_W { w: self }
            }
            ///Bit 5 - Flash power down mode during LPSleep for CPU2
            #[inline(always)]
            pub fn fpds(&mut self) -> FPDS_W {
                FPDS_W { w: self }
            }
            ///Bit 4 - Flash power down mode during LPRun for CPU2
            #[inline(always)]
            pub fn fpdr(&mut self) -> FPDR_W {
                FPDR_W { w: self }
            }
            ///Bits 0:2 - Low-power mode selection for CPU2
            #[inline(always)]
            pub fn lpms(&mut self) -> LPMS_W {
                LPMS_W { w: self }
            }
        }
    }
    ///CPU2 Power control register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2cr3](c2cr3) module
    pub type C2CR3 = crate::Reg<u32, _C2CR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2CR3;
    ///`read()` method returns [c2cr3::R](c2cr3::R) reader structure
    impl crate::Readable for C2CR3 {}
    ///`write(|w| ..)` method takes [c2cr3::W](c2cr3::W) writer structure
    impl crate::Writable for C2CR3 {}
    ///CPU2 Power control register 3
    pub mod c2cr3 {
        ///Reader of register C2CR3
        pub type R = crate::R<u32, super::C2CR3>;
        ///Writer for register C2CR3
        pub type W = crate::W<u32, super::C2CR3>;
        ///Register C2CR3 `reset()`'s with value 0x8000
        impl crate::ResetValue for super::C2CR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x8000
            }
        }
        ///Reader of field `EIWUL`
        pub type EIWUL_R = crate::R<bool, bool>;
        ///Write proxy for field `EIWUL`
        pub struct EIWUL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EIWUL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `APC`
        pub type APC_R = crate::R<bool, bool>;
        ///Write proxy for field `APC`
        pub struct APC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> APC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `E802WUP`
        pub type E802WUP_R = crate::R<bool, bool>;
        ///Write proxy for field `E802WUP`
        pub struct E802WUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> E802WUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `EBLEWUP`
        pub type EBLEWUP_R = crate::R<bool, bool>;
        ///Write proxy for field `EBLEWUP`
        pub struct EBLEWUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EBLEWUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `EWUP5`
        pub type EWUP5_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP5`
        pub struct EWUP5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `EWUP4`
        pub type EWUP4_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP4`
        pub struct EWUP4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `EWUP3`
        pub type EWUP3_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP3`
        pub struct EWUP3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `EWUP2`
        pub type EWUP2_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP2`
        pub struct EWUP2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EWUP1`
        pub type EWUP1_R = crate::R<bool, bool>;
        ///Write proxy for field `EWUP1`
        pub struct EWUP1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EWUP1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Enable internal wakeup line for CPU2
            #[inline(always)]
            pub fn eiwul(&self) -> EIWUL_R {
                EIWUL_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 12 - Apply pull-up and pull-down configuration for CPU2
            #[inline(always)]
            pub fn apc(&self) -> APC_R {
                APC_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 10 - Enable 802.15.4 host wakeup interrupt for CPU2
            #[inline(always)]
            pub fn e802wup(&self) -> E802WUP_R {
                E802WUP_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Enable BLE host wakeup interrupt for CPU2
            #[inline(always)]
            pub fn eblewup(&self) -> EBLEWUP_R {
                EBLEWUP_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 4 - Enable Wakeup pin WKUP5 for CPU2
            #[inline(always)]
            pub fn ewup5(&self) -> EWUP5_R {
                EWUP5_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Enable Wakeup pin WKUP4 for CPU2
            #[inline(always)]
            pub fn ewup4(&self) -> EWUP4_R {
                EWUP4_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Enable Wakeup pin WKUP3 for CPU2
            #[inline(always)]
            pub fn ewup3(&self) -> EWUP3_R {
                EWUP3_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Enable Wakeup pin WKUP2 for CPU2
            #[inline(always)]
            pub fn ewup2(&self) -> EWUP2_R {
                EWUP2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Enable Wakeup pin WKUP1 for CPU2
            #[inline(always)]
            pub fn ewup1(&self) -> EWUP1_R {
                EWUP1_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Enable internal wakeup line for CPU2
            #[inline(always)]
            pub fn eiwul(&mut self) -> EIWUL_W {
                EIWUL_W { w: self }
            }
            ///Bit 12 - Apply pull-up and pull-down configuration for CPU2
            #[inline(always)]
            pub fn apc(&mut self) -> APC_W {
                APC_W { w: self }
            }
            ///Bit 10 - Enable 802.15.4 host wakeup interrupt for CPU2
            #[inline(always)]
            pub fn e802wup(&mut self) -> E802WUP_W {
                E802WUP_W { w: self }
            }
            ///Bit 9 - Enable BLE host wakeup interrupt for CPU2
            #[inline(always)]
            pub fn eblewup(&mut self) -> EBLEWUP_W {
                EBLEWUP_W { w: self }
            }
            ///Bit 4 - Enable Wakeup pin WKUP5 for CPU2
            #[inline(always)]
            pub fn ewup5(&mut self) -> EWUP5_W {
                EWUP5_W { w: self }
            }
            ///Bit 3 - Enable Wakeup pin WKUP4 for CPU2
            #[inline(always)]
            pub fn ewup4(&mut self) -> EWUP4_W {
                EWUP4_W { w: self }
            }
            ///Bit 2 - Enable Wakeup pin WKUP3 for CPU2
            #[inline(always)]
            pub fn ewup3(&mut self) -> EWUP3_W {
                EWUP3_W { w: self }
            }
            ///Bit 1 - Enable Wakeup pin WKUP2 for CPU2
            #[inline(always)]
            pub fn ewup2(&mut self) -> EWUP2_W {
                EWUP2_W { w: self }
            }
            ///Bit 0 - Enable Wakeup pin WKUP1 for CPU2
            #[inline(always)]
            pub fn ewup1(&mut self) -> EWUP1_W {
                EWUP1_W { w: self }
            }
        }
    }
    ///Power status clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [extscr](extscr) module
    pub type EXTSCR = crate::Reg<u32, _EXTSCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EXTSCR;
    ///`read()` method returns [extscr::R](extscr::R) reader structure
    impl crate::Readable for EXTSCR {}
    ///`write(|w| ..)` method takes [extscr::W](extscr::W) writer structure
    impl crate::Writable for EXTSCR {}
    ///Power status clear register
    pub mod extscr {
        ///Reader of register EXTSCR
        pub type R = crate::R<u32, super::EXTSCR>;
        ///Writer for register EXTSCR
        pub type W = crate::W<u32, super::EXTSCR>;
        ///Register EXTSCR `reset()`'s with value 0
        impl crate::ResetValue for super::EXTSCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `C2DS`
        pub type C2DS_R = crate::R<bool, bool>;
        ///Reader of field `C1DS`
        pub type C1DS_R = crate::R<bool, bool>;
        ///Reader of field `CRPF`
        pub type CRPF_R = crate::R<bool, bool>;
        ///Reader of field `C2STOPF`
        pub type C2STOPF_R = crate::R<bool, bool>;
        ///Reader of field `C2SBF`
        pub type C2SBF_R = crate::R<bool, bool>;
        ///Reader of field `C1STOPF`
        pub type C1STOPF_R = crate::R<bool, bool>;
        ///Reader of field `C1SBF`
        pub type C1SBF_R = crate::R<bool, bool>;
        ///Write proxy for field `CCRPF`
        pub struct CCRPF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCRPF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `C2CSSF`
        pub struct C2CSSF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C2CSSF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `C1CSSF`
        pub struct C1CSSF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C1CSSF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - CPU2 deepsleep mode
            #[inline(always)]
            pub fn c2ds(&self) -> C2DS_R {
                C2DS_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - CPU1 deepsleep mode
            #[inline(always)]
            pub fn c1ds(&self) -> C1DS_R {
                C1DS_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Critical Radio system phase
            #[inline(always)]
            pub fn crpf(&self) -> CRPF_R {
                CRPF_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 11 - System Stop flag for CPU2
            #[inline(always)]
            pub fn c2stopf(&self) -> C2STOPF_R {
                C2STOPF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - System Standby flag for CPU2
            #[inline(always)]
            pub fn c2sbf(&self) -> C2SBF_R {
                C2SBF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - System Stop flag for CPU1
            #[inline(always)]
            pub fn c1stopf(&self) -> C1STOPF_R {
                C1STOPF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - System Standby flag for CPU1
            #[inline(always)]
            pub fn c1sbf(&self) -> C1SBF_R {
                C1SBF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 2 - Clear Critical Radio system phase
            #[inline(always)]
            pub fn ccrpf(&mut self) -> CCRPF_W {
                CCRPF_W { w: self }
            }
            ///Bit 1 - Clear CPU2 Stop Standby flags
            #[inline(always)]
            pub fn c2cssf(&mut self) -> C2CSSF_W {
                C2CSSF_W { w: self }
            }
            ///Bit 0 - Clear CPU1 Stop Standby flags
            #[inline(always)]
            pub fn c1cssf(&mut self) -> C1CSSF_W {
                C1CSSF_W { w: self }
            }
        }
    }
}
///System configuration controller
pub struct SYSCFG {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SYSCFG {}
impl SYSCFG {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const syscfg::RegisterBlock {
        0x4001_0100 as *const _
    }
}
impl Deref for SYSCFG {
    type Target = syscfg::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*SYSCFG::ptr() }
    }
}
///System configuration controller
pub mod syscfg {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - memory remap register
        pub memrmp: MEMRMP,
        ///0x04 - configuration register 1
        pub cfgr1: CFGR1,
        ///0x08 - external interrupt configuration register 1
        pub exticr1: EXTICR1,
        ///0x0c - external interrupt configuration register 2
        pub exticr2: EXTICR2,
        ///0x10 - external interrupt configuration register 3
        pub exticr3: EXTICR3,
        ///0x14 - external interrupt configuration register 4
        pub exticr4: EXTICR4,
        ///0x18 - SCSR
        pub scsr: SCSR,
        ///0x1c - CFGR2
        pub cfgr2: CFGR2,
        ///0x20 - SRAM2 write protection register
        pub swpr: SWPR,
        ///0x24 - SKR
        pub skr: SKR,
        ///0x28 - SRAM2 write protection register 2
        pub swpr2: SWPR2,
        ///0x2c - CPU1 interrupt mask register 1
        pub imr1: IMR1,
        ///0x30 - CPU1 interrupt mask register 2
        pub imr2: IMR2,
        ///0x34 - CPU2 interrupt mask register 1
        pub c2imr1: C2IMR1,
        ///0x38 - CPU2 interrupt mask register 1
        pub c2imr2: C2IMR2,
        ///0x3c - secure IP control register
        pub sipcr: SIPCR,
    }
    ///memory remap register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [memrmp](memrmp) module
    pub type MEMRMP = crate::Reg<u32, _MEMRMP>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _MEMRMP;
    ///`read()` method returns [memrmp::R](memrmp::R) reader structure
    impl crate::Readable for MEMRMP {}
    ///`write(|w| ..)` method takes [memrmp::W](memrmp::W) writer structure
    impl crate::Writable for MEMRMP {}
    ///memory remap register
    pub mod memrmp {
        ///Reader of register MEMRMP
        pub type R = crate::R<u32, super::MEMRMP>;
        ///Writer for register MEMRMP
        pub type W = crate::W<u32, super::MEMRMP>;
        ///Register MEMRMP `reset()`'s with value 0
        impl crate::ResetValue for super::MEMRMP {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MEM_MODE`
        pub type MEM_MODE_R = crate::R<u8, u8>;
        ///Write proxy for field `MEM_MODE`
        pub struct MEM_MODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MEM_MODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 0:2 - Memory mapping selection
            #[inline(always)]
            pub fn mem_mode(&self) -> MEM_MODE_R {
                MEM_MODE_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 0:2 - Memory mapping selection
            #[inline(always)]
            pub fn mem_mode(&mut self) -> MEM_MODE_W {
                MEM_MODE_W { w: self }
            }
        }
    }
    ///configuration register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfgr1](cfgr1) module
    pub type CFGR1 = crate::Reg<u32, _CFGR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFGR1;
    ///`read()` method returns [cfgr1::R](cfgr1::R) reader structure
    impl crate::Readable for CFGR1 {}
    ///`write(|w| ..)` method takes [cfgr1::W](cfgr1::W) writer structure
    impl crate::Writable for CFGR1 {}
    ///configuration register 1
    pub mod cfgr1 {
        ///Reader of register CFGR1
        pub type R = crate::R<u32, super::CFGR1>;
        ///Writer for register CFGR1
        pub type W = crate::W<u32, super::CFGR1>;
        ///Register CFGR1 `reset()`'s with value 0x7c00_0001
        impl crate::ResetValue for super::CFGR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x7c00_0001
            }
        }
        ///Reader of field `FPU_IE`
        pub type FPU_IE_R = crate::R<u8, u8>;
        ///Write proxy for field `FPU_IE`
        pub struct FPU_IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FPU_IE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x3f << 26)) | (((value as u32) & 0x3f) << 26);
                self.w
            }
        }
        ///Reader of field `I2C3_FMP`
        pub type I2C3_FMP_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C3_FMP`
        pub struct I2C3_FMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C3_FMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `I2C1_FMP`
        pub type I2C1_FMP_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C1_FMP`
        pub struct I2C1_FMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C1_FMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `I2C_PB9_FMP`
        pub type I2C_PB9_FMP_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C_PB9_FMP`
        pub struct I2C_PB9_FMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C_PB9_FMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `I2C_PB8_FMP`
        pub type I2C_PB8_FMP_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C_PB8_FMP`
        pub struct I2C_PB8_FMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C_PB8_FMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `I2C_PB7_FMP`
        pub type I2C_PB7_FMP_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C_PB7_FMP`
        pub struct I2C_PB7_FMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C_PB7_FMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `I2C_PB6_FMP`
        pub type I2C_PB6_FMP_R = crate::R<bool, bool>;
        ///Write proxy for field `I2C_PB6_FMP`
        pub struct I2C_PB6_FMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> I2C_PB6_FMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `BOOSTEN`
        pub type BOOSTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `BOOSTEN`
        pub struct BOOSTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BOOSTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        impl R {
            ///Bits 26:31 - Floating Point Unit interrupts enable bits
            #[inline(always)]
            pub fn fpu_ie(&self) -> FPU_IE_R {
                FPU_IE_R::new(((self.bits >> 26) & 0x3f) as u8)
            }
            ///Bit 22 - I2C3 Fast-mode Plus driving capability activation
            #[inline(always)]
            pub fn i2c3_fmp(&self) -> I2C3_FMP_R {
                I2C3_FMP_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 20 - I2C1 Fast-mode Plus driving capability activation
            #[inline(always)]
            pub fn i2c1_fmp(&self) -> I2C1_FMP_R {
                I2C1_FMP_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9
            #[inline(always)]
            pub fn i2c_pb9_fmp(&self) -> I2C_PB9_FMP_R {
                I2C_PB9_FMP_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8
            #[inline(always)]
            pub fn i2c_pb8_fmp(&self) -> I2C_PB8_FMP_R {
                I2C_PB8_FMP_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7
            #[inline(always)]
            pub fn i2c_pb7_fmp(&self) -> I2C_PB7_FMP_R {
                I2C_PB7_FMP_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6
            #[inline(always)]
            pub fn i2c_pb6_fmp(&self) -> I2C_PB6_FMP_R {
                I2C_PB6_FMP_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 8 - I/O analog switch voltage booster enable
            #[inline(always)]
            pub fn boosten(&self) -> BOOSTEN_R {
                BOOSTEN_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 26:31 - Floating Point Unit interrupts enable bits
            #[inline(always)]
            pub fn fpu_ie(&mut self) -> FPU_IE_W {
                FPU_IE_W { w: self }
            }
            ///Bit 22 - I2C3 Fast-mode Plus driving capability activation
            #[inline(always)]
            pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W {
                I2C3_FMP_W { w: self }
            }
            ///Bit 20 - I2C1 Fast-mode Plus driving capability activation
            #[inline(always)]
            pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W {
                I2C1_FMP_W { w: self }
            }
            ///Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9
            #[inline(always)]
            pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W {
                I2C_PB9_FMP_W { w: self }
            }
            ///Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8
            #[inline(always)]
            pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W {
                I2C_PB8_FMP_W { w: self }
            }
            ///Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7
            #[inline(always)]
            pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W {
                I2C_PB7_FMP_W { w: self }
            }
            ///Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6
            #[inline(always)]
            pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W {
                I2C_PB6_FMP_W { w: self }
            }
            ///Bit 8 - I/O analog switch voltage booster enable
            #[inline(always)]
            pub fn boosten(&mut self) -> BOOSTEN_W {
                BOOSTEN_W { w: self }
            }
        }
    }
    ///external interrupt configuration register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [exticr1](exticr1) module
    pub type EXTICR1 = crate::Reg<u32, _EXTICR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EXTICR1;
    ///`read()` method returns [exticr1::R](exticr1::R) reader structure
    impl crate::Readable for EXTICR1 {}
    ///`write(|w| ..)` method takes [exticr1::W](exticr1::W) writer structure
    impl crate::Writable for EXTICR1 {}
    ///external interrupt configuration register 1
    pub mod exticr1 {
        ///Reader of register EXTICR1
        pub type R = crate::R<u32, super::EXTICR1>;
        ///Writer for register EXTICR1
        pub type W = crate::W<u32, super::EXTICR1>;
        ///Register EXTICR1 `reset()`'s with value 0
        impl crate::ResetValue for super::EXTICR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EXTI3`
        pub type EXTI3_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI3`
        pub struct EXTI3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `EXTI2`
        pub type EXTI2_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI2`
        pub struct EXTI2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `EXTI1`
        pub type EXTI1_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI1`
        pub struct EXTI1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `EXTI0`
        pub type EXTI0_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI0`
        pub struct EXTI0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 12:14 - EXTI 3 configuration bits
            #[inline(always)]
            pub fn exti3(&self) -> EXTI3_R {
                EXTI3_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:10 - EXTI 2 configuration bits
            #[inline(always)]
            pub fn exti2(&self) -> EXTI2_R {
                EXTI2_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bits 4:6 - EXTI 1 configuration bits
            #[inline(always)]
            pub fn exti1(&self) -> EXTI1_R {
                EXTI1_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:2 - EXTI 0 configuration bits
            #[inline(always)]
            pub fn exti0(&self) -> EXTI0_R {
                EXTI0_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 12:14 - EXTI 3 configuration bits
            #[inline(always)]
            pub fn exti3(&mut self) -> EXTI3_W {
                EXTI3_W { w: self }
            }
            ///Bits 8:10 - EXTI 2 configuration bits
            #[inline(always)]
            pub fn exti2(&mut self) -> EXTI2_W {
                EXTI2_W { w: self }
            }
            ///Bits 4:6 - EXTI 1 configuration bits
            #[inline(always)]
            pub fn exti1(&mut self) -> EXTI1_W {
                EXTI1_W { w: self }
            }
            ///Bits 0:2 - EXTI 0 configuration bits
            #[inline(always)]
            pub fn exti0(&mut self) -> EXTI0_W {
                EXTI0_W { w: self }
            }
        }
    }
    ///external interrupt configuration register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [exticr2](exticr2) module
    pub type EXTICR2 = crate::Reg<u32, _EXTICR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EXTICR2;
    ///`read()` method returns [exticr2::R](exticr2::R) reader structure
    impl crate::Readable for EXTICR2 {}
    ///`write(|w| ..)` method takes [exticr2::W](exticr2::W) writer structure
    impl crate::Writable for EXTICR2 {}
    ///external interrupt configuration register 2
    pub mod exticr2 {
        ///Reader of register EXTICR2
        pub type R = crate::R<u32, super::EXTICR2>;
        ///Writer for register EXTICR2
        pub type W = crate::W<u32, super::EXTICR2>;
        ///Register EXTICR2 `reset()`'s with value 0
        impl crate::ResetValue for super::EXTICR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EXTI7`
        pub type EXTI7_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI7`
        pub struct EXTI7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `EXTI6`
        pub type EXTI6_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI6`
        pub struct EXTI6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `EXTI5`
        pub type EXTI5_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI5`
        pub struct EXTI5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `EXTI4`
        pub type EXTI4_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI4`
        pub struct EXTI4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 12:14 - EXTI 7 configuration bits
            #[inline(always)]
            pub fn exti7(&self) -> EXTI7_R {
                EXTI7_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:10 - EXTI 6 configuration bits
            #[inline(always)]
            pub fn exti6(&self) -> EXTI6_R {
                EXTI6_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bits 4:6 - EXTI 5 configuration bits
            #[inline(always)]
            pub fn exti5(&self) -> EXTI5_R {
                EXTI5_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:2 - EXTI 4 configuration bits
            #[inline(always)]
            pub fn exti4(&self) -> EXTI4_R {
                EXTI4_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 12:14 - EXTI 7 configuration bits
            #[inline(always)]
            pub fn exti7(&mut self) -> EXTI7_W {
                EXTI7_W { w: self }
            }
            ///Bits 8:10 - EXTI 6 configuration bits
            #[inline(always)]
            pub fn exti6(&mut self) -> EXTI6_W {
                EXTI6_W { w: self }
            }
            ///Bits 4:6 - EXTI 5 configuration bits
            #[inline(always)]
            pub fn exti5(&mut self) -> EXTI5_W {
                EXTI5_W { w: self }
            }
            ///Bits 0:2 - EXTI 4 configuration bits
            #[inline(always)]
            pub fn exti4(&mut self) -> EXTI4_W {
                EXTI4_W { w: self }
            }
        }
    }
    ///external interrupt configuration register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [exticr3](exticr3) module
    pub type EXTICR3 = crate::Reg<u32, _EXTICR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EXTICR3;
    ///`read()` method returns [exticr3::R](exticr3::R) reader structure
    impl crate::Readable for EXTICR3 {}
    ///`write(|w| ..)` method takes [exticr3::W](exticr3::W) writer structure
    impl crate::Writable for EXTICR3 {}
    ///external interrupt configuration register 3
    pub mod exticr3 {
        ///Reader of register EXTICR3
        pub type R = crate::R<u32, super::EXTICR3>;
        ///Writer for register EXTICR3
        pub type W = crate::W<u32, super::EXTICR3>;
        ///Register EXTICR3 `reset()`'s with value 0
        impl crate::ResetValue for super::EXTICR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EXTI11`
        pub type EXTI11_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI11`
        pub struct EXTI11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `EXTI10`
        pub type EXTI10_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI10`
        pub struct EXTI10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `EXTI9`
        pub type EXTI9_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI9`
        pub struct EXTI9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `EXTI8`
        pub type EXTI8_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI8`
        pub struct EXTI8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 12:14 - EXTI 11 configuration bits
            #[inline(always)]
            pub fn exti11(&self) -> EXTI11_R {
                EXTI11_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:10 - EXTI 10 configuration bits
            #[inline(always)]
            pub fn exti10(&self) -> EXTI10_R {
                EXTI10_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bits 4:6 - EXTI 9 configuration bits
            #[inline(always)]
            pub fn exti9(&self) -> EXTI9_R {
                EXTI9_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:2 - EXTI 8 configuration bits
            #[inline(always)]
            pub fn exti8(&self) -> EXTI8_R {
                EXTI8_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 12:14 - EXTI 11 configuration bits
            #[inline(always)]
            pub fn exti11(&mut self) -> EXTI11_W {
                EXTI11_W { w: self }
            }
            ///Bits 8:10 - EXTI 10 configuration bits
            #[inline(always)]
            pub fn exti10(&mut self) -> EXTI10_W {
                EXTI10_W { w: self }
            }
            ///Bits 4:6 - EXTI 9 configuration bits
            #[inline(always)]
            pub fn exti9(&mut self) -> EXTI9_W {
                EXTI9_W { w: self }
            }
            ///Bits 0:2 - EXTI 8 configuration bits
            #[inline(always)]
            pub fn exti8(&mut self) -> EXTI8_W {
                EXTI8_W { w: self }
            }
        }
    }
    ///external interrupt configuration register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [exticr4](exticr4) module
    pub type EXTICR4 = crate::Reg<u32, _EXTICR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EXTICR4;
    ///`read()` method returns [exticr4::R](exticr4::R) reader structure
    impl crate::Readable for EXTICR4 {}
    ///`write(|w| ..)` method takes [exticr4::W](exticr4::W) writer structure
    impl crate::Writable for EXTICR4 {}
    ///external interrupt configuration register 4
    pub mod exticr4 {
        ///Reader of register EXTICR4
        pub type R = crate::R<u32, super::EXTICR4>;
        ///Writer for register EXTICR4
        pub type W = crate::W<u32, super::EXTICR4>;
        ///Register EXTICR4 `reset()`'s with value 0
        impl crate::ResetValue for super::EXTICR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EXTI15`
        pub type EXTI15_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI15`
        pub struct EXTI15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `EXTI14`
        pub type EXTI14_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI14`
        pub struct EXTI14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `EXTI13`
        pub type EXTI13_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI13`
        pub struct EXTI13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `EXTI12`
        pub type EXTI12_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTI12`
        pub struct EXTI12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTI12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 12:14 - EXTI15 configuration bits
            #[inline(always)]
            pub fn exti15(&self) -> EXTI15_R {
                EXTI15_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:10 - EXTI14 configuration bits
            #[inline(always)]
            pub fn exti14(&self) -> EXTI14_R {
                EXTI14_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bits 4:6 - EXTI13 configuration bits
            #[inline(always)]
            pub fn exti13(&self) -> EXTI13_R {
                EXTI13_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:2 - EXTI12 configuration bits
            #[inline(always)]
            pub fn exti12(&self) -> EXTI12_R {
                EXTI12_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 12:14 - EXTI15 configuration bits
            #[inline(always)]
            pub fn exti15(&mut self) -> EXTI15_W {
                EXTI15_W { w: self }
            }
            ///Bits 8:10 - EXTI14 configuration bits
            #[inline(always)]
            pub fn exti14(&mut self) -> EXTI14_W {
                EXTI14_W { w: self }
            }
            ///Bits 4:6 - EXTI13 configuration bits
            #[inline(always)]
            pub fn exti13(&mut self) -> EXTI13_W {
                EXTI13_W { w: self }
            }
            ///Bits 0:2 - EXTI12 configuration bits
            #[inline(always)]
            pub fn exti12(&mut self) -> EXTI12_W {
                EXTI12_W { w: self }
            }
        }
    }
    ///SCSR
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [scsr](scsr) module
    pub type SCSR = crate::Reg<u32, _SCSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SCSR;
    ///`read()` method returns [scsr::R](scsr::R) reader structure
    impl crate::Readable for SCSR {}
    ///`write(|w| ..)` method takes [scsr::W](scsr::W) writer structure
    impl crate::Writable for SCSR {}
    ///SCSR
    pub mod scsr {
        ///Reader of register SCSR
        pub type R = crate::R<u32, super::SCSR>;
        ///Writer for register SCSR
        pub type W = crate::W<u32, super::SCSR>;
        ///Register SCSR `reset()`'s with value 0
        impl crate::ResetValue for super::SCSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SRAM2BSY`
        pub type SRAM2BSY_R = crate::R<bool, bool>;
        ///Reader of field `SRAM2ER`
        pub type SRAM2ER_R = crate::R<bool, bool>;
        ///Write proxy for field `SRAM2ER`
        pub struct SRAM2ER_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRAM2ER_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `C2RFD`
        pub type C2RFD_R = crate::R<bool, bool>;
        ///Write proxy for field `C2RFD`
        pub struct C2RFD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C2RFD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bit 1 - SRAM2 busy by erase operation
            #[inline(always)]
            pub fn sram2bsy(&self) -> SRAM2BSY_R {
                SRAM2BSY_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - SRAM2 Erase
            #[inline(always)]
            pub fn sram2er(&self) -> SRAM2ER_R {
                SRAM2ER_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 31 - CPU2 SRAM fetch (execution) disable.
            #[inline(always)]
            pub fn c2rfd(&self) -> C2RFD_R {
                C2RFD_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - SRAM2 Erase
            #[inline(always)]
            pub fn sram2er(&mut self) -> SRAM2ER_W {
                SRAM2ER_W { w: self }
            }
            ///Bit 31 - CPU2 SRAM fetch (execution) disable.
            #[inline(always)]
            pub fn c2rfd(&mut self) -> C2RFD_W {
                C2RFD_W { w: self }
            }
        }
    }
    ///CFGR2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfgr2](cfgr2) module
    pub type CFGR2 = crate::Reg<u32, _CFGR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFGR2;
    ///`read()` method returns [cfgr2::R](cfgr2::R) reader structure
    impl crate::Readable for CFGR2 {}
    ///`write(|w| ..)` method takes [cfgr2::W](cfgr2::W) writer structure
    impl crate::Writable for CFGR2 {}
    ///CFGR2
    pub mod cfgr2 {
        ///Reader of register CFGR2
        pub type R = crate::R<u32, super::CFGR2>;
        ///Writer for register CFGR2
        pub type W = crate::W<u32, super::CFGR2>;
        ///Register CFGR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CFGR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SPF`
        pub type SPF_R = crate::R<bool, bool>;
        ///Write proxy for field `SPF`
        pub struct SPF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `ECCL`
        pub struct ECCL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ECCL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `PVDL`
        pub struct PVDL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVDL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `SPL`
        pub struct SPL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CLL`
        pub struct CLL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CLL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 8 - SRAM2 parity error flag
            #[inline(always)]
            pub fn spf(&self) -> SPF_R {
                SPF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 8 - SRAM2 parity error flag
            #[inline(always)]
            pub fn spf(&mut self) -> SPF_W {
                SPF_W { w: self }
            }
            ///Bit 3 - ECC Lock
            #[inline(always)]
            pub fn eccl(&mut self) -> ECCL_W {
                ECCL_W { w: self }
            }
            ///Bit 2 - PVD lock enable bit
            #[inline(always)]
            pub fn pvdl(&mut self) -> PVDL_W {
                PVDL_W { w: self }
            }
            ///Bit 1 - SRAM2 parity lock bit
            #[inline(always)]
            pub fn spl(&mut self) -> SPL_W {
                SPL_W { w: self }
            }
            ///Bit 0 - Cortex-M4 LOCKUP (Hardfault) output enable bit
            #[inline(always)]
            pub fn cll(&mut self) -> CLL_W {
                CLL_W { w: self }
            }
        }
    }
    ///SRAM2 write protection register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [swpr](swpr) module
    pub type SWPR = crate::Reg<u32, _SWPR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SWPR;
    ///`write(|w| ..)` method takes [swpr::W](swpr::W) writer structure
    impl crate::Writable for SWPR {}
    ///SRAM2 write protection register
    pub mod swpr {
        ///Writer for register SWPR
        pub type W = crate::W<u32, super::SWPR>;
        ///Register SWPR `reset()`'s with value 0
        impl crate::ResetValue for super::SWPR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `P31WP`
        pub struct P31WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P31WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Write proxy for field `P30WP`
        pub struct P30WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P30WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Write proxy for field `P29WP`
        pub struct P29WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P29WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Write proxy for field `P28WP`
        pub struct P28WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P28WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Write proxy for field `P27WP`
        pub struct P27WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P27WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Write proxy for field `P26WP`
        pub struct P26WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P26WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Write proxy for field `P25WP`
        pub struct P25WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P25WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Write proxy for field `P24WP`
        pub struct P24WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P24WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Write proxy for field `P23WP`
        pub struct P23WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P23WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Write proxy for field `P22WP`
        pub struct P22WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P22WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Write proxy for field `P21WP`
        pub struct P21WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P21WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `P20WP`
        pub struct P20WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P20WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `P19WP`
        pub struct P19WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P19WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `P18WP`
        pub struct P18WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P18WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `P17WP`
        pub struct P17WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P17WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `P16WP`
        pub struct P16WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P16WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `P15WP`
        pub struct P15WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P15WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Write proxy for field `P14WP`
        pub struct P14WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P14WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `P13WP`
        pub struct P13WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P13WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `P12WP`
        pub struct P12WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P12WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `P11WP`
        pub struct P11WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P11WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `P10WP`
        pub struct P10WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P10WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `P9WP`
        pub struct P9WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P9WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `P8WP`
        pub struct P8WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P8WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `P7WP`
        pub struct P7WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P7WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `P6WP`
        pub struct P6WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P6WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `P5WP`
        pub struct P5WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P5WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `P4WP`
        pub struct P4WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P4WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `P3WP`
        pub struct P3WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P3WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `P2WP`
        pub struct P2WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P2WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `P1WP`
        pub struct P1WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P1WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `P0WP`
        pub struct P0WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P0WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 31 - SRAM2 page 31 write protection
            #[inline(always)]
            pub fn p31wp(&mut self) -> P31WP_W {
                P31WP_W { w: self }
            }
            ///Bit 30 - P30WP
            #[inline(always)]
            pub fn p30wp(&mut self) -> P30WP_W {
                P30WP_W { w: self }
            }
            ///Bit 29 - P29WP
            #[inline(always)]
            pub fn p29wp(&mut self) -> P29WP_W {
                P29WP_W { w: self }
            }
            ///Bit 28 - P28WP
            #[inline(always)]
            pub fn p28wp(&mut self) -> P28WP_W {
                P28WP_W { w: self }
            }
            ///Bit 27 - P27WP
            #[inline(always)]
            pub fn p27wp(&mut self) -> P27WP_W {
                P27WP_W { w: self }
            }
            ///Bit 26 - P26WP
            #[inline(always)]
            pub fn p26wp(&mut self) -> P26WP_W {
                P26WP_W { w: self }
            }
            ///Bit 25 - P25WP
            #[inline(always)]
            pub fn p25wp(&mut self) -> P25WP_W {
                P25WP_W { w: self }
            }
            ///Bit 24 - P24WP
            #[inline(always)]
            pub fn p24wp(&mut self) -> P24WP_W {
                P24WP_W { w: self }
            }
            ///Bit 23 - P23WP
            #[inline(always)]
            pub fn p23wp(&mut self) -> P23WP_W {
                P23WP_W { w: self }
            }
            ///Bit 22 - P22WP
            #[inline(always)]
            pub fn p22wp(&mut self) -> P22WP_W {
                P22WP_W { w: self }
            }
            ///Bit 21 - P21WP
            #[inline(always)]
            pub fn p21wp(&mut self) -> P21WP_W {
                P21WP_W { w: self }
            }
            ///Bit 20 - P20WP
            #[inline(always)]
            pub fn p20wp(&mut self) -> P20WP_W {
                P20WP_W { w: self }
            }
            ///Bit 19 - P19WP
            #[inline(always)]
            pub fn p19wp(&mut self) -> P19WP_W {
                P19WP_W { w: self }
            }
            ///Bit 18 - P18WP
            #[inline(always)]
            pub fn p18wp(&mut self) -> P18WP_W {
                P18WP_W { w: self }
            }
            ///Bit 17 - P17WP
            #[inline(always)]
            pub fn p17wp(&mut self) -> P17WP_W {
                P17WP_W { w: self }
            }
            ///Bit 16 - P16WP
            #[inline(always)]
            pub fn p16wp(&mut self) -> P16WP_W {
                P16WP_W { w: self }
            }
            ///Bit 15 - P15WP
            #[inline(always)]
            pub fn p15wp(&mut self) -> P15WP_W {
                P15WP_W { w: self }
            }
            ///Bit 14 - P14WP
            #[inline(always)]
            pub fn p14wp(&mut self) -> P14WP_W {
                P14WP_W { w: self }
            }
            ///Bit 13 - P13WP
            #[inline(always)]
            pub fn p13wp(&mut self) -> P13WP_W {
                P13WP_W { w: self }
            }
            ///Bit 12 - P12WP
            #[inline(always)]
            pub fn p12wp(&mut self) -> P12WP_W {
                P12WP_W { w: self }
            }
            ///Bit 11 - P11WP
            #[inline(always)]
            pub fn p11wp(&mut self) -> P11WP_W {
                P11WP_W { w: self }
            }
            ///Bit 10 - P10WP
            #[inline(always)]
            pub fn p10wp(&mut self) -> P10WP_W {
                P10WP_W { w: self }
            }
            ///Bit 9 - P9WP
            #[inline(always)]
            pub fn p9wp(&mut self) -> P9WP_W {
                P9WP_W { w: self }
            }
            ///Bit 8 - P8WP
            #[inline(always)]
            pub fn p8wp(&mut self) -> P8WP_W {
                P8WP_W { w: self }
            }
            ///Bit 7 - P7WP
            #[inline(always)]
            pub fn p7wp(&mut self) -> P7WP_W {
                P7WP_W { w: self }
            }
            ///Bit 6 - P6WP
            #[inline(always)]
            pub fn p6wp(&mut self) -> P6WP_W {
                P6WP_W { w: self }
            }
            ///Bit 5 - P5WP
            #[inline(always)]
            pub fn p5wp(&mut self) -> P5WP_W {
                P5WP_W { w: self }
            }
            ///Bit 4 - P4WP
            #[inline(always)]
            pub fn p4wp(&mut self) -> P4WP_W {
                P4WP_W { w: self }
            }
            ///Bit 3 - P3WP
            #[inline(always)]
            pub fn p3wp(&mut self) -> P3WP_W {
                P3WP_W { w: self }
            }
            ///Bit 2 - P2WP
            #[inline(always)]
            pub fn p2wp(&mut self) -> P2WP_W {
                P2WP_W { w: self }
            }
            ///Bit 1 - P1WP
            #[inline(always)]
            pub fn p1wp(&mut self) -> P1WP_W {
                P1WP_W { w: self }
            }
            ///Bit 0 - P0WP
            #[inline(always)]
            pub fn p0wp(&mut self) -> P0WP_W {
                P0WP_W { w: self }
            }
        }
    }
    ///SKR
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [skr](skr) module
    pub type SKR = crate::Reg<u32, _SKR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SKR;
    ///`write(|w| ..)` method takes [skr::W](skr::W) writer structure
    impl crate::Writable for SKR {}
    ///SKR
    pub mod skr {
        ///Writer for register SKR
        pub type W = crate::W<u32, super::SKR>;
        ///Register SKR `reset()`'s with value 0
        impl crate::ResetValue for super::SKR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `KEY`
        pub struct KEY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl W {
            ///Bits 0:7 - SRAM2 write protection key for software erase
            #[inline(always)]
            pub fn key(&mut self) -> KEY_W {
                KEY_W { w: self }
            }
        }
    }
    ///SRAM2 write protection register 2
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [swpr2](swpr2) module
    pub type SWPR2 = crate::Reg<u32, _SWPR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SWPR2;
    ///`write(|w| ..)` method takes [swpr2::W](swpr2::W) writer structure
    impl crate::Writable for SWPR2 {}
    ///SRAM2 write protection register 2
    pub mod swpr2 {
        ///Writer for register SWPR2
        pub type W = crate::W<u32, super::SWPR2>;
        ///Register SWPR2 `reset()`'s with value 0
        impl crate::ResetValue for super::SWPR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `P63WP`
        pub struct P63WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P63WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Write proxy for field `P62WP`
        pub struct P62WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P62WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Write proxy for field `P61WP`
        pub struct P61WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P61WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Write proxy for field `P60WP`
        pub struct P60WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P60WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Write proxy for field `P59WP`
        pub struct P59WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P59WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Write proxy for field `P58WP`
        pub struct P58WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P58WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Write proxy for field `P57WP`
        pub struct P57WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P57WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Write proxy for field `P56WP`
        pub struct P56WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P56WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Write proxy for field `P55WP`
        pub struct P55WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P55WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Write proxy for field `P54WP`
        pub struct P54WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P54WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Write proxy for field `P53WP`
        pub struct P53WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P53WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `P52WP`
        pub struct P52WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P52WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `P51WP`
        pub struct P51WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P51WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `P50WP`
        pub struct P50WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P50WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `P49WP`
        pub struct P49WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P49WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `P48WP`
        pub struct P48WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P48WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `P47WP`
        pub struct P47WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P47WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Write proxy for field `P46WP`
        pub struct P46WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P46WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `P45WP`
        pub struct P45WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P45WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `P44WP`
        pub struct P44WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P44WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `P43WP`
        pub struct P43WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P43WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `P42WP`
        pub struct P42WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P42WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `P41WP`
        pub struct P41WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P41WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `P40WP`
        pub struct P40WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P40WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `P39WP`
        pub struct P39WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P39WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `P38WP`
        pub struct P38WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P38WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `P37WP`
        pub struct P37WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P37WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `P36WP`
        pub struct P36WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P36WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `P35WP`
        pub struct P35WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P35WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `P34WP`
        pub struct P34WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P34WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `P33WP`
        pub struct P33WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P33WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `P32WP`
        pub struct P32WP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> P32WP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 31 - SRAM2 page 63 write protection
            #[inline(always)]
            pub fn p63wp(&mut self) -> P63WP_W {
                P63WP_W { w: self }
            }
            ///Bit 30 - P62WP
            #[inline(always)]
            pub fn p62wp(&mut self) -> P62WP_W {
                P62WP_W { w: self }
            }
            ///Bit 29 - P61WP
            #[inline(always)]
            pub fn p61wp(&mut self) -> P61WP_W {
                P61WP_W { w: self }
            }
            ///Bit 28 - P60WP
            #[inline(always)]
            pub fn p60wp(&mut self) -> P60WP_W {
                P60WP_W { w: self }
            }
            ///Bit 27 - P59WP
            #[inline(always)]
            pub fn p59wp(&mut self) -> P59WP_W {
                P59WP_W { w: self }
            }
            ///Bit 26 - P58WP
            #[inline(always)]
            pub fn p58wp(&mut self) -> P58WP_W {
                P58WP_W { w: self }
            }
            ///Bit 25 - P57WP
            #[inline(always)]
            pub fn p57wp(&mut self) -> P57WP_W {
                P57WP_W { w: self }
            }
            ///Bit 24 - P56WP
            #[inline(always)]
            pub fn p56wp(&mut self) -> P56WP_W {
                P56WP_W { w: self }
            }
            ///Bit 23 - P55WP
            #[inline(always)]
            pub fn p55wp(&mut self) -> P55WP_W {
                P55WP_W { w: self }
            }
            ///Bit 22 - P54WP
            #[inline(always)]
            pub fn p54wp(&mut self) -> P54WP_W {
                P54WP_W { w: self }
            }
            ///Bit 21 - P53WP
            #[inline(always)]
            pub fn p53wp(&mut self) -> P53WP_W {
                P53WP_W { w: self }
            }
            ///Bit 20 - P52WP
            #[inline(always)]
            pub fn p52wp(&mut self) -> P52WP_W {
                P52WP_W { w: self }
            }
            ///Bit 19 - P51WP
            #[inline(always)]
            pub fn p51wp(&mut self) -> P51WP_W {
                P51WP_W { w: self }
            }
            ///Bit 18 - P50WP
            #[inline(always)]
            pub fn p50wp(&mut self) -> P50WP_W {
                P50WP_W { w: self }
            }
            ///Bit 17 - P49WP
            #[inline(always)]
            pub fn p49wp(&mut self) -> P49WP_W {
                P49WP_W { w: self }
            }
            ///Bit 16 - P48WP
            #[inline(always)]
            pub fn p48wp(&mut self) -> P48WP_W {
                P48WP_W { w: self }
            }
            ///Bit 15 - P47WP
            #[inline(always)]
            pub fn p47wp(&mut self) -> P47WP_W {
                P47WP_W { w: self }
            }
            ///Bit 14 - P46WP
            #[inline(always)]
            pub fn p46wp(&mut self) -> P46WP_W {
                P46WP_W { w: self }
            }
            ///Bit 13 - P45WP
            #[inline(always)]
            pub fn p45wp(&mut self) -> P45WP_W {
                P45WP_W { w: self }
            }
            ///Bit 12 - P44WP
            #[inline(always)]
            pub fn p44wp(&mut self) -> P44WP_W {
                P44WP_W { w: self }
            }
            ///Bit 11 - P43WP
            #[inline(always)]
            pub fn p43wp(&mut self) -> P43WP_W {
                P43WP_W { w: self }
            }
            ///Bit 10 - P42WP
            #[inline(always)]
            pub fn p42wp(&mut self) -> P42WP_W {
                P42WP_W { w: self }
            }
            ///Bit 9 - P41WP
            #[inline(always)]
            pub fn p41wp(&mut self) -> P41WP_W {
                P41WP_W { w: self }
            }
            ///Bit 8 - P40WP
            #[inline(always)]
            pub fn p40wp(&mut self) -> P40WP_W {
                P40WP_W { w: self }
            }
            ///Bit 7 - P39WP
            #[inline(always)]
            pub fn p39wp(&mut self) -> P39WP_W {
                P39WP_W { w: self }
            }
            ///Bit 6 - P38WP
            #[inline(always)]
            pub fn p38wp(&mut self) -> P38WP_W {
                P38WP_W { w: self }
            }
            ///Bit 5 - P37WP
            #[inline(always)]
            pub fn p37wp(&mut self) -> P37WP_W {
                P37WP_W { w: self }
            }
            ///Bit 4 - P36WP
            #[inline(always)]
            pub fn p36wp(&mut self) -> P36WP_W {
                P36WP_W { w: self }
            }
            ///Bit 3 - P35WP
            #[inline(always)]
            pub fn p35wp(&mut self) -> P35WP_W {
                P35WP_W { w: self }
            }
            ///Bit 2 - P34WP
            #[inline(always)]
            pub fn p34wp(&mut self) -> P34WP_W {
                P34WP_W { w: self }
            }
            ///Bit 1 - P33WP
            #[inline(always)]
            pub fn p33wp(&mut self) -> P33WP_W {
                P33WP_W { w: self }
            }
            ///Bit 0 - P32WP
            #[inline(always)]
            pub fn p32wp(&mut self) -> P32WP_W {
                P32WP_W { w: self }
            }
        }
    }
    ///CPU1 interrupt mask register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [imr1](imr1) module
    pub type IMR1 = crate::Reg<u32, _IMR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IMR1;
    ///`read()` method returns [imr1::R](imr1::R) reader structure
    impl crate::Readable for IMR1 {}
    ///`write(|w| ..)` method takes [imr1::W](imr1::W) writer structure
    impl crate::Writable for IMR1 {}
    ///CPU1 interrupt mask register 1
    pub mod imr1 {
        ///Reader of register IMR1
        pub type R = crate::R<u32, super::IMR1>;
        ///Writer for register IMR1
        pub type W = crate::W<u32, super::IMR1>;
        ///Register IMR1 `reset()`'s with value 0
        impl crate::ResetValue for super::IMR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TIM1IM`
        pub type TIM1IM_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM1IM`
        pub struct TIM1IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM1IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `TIM16IM`
        pub type TIM16IM_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM16IM`
        pub struct TIM16IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM16IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `TIM17IM`
        pub type TIM17IM_R = crate::R<bool, bool>;
        ///Write proxy for field `TIM17IM`
        pub struct TIM17IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM17IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `EXIT5IM`
        pub type EXIT5IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT5IM`
        pub struct EXIT5IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT5IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `EXIT6IM`
        pub type EXIT6IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT6IM`
        pub struct EXIT6IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT6IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `EXIT7IM`
        pub type EXIT7IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT7IM`
        pub struct EXIT7IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT7IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `EXIT8IM`
        pub type EXIT8IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT8IM`
        pub struct EXIT8IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT8IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `EXIT9IM`
        pub type EXIT9IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT9IM`
        pub struct EXIT9IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT9IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `EXIT10IM`
        pub type EXIT10IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT10IM`
        pub struct EXIT10IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT10IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `EXIT11IM`
        pub type EXIT11IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT11IM`
        pub struct EXIT11IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT11IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `EXIT12IM`
        pub type EXIT12IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT12IM`
        pub struct EXIT12IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT12IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `EXIT13IM`
        pub type EXIT13IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT13IM`
        pub struct EXIT13IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT13IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `EXIT14IM`
        pub type EXIT14IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT14IM`
        pub struct EXIT14IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT14IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `EXIT15IM`
        pub type EXIT15IM_R = crate::R<bool, bool>;
        ///Write proxy for field `EXIT15IM`
        pub struct EXIT15IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXIT15IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bit 13 - Peripheral TIM1 interrupt mask to CPU1
            #[inline(always)]
            pub fn tim1im(&self) -> TIM1IM_R {
                TIM1IM_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Peripheral TIM16 interrupt mask to CPU1
            #[inline(always)]
            pub fn tim16im(&self) -> TIM16IM_R {
                TIM16IM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Peripheral TIM17 interrupt mask to CPU1
            #[inline(always)]
            pub fn tim17im(&self) -> TIM17IM_R {
                TIM17IM_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 21 - Peripheral EXIT5 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit5im(&self) -> EXIT5IM_R {
                EXIT5IM_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 22 - Peripheral EXIT6 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit6im(&self) -> EXIT6IM_R {
                EXIT6IM_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 23 - Peripheral EXIT7 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit7im(&self) -> EXIT7IM_R {
                EXIT7IM_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 24 - Peripheral EXIT8 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit8im(&self) -> EXIT8IM_R {
                EXIT8IM_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 25 - Peripheral EXIT9 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit9im(&self) -> EXIT9IM_R {
                EXIT9IM_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 26 - Peripheral EXIT10 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit10im(&self) -> EXIT10IM_R {
                EXIT10IM_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 27 - Peripheral EXIT11 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit11im(&self) -> EXIT11IM_R {
                EXIT11IM_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 28 - Peripheral EXIT12 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit12im(&self) -> EXIT12IM_R {
                EXIT12IM_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 29 - Peripheral EXIT13 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit13im(&self) -> EXIT13IM_R {
                EXIT13IM_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 30 - Peripheral EXIT14 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit14im(&self) -> EXIT14IM_R {
                EXIT14IM_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - Peripheral EXIT15 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit15im(&self) -> EXIT15IM_R {
                EXIT15IM_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 13 - Peripheral TIM1 interrupt mask to CPU1
            #[inline(always)]
            pub fn tim1im(&mut self) -> TIM1IM_W {
                TIM1IM_W { w: self }
            }
            ///Bit 14 - Peripheral TIM16 interrupt mask to CPU1
            #[inline(always)]
            pub fn tim16im(&mut self) -> TIM16IM_W {
                TIM16IM_W { w: self }
            }
            ///Bit 15 - Peripheral TIM17 interrupt mask to CPU1
            #[inline(always)]
            pub fn tim17im(&mut self) -> TIM17IM_W {
                TIM17IM_W { w: self }
            }
            ///Bit 21 - Peripheral EXIT5 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit5im(&mut self) -> EXIT5IM_W {
                EXIT5IM_W { w: self }
            }
            ///Bit 22 - Peripheral EXIT6 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit6im(&mut self) -> EXIT6IM_W {
                EXIT6IM_W { w: self }
            }
            ///Bit 23 - Peripheral EXIT7 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit7im(&mut self) -> EXIT7IM_W {
                EXIT7IM_W { w: self }
            }
            ///Bit 24 - Peripheral EXIT8 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit8im(&mut self) -> EXIT8IM_W {
                EXIT8IM_W { w: self }
            }
            ///Bit 25 - Peripheral EXIT9 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit9im(&mut self) -> EXIT9IM_W {
                EXIT9IM_W { w: self }
            }
            ///Bit 26 - Peripheral EXIT10 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit10im(&mut self) -> EXIT10IM_W {
                EXIT10IM_W { w: self }
            }
            ///Bit 27 - Peripheral EXIT11 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit11im(&mut self) -> EXIT11IM_W {
                EXIT11IM_W { w: self }
            }
            ///Bit 28 - Peripheral EXIT12 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit12im(&mut self) -> EXIT12IM_W {
                EXIT12IM_W { w: self }
            }
            ///Bit 29 - Peripheral EXIT13 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit13im(&mut self) -> EXIT13IM_W {
                EXIT13IM_W { w: self }
            }
            ///Bit 30 - Peripheral EXIT14 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit14im(&mut self) -> EXIT14IM_W {
                EXIT14IM_W { w: self }
            }
            ///Bit 31 - Peripheral EXIT15 interrupt mask to CPU1
            #[inline(always)]
            pub fn exit15im(&mut self) -> EXIT15IM_W {
                EXIT15IM_W { w: self }
            }
        }
    }
    ///CPU1 interrupt mask register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [imr2](imr2) module
    pub type IMR2 = crate::Reg<u32, _IMR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IMR2;
    ///`read()` method returns [imr2::R](imr2::R) reader structure
    impl crate::Readable for IMR2 {}
    ///`write(|w| ..)` method takes [imr2::W](imr2::W) writer structure
    impl crate::Writable for IMR2 {}
    ///CPU1 interrupt mask register 2
    pub mod imr2 {
        ///Reader of register IMR2
        pub type R = crate::R<u32, super::IMR2>;
        ///Writer for register IMR2
        pub type W = crate::W<u32, super::IMR2>;
        ///Register IMR2 `reset()`'s with value 0
        impl crate::ResetValue for super::IMR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PVM3IM`
        pub type PVM3IM_R = crate::R<bool, bool>;
        ///Write proxy for field `PVM3IM`
        pub struct PVM3IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVM3IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `PVM1IM`
        pub type PVM1IM_R = crate::R<bool, bool>;
        ///Write proxy for field `PVM1IM`
        pub struct PVM1IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVM1IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `PVDIM`
        pub type PVDIM_R = crate::R<bool, bool>;
        ///Write proxy for field `PVDIM`
        pub struct PVDIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVDIM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        impl R {
            ///Bit 18 - Peripheral PVM3 interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm3im(&self) -> PVM3IM_R {
                PVM3IM_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 16 - Peripheral PVM1 interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm1im(&self) -> PVM1IM_R {
                PVM1IM_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 20 - Peripheral PVD interrupt mask to CPU1
            #[inline(always)]
            pub fn pvdim(&self) -> PVDIM_R {
                PVDIM_R::new(((self.bits >> 20) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 18 - Peripheral PVM3 interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm3im(&mut self) -> PVM3IM_W {
                PVM3IM_W { w: self }
            }
            ///Bit 16 - Peripheral PVM1 interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm1im(&mut self) -> PVM1IM_W {
                PVM1IM_W { w: self }
            }
            ///Bit 20 - Peripheral PVD interrupt mask to CPU1
            #[inline(always)]
            pub fn pvdim(&mut self) -> PVDIM_W {
                PVDIM_W { w: self }
            }
        }
    }
    ///CPU2 interrupt mask register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2imr1](c2imr1) module
    pub type C2IMR1 = crate::Reg<u32, _C2IMR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2IMR1;
    ///`read()` method returns [c2imr1::R](c2imr1::R) reader structure
    impl crate::Readable for C2IMR1 {}
    ///`write(|w| ..)` method takes [c2imr1::W](c2imr1::W) writer structure
    impl crate::Writable for C2IMR1 {}
    ///CPU2 interrupt mask register 1
    pub mod c2imr1 {
        ///Reader of register C2IMR1
        pub type R = crate::R<u32, super::C2IMR1>;
        ///Writer for register C2IMR1
        pub type W = crate::W<u32, super::C2IMR1>;
        ///Register C2IMR1 `reset()`'s with value 0
        impl crate::ResetValue for super::C2IMR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RTCSTAMP`
        pub type RTCSTAMP_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCSTAMP`
        pub struct RTCSTAMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCSTAMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `RTCWKUP`
        pub type RTCWKUP_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCWKUP`
        pub struct RTCWKUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCWKUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `RTCALARM`
        pub type RTCALARM_R = crate::R<bool, bool>;
        ///Write proxy for field `RTCALARM`
        pub struct RTCALARM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTCALARM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `RCC`
        pub type RCC_R = crate::R<bool, bool>;
        ///Write proxy for field `RCC`
        pub struct RCC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RCC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `FLASH`
        pub type FLASH_R = crate::R<bool, bool>;
        ///Write proxy for field `FLASH`
        pub struct FLASH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FLASH_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `PKA`
        pub type PKA_R = crate::R<bool, bool>;
        ///Write proxy for field `PKA`
        pub struct PKA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PKA_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `RNG`
        pub type RNG_R = crate::R<bool, bool>;
        ///Write proxy for field `RNG`
        pub struct RNG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `AES1`
        pub type AES1_R = crate::R<bool, bool>;
        ///Write proxy for field `AES1`
        pub struct AES1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `COMP`
        pub type COMP_R = crate::R<bool, bool>;
        ///Write proxy for field `COMP`
        pub struct COMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ADC`
        pub type ADC_R = crate::R<bool, bool>;
        ///Write proxy for field `ADC`
        pub struct ADC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Peripheral RTCSTAMP interrupt mask to CPU2
            #[inline(always)]
            pub fn rtcstamp(&self) -> RTCSTAMP_R {
                RTCSTAMP_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 3 - Peripheral RTCWKUP interrupt mask to CPU2
            #[inline(always)]
            pub fn rtcwkup(&self) -> RTCWKUP_R {
                RTCWKUP_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Peripheral RTCALARM interrupt mask to CPU2
            #[inline(always)]
            pub fn rtcalarm(&self) -> RTCALARM_R {
                RTCALARM_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Peripheral RCC interrupt mask to CPU2
            #[inline(always)]
            pub fn rcc(&self) -> RCC_R {
                RCC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral FLASH interrupt mask to CPU2
            #[inline(always)]
            pub fn flash(&self) -> FLASH_R {
                FLASH_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 8 - Peripheral PKA interrupt mask to CPU2
            #[inline(always)]
            pub fn pka(&self) -> PKA_R {
                PKA_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Peripheral RNG interrupt mask to CPU2
            #[inline(always)]
            pub fn rng(&self) -> RNG_R {
                RNG_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Peripheral AES1 interrupt mask to CPU2
            #[inline(always)]
            pub fn aes1(&self) -> AES1_R {
                AES1_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Peripheral COMP interrupt mask to CPU2
            #[inline(always)]
            pub fn comp(&self) -> COMP_R {
                COMP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Peripheral ADC interrupt mask to CPU2
            #[inline(always)]
            pub fn adc(&self) -> ADC_R {
                ADC_R::new(((self.bits >> 12) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Peripheral RTCSTAMP interrupt mask to CPU2
            #[inline(always)]
            pub fn rtcstamp(&mut self) -> RTCSTAMP_W {
                RTCSTAMP_W { w: self }
            }
            ///Bit 3 - Peripheral RTCWKUP interrupt mask to CPU2
            #[inline(always)]
            pub fn rtcwkup(&mut self) -> RTCWKUP_W {
                RTCWKUP_W { w: self }
            }
            ///Bit 4 - Peripheral RTCALARM interrupt mask to CPU2
            #[inline(always)]
            pub fn rtcalarm(&mut self) -> RTCALARM_W {
                RTCALARM_W { w: self }
            }
            ///Bit 5 - Peripheral RCC interrupt mask to CPU2
            #[inline(always)]
            pub fn rcc(&mut self) -> RCC_W {
                RCC_W { w: self }
            }
            ///Bit 6 - Peripheral FLASH interrupt mask to CPU2
            #[inline(always)]
            pub fn flash(&mut self) -> FLASH_W {
                FLASH_W { w: self }
            }
            ///Bit 8 - Peripheral PKA interrupt mask to CPU2
            #[inline(always)]
            pub fn pka(&mut self) -> PKA_W {
                PKA_W { w: self }
            }
            ///Bit 9 - Peripheral RNG interrupt mask to CPU2
            #[inline(always)]
            pub fn rng(&mut self) -> RNG_W {
                RNG_W { w: self }
            }
            ///Bit 10 - Peripheral AES1 interrupt mask to CPU2
            #[inline(always)]
            pub fn aes1(&mut self) -> AES1_W {
                AES1_W { w: self }
            }
            ///Bit 11 - Peripheral COMP interrupt mask to CPU2
            #[inline(always)]
            pub fn comp(&mut self) -> COMP_W {
                COMP_W { w: self }
            }
            ///Bit 12 - Peripheral ADC interrupt mask to CPU2
            #[inline(always)]
            pub fn adc(&mut self) -> ADC_W {
                ADC_W { w: self }
            }
        }
    }
    ///CPU2 interrupt mask register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2imr2](c2imr2) module
    pub type C2IMR2 = crate::Reg<u32, _C2IMR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2IMR2;
    ///`read()` method returns [c2imr2::R](c2imr2::R) reader structure
    impl crate::Readable for C2IMR2 {}
    ///`write(|w| ..)` method takes [c2imr2::W](c2imr2::W) writer structure
    impl crate::Writable for C2IMR2 {}
    ///CPU2 interrupt mask register 1
    pub mod c2imr2 {
        ///Reader of register C2IMR2
        pub type R = crate::R<u32, super::C2IMR2>;
        ///Writer for register C2IMR2
        pub type W = crate::W<u32, super::C2IMR2>;
        ///Register C2IMR2 `reset()`'s with value 0
        impl crate::ResetValue for super::C2IMR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DMA1_CH1_IM`
        pub type DMA1_CH1_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1_CH1_IM`
        pub struct DMA1_CH1_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1_CH1_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `DMA1_CH2_IM`
        pub type DMA1_CH2_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1_CH2_IM`
        pub struct DMA1_CH2_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1_CH2_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DMA1_CH3_IM`
        pub type DMA1_CH3_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1_CH3_IM`
        pub struct DMA1_CH3_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1_CH3_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DMA1_CH4_IM`
        pub type DMA1_CH4_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1_CH4_IM`
        pub struct DMA1_CH4_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1_CH4_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `DMA1_CH5_IM`
        pub type DMA1_CH5_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1_CH5_IM`
        pub struct DMA1_CH5_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1_CH5_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `DMA1_CH6_IM`
        pub type DMA1_CH6_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1_CH6_IM`
        pub struct DMA1_CH6_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1_CH6_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `DMA1_CH7_IM`
        pub type DMA1_CH7_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA1_CH7_IM`
        pub struct DMA1_CH7_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA1_CH7_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `DMA2_CH1_IM`
        pub type DMA2_CH1_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2_CH1_IM`
        pub struct DMA2_CH1_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2_CH1_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMA2_CH2_IM`
        pub type DMA2_CH2_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2_CH2_IM`
        pub struct DMA2_CH2_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2_CH2_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `DMA2_CH3_IM`
        pub type DMA2_CH3_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2_CH3_IM`
        pub struct DMA2_CH3_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2_CH3_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `DMA2_CH4_IM`
        pub type DMA2_CH4_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2_CH4_IM`
        pub struct DMA2_CH4_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2_CH4_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `DMA2_CH5_IM`
        pub type DMA2_CH5_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2_CH5_IM`
        pub struct DMA2_CH5_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2_CH5_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DMA2_CH6_IM`
        pub type DMA2_CH6_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2_CH6_IM`
        pub struct DMA2_CH6_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2_CH6_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `DMA2_CH7_IM`
        pub type DMA2_CH7_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMA2_CH7_IM`
        pub struct DMA2_CH7_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMA2_CH7_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `DMAM_UX1_IM`
        pub type DMAM_UX1_IM_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAM_UX1_IM`
        pub struct DMAM_UX1_IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAM_UX1_IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `PVM1IM`
        pub type PVM1IM_R = crate::R<bool, bool>;
        ///Write proxy for field `PVM1IM`
        pub struct PVM1IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVM1IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `PVM3IM`
        pub type PVM3IM_R = crate::R<bool, bool>;
        ///Write proxy for field `PVM3IM`
        pub struct PVM3IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVM3IM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `PVDIM`
        pub type PVDIM_R = crate::R<bool, bool>;
        ///Write proxy for field `PVDIM`
        pub struct PVDIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PVDIM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `TSCIM`
        pub type TSCIM_R = crate::R<bool, bool>;
        ///Write proxy for field `TSCIM`
        pub struct TSCIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSCIM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `LCDIM`
        pub type LCDIM_R = crate::R<bool, bool>;
        ///Write proxy for field `LCDIM`
        pub struct LCDIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCDIM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Peripheral DMA1 CH1 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch1_im(&self) -> DMA1_CH1_IM_R {
                DMA1_CH1_IM_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Peripheral DMA1 CH2 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch2_im(&self) -> DMA1_CH2_IM_R {
                DMA1_CH2_IM_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Peripheral DMA1 CH3 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch3_im(&self) -> DMA1_CH3_IM_R {
                DMA1_CH3_IM_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Peripheral DMA1 CH4 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch4_im(&self) -> DMA1_CH4_IM_R {
                DMA1_CH4_IM_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Peripheral DMA1 CH5 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch5_im(&self) -> DMA1_CH5_IM_R {
                DMA1_CH5_IM_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Peripheral DMA1 CH6 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch6_im(&self) -> DMA1_CH6_IM_R {
                DMA1_CH6_IM_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Peripheral DMA1 CH7 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch7_im(&self) -> DMA1_CH7_IM_R {
                DMA1_CH7_IM_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 8 - Peripheral DMA2 CH1 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch1_im(&self) -> DMA2_CH1_IM_R {
                DMA2_CH1_IM_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Peripheral DMA2 CH2 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch2_im(&self) -> DMA2_CH2_IM_R {
                DMA2_CH2_IM_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Peripheral DMA2 CH3 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch3_im(&self) -> DMA2_CH3_IM_R {
                DMA2_CH3_IM_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Peripheral DMA2 CH4 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch4_im(&self) -> DMA2_CH4_IM_R {
                DMA2_CH4_IM_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Peripheral DMA2 CH5 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch5_im(&self) -> DMA2_CH5_IM_R {
                DMA2_CH5_IM_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Peripheral DMA2 CH6 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch6_im(&self) -> DMA2_CH6_IM_R {
                DMA2_CH6_IM_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Peripheral DMA2 CH7 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch7_im(&self) -> DMA2_CH7_IM_R {
                DMA2_CH7_IM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Peripheral DMAM UX1 interrupt mask to CPU1
            #[inline(always)]
            pub fn dmam_ux1_im(&self) -> DMAM_UX1_IM_R {
                DMAM_UX1_IM_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Peripheral PVM1IM interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm1im(&self) -> PVM1IM_R {
                PVM1IM_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 18 - Peripheral PVM3IM interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm3im(&self) -> PVM3IM_R {
                PVM3IM_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 20 - Peripheral PVDIM interrupt mask to CPU1
            #[inline(always)]
            pub fn pvdim(&self) -> PVDIM_R {
                PVDIM_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 21 - Peripheral TSCIM interrupt mask to CPU1
            #[inline(always)]
            pub fn tscim(&self) -> TSCIM_R {
                TSCIM_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 22 - Peripheral LCDIM interrupt mask to CPU1
            #[inline(always)]
            pub fn lcdim(&self) -> LCDIM_R {
                LCDIM_R::new(((self.bits >> 22) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Peripheral DMA1 CH1 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch1_im(&mut self) -> DMA1_CH1_IM_W {
                DMA1_CH1_IM_W { w: self }
            }
            ///Bit 1 - Peripheral DMA1 CH2 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch2_im(&mut self) -> DMA1_CH2_IM_W {
                DMA1_CH2_IM_W { w: self }
            }
            ///Bit 2 - Peripheral DMA1 CH3 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch3_im(&mut self) -> DMA1_CH3_IM_W {
                DMA1_CH3_IM_W { w: self }
            }
            ///Bit 3 - Peripheral DMA1 CH4 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch4_im(&mut self) -> DMA1_CH4_IM_W {
                DMA1_CH4_IM_W { w: self }
            }
            ///Bit 4 - Peripheral DMA1 CH5 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch5_im(&mut self) -> DMA1_CH5_IM_W {
                DMA1_CH5_IM_W { w: self }
            }
            ///Bit 5 - Peripheral DMA1 CH6 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch6_im(&mut self) -> DMA1_CH6_IM_W {
                DMA1_CH6_IM_W { w: self }
            }
            ///Bit 6 - Peripheral DMA1 CH7 interrupt mask to CPU2
            #[inline(always)]
            pub fn dma1_ch7_im(&mut self) -> DMA1_CH7_IM_W {
                DMA1_CH7_IM_W { w: self }
            }
            ///Bit 8 - Peripheral DMA2 CH1 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch1_im(&mut self) -> DMA2_CH1_IM_W {
                DMA2_CH1_IM_W { w: self }
            }
            ///Bit 9 - Peripheral DMA2 CH2 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch2_im(&mut self) -> DMA2_CH2_IM_W {
                DMA2_CH2_IM_W { w: self }
            }
            ///Bit 10 - Peripheral DMA2 CH3 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch3_im(&mut self) -> DMA2_CH3_IM_W {
                DMA2_CH3_IM_W { w: self }
            }
            ///Bit 11 - Peripheral DMA2 CH4 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch4_im(&mut self) -> DMA2_CH4_IM_W {
                DMA2_CH4_IM_W { w: self }
            }
            ///Bit 12 - Peripheral DMA2 CH5 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch5_im(&mut self) -> DMA2_CH5_IM_W {
                DMA2_CH5_IM_W { w: self }
            }
            ///Bit 13 - Peripheral DMA2 CH6 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch6_im(&mut self) -> DMA2_CH6_IM_W {
                DMA2_CH6_IM_W { w: self }
            }
            ///Bit 14 - Peripheral DMA2 CH7 interrupt mask to CPU1
            #[inline(always)]
            pub fn dma2_ch7_im(&mut self) -> DMA2_CH7_IM_W {
                DMA2_CH7_IM_W { w: self }
            }
            ///Bit 15 - Peripheral DMAM UX1 interrupt mask to CPU1
            #[inline(always)]
            pub fn dmam_ux1_im(&mut self) -> DMAM_UX1_IM_W {
                DMAM_UX1_IM_W { w: self }
            }
            ///Bit 16 - Peripheral PVM1IM interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm1im(&mut self) -> PVM1IM_W {
                PVM1IM_W { w: self }
            }
            ///Bit 18 - Peripheral PVM3IM interrupt mask to CPU1
            #[inline(always)]
            pub fn pvm3im(&mut self) -> PVM3IM_W {
                PVM3IM_W { w: self }
            }
            ///Bit 20 - Peripheral PVDIM interrupt mask to CPU1
            #[inline(always)]
            pub fn pvdim(&mut self) -> PVDIM_W {
                PVDIM_W { w: self }
            }
            ///Bit 21 - Peripheral TSCIM interrupt mask to CPU1
            #[inline(always)]
            pub fn tscim(&mut self) -> TSCIM_W {
                TSCIM_W { w: self }
            }
            ///Bit 22 - Peripheral LCDIM interrupt mask to CPU1
            #[inline(always)]
            pub fn lcdim(&mut self) -> LCDIM_W {
                LCDIM_W { w: self }
            }
        }
    }
    ///secure IP control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sipcr](sipcr) module
    pub type SIPCR = crate::Reg<u32, _SIPCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SIPCR;
    ///`read()` method returns [sipcr::R](sipcr::R) reader structure
    impl crate::Readable for SIPCR {}
    ///`write(|w| ..)` method takes [sipcr::W](sipcr::W) writer structure
    impl crate::Writable for SIPCR {}
    ///secure IP control register
    pub mod sipcr {
        ///Reader of register SIPCR
        pub type R = crate::R<u32, super::SIPCR>;
        ///Writer for register SIPCR
        pub type W = crate::W<u32, super::SIPCR>;
        ///Register SIPCR `reset()`'s with value 0
        impl crate::ResetValue for super::SIPCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SAES1`
        pub type SAES1_R = crate::R<bool, bool>;
        ///Write proxy for field `SAES1`
        pub struct SAES1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAES1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `SAES2`
        pub type SAES2_R = crate::R<bool, bool>;
        ///Write proxy for field `SAES2`
        pub struct SAES2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SAES2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `SPKA`
        pub type SPKA_R = crate::R<bool, bool>;
        ///Write proxy for field `SPKA`
        pub struct SPKA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPKA_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `SRNG`
        pub type SRNG_R = crate::R<bool, bool>;
        ///Write proxy for field `SRNG`
        pub struct SRNG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SRNG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Enable AES1 KEY\[7:0\]
            ///security.
            #[inline(always)]
            pub fn saes1(&self) -> SAES1_R {
                SAES1_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Enable AES2 security.
            #[inline(always)]
            pub fn saes2(&self) -> SAES2_R {
                SAES2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Enable PKA security
            #[inline(always)]
            pub fn spka(&self) -> SPKA_R {
                SPKA_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Enable True RNG security
            #[inline(always)]
            pub fn srng(&self) -> SRNG_R {
                SRNG_R::new(((self.bits >> 3) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Enable AES1 KEY\[7:0\]
            ///security.
            #[inline(always)]
            pub fn saes1(&mut self) -> SAES1_W {
                SAES1_W { w: self }
            }
            ///Bit 1 - Enable AES2 security.
            #[inline(always)]
            pub fn saes2(&mut self) -> SAES2_W {
                SAES2_W { w: self }
            }
            ///Bit 2 - Enable PKA security
            #[inline(always)]
            pub fn spka(&mut self) -> SPKA_W {
                SPKA_W { w: self }
            }
            ///Bit 3 - Enable True RNG security
            #[inline(always)]
            pub fn srng(&mut self) -> SRNG_W {
                SRNG_W { w: self }
            }
        }
    }
}
///Random number generator
pub struct RNG {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for RNG {}
impl RNG {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const rng::RegisterBlock {
        0x5800_1000 as *const _
    }
}
impl Deref for RNG {
    type Target = rng::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*RNG::ptr() }
    }
}
///Random number generator
pub mod rng {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register
        pub cr: CR,
        ///0x04 - status register
        pub sr: SR,
        ///0x08 - data register
        pub dr: DR,
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RNGEN`
        pub type RNGEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RNGEN`
        pub struct RNGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RNGEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `IE`
        pub type IE_R = crate::R<bool, bool>;
        ///Write proxy for field `IE`
        pub struct IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `BYP`
        pub type BYP_R = crate::R<bool, bool>;
        ///Write proxy for field `BYP`
        pub struct BYP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BYP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        impl R {
            ///Bit 2 - Random number generator enable
            #[inline(always)]
            pub fn rngen(&self) -> RNGEN_R {
                RNGEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Interrupt enable
            #[inline(always)]
            pub fn ie(&self) -> IE_R {
                IE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 6 - Bypass mode enable
            #[inline(always)]
            pub fn byp(&self) -> BYP_R {
                BYP_R::new(((self.bits >> 6) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 2 - Random number generator enable
            #[inline(always)]
            pub fn rngen(&mut self) -> RNGEN_W {
                RNGEN_W { w: self }
            }
            ///Bit 3 - Interrupt enable
            #[inline(always)]
            pub fn ie(&mut self) -> IE_W {
                IE_W { w: self }
            }
            ///Bit 6 - Bypass mode enable
            #[inline(always)]
            pub fn byp(&mut self) -> BYP_W {
                BYP_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SEIS`
        pub type SEIS_R = crate::R<bool, bool>;
        ///Write proxy for field `SEIS`
        pub struct SEIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SEIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CEIS`
        pub type CEIS_R = crate::R<bool, bool>;
        ///Write proxy for field `CEIS`
        pub struct CEIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CEIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `SECS`
        pub type SECS_R = crate::R<bool, bool>;
        ///Reader of field `CECS`
        pub type CECS_R = crate::R<bool, bool>;
        ///Reader of field `DRDY`
        pub type DRDY_R = crate::R<bool, bool>;
        impl R {
            ///Bit 6 - Seed error interrupt status
            #[inline(always)]
            pub fn seis(&self) -> SEIS_R {
                SEIS_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Clock error interrupt status
            #[inline(always)]
            pub fn ceis(&self) -> CEIS_R {
                CEIS_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 2 - Seed error current status
            #[inline(always)]
            pub fn secs(&self) -> SECS_R {
                SECS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Clock error current status
            #[inline(always)]
            pub fn cecs(&self) -> CECS_R {
                CECS_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Data ready
            #[inline(always)]
            pub fn drdy(&self) -> DRDY_R {
                DRDY_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 6 - Seed error interrupt status
            #[inline(always)]
            pub fn seis(&mut self) -> SEIS_W {
                SEIS_W { w: self }
            }
            ///Bit 5 - Clock error interrupt status
            #[inline(always)]
            pub fn ceis(&mut self) -> CEIS_W {
                CEIS_W { w: self }
            }
        }
    }
    ///data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dr](dr) module
    pub type DR = crate::Reg<u32, _DR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DR;
    ///`read()` method returns [dr::R](dr::R) reader structure
    impl crate::Readable for DR {}
    ///data register
    pub mod dr {
        ///Reader of register DR
        pub type R = crate::R<u32, super::DR>;
        ///Reader of field `RNDATA`
        pub type RNDATA_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Random data
            #[inline(always)]
            pub fn rndata(&self) -> RNDATA_R {
                RNDATA_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
}
///Advanced encryption standard hardware accelerator 1
pub struct AES1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for AES1 {}
impl AES1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const aes1::RegisterBlock {
        0x5006_0000 as *const _
    }
}
impl Deref for AES1 {
    type Target = aes1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*AES1::ptr() }
    }
}
///Advanced encryption standard hardware accelerator 1
pub mod aes1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register
        pub cr: CR,
        ///0x04 - status register
        pub sr: SR,
        ///0x08 - data input register
        pub dinr: DINR,
        ///0x0c - data output register
        pub doutr: DOUTR,
        ///0x10 - key register 0
        pub keyr0: KEYR0,
        ///0x14 - key register 1
        pub keyr1: KEYR1,
        ///0x18 - key register 2
        pub keyr2: KEYR2,
        ///0x1c - key register 3
        pub keyr3: KEYR3,
        ///0x20 - initialization vector register 0
        pub ivr0: IVR0,
        ///0x24 - initialization vector register 1
        pub ivr1: IVR1,
        ///0x28 - initialization vector register 2
        pub ivr2: IVR2,
        ///0x2c - initialization vector register 3
        pub ivr3: IVR3,
        ///0x30 - key register 4
        pub keyr4: KEYR4,
        ///0x34 - key register 5
        pub keyr5: KEYR5,
        ///0x38 - key register 6
        pub keyr6: KEYR6,
        ///0x3c - key register 7
        pub keyr7: KEYR7,
        ///0x40 - AES suspend register 0
        pub susp0r: SUSP0R,
        ///0x44 - AES suspend register 1
        pub susp1r: SUSP1R,
        ///0x48 - AES suspend register 2
        pub susp2r: SUSP2R,
        ///0x4c - AES suspend register 3
        pub susp3r: SUSP3R,
        ///0x50 - AES suspend register 4
        pub susp4r: SUSP4R,
        ///0x54 - AES suspend register 5
        pub susp5r: SUSP5R,
        ///0x58 - AES suspend register 6
        pub susp6r: SUSP6R,
        ///0x5c - AES suspend register 7
        pub susp7r: SUSP7R,
        _reserved24: [u8; 912usize],
        ///0x3f0 - AES hardware configuration register
        pub hwcfr: HWCFR,
        ///0x3f4 - AES version register
        pub verr: VERR,
        ///0x3f8 - AES identification register
        pub ipidr: IPIDR,
        ///0x3fc - AES size ID register
        pub sidr: SIDR,
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NPBLB`
        pub type NPBLB_R = crate::R<u8, u8>;
        ///Write proxy for field `NPBLB`
        pub struct NPBLB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NPBLB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `KEYSIZE`
        pub type KEYSIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `KEYSIZE`
        pub struct KEYSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEYSIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `CHMOD2`
        pub type CHMOD2_R = crate::R<bool, bool>;
        ///Write proxy for field `CHMOD2`
        pub struct CHMOD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHMOD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `GCMPH`
        pub type GCMPH_R = crate::R<u8, u8>;
        ///Write proxy for field `GCMPH`
        pub struct GCMPH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GCMPH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 13)) | (((value as u32) & 0x03) << 13);
                self.w
            }
        }
        ///Reader of field `DMAOUTEN`
        pub type DMAOUTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAOUTEN`
        pub struct DMAOUTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAOUTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DMAINEN`
        pub type DMAINEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAINEN`
        pub struct DMAINEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAINEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ERRIE`
        pub type ERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRIE`
        pub struct ERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CCFIE`
        pub type CCFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `CCFIE`
        pub struct CCFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `ERRC`
        pub type ERRC_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRC`
        pub struct ERRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CCFC`
        pub type CCFC_R = crate::R<bool, bool>;
        ///Write proxy for field `CCFC`
        pub struct CCFC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCFC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CHMOD10`
        pub type CHMOD10_R = crate::R<u8, u8>;
        ///Write proxy for field `CHMOD10`
        pub struct CHMOD10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHMOD10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
                self.w
            }
        }
        ///Reader of field `MODE`
        pub type MODE_R = crate::R<u8, u8>;
        ///Write proxy for field `MODE`
        pub struct MODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
                self.w
            }
        }
        ///Reader of field `DATATYPE`
        pub type DATATYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `DATATYPE`
        pub struct DATATYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DATATYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 20:23 - Number of padding bytes in last block of payload
            #[inline(always)]
            pub fn npblb(&self) -> NPBLB_R {
                NPBLB_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bit 18 - Key size selection
            #[inline(always)]
            pub fn keysize(&self) -> KEYSIZE_R {
                KEYSIZE_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 16 - AES chaining mode Bit2
            #[inline(always)]
            pub fn chmod2(&self) -> CHMOD2_R {
                CHMOD2_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
            #[inline(always)]
            pub fn gcmph(&self) -> GCMPH_R {
                GCMPH_R::new(((self.bits >> 13) & 0x03) as u8)
            }
            ///Bit 12 - Enable DMA management of data output phase
            #[inline(always)]
            pub fn dmaouten(&self) -> DMAOUTEN_R {
                DMAOUTEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Enable DMA management of data input phase
            #[inline(always)]
            pub fn dmainen(&self) -> DMAINEN_R {
                DMAINEN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&self) -> ERRIE_R {
                ERRIE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - CCF flag interrupt enable
            #[inline(always)]
            pub fn ccfie(&self) -> CCFIE_R {
                CCFIE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Error clear
            #[inline(always)]
            pub fn errc(&self) -> ERRC_R {
                ERRC_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Computation Complete Flag Clear
            #[inline(always)]
            pub fn ccfc(&self) -> CCFC_R {
                CCFC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 5:6 - AES chaining mode Bit1 Bit0
            #[inline(always)]
            pub fn chmod10(&self) -> CHMOD10_R {
                CHMOD10_R::new(((self.bits >> 5) & 0x03) as u8)
            }
            ///Bits 3:4 - AES operating mode
            #[inline(always)]
            pub fn mode(&self) -> MODE_R {
                MODE_R::new(((self.bits >> 3) & 0x03) as u8)
            }
            ///Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
            #[inline(always)]
            pub fn datatype(&self) -> DATATYPE_R {
                DATATYPE_R::new(((self.bits >> 1) & 0x03) as u8)
            }
            ///Bit 0 - AES enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 20:23 - Number of padding bytes in last block of payload
            #[inline(always)]
            pub fn npblb(&mut self) -> NPBLB_W {
                NPBLB_W { w: self }
            }
            ///Bit 18 - Key size selection
            #[inline(always)]
            pub fn keysize(&mut self) -> KEYSIZE_W {
                KEYSIZE_W { w: self }
            }
            ///Bit 16 - AES chaining mode Bit2
            #[inline(always)]
            pub fn chmod2(&mut self) -> CHMOD2_W {
                CHMOD2_W { w: self }
            }
            ///Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
            #[inline(always)]
            pub fn gcmph(&mut self) -> GCMPH_W {
                GCMPH_W { w: self }
            }
            ///Bit 12 - Enable DMA management of data output phase
            #[inline(always)]
            pub fn dmaouten(&mut self) -> DMAOUTEN_W {
                DMAOUTEN_W { w: self }
            }
            ///Bit 11 - Enable DMA management of data input phase
            #[inline(always)]
            pub fn dmainen(&mut self) -> DMAINEN_W {
                DMAINEN_W { w: self }
            }
            ///Bit 10 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&mut self) -> ERRIE_W {
                ERRIE_W { w: self }
            }
            ///Bit 9 - CCF flag interrupt enable
            #[inline(always)]
            pub fn ccfie(&mut self) -> CCFIE_W {
                CCFIE_W { w: self }
            }
            ///Bit 8 - Error clear
            #[inline(always)]
            pub fn errc(&mut self) -> ERRC_W {
                ERRC_W { w: self }
            }
            ///Bit 7 - Computation Complete Flag Clear
            #[inline(always)]
            pub fn ccfc(&mut self) -> CCFC_W {
                CCFC_W { w: self }
            }
            ///Bits 5:6 - AES chaining mode Bit1 Bit0
            #[inline(always)]
            pub fn chmod10(&mut self) -> CHMOD10_W {
                CHMOD10_W { w: self }
            }
            ///Bits 3:4 - AES operating mode
            #[inline(always)]
            pub fn mode(&mut self) -> MODE_W {
                MODE_W { w: self }
            }
            ///Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
            #[inline(always)]
            pub fn datatype(&mut self) -> DATATYPE_W {
                DATATYPE_W { w: self }
            }
            ///Bit 0 - AES enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Reader of field `BUSY`
        pub type BUSY_R = crate::R<bool, bool>;
        ///Reader of field `WRERR`
        pub type WRERR_R = crate::R<bool, bool>;
        ///Reader of field `RDERR`
        pub type RDERR_R = crate::R<bool, bool>;
        ///Reader of field `CCF`
        pub type CCF_R = crate::R<bool, bool>;
        impl R {
            ///Bit 3 - Busy flag
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Write error flag
            #[inline(always)]
            pub fn wrerr(&self) -> WRERR_R {
                WRERR_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Read error flag
            #[inline(always)]
            pub fn rderr(&self) -> RDERR_R {
                RDERR_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Computation complete flag
            #[inline(always)]
            pub fn ccf(&self) -> CCF_R {
                CCF_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///data input register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dinr](dinr) module
    pub type DINR = crate::Reg<u32, _DINR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DINR;
    ///`read()` method returns [dinr::R](dinr::R) reader structure
    impl crate::Readable for DINR {}
    ///`write(|w| ..)` method takes [dinr::W](dinr::W) writer structure
    impl crate::Writable for DINR {}
    ///data input register
    pub mod dinr {
        ///Reader of register DINR
        pub type R = crate::R<u32, super::DINR>;
        ///Writer for register DINR
        pub type W = crate::W<u32, super::DINR>;
        ///Register DINR `reset()`'s with value 0
        impl crate::ResetValue for super::DINR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_DINR`
        pub type AES_DINR_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_DINR`
        pub struct AES_DINR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_DINR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Data Input Register
            #[inline(always)]
            pub fn aes_dinr(&self) -> AES_DINR_R {
                AES_DINR_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Data Input Register
            #[inline(always)]
            pub fn aes_dinr(&mut self) -> AES_DINR_W {
                AES_DINR_W { w: self }
            }
        }
    }
    ///data output register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [doutr](doutr) module
    pub type DOUTR = crate::Reg<u32, _DOUTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DOUTR;
    ///`read()` method returns [doutr::R](doutr::R) reader structure
    impl crate::Readable for DOUTR {}
    ///data output register
    pub mod doutr {
        ///Reader of register DOUTR
        pub type R = crate::R<u32, super::DOUTR>;
        ///Reader of field `AES_DOUTR`
        pub type AES_DOUTR_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Data output register
            #[inline(always)]
            pub fn aes_doutr(&self) -> AES_DOUTR_R {
                AES_DOUTR_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///key register 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr0](keyr0) module
    pub type KEYR0 = crate::Reg<u32, _KEYR0>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR0;
    ///`read()` method returns [keyr0::R](keyr0::R) reader structure
    impl crate::Readable for KEYR0 {}
    ///`write(|w| ..)` method takes [keyr0::W](keyr0::W) writer structure
    impl crate::Writable for KEYR0 {}
    ///key register 0
    pub mod keyr0 {
        ///Reader of register KEYR0
        pub type R = crate::R<u32, super::KEYR0>;
        ///Writer for register KEYR0
        pub type W = crate::W<u32, super::KEYR0>;
        ///Register KEYR0 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR0 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR0`
        pub type AES_KEYR0_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR0`
        pub struct AES_KEYR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Data Output Register (LSB key \[31:0\])
            #[inline(always)]
            pub fn aes_keyr0(&self) -> AES_KEYR0_R {
                AES_KEYR0_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Data Output Register (LSB key \[31:0\])
            #[inline(always)]
            pub fn aes_keyr0(&mut self) -> AES_KEYR0_W {
                AES_KEYR0_W { w: self }
            }
        }
    }
    ///key register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr1](keyr1) module
    pub type KEYR1 = crate::Reg<u32, _KEYR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR1;
    ///`read()` method returns [keyr1::R](keyr1::R) reader structure
    impl crate::Readable for KEYR1 {}
    ///`write(|w| ..)` method takes [keyr1::W](keyr1::W) writer structure
    impl crate::Writable for KEYR1 {}
    ///key register 1
    pub mod keyr1 {
        ///Reader of register KEYR1
        pub type R = crate::R<u32, super::KEYR1>;
        ///Writer for register KEYR1
        pub type W = crate::W<u32, super::KEYR1>;
        ///Register KEYR1 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR1`
        pub type AES_KEYR1_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR1`
        pub struct AES_KEYR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (key \[63:32\])
            #[inline(always)]
            pub fn aes_keyr1(&self) -> AES_KEYR1_R {
                AES_KEYR1_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (key \[63:32\])
            #[inline(always)]
            pub fn aes_keyr1(&mut self) -> AES_KEYR1_W {
                AES_KEYR1_W { w: self }
            }
        }
    }
    ///key register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr2](keyr2) module
    pub type KEYR2 = crate::Reg<u32, _KEYR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR2;
    ///`read()` method returns [keyr2::R](keyr2::R) reader structure
    impl crate::Readable for KEYR2 {}
    ///`write(|w| ..)` method takes [keyr2::W](keyr2::W) writer structure
    impl crate::Writable for KEYR2 {}
    ///key register 2
    pub mod keyr2 {
        ///Reader of register KEYR2
        pub type R = crate::R<u32, super::KEYR2>;
        ///Writer for register KEYR2
        pub type W = crate::W<u32, super::KEYR2>;
        ///Register KEYR2 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR2`
        pub type AES_KEYR2_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR2`
        pub struct AES_KEYR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (key \[95:64\])
            #[inline(always)]
            pub fn aes_keyr2(&self) -> AES_KEYR2_R {
                AES_KEYR2_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (key \[95:64\])
            #[inline(always)]
            pub fn aes_keyr2(&mut self) -> AES_KEYR2_W {
                AES_KEYR2_W { w: self }
            }
        }
    }
    ///key register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr3](keyr3) module
    pub type KEYR3 = crate::Reg<u32, _KEYR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR3;
    ///`read()` method returns [keyr3::R](keyr3::R) reader structure
    impl crate::Readable for KEYR3 {}
    ///`write(|w| ..)` method takes [keyr3::W](keyr3::W) writer structure
    impl crate::Writable for KEYR3 {}
    ///key register 3
    pub mod keyr3 {
        ///Reader of register KEYR3
        pub type R = crate::R<u32, super::KEYR3>;
        ///Writer for register KEYR3
        pub type W = crate::W<u32, super::KEYR3>;
        ///Register KEYR3 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR3`
        pub type AES_KEYR3_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR3`
        pub struct AES_KEYR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[127:96\])
            #[inline(always)]
            pub fn aes_keyr3(&self) -> AES_KEYR3_R {
                AES_KEYR3_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[127:96\])
            #[inline(always)]
            pub fn aes_keyr3(&mut self) -> AES_KEYR3_W {
                AES_KEYR3_W { w: self }
            }
        }
    }
    ///initialization vector register 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr0](ivr0) module
    pub type IVR0 = crate::Reg<u32, _IVR0>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR0;
    ///`read()` method returns [ivr0::R](ivr0::R) reader structure
    impl crate::Readable for IVR0 {}
    ///`write(|w| ..)` method takes [ivr0::W](ivr0::W) writer structure
    impl crate::Writable for IVR0 {}
    ///initialization vector register 0
    pub mod ivr0 {
        ///Reader of register IVR0
        pub type R = crate::R<u32, super::IVR0>;
        ///Writer for register IVR0
        pub type W = crate::W<u32, super::IVR0>;
        ///Register IVR0 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR0 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR0`
        pub type AES_IVR0_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR0`
        pub struct AES_IVR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - initialization vector register (LSB IVR \[31:0\])
            #[inline(always)]
            pub fn aes_ivr0(&self) -> AES_IVR0_R {
                AES_IVR0_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - initialization vector register (LSB IVR \[31:0\])
            #[inline(always)]
            pub fn aes_ivr0(&mut self) -> AES_IVR0_W {
                AES_IVR0_W { w: self }
            }
        }
    }
    ///initialization vector register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr1](ivr1) module
    pub type IVR1 = crate::Reg<u32, _IVR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR1;
    ///`read()` method returns [ivr1::R](ivr1::R) reader structure
    impl crate::Readable for IVR1 {}
    ///`write(|w| ..)` method takes [ivr1::W](ivr1::W) writer structure
    impl crate::Writable for IVR1 {}
    ///initialization vector register 1
    pub mod ivr1 {
        ///Reader of register IVR1
        pub type R = crate::R<u32, super::IVR1>;
        ///Writer for register IVR1
        pub type W = crate::W<u32, super::IVR1>;
        ///Register IVR1 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR1`
        pub type AES_IVR1_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR1`
        pub struct AES_IVR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Initialization Vector Register (IVR \[63:32\])
            #[inline(always)]
            pub fn aes_ivr1(&self) -> AES_IVR1_R {
                AES_IVR1_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Initialization Vector Register (IVR \[63:32\])
            #[inline(always)]
            pub fn aes_ivr1(&mut self) -> AES_IVR1_W {
                AES_IVR1_W { w: self }
            }
        }
    }
    ///initialization vector register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr2](ivr2) module
    pub type IVR2 = crate::Reg<u32, _IVR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR2;
    ///`read()` method returns [ivr2::R](ivr2::R) reader structure
    impl crate::Readable for IVR2 {}
    ///`write(|w| ..)` method takes [ivr2::W](ivr2::W) writer structure
    impl crate::Writable for IVR2 {}
    ///initialization vector register 2
    pub mod ivr2 {
        ///Reader of register IVR2
        pub type R = crate::R<u32, super::IVR2>;
        ///Writer for register IVR2
        pub type W = crate::W<u32, super::IVR2>;
        ///Register IVR2 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR2`
        pub type AES_IVR2_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR2`
        pub struct AES_IVR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Initialization Vector Register (IVR \[95:64\])
            #[inline(always)]
            pub fn aes_ivr2(&self) -> AES_IVR2_R {
                AES_IVR2_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Initialization Vector Register (IVR \[95:64\])
            #[inline(always)]
            pub fn aes_ivr2(&mut self) -> AES_IVR2_W {
                AES_IVR2_W { w: self }
            }
        }
    }
    ///initialization vector register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr3](ivr3) module
    pub type IVR3 = crate::Reg<u32, _IVR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR3;
    ///`read()` method returns [ivr3::R](ivr3::R) reader structure
    impl crate::Readable for IVR3 {}
    ///`write(|w| ..)` method takes [ivr3::W](ivr3::W) writer structure
    impl crate::Writable for IVR3 {}
    ///initialization vector register 3
    pub mod ivr3 {
        ///Reader of register IVR3
        pub type R = crate::R<u32, super::IVR3>;
        ///Writer for register IVR3
        pub type W = crate::W<u32, super::IVR3>;
        ///Register IVR3 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR3`
        pub type AES_IVR3_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR3`
        pub struct AES_IVR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Initialization Vector Register (MSB IVR \[127:96\])
            #[inline(always)]
            pub fn aes_ivr3(&self) -> AES_IVR3_R {
                AES_IVR3_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Initialization Vector Register (MSB IVR \[127:96\])
            #[inline(always)]
            pub fn aes_ivr3(&mut self) -> AES_IVR3_W {
                AES_IVR3_W { w: self }
            }
        }
    }
    ///key register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr4](keyr4) module
    pub type KEYR4 = crate::Reg<u32, _KEYR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR4;
    ///`read()` method returns [keyr4::R](keyr4::R) reader structure
    impl crate::Readable for KEYR4 {}
    ///`write(|w| ..)` method takes [keyr4::W](keyr4::W) writer structure
    impl crate::Writable for KEYR4 {}
    ///key register 4
    pub mod keyr4 {
        ///Reader of register KEYR4
        pub type R = crate::R<u32, super::KEYR4>;
        ///Writer for register KEYR4
        pub type W = crate::W<u32, super::KEYR4>;
        ///Register KEYR4 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR4`
        pub type AES_KEYR4_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR4`
        pub struct AES_KEYR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[159:128\])
            #[inline(always)]
            pub fn aes_keyr4(&self) -> AES_KEYR4_R {
                AES_KEYR4_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[159:128\])
            #[inline(always)]
            pub fn aes_keyr4(&mut self) -> AES_KEYR4_W {
                AES_KEYR4_W { w: self }
            }
        }
    }
    ///key register 5
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr5](keyr5) module
    pub type KEYR5 = crate::Reg<u32, _KEYR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR5;
    ///`read()` method returns [keyr5::R](keyr5::R) reader structure
    impl crate::Readable for KEYR5 {}
    ///`write(|w| ..)` method takes [keyr5::W](keyr5::W) writer structure
    impl crate::Writable for KEYR5 {}
    ///key register 5
    pub mod keyr5 {
        ///Reader of register KEYR5
        pub type R = crate::R<u32, super::KEYR5>;
        ///Writer for register KEYR5
        pub type W = crate::W<u32, super::KEYR5>;
        ///Register KEYR5 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR5`
        pub type AES_KEYR5_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR5`
        pub struct AES_KEYR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[191:160\])
            #[inline(always)]
            pub fn aes_keyr5(&self) -> AES_KEYR5_R {
                AES_KEYR5_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[191:160\])
            #[inline(always)]
            pub fn aes_keyr5(&mut self) -> AES_KEYR5_W {
                AES_KEYR5_W { w: self }
            }
        }
    }
    ///key register 6
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr6](keyr6) module
    pub type KEYR6 = crate::Reg<u32, _KEYR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR6;
    ///`read()` method returns [keyr6::R](keyr6::R) reader structure
    impl crate::Readable for KEYR6 {}
    ///`write(|w| ..)` method takes [keyr6::W](keyr6::W) writer structure
    impl crate::Writable for KEYR6 {}
    ///key register 6
    pub mod keyr6 {
        ///Reader of register KEYR6
        pub type R = crate::R<u32, super::KEYR6>;
        ///Writer for register KEYR6
        pub type W = crate::W<u32, super::KEYR6>;
        ///Register KEYR6 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR6`
        pub type AES_KEYR6_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR6`
        pub struct AES_KEYR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[223:192\])
            #[inline(always)]
            pub fn aes_keyr6(&self) -> AES_KEYR6_R {
                AES_KEYR6_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[223:192\])
            #[inline(always)]
            pub fn aes_keyr6(&mut self) -> AES_KEYR6_W {
                AES_KEYR6_W { w: self }
            }
        }
    }
    ///key register 7
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr7](keyr7) module
    pub type KEYR7 = crate::Reg<u32, _KEYR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR7;
    ///`read()` method returns [keyr7::R](keyr7::R) reader structure
    impl crate::Readable for KEYR7 {}
    ///`write(|w| ..)` method takes [keyr7::W](keyr7::W) writer structure
    impl crate::Writable for KEYR7 {}
    ///key register 7
    pub mod keyr7 {
        ///Reader of register KEYR7
        pub type R = crate::R<u32, super::KEYR7>;
        ///Writer for register KEYR7
        pub type W = crate::W<u32, super::KEYR7>;
        ///Register KEYR7 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR7`
        pub type AES_KEYR7_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR7`
        pub struct AES_KEYR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[255:224\])
            #[inline(always)]
            pub fn aes_keyr7(&self) -> AES_KEYR7_R {
                AES_KEYR7_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[255:224\])
            #[inline(always)]
            pub fn aes_keyr7(&mut self) -> AES_KEYR7_W {
                AES_KEYR7_W { w: self }
            }
        }
    }
    ///AES suspend register 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp0r](susp0r) module
    pub type SUSP0R = crate::Reg<u32, _SUSP0R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP0R;
    ///`read()` method returns [susp0r::R](susp0r::R) reader structure
    impl crate::Readable for SUSP0R {}
    ///`write(|w| ..)` method takes [susp0r::W](susp0r::W) writer structure
    impl crate::Writable for SUSP0R {}
    ///AES suspend register 0
    pub mod susp0r {
        ///Reader of register SUSP0R
        pub type R = crate::R<u32, super::SUSP0R>;
        ///Writer for register SUSP0R
        pub type W = crate::W<u32, super::SUSP0R>;
        ///Register SUSP0R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP0R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP0R`
        pub type AES_SUSP0R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP0R`
        pub struct AES_SUSP0R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP0R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 0
            #[inline(always)]
            pub fn aes_susp0r(&self) -> AES_SUSP0R_R {
                AES_SUSP0R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 0
            #[inline(always)]
            pub fn aes_susp0r(&mut self) -> AES_SUSP0R_W {
                AES_SUSP0R_W { w: self }
            }
        }
    }
    ///AES suspend register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp1r](susp1r) module
    pub type SUSP1R = crate::Reg<u32, _SUSP1R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP1R;
    ///`read()` method returns [susp1r::R](susp1r::R) reader structure
    impl crate::Readable for SUSP1R {}
    ///`write(|w| ..)` method takes [susp1r::W](susp1r::W) writer structure
    impl crate::Writable for SUSP1R {}
    ///AES suspend register 1
    pub mod susp1r {
        ///Reader of register SUSP1R
        pub type R = crate::R<u32, super::SUSP1R>;
        ///Writer for register SUSP1R
        pub type W = crate::W<u32, super::SUSP1R>;
        ///Register SUSP1R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP1R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP1R`
        pub type AES_SUSP1R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP1R`
        pub struct AES_SUSP1R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP1R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 1
            #[inline(always)]
            pub fn aes_susp1r(&self) -> AES_SUSP1R_R {
                AES_SUSP1R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 1
            #[inline(always)]
            pub fn aes_susp1r(&mut self) -> AES_SUSP1R_W {
                AES_SUSP1R_W { w: self }
            }
        }
    }
    ///AES suspend register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp2r](susp2r) module
    pub type SUSP2R = crate::Reg<u32, _SUSP2R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP2R;
    ///`read()` method returns [susp2r::R](susp2r::R) reader structure
    impl crate::Readable for SUSP2R {}
    ///`write(|w| ..)` method takes [susp2r::W](susp2r::W) writer structure
    impl crate::Writable for SUSP2R {}
    ///AES suspend register 2
    pub mod susp2r {
        ///Reader of register SUSP2R
        pub type R = crate::R<u32, super::SUSP2R>;
        ///Writer for register SUSP2R
        pub type W = crate::W<u32, super::SUSP2R>;
        ///Register SUSP2R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP2R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP2R`
        pub type AES_SUSP2R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP2R`
        pub struct AES_SUSP2R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP2R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 2
            #[inline(always)]
            pub fn aes_susp2r(&self) -> AES_SUSP2R_R {
                AES_SUSP2R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 2
            #[inline(always)]
            pub fn aes_susp2r(&mut self) -> AES_SUSP2R_W {
                AES_SUSP2R_W { w: self }
            }
        }
    }
    ///AES suspend register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp3r](susp3r) module
    pub type SUSP3R = crate::Reg<u32, _SUSP3R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP3R;
    ///`read()` method returns [susp3r::R](susp3r::R) reader structure
    impl crate::Readable for SUSP3R {}
    ///`write(|w| ..)` method takes [susp3r::W](susp3r::W) writer structure
    impl crate::Writable for SUSP3R {}
    ///AES suspend register 3
    pub mod susp3r {
        ///Reader of register SUSP3R
        pub type R = crate::R<u32, super::SUSP3R>;
        ///Writer for register SUSP3R
        pub type W = crate::W<u32, super::SUSP3R>;
        ///Register SUSP3R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP3R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP3R`
        pub type AES_SUSP3R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP3R`
        pub struct AES_SUSP3R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP3R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 3
            #[inline(always)]
            pub fn aes_susp3r(&self) -> AES_SUSP3R_R {
                AES_SUSP3R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 3
            #[inline(always)]
            pub fn aes_susp3r(&mut self) -> AES_SUSP3R_W {
                AES_SUSP3R_W { w: self }
            }
        }
    }
    ///AES suspend register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp4r](susp4r) module
    pub type SUSP4R = crate::Reg<u32, _SUSP4R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP4R;
    ///`read()` method returns [susp4r::R](susp4r::R) reader structure
    impl crate::Readable for SUSP4R {}
    ///`write(|w| ..)` method takes [susp4r::W](susp4r::W) writer structure
    impl crate::Writable for SUSP4R {}
    ///AES suspend register 4
    pub mod susp4r {
        ///Reader of register SUSP4R
        pub type R = crate::R<u32, super::SUSP4R>;
        ///Writer for register SUSP4R
        pub type W = crate::W<u32, super::SUSP4R>;
        ///Register SUSP4R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP4R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP4R`
        pub type AES_SUSP4R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP4R`
        pub struct AES_SUSP4R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP4R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 4
            #[inline(always)]
            pub fn aes_susp4r(&self) -> AES_SUSP4R_R {
                AES_SUSP4R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 4
            #[inline(always)]
            pub fn aes_susp4r(&mut self) -> AES_SUSP4R_W {
                AES_SUSP4R_W { w: self }
            }
        }
    }
    ///AES suspend register 5
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp5r](susp5r) module
    pub type SUSP5R = crate::Reg<u32, _SUSP5R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP5R;
    ///`read()` method returns [susp5r::R](susp5r::R) reader structure
    impl crate::Readable for SUSP5R {}
    ///`write(|w| ..)` method takes [susp5r::W](susp5r::W) writer structure
    impl crate::Writable for SUSP5R {}
    ///AES suspend register 5
    pub mod susp5r {
        ///Reader of register SUSP5R
        pub type R = crate::R<u32, super::SUSP5R>;
        ///Writer for register SUSP5R
        pub type W = crate::W<u32, super::SUSP5R>;
        ///Register SUSP5R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP5R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP5R`
        pub type AES_SUSP5R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP5R`
        pub struct AES_SUSP5R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP5R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 5
            #[inline(always)]
            pub fn aes_susp5r(&self) -> AES_SUSP5R_R {
                AES_SUSP5R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 5
            #[inline(always)]
            pub fn aes_susp5r(&mut self) -> AES_SUSP5R_W {
                AES_SUSP5R_W { w: self }
            }
        }
    }
    ///AES suspend register 6
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp6r](susp6r) module
    pub type SUSP6R = crate::Reg<u32, _SUSP6R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP6R;
    ///`read()` method returns [susp6r::R](susp6r::R) reader structure
    impl crate::Readable for SUSP6R {}
    ///`write(|w| ..)` method takes [susp6r::W](susp6r::W) writer structure
    impl crate::Writable for SUSP6R {}
    ///AES suspend register 6
    pub mod susp6r {
        ///Reader of register SUSP6R
        pub type R = crate::R<u32, super::SUSP6R>;
        ///Writer for register SUSP6R
        pub type W = crate::W<u32, super::SUSP6R>;
        ///Register SUSP6R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP6R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP6R`
        pub type AES_SUSP6R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP6R`
        pub struct AES_SUSP6R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP6R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 6
            #[inline(always)]
            pub fn aes_susp6r(&self) -> AES_SUSP6R_R {
                AES_SUSP6R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 6
            #[inline(always)]
            pub fn aes_susp6r(&mut self) -> AES_SUSP6R_W {
                AES_SUSP6R_W { w: self }
            }
        }
    }
    ///AES suspend register 7
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp7r](susp7r) module
    pub type SUSP7R = crate::Reg<u32, _SUSP7R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP7R;
    ///`read()` method returns [susp7r::R](susp7r::R) reader structure
    impl crate::Readable for SUSP7R {}
    ///`write(|w| ..)` method takes [susp7r::W](susp7r::W) writer structure
    impl crate::Writable for SUSP7R {}
    ///AES suspend register 7
    pub mod susp7r {
        ///Reader of register SUSP7R
        pub type R = crate::R<u32, super::SUSP7R>;
        ///Writer for register SUSP7R
        pub type W = crate::W<u32, super::SUSP7R>;
        ///Register SUSP7R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP7R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP7R`
        pub type AES_SUSP7R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP7R`
        pub struct AES_SUSP7R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP7R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 7
            #[inline(always)]
            pub fn aes_susp7r(&self) -> AES_SUSP7R_R {
                AES_SUSP7R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 7
            #[inline(always)]
            pub fn aes_susp7r(&mut self) -> AES_SUSP7R_W {
                AES_SUSP7R_W { w: self }
            }
        }
    }
    ///AES hardware configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfr](hwcfr) module
    pub type HWCFR = crate::Reg<u32, _HWCFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFR;
    ///`read()` method returns [hwcfr::R](hwcfr::R) reader structure
    impl crate::Readable for HWCFR {}
    ///AES hardware configuration register
    pub mod hwcfr {
        ///Reader of register HWCFR
        pub type R = crate::R<u32, super::HWCFR>;
        ///Reader of field `CFG4`
        pub type CFG4_R = crate::R<u8, u8>;
        ///Reader of field `CFG3`
        pub type CFG3_R = crate::R<u8, u8>;
        ///Reader of field `CFG2`
        pub type CFG2_R = crate::R<u8, u8>;
        ///Reader of field `CFG1`
        pub type CFG1_R = crate::R<u8, u8>;
        impl R {
            ///Bits 12:15 - HW Generic 4
            #[inline(always)]
            pub fn cfg4(&self) -> CFG4_R {
                CFG4_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - HW Generic 3
            #[inline(always)]
            pub fn cfg3(&self) -> CFG3_R {
                CFG3_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - HW Generic 2
            #[inline(always)]
            pub fn cfg2(&self) -> CFG2_R {
                CFG2_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - HW Generic 1
            #[inline(always)]
            pub fn cfg1(&self) -> CFG1_R {
                CFG1_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///AES version register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [verr](verr) module
    pub type VERR = crate::Reg<u32, _VERR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _VERR;
    ///`read()` method returns [verr::R](verr::R) reader structure
    impl crate::Readable for VERR {}
    ///AES version register
    pub mod verr {
        ///Reader of register VERR
        pub type R = crate::R<u32, super::VERR>;
        ///Reader of field `MAJREV`
        pub type MAJREV_R = crate::R<u8, u8>;
        ///Reader of field `MINREV`
        pub type MINREV_R = crate::R<u8, u8>;
        impl R {
            ///Bits 4:7 - Major revision
            #[inline(always)]
            pub fn majrev(&self) -> MAJREV_R {
                MAJREV_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Minor revision
            #[inline(always)]
            pub fn minrev(&self) -> MINREV_R {
                MINREV_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///AES identification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ipidr](ipidr) module
    pub type IPIDR = crate::Reg<u32, _IPIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IPIDR;
    ///`read()` method returns [ipidr::R](ipidr::R) reader structure
    impl crate::Readable for IPIDR {}
    ///AES identification register
    pub mod ipidr {
        ///Reader of register IPIDR
        pub type R = crate::R<u32, super::IPIDR>;
        ///Reader of field `ID`
        pub type ID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Identification code
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///AES size ID register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sidr](sidr) module
    pub type SIDR = crate::Reg<u32, _SIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SIDR;
    ///`read()` method returns [sidr::R](sidr::R) reader structure
    impl crate::Readable for SIDR {}
    ///AES size ID register
    pub mod sidr {
        ///Reader of register SIDR
        pub type R = crate::R<u32, super::SIDR>;
        ///Reader of field `ID`
        pub type ID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Size Identification code
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
}
///Advanced encryption standard hardware accelerator 1
pub struct AES2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for AES2 {}
impl AES2 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const aes2::RegisterBlock {
        0x5800_1800 as *const _
    }
}
impl Deref for AES2 {
    type Target = aes2::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*AES2::ptr() }
    }
}
///Advanced encryption standard hardware accelerator 1
pub mod aes2 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register
        pub cr: CR,
        ///0x04 - status register
        pub sr: SR,
        ///0x08 - data input register
        pub dinr: DINR,
        ///0x0c - data output register
        pub doutr: DOUTR,
        ///0x10 - key register 0
        pub keyr0: KEYR0,
        ///0x14 - key register 1
        pub keyr1: KEYR1,
        ///0x18 - key register 2
        pub keyr2: KEYR2,
        ///0x1c - key register 3
        pub keyr3: KEYR3,
        ///0x20 - initialization vector register 0
        pub ivr0: IVR0,
        ///0x24 - initialization vector register 1
        pub ivr1: IVR1,
        ///0x28 - initialization vector register 2
        pub ivr2: IVR2,
        ///0x2c - initialization vector register 3
        pub ivr3: IVR3,
        ///0x30 - key register 4
        pub keyr4: KEYR4,
        ///0x34 - key register 5
        pub keyr5: KEYR5,
        ///0x38 - key register 6
        pub keyr6: KEYR6,
        ///0x3c - key register 7
        pub keyr7: KEYR7,
        ///0x40 - AES suspend register 0
        pub susp0r: SUSP0R,
        ///0x44 - AES suspend register 1
        pub susp1r: SUSP1R,
        ///0x48 - AES suspend register 2
        pub susp2r: SUSP2R,
        ///0x4c - AES suspend register 3
        pub susp3r: SUSP3R,
        ///0x50 - AES suspend register 4
        pub susp4r: SUSP4R,
        ///0x54 - AES suspend register 5
        pub susp5r: SUSP5R,
        ///0x58 - AES suspend register 6
        pub susp6r: SUSP6R,
        ///0x5c - AES suspend register 7
        pub susp7r: SUSP7R,
        ///0x60 - AES hardware configuration register
        pub hwcfr: HWCFR,
        ///0x64 - AES version register
        pub verr: VERR,
        ///0x68 - AES identification register
        pub ipidr: IPIDR,
        ///0x6c - AES size ID register
        pub sidr: SIDR,
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `NPBLB`
        pub type NPBLB_R = crate::R<u8, u8>;
        ///Write proxy for field `NPBLB`
        pub struct NPBLB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NPBLB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `KEYSIZE`
        pub type KEYSIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `KEYSIZE`
        pub struct KEYSIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEYSIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `CHMOD2`
        pub type CHMOD2_R = crate::R<bool, bool>;
        ///Write proxy for field `CHMOD2`
        pub struct CHMOD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHMOD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `GCMPH`
        pub type GCMPH_R = crate::R<u8, u8>;
        ///Write proxy for field `GCMPH`
        pub struct GCMPH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GCMPH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 13)) | (((value as u32) & 0x03) << 13);
                self.w
            }
        }
        ///Reader of field `DMAOUTEN`
        pub type DMAOUTEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAOUTEN`
        pub struct DMAOUTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAOUTEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DMAINEN`
        pub type DMAINEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAINEN`
        pub struct DMAINEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAINEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ERRIE`
        pub type ERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRIE`
        pub struct ERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CCFIE`
        pub type CCFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `CCFIE`
        pub struct CCFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `ERRC`
        pub type ERRC_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRC`
        pub struct ERRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CCFC`
        pub type CCFC_R = crate::R<bool, bool>;
        ///Write proxy for field `CCFC`
        pub struct CCFC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCFC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CHMOD10`
        pub type CHMOD10_R = crate::R<u8, u8>;
        ///Write proxy for field `CHMOD10`
        pub struct CHMOD10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CHMOD10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
                self.w
            }
        }
        ///Reader of field `MODE`
        pub type MODE_R = crate::R<u8, u8>;
        ///Write proxy for field `MODE`
        pub struct MODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
                self.w
            }
        }
        ///Reader of field `DATATYPE`
        pub type DATATYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `DATATYPE`
        pub struct DATATYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DATATYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 20:23 - Number of padding bytes in last block of payload
            #[inline(always)]
            pub fn npblb(&self) -> NPBLB_R {
                NPBLB_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bit 18 - Key size selection
            #[inline(always)]
            pub fn keysize(&self) -> KEYSIZE_R {
                KEYSIZE_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 16 - AES chaining mode Bit2
            #[inline(always)]
            pub fn chmod2(&self) -> CHMOD2_R {
                CHMOD2_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
            #[inline(always)]
            pub fn gcmph(&self) -> GCMPH_R {
                GCMPH_R::new(((self.bits >> 13) & 0x03) as u8)
            }
            ///Bit 12 - Enable DMA management of data output phase
            #[inline(always)]
            pub fn dmaouten(&self) -> DMAOUTEN_R {
                DMAOUTEN_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Enable DMA management of data input phase
            #[inline(always)]
            pub fn dmainen(&self) -> DMAINEN_R {
                DMAINEN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&self) -> ERRIE_R {
                ERRIE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - CCF flag interrupt enable
            #[inline(always)]
            pub fn ccfie(&self) -> CCFIE_R {
                CCFIE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Error clear
            #[inline(always)]
            pub fn errc(&self) -> ERRC_R {
                ERRC_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Computation Complete Flag Clear
            #[inline(always)]
            pub fn ccfc(&self) -> CCFC_R {
                CCFC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 5:6 - AES chaining mode Bit1 Bit0
            #[inline(always)]
            pub fn chmod10(&self) -> CHMOD10_R {
                CHMOD10_R::new(((self.bits >> 5) & 0x03) as u8)
            }
            ///Bits 3:4 - AES operating mode
            #[inline(always)]
            pub fn mode(&self) -> MODE_R {
                MODE_R::new(((self.bits >> 3) & 0x03) as u8)
            }
            ///Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
            #[inline(always)]
            pub fn datatype(&self) -> DATATYPE_R {
                DATATYPE_R::new(((self.bits >> 1) & 0x03) as u8)
            }
            ///Bit 0 - AES enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 20:23 - Number of padding bytes in last block of payload
            #[inline(always)]
            pub fn npblb(&mut self) -> NPBLB_W {
                NPBLB_W { w: self }
            }
            ///Bit 18 - Key size selection
            #[inline(always)]
            pub fn keysize(&mut self) -> KEYSIZE_W {
                KEYSIZE_W { w: self }
            }
            ///Bit 16 - AES chaining mode Bit2
            #[inline(always)]
            pub fn chmod2(&mut self) -> CHMOD2_W {
                CHMOD2_W { w: self }
            }
            ///Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
            #[inline(always)]
            pub fn gcmph(&mut self) -> GCMPH_W {
                GCMPH_W { w: self }
            }
            ///Bit 12 - Enable DMA management of data output phase
            #[inline(always)]
            pub fn dmaouten(&mut self) -> DMAOUTEN_W {
                DMAOUTEN_W { w: self }
            }
            ///Bit 11 - Enable DMA management of data input phase
            #[inline(always)]
            pub fn dmainen(&mut self) -> DMAINEN_W {
                DMAINEN_W { w: self }
            }
            ///Bit 10 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&mut self) -> ERRIE_W {
                ERRIE_W { w: self }
            }
            ///Bit 9 - CCF flag interrupt enable
            #[inline(always)]
            pub fn ccfie(&mut self) -> CCFIE_W {
                CCFIE_W { w: self }
            }
            ///Bit 8 - Error clear
            #[inline(always)]
            pub fn errc(&mut self) -> ERRC_W {
                ERRC_W { w: self }
            }
            ///Bit 7 - Computation Complete Flag Clear
            #[inline(always)]
            pub fn ccfc(&mut self) -> CCFC_W {
                CCFC_W { w: self }
            }
            ///Bits 5:6 - AES chaining mode Bit1 Bit0
            #[inline(always)]
            pub fn chmod10(&mut self) -> CHMOD10_W {
                CHMOD10_W { w: self }
            }
            ///Bits 3:4 - AES operating mode
            #[inline(always)]
            pub fn mode(&mut self) -> MODE_W {
                MODE_W { w: self }
            }
            ///Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
            #[inline(always)]
            pub fn datatype(&mut self) -> DATATYPE_W {
                DATATYPE_W { w: self }
            }
            ///Bit 0 - AES enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Reader of field `BUSY`
        pub type BUSY_R = crate::R<bool, bool>;
        ///Reader of field `WRERR`
        pub type WRERR_R = crate::R<bool, bool>;
        ///Reader of field `RDERR`
        pub type RDERR_R = crate::R<bool, bool>;
        ///Reader of field `CCF`
        pub type CCF_R = crate::R<bool, bool>;
        impl R {
            ///Bit 3 - Busy flag
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Write error flag
            #[inline(always)]
            pub fn wrerr(&self) -> WRERR_R {
                WRERR_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Read error flag
            #[inline(always)]
            pub fn rderr(&self) -> RDERR_R {
                RDERR_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Computation complete flag
            #[inline(always)]
            pub fn ccf(&self) -> CCF_R {
                CCF_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///data input register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dinr](dinr) module
    pub type DINR = crate::Reg<u32, _DINR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DINR;
    ///`read()` method returns [dinr::R](dinr::R) reader structure
    impl crate::Readable for DINR {}
    ///`write(|w| ..)` method takes [dinr::W](dinr::W) writer structure
    impl crate::Writable for DINR {}
    ///data input register
    pub mod dinr {
        ///Reader of register DINR
        pub type R = crate::R<u32, super::DINR>;
        ///Writer for register DINR
        pub type W = crate::W<u32, super::DINR>;
        ///Register DINR `reset()`'s with value 0
        impl crate::ResetValue for super::DINR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_DINR`
        pub type AES_DINR_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_DINR`
        pub struct AES_DINR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_DINR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Data Input Register
            #[inline(always)]
            pub fn aes_dinr(&self) -> AES_DINR_R {
                AES_DINR_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Data Input Register
            #[inline(always)]
            pub fn aes_dinr(&mut self) -> AES_DINR_W {
                AES_DINR_W { w: self }
            }
        }
    }
    ///data output register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [doutr](doutr) module
    pub type DOUTR = crate::Reg<u32, _DOUTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DOUTR;
    ///`read()` method returns [doutr::R](doutr::R) reader structure
    impl crate::Readable for DOUTR {}
    ///data output register
    pub mod doutr {
        ///Reader of register DOUTR
        pub type R = crate::R<u32, super::DOUTR>;
        ///Reader of field `AES_DOUTR`
        pub type AES_DOUTR_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Data output register
            #[inline(always)]
            pub fn aes_doutr(&self) -> AES_DOUTR_R {
                AES_DOUTR_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///key register 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr0](keyr0) module
    pub type KEYR0 = crate::Reg<u32, _KEYR0>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR0;
    ///`read()` method returns [keyr0::R](keyr0::R) reader structure
    impl crate::Readable for KEYR0 {}
    ///`write(|w| ..)` method takes [keyr0::W](keyr0::W) writer structure
    impl crate::Writable for KEYR0 {}
    ///key register 0
    pub mod keyr0 {
        ///Reader of register KEYR0
        pub type R = crate::R<u32, super::KEYR0>;
        ///Writer for register KEYR0
        pub type W = crate::W<u32, super::KEYR0>;
        ///Register KEYR0 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR0 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR0`
        pub type AES_KEYR0_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR0`
        pub struct AES_KEYR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Data Output Register (LSB key \[31:0\])
            #[inline(always)]
            pub fn aes_keyr0(&self) -> AES_KEYR0_R {
                AES_KEYR0_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Data Output Register (LSB key \[31:0\])
            #[inline(always)]
            pub fn aes_keyr0(&mut self) -> AES_KEYR0_W {
                AES_KEYR0_W { w: self }
            }
        }
    }
    ///key register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr1](keyr1) module
    pub type KEYR1 = crate::Reg<u32, _KEYR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR1;
    ///`read()` method returns [keyr1::R](keyr1::R) reader structure
    impl crate::Readable for KEYR1 {}
    ///`write(|w| ..)` method takes [keyr1::W](keyr1::W) writer structure
    impl crate::Writable for KEYR1 {}
    ///key register 1
    pub mod keyr1 {
        ///Reader of register KEYR1
        pub type R = crate::R<u32, super::KEYR1>;
        ///Writer for register KEYR1
        pub type W = crate::W<u32, super::KEYR1>;
        ///Register KEYR1 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR1`
        pub type AES_KEYR1_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR1`
        pub struct AES_KEYR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (key \[63:32\])
            #[inline(always)]
            pub fn aes_keyr1(&self) -> AES_KEYR1_R {
                AES_KEYR1_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (key \[63:32\])
            #[inline(always)]
            pub fn aes_keyr1(&mut self) -> AES_KEYR1_W {
                AES_KEYR1_W { w: self }
            }
        }
    }
    ///key register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr2](keyr2) module
    pub type KEYR2 = crate::Reg<u32, _KEYR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR2;
    ///`read()` method returns [keyr2::R](keyr2::R) reader structure
    impl crate::Readable for KEYR2 {}
    ///`write(|w| ..)` method takes [keyr2::W](keyr2::W) writer structure
    impl crate::Writable for KEYR2 {}
    ///key register 2
    pub mod keyr2 {
        ///Reader of register KEYR2
        pub type R = crate::R<u32, super::KEYR2>;
        ///Writer for register KEYR2
        pub type W = crate::W<u32, super::KEYR2>;
        ///Register KEYR2 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR2`
        pub type AES_KEYR2_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR2`
        pub struct AES_KEYR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (key \[95:64\])
            #[inline(always)]
            pub fn aes_keyr2(&self) -> AES_KEYR2_R {
                AES_KEYR2_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (key \[95:64\])
            #[inline(always)]
            pub fn aes_keyr2(&mut self) -> AES_KEYR2_W {
                AES_KEYR2_W { w: self }
            }
        }
    }
    ///key register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr3](keyr3) module
    pub type KEYR3 = crate::Reg<u32, _KEYR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR3;
    ///`read()` method returns [keyr3::R](keyr3::R) reader structure
    impl crate::Readable for KEYR3 {}
    ///`write(|w| ..)` method takes [keyr3::W](keyr3::W) writer structure
    impl crate::Writable for KEYR3 {}
    ///key register 3
    pub mod keyr3 {
        ///Reader of register KEYR3
        pub type R = crate::R<u32, super::KEYR3>;
        ///Writer for register KEYR3
        pub type W = crate::W<u32, super::KEYR3>;
        ///Register KEYR3 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR3`
        pub type AES_KEYR3_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR3`
        pub struct AES_KEYR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[127:96\])
            #[inline(always)]
            pub fn aes_keyr3(&self) -> AES_KEYR3_R {
                AES_KEYR3_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[127:96\])
            #[inline(always)]
            pub fn aes_keyr3(&mut self) -> AES_KEYR3_W {
                AES_KEYR3_W { w: self }
            }
        }
    }
    ///initialization vector register 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr0](ivr0) module
    pub type IVR0 = crate::Reg<u32, _IVR0>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR0;
    ///`read()` method returns [ivr0::R](ivr0::R) reader structure
    impl crate::Readable for IVR0 {}
    ///`write(|w| ..)` method takes [ivr0::W](ivr0::W) writer structure
    impl crate::Writable for IVR0 {}
    ///initialization vector register 0
    pub mod ivr0 {
        ///Reader of register IVR0
        pub type R = crate::R<u32, super::IVR0>;
        ///Writer for register IVR0
        pub type W = crate::W<u32, super::IVR0>;
        ///Register IVR0 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR0 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR0`
        pub type AES_IVR0_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR0`
        pub struct AES_IVR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - initialization vector register (LSB IVR \[31:0\])
            #[inline(always)]
            pub fn aes_ivr0(&self) -> AES_IVR0_R {
                AES_IVR0_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - initialization vector register (LSB IVR \[31:0\])
            #[inline(always)]
            pub fn aes_ivr0(&mut self) -> AES_IVR0_W {
                AES_IVR0_W { w: self }
            }
        }
    }
    ///initialization vector register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr1](ivr1) module
    pub type IVR1 = crate::Reg<u32, _IVR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR1;
    ///`read()` method returns [ivr1::R](ivr1::R) reader structure
    impl crate::Readable for IVR1 {}
    ///`write(|w| ..)` method takes [ivr1::W](ivr1::W) writer structure
    impl crate::Writable for IVR1 {}
    ///initialization vector register 1
    pub mod ivr1 {
        ///Reader of register IVR1
        pub type R = crate::R<u32, super::IVR1>;
        ///Writer for register IVR1
        pub type W = crate::W<u32, super::IVR1>;
        ///Register IVR1 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR1`
        pub type AES_IVR1_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR1`
        pub struct AES_IVR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Initialization Vector Register (IVR \[63:32\])
            #[inline(always)]
            pub fn aes_ivr1(&self) -> AES_IVR1_R {
                AES_IVR1_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Initialization Vector Register (IVR \[63:32\])
            #[inline(always)]
            pub fn aes_ivr1(&mut self) -> AES_IVR1_W {
                AES_IVR1_W { w: self }
            }
        }
    }
    ///initialization vector register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr2](ivr2) module
    pub type IVR2 = crate::Reg<u32, _IVR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR2;
    ///`read()` method returns [ivr2::R](ivr2::R) reader structure
    impl crate::Readable for IVR2 {}
    ///`write(|w| ..)` method takes [ivr2::W](ivr2::W) writer structure
    impl crate::Writable for IVR2 {}
    ///initialization vector register 2
    pub mod ivr2 {
        ///Reader of register IVR2
        pub type R = crate::R<u32, super::IVR2>;
        ///Writer for register IVR2
        pub type W = crate::W<u32, super::IVR2>;
        ///Register IVR2 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR2`
        pub type AES_IVR2_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR2`
        pub struct AES_IVR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Initialization Vector Register (IVR \[95:64\])
            #[inline(always)]
            pub fn aes_ivr2(&self) -> AES_IVR2_R {
                AES_IVR2_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Initialization Vector Register (IVR \[95:64\])
            #[inline(always)]
            pub fn aes_ivr2(&mut self) -> AES_IVR2_W {
                AES_IVR2_W { w: self }
            }
        }
    }
    ///initialization vector register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ivr3](ivr3) module
    pub type IVR3 = crate::Reg<u32, _IVR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IVR3;
    ///`read()` method returns [ivr3::R](ivr3::R) reader structure
    impl crate::Readable for IVR3 {}
    ///`write(|w| ..)` method takes [ivr3::W](ivr3::W) writer structure
    impl crate::Writable for IVR3 {}
    ///initialization vector register 3
    pub mod ivr3 {
        ///Reader of register IVR3
        pub type R = crate::R<u32, super::IVR3>;
        ///Writer for register IVR3
        pub type W = crate::W<u32, super::IVR3>;
        ///Register IVR3 `reset()`'s with value 0
        impl crate::ResetValue for super::IVR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_IVR3`
        pub type AES_IVR3_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_IVR3`
        pub struct AES_IVR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_IVR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - Initialization Vector Register (MSB IVR \[127:96\])
            #[inline(always)]
            pub fn aes_ivr3(&self) -> AES_IVR3_R {
                AES_IVR3_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - Initialization Vector Register (MSB IVR \[127:96\])
            #[inline(always)]
            pub fn aes_ivr3(&mut self) -> AES_IVR3_W {
                AES_IVR3_W { w: self }
            }
        }
    }
    ///key register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr4](keyr4) module
    pub type KEYR4 = crate::Reg<u32, _KEYR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR4;
    ///`read()` method returns [keyr4::R](keyr4::R) reader structure
    impl crate::Readable for KEYR4 {}
    ///`write(|w| ..)` method takes [keyr4::W](keyr4::W) writer structure
    impl crate::Writable for KEYR4 {}
    ///key register 4
    pub mod keyr4 {
        ///Reader of register KEYR4
        pub type R = crate::R<u32, super::KEYR4>;
        ///Writer for register KEYR4
        pub type W = crate::W<u32, super::KEYR4>;
        ///Register KEYR4 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR4`
        pub type AES_KEYR4_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR4`
        pub struct AES_KEYR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[159:128\])
            #[inline(always)]
            pub fn aes_keyr4(&self) -> AES_KEYR4_R {
                AES_KEYR4_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[159:128\])
            #[inline(always)]
            pub fn aes_keyr4(&mut self) -> AES_KEYR4_W {
                AES_KEYR4_W { w: self }
            }
        }
    }
    ///key register 5
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr5](keyr5) module
    pub type KEYR5 = crate::Reg<u32, _KEYR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR5;
    ///`read()` method returns [keyr5::R](keyr5::R) reader structure
    impl crate::Readable for KEYR5 {}
    ///`write(|w| ..)` method takes [keyr5::W](keyr5::W) writer structure
    impl crate::Writable for KEYR5 {}
    ///key register 5
    pub mod keyr5 {
        ///Reader of register KEYR5
        pub type R = crate::R<u32, super::KEYR5>;
        ///Writer for register KEYR5
        pub type W = crate::W<u32, super::KEYR5>;
        ///Register KEYR5 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR5`
        pub type AES_KEYR5_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR5`
        pub struct AES_KEYR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[191:160\])
            #[inline(always)]
            pub fn aes_keyr5(&self) -> AES_KEYR5_R {
                AES_KEYR5_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[191:160\])
            #[inline(always)]
            pub fn aes_keyr5(&mut self) -> AES_KEYR5_W {
                AES_KEYR5_W { w: self }
            }
        }
    }
    ///key register 6
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr6](keyr6) module
    pub type KEYR6 = crate::Reg<u32, _KEYR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR6;
    ///`read()` method returns [keyr6::R](keyr6::R) reader structure
    impl crate::Readable for KEYR6 {}
    ///`write(|w| ..)` method takes [keyr6::W](keyr6::W) writer structure
    impl crate::Writable for KEYR6 {}
    ///key register 6
    pub mod keyr6 {
        ///Reader of register KEYR6
        pub type R = crate::R<u32, super::KEYR6>;
        ///Writer for register KEYR6
        pub type W = crate::W<u32, super::KEYR6>;
        ///Register KEYR6 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR6`
        pub type AES_KEYR6_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR6`
        pub struct AES_KEYR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[223:192\])
            #[inline(always)]
            pub fn aes_keyr6(&self) -> AES_KEYR6_R {
                AES_KEYR6_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[223:192\])
            #[inline(always)]
            pub fn aes_keyr6(&mut self) -> AES_KEYR6_W {
                AES_KEYR6_W { w: self }
            }
        }
    }
    ///key register 7
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr7](keyr7) module
    pub type KEYR7 = crate::Reg<u32, _KEYR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR7;
    ///`read()` method returns [keyr7::R](keyr7::R) reader structure
    impl crate::Readable for KEYR7 {}
    ///`write(|w| ..)` method takes [keyr7::W](keyr7::W) writer structure
    impl crate::Writable for KEYR7 {}
    ///key register 7
    pub mod keyr7 {
        ///Reader of register KEYR7
        pub type R = crate::R<u32, super::KEYR7>;
        ///Writer for register KEYR7
        pub type W = crate::W<u32, super::KEYR7>;
        ///Register KEYR7 `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_KEYR7`
        pub type AES_KEYR7_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_KEYR7`
        pub struct AES_KEYR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_KEYR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES key register (MSB key \[255:224\])
            #[inline(always)]
            pub fn aes_keyr7(&self) -> AES_KEYR7_R {
                AES_KEYR7_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES key register (MSB key \[255:224\])
            #[inline(always)]
            pub fn aes_keyr7(&mut self) -> AES_KEYR7_W {
                AES_KEYR7_W { w: self }
            }
        }
    }
    ///AES suspend register 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp0r](susp0r) module
    pub type SUSP0R = crate::Reg<u32, _SUSP0R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP0R;
    ///`read()` method returns [susp0r::R](susp0r::R) reader structure
    impl crate::Readable for SUSP0R {}
    ///`write(|w| ..)` method takes [susp0r::W](susp0r::W) writer structure
    impl crate::Writable for SUSP0R {}
    ///AES suspend register 0
    pub mod susp0r {
        ///Reader of register SUSP0R
        pub type R = crate::R<u32, super::SUSP0R>;
        ///Writer for register SUSP0R
        pub type W = crate::W<u32, super::SUSP0R>;
        ///Register SUSP0R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP0R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP0R`
        pub type AES_SUSP0R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP0R`
        pub struct AES_SUSP0R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP0R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 0
            #[inline(always)]
            pub fn aes_susp0r(&self) -> AES_SUSP0R_R {
                AES_SUSP0R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 0
            #[inline(always)]
            pub fn aes_susp0r(&mut self) -> AES_SUSP0R_W {
                AES_SUSP0R_W { w: self }
            }
        }
    }
    ///AES suspend register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp1r](susp1r) module
    pub type SUSP1R = crate::Reg<u32, _SUSP1R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP1R;
    ///`read()` method returns [susp1r::R](susp1r::R) reader structure
    impl crate::Readable for SUSP1R {}
    ///`write(|w| ..)` method takes [susp1r::W](susp1r::W) writer structure
    impl crate::Writable for SUSP1R {}
    ///AES suspend register 1
    pub mod susp1r {
        ///Reader of register SUSP1R
        pub type R = crate::R<u32, super::SUSP1R>;
        ///Writer for register SUSP1R
        pub type W = crate::W<u32, super::SUSP1R>;
        ///Register SUSP1R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP1R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP1R`
        pub type AES_SUSP1R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP1R`
        pub struct AES_SUSP1R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP1R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 1
            #[inline(always)]
            pub fn aes_susp1r(&self) -> AES_SUSP1R_R {
                AES_SUSP1R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 1
            #[inline(always)]
            pub fn aes_susp1r(&mut self) -> AES_SUSP1R_W {
                AES_SUSP1R_W { w: self }
            }
        }
    }
    ///AES suspend register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp2r](susp2r) module
    pub type SUSP2R = crate::Reg<u32, _SUSP2R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP2R;
    ///`read()` method returns [susp2r::R](susp2r::R) reader structure
    impl crate::Readable for SUSP2R {}
    ///`write(|w| ..)` method takes [susp2r::W](susp2r::W) writer structure
    impl crate::Writable for SUSP2R {}
    ///AES suspend register 2
    pub mod susp2r {
        ///Reader of register SUSP2R
        pub type R = crate::R<u32, super::SUSP2R>;
        ///Writer for register SUSP2R
        pub type W = crate::W<u32, super::SUSP2R>;
        ///Register SUSP2R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP2R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP2R`
        pub type AES_SUSP2R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP2R`
        pub struct AES_SUSP2R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP2R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 2
            #[inline(always)]
            pub fn aes_susp2r(&self) -> AES_SUSP2R_R {
                AES_SUSP2R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 2
            #[inline(always)]
            pub fn aes_susp2r(&mut self) -> AES_SUSP2R_W {
                AES_SUSP2R_W { w: self }
            }
        }
    }
    ///AES suspend register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp3r](susp3r) module
    pub type SUSP3R = crate::Reg<u32, _SUSP3R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP3R;
    ///`read()` method returns [susp3r::R](susp3r::R) reader structure
    impl crate::Readable for SUSP3R {}
    ///`write(|w| ..)` method takes [susp3r::W](susp3r::W) writer structure
    impl crate::Writable for SUSP3R {}
    ///AES suspend register 3
    pub mod susp3r {
        ///Reader of register SUSP3R
        pub type R = crate::R<u32, super::SUSP3R>;
        ///Writer for register SUSP3R
        pub type W = crate::W<u32, super::SUSP3R>;
        ///Register SUSP3R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP3R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP3R`
        pub type AES_SUSP3R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP3R`
        pub struct AES_SUSP3R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP3R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 3
            #[inline(always)]
            pub fn aes_susp3r(&self) -> AES_SUSP3R_R {
                AES_SUSP3R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 3
            #[inline(always)]
            pub fn aes_susp3r(&mut self) -> AES_SUSP3R_W {
                AES_SUSP3R_W { w: self }
            }
        }
    }
    ///AES suspend register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp4r](susp4r) module
    pub type SUSP4R = crate::Reg<u32, _SUSP4R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP4R;
    ///`read()` method returns [susp4r::R](susp4r::R) reader structure
    impl crate::Readable for SUSP4R {}
    ///`write(|w| ..)` method takes [susp4r::W](susp4r::W) writer structure
    impl crate::Writable for SUSP4R {}
    ///AES suspend register 4
    pub mod susp4r {
        ///Reader of register SUSP4R
        pub type R = crate::R<u32, super::SUSP4R>;
        ///Writer for register SUSP4R
        pub type W = crate::W<u32, super::SUSP4R>;
        ///Register SUSP4R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP4R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP4R`
        pub type AES_SUSP4R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP4R`
        pub struct AES_SUSP4R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP4R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 4
            #[inline(always)]
            pub fn aes_susp4r(&self) -> AES_SUSP4R_R {
                AES_SUSP4R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 4
            #[inline(always)]
            pub fn aes_susp4r(&mut self) -> AES_SUSP4R_W {
                AES_SUSP4R_W { w: self }
            }
        }
    }
    ///AES suspend register 5
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp5r](susp5r) module
    pub type SUSP5R = crate::Reg<u32, _SUSP5R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP5R;
    ///`read()` method returns [susp5r::R](susp5r::R) reader structure
    impl crate::Readable for SUSP5R {}
    ///`write(|w| ..)` method takes [susp5r::W](susp5r::W) writer structure
    impl crate::Writable for SUSP5R {}
    ///AES suspend register 5
    pub mod susp5r {
        ///Reader of register SUSP5R
        pub type R = crate::R<u32, super::SUSP5R>;
        ///Writer for register SUSP5R
        pub type W = crate::W<u32, super::SUSP5R>;
        ///Register SUSP5R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP5R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP5R`
        pub type AES_SUSP5R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP5R`
        pub struct AES_SUSP5R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP5R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 5
            #[inline(always)]
            pub fn aes_susp5r(&self) -> AES_SUSP5R_R {
                AES_SUSP5R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 5
            #[inline(always)]
            pub fn aes_susp5r(&mut self) -> AES_SUSP5R_W {
                AES_SUSP5R_W { w: self }
            }
        }
    }
    ///AES suspend register 6
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp6r](susp6r) module
    pub type SUSP6R = crate::Reg<u32, _SUSP6R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP6R;
    ///`read()` method returns [susp6r::R](susp6r::R) reader structure
    impl crate::Readable for SUSP6R {}
    ///`write(|w| ..)` method takes [susp6r::W](susp6r::W) writer structure
    impl crate::Writable for SUSP6R {}
    ///AES suspend register 6
    pub mod susp6r {
        ///Reader of register SUSP6R
        pub type R = crate::R<u32, super::SUSP6R>;
        ///Writer for register SUSP6R
        pub type W = crate::W<u32, super::SUSP6R>;
        ///Register SUSP6R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP6R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP6R`
        pub type AES_SUSP6R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP6R`
        pub struct AES_SUSP6R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP6R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 6
            #[inline(always)]
            pub fn aes_susp6r(&self) -> AES_SUSP6R_R {
                AES_SUSP6R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 6
            #[inline(always)]
            pub fn aes_susp6r(&mut self) -> AES_SUSP6R_W {
                AES_SUSP6R_W { w: self }
            }
        }
    }
    ///AES suspend register 7
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [susp7r](susp7r) module
    pub type SUSP7R = crate::Reg<u32, _SUSP7R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SUSP7R;
    ///`read()` method returns [susp7r::R](susp7r::R) reader structure
    impl crate::Readable for SUSP7R {}
    ///`write(|w| ..)` method takes [susp7r::W](susp7r::W) writer structure
    impl crate::Writable for SUSP7R {}
    ///AES suspend register 7
    pub mod susp7r {
        ///Reader of register SUSP7R
        pub type R = crate::R<u32, super::SUSP7R>;
        ///Writer for register SUSP7R
        pub type W = crate::W<u32, super::SUSP7R>;
        ///Register SUSP7R `reset()`'s with value 0
        impl crate::ResetValue for super::SUSP7R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AES_SUSP7R`
        pub type AES_SUSP7R_R = crate::R<u32, u32>;
        ///Write proxy for field `AES_SUSP7R`
        pub struct AES_SUSP7R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AES_SUSP7R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - AES suspend register 7
            #[inline(always)]
            pub fn aes_susp7r(&self) -> AES_SUSP7R_R {
                AES_SUSP7R_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - AES suspend register 7
            #[inline(always)]
            pub fn aes_susp7r(&mut self) -> AES_SUSP7R_W {
                AES_SUSP7R_W { w: self }
            }
        }
    }
    ///AES hardware configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfr](hwcfr) module
    pub type HWCFR = crate::Reg<u32, _HWCFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFR;
    ///`read()` method returns [hwcfr::R](hwcfr::R) reader structure
    impl crate::Readable for HWCFR {}
    ///AES hardware configuration register
    pub mod hwcfr {
        ///Reader of register HWCFR
        pub type R = crate::R<u32, super::HWCFR>;
        ///Reader of field `CFG4`
        pub type CFG4_R = crate::R<u8, u8>;
        ///Reader of field `CFG3`
        pub type CFG3_R = crate::R<u8, u8>;
        ///Reader of field `CFG2`
        pub type CFG2_R = crate::R<u8, u8>;
        ///Reader of field `CFG1`
        pub type CFG1_R = crate::R<u8, u8>;
        impl R {
            ///Bits 12:15 - HW Generic 4
            #[inline(always)]
            pub fn cfg4(&self) -> CFG4_R {
                CFG4_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - HW Generic 3
            #[inline(always)]
            pub fn cfg3(&self) -> CFG3_R {
                CFG3_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - HW Generic 2
            #[inline(always)]
            pub fn cfg2(&self) -> CFG2_R {
                CFG2_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - HW Generic 1
            #[inline(always)]
            pub fn cfg1(&self) -> CFG1_R {
                CFG1_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///AES version register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [verr](verr) module
    pub type VERR = crate::Reg<u32, _VERR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _VERR;
    ///`read()` method returns [verr::R](verr::R) reader structure
    impl crate::Readable for VERR {}
    ///AES version register
    pub mod verr {
        ///Reader of register VERR
        pub type R = crate::R<u32, super::VERR>;
        ///Reader of field `MAJREV`
        pub type MAJREV_R = crate::R<u8, u8>;
        ///Reader of field `MINREV`
        pub type MINREV_R = crate::R<u8, u8>;
        impl R {
            ///Bits 4:7 - Major revision
            #[inline(always)]
            pub fn majrev(&self) -> MAJREV_R {
                MAJREV_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Minor revision
            #[inline(always)]
            pub fn minrev(&self) -> MINREV_R {
                MINREV_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///AES identification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ipidr](ipidr) module
    pub type IPIDR = crate::Reg<u32, _IPIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IPIDR;
    ///`read()` method returns [ipidr::R](ipidr::R) reader structure
    impl crate::Readable for IPIDR {}
    ///AES identification register
    pub mod ipidr {
        ///Reader of register IPIDR
        pub type R = crate::R<u32, super::IPIDR>;
        ///Reader of field `ID`
        pub type ID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Identification code
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///AES size ID register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sidr](sidr) module
    pub type SIDR = crate::Reg<u32, _SIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SIDR;
    ///`read()` method returns [sidr::R](sidr::R) reader structure
    impl crate::Readable for SIDR {}
    ///AES size ID register
    pub mod sidr {
        ///Reader of register SIDR
        pub type R = crate::R<u32, super::SIDR>;
        ///Reader of field `ID`
        pub type ID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Size Identification code
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
}
///HSEM
pub struct HSEM {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for HSEM {}
impl HSEM {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const hsem::RegisterBlock {
        0x5800_1400 as *const _
    }
}
impl Deref for HSEM {
    type Target = hsem::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*HSEM::ptr() }
    }
}
///HSEM
pub mod hsem {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Semaphore 0 register
        pub r0: R0,
        ///0x04 - Semaphore 1 register
        pub r1: R1,
        ///0x08 - Semaphore 2 register
        pub r2: R2,
        ///0x0c - Semaphore 3 register
        pub r3: R3,
        ///0x10 - Semaphore 4 register
        pub r4: R4,
        ///0x14 - Semaphore 5 register
        pub r5: R5,
        ///0x18 - Semaphore 6 register
        pub r6: R6,
        ///0x1c - Semaphore 7 register
        pub r7: R7,
        ///0x20 - Semaphore 8 register
        pub r8: R8,
        ///0x24 - Semaphore 9 register
        pub r9: R9,
        ///0x28 - Semaphore 10 register
        pub r10: R10,
        ///0x2c - Semaphore 11 register
        pub r11: R11,
        ///0x30 - Semaphore 12 register
        pub r12: R12,
        ///0x34 - Semaphore 13 register
        pub r13: R13,
        ///0x38 - Semaphore 14 register
        pub r14: R14,
        ///0x3c - Semaphore 15 register
        pub r15: R15,
        ///0x40 - Semaphore 16 register
        pub r16: R16,
        ///0x44 - Semaphore 17 register
        pub r17: R17,
        ///0x48 - Semaphore 18 register
        pub r18: R18,
        ///0x4c - Semaphore 19 register
        pub r19: R19,
        ///0x50 - Semaphore 20 register
        pub r20: R20,
        ///0x54 - Semaphore 21 register
        pub r21: R21,
        ///0x58 - Semaphore 22 register
        pub r22: R22,
        ///0x5c - Semaphore 23 register
        pub r23: R23,
        ///0x60 - Semaphore 24 register
        pub r24: R24,
        ///0x64 - Semaphore 25 register
        pub r25: R25,
        ///0x68 - Semaphore 26 register
        pub r26: R26,
        ///0x6c - Semaphore 27 register
        pub r27: R27,
        ///0x70 - Semaphore 28 register
        pub r28: R28,
        ///0x74 - Semaphore 29 register
        pub r29: R29,
        ///0x78 - Semaphore 30 register
        pub r30: R30,
        ///0x7c - Semaphore 31 register
        pub r31: R31,
        ///0x80 - Semaphore 0 read lock register
        pub rlr0: RLR0,
        ///0x84 - Semaphore 1 read lock register
        pub rlr1: RLR1,
        ///0x88 - Semaphore 2 read lock register
        pub rlr2: RLR2,
        ///0x8c - Semaphore 3 read lock register
        pub rlr3: RLR3,
        ///0x90 - Semaphore 4 read lock read lock register
        pub rlr4: RLR4,
        ///0x94 - Semaphore 5 read lock register
        pub rlr5: RLR5,
        ///0x98 - Semaphore 6 read lock register
        pub rlr6: RLR6,
        ///0x9c - Semaphore 7 read lock register
        pub rlr7: RLR7,
        ///0xa0 - Semaphore 8 read lock register
        pub rlr8: RLR8,
        ///0xa4 - Semaphore 9 read lock register
        pub rlr9: RLR9,
        ///0xa8 - Semaphore 10 read lock register
        pub rlr10: RLR10,
        ///0xac - Semaphore 11 read lock register
        pub rlr11: RLR11,
        ///0xb0 - Semaphore 12 read lock register
        pub rlr12: RLR12,
        ///0xb4 - Semaphore 13 read lock register
        pub rlr13: RLR13,
        ///0xb8 - Semaphore 14 read lock register
        pub rlr14: RLR14,
        ///0xbc - Semaphore 15 read lock register
        pub rlr15: RLR15,
        ///0xc0 - Semaphore 16 read lock register
        pub rlr16: RLR16,
        ///0xc4 - Semaphore 17 read lock register
        pub rlr17: RLR17,
        ///0xc8 - Semaphore 18 read lock register
        pub rlr18: RLR18,
        ///0xcc - Semaphore 19 read lock register
        pub rlr19: RLR19,
        ///0xd0 - Semaphore 20 read lock register
        pub rlr20: RLR20,
        ///0xd4 - Semaphore 21 read lock register
        pub rlr21: RLR21,
        ///0xd8 - Semaphore 22 read lock register
        pub rlr22: RLR22,
        ///0xdc - Semaphore 23 read lock register
        pub rlr23: RLR23,
        ///0xe0 - Semaphore 24 read lock register
        pub rlr24: RLR24,
        ///0xe4 - Semaphore 25 read lock register
        pub rlr25: RLR25,
        ///0xe8 - Semaphore 26 read lock register
        pub rlr26: RLR26,
        ///0xec - Semaphore 27 read lock register
        pub rlr27: RLR27,
        ///0xf0 - Semaphore 28 read lock register
        pub rlr28: RLR28,
        ///0xf4 - Semaphore 29 read lock register
        pub rlr29: RLR29,
        ///0xf8 - Semaphore 30 read lock register
        pub rlr30: RLR30,
        ///0xfc - Semaphore 31 read lock register
        pub rlr31: RLR31,
        ///0x100 - HSEM Interrupt enable register
        pub c1ier: C1IER,
        ///0x104 - HSEM Interrupt clear register
        pub c1icr: C1ICR,
        ///0x108 - HSEM Interrupt status register
        pub c1isr: C1ISR,
        ///0x10c - HSEM Masked interrupt status register
        pub c1misr: C1MISR,
        ///0x110 - HSEM Interrupt enable register
        pub c2ier: C2IER,
        ///0x114 - HSEM Interrupt clear register
        pub c2icr: C2ICR,
        ///0x118 - HSEM Interrupt status register
        pub c2isr: C2ISR,
        ///0x11c - HSEM Masked interrupt status register
        pub c2misr: C2MISR,
        _reserved72: [u8; 32usize],
        ///0x140 - Semaphore Clear register
        pub cr: CR,
        ///0x144 - Interrupt clear register
        pub keyr: KEYR,
        _reserved74: [u8; 676usize],
        ///0x3ec - Semaphore hardware configuration register 2
        pub hwcfgr2: HWCFGR2,
        ///0x3f0 - Semaphore hardware configuration register 1
        pub hwcfgr1: HWCFGR1,
        ///0x3f4 - HSEM version register
        pub verr: VERR,
        ///0x3f8 - HSEM indentification register
        pub ipidr: IPIDR,
        ///0x3fc - HSEM size indentification register
        pub sidr: SIDR,
    }
    ///Semaphore 0 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r0](r0) module
    pub type R0 = crate::Reg<u32, _R0>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R0;
    ///`read()` method returns [r0::R](r0::R) reader structure
    impl crate::Readable for R0 {}
    ///`write(|w| ..)` method takes [r0::W](r0::W) writer structure
    impl crate::Writable for R0 {}
    ///Semaphore 0 register
    pub mod r0 {
        ///Reader of register R0
        pub type R = crate::R<u32, super::R0>;
        ///Writer for register R0
        pub type W = crate::W<u32, super::R0>;
        ///Register R0 `reset()`'s with value 0
        impl crate::ResetValue for super::R0 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 1 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r1](r1) module
    pub type R1 = crate::Reg<u32, _R1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R1;
    ///`read()` method returns [r1::R](r1::R) reader structure
    impl crate::Readable for R1 {}
    ///`write(|w| ..)` method takes [r1::W](r1::W) writer structure
    impl crate::Writable for R1 {}
    ///Semaphore 1 register
    pub mod r1 {
        ///Reader of register R1
        pub type R = crate::R<u32, super::R1>;
        ///Writer for register R1
        pub type W = crate::W<u32, super::R1>;
        ///Register R1 `reset()`'s with value 0
        impl crate::ResetValue for super::R1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 2 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r2](r2) module
    pub type R2 = crate::Reg<u32, _R2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R2;
    ///`read()` method returns [r2::R](r2::R) reader structure
    impl crate::Readable for R2 {}
    ///`write(|w| ..)` method takes [r2::W](r2::W) writer structure
    impl crate::Writable for R2 {}
    ///Semaphore 2 register
    pub mod r2 {
        ///Reader of register R2
        pub type R = crate::R<u32, super::R2>;
        ///Writer for register R2
        pub type W = crate::W<u32, super::R2>;
        ///Register R2 `reset()`'s with value 0
        impl crate::ResetValue for super::R2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 3 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r3](r3) module
    pub type R3 = crate::Reg<u32, _R3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R3;
    ///`read()` method returns [r3::R](r3::R) reader structure
    impl crate::Readable for R3 {}
    ///`write(|w| ..)` method takes [r3::W](r3::W) writer structure
    impl crate::Writable for R3 {}
    ///Semaphore 3 register
    pub mod r3 {
        ///Reader of register R3
        pub type R = crate::R<u32, super::R3>;
        ///Writer for register R3
        pub type W = crate::W<u32, super::R3>;
        ///Register R3 `reset()`'s with value 0
        impl crate::ResetValue for super::R3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 4 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r4](r4) module
    pub type R4 = crate::Reg<u32, _R4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R4;
    ///`read()` method returns [r4::R](r4::R) reader structure
    impl crate::Readable for R4 {}
    ///`write(|w| ..)` method takes [r4::W](r4::W) writer structure
    impl crate::Writable for R4 {}
    ///Semaphore 4 register
    pub mod r4 {
        ///Reader of register R4
        pub type R = crate::R<u32, super::R4>;
        ///Writer for register R4
        pub type W = crate::W<u32, super::R4>;
        ///Register R4 `reset()`'s with value 0
        impl crate::ResetValue for super::R4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 5 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r5](r5) module
    pub type R5 = crate::Reg<u32, _R5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R5;
    ///`read()` method returns [r5::R](r5::R) reader structure
    impl crate::Readable for R5 {}
    ///`write(|w| ..)` method takes [r5::W](r5::W) writer structure
    impl crate::Writable for R5 {}
    ///Semaphore 5 register
    pub mod r5 {
        ///Reader of register R5
        pub type R = crate::R<u32, super::R5>;
        ///Writer for register R5
        pub type W = crate::W<u32, super::R5>;
        ///Register R5 `reset()`'s with value 0
        impl crate::ResetValue for super::R5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 6 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r6](r6) module
    pub type R6 = crate::Reg<u32, _R6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R6;
    ///`read()` method returns [r6::R](r6::R) reader structure
    impl crate::Readable for R6 {}
    ///`write(|w| ..)` method takes [r6::W](r6::W) writer structure
    impl crate::Writable for R6 {}
    ///Semaphore 6 register
    pub mod r6 {
        ///Reader of register R6
        pub type R = crate::R<u32, super::R6>;
        ///Writer for register R6
        pub type W = crate::W<u32, super::R6>;
        ///Register R6 `reset()`'s with value 0
        impl crate::ResetValue for super::R6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 7 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r7](r7) module
    pub type R7 = crate::Reg<u32, _R7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R7;
    ///`read()` method returns [r7::R](r7::R) reader structure
    impl crate::Readable for R7 {}
    ///`write(|w| ..)` method takes [r7::W](r7::W) writer structure
    impl crate::Writable for R7 {}
    ///Semaphore 7 register
    pub mod r7 {
        ///Reader of register R7
        pub type R = crate::R<u32, super::R7>;
        ///Writer for register R7
        pub type W = crate::W<u32, super::R7>;
        ///Register R7 `reset()`'s with value 0
        impl crate::ResetValue for super::R7 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 8 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r8](r8) module
    pub type R8 = crate::Reg<u32, _R8>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R8;
    ///`read()` method returns [r8::R](r8::R) reader structure
    impl crate::Readable for R8 {}
    ///`write(|w| ..)` method takes [r8::W](r8::W) writer structure
    impl crate::Writable for R8 {}
    ///Semaphore 8 register
    pub mod r8 {
        ///Reader of register R8
        pub type R = crate::R<u32, super::R8>;
        ///Writer for register R8
        pub type W = crate::W<u32, super::R8>;
        ///Register R8 `reset()`'s with value 0
        impl crate::ResetValue for super::R8 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 9 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r9](r9) module
    pub type R9 = crate::Reg<u32, _R9>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R9;
    ///`read()` method returns [r9::R](r9::R) reader structure
    impl crate::Readable for R9 {}
    ///`write(|w| ..)` method takes [r9::W](r9::W) writer structure
    impl crate::Writable for R9 {}
    ///Semaphore 9 register
    pub mod r9 {
        ///Reader of register R9
        pub type R = crate::R<u32, super::R9>;
        ///Writer for register R9
        pub type W = crate::W<u32, super::R9>;
        ///Register R9 `reset()`'s with value 0
        impl crate::ResetValue for super::R9 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 10 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r10](r10) module
    pub type R10 = crate::Reg<u32, _R10>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R10;
    ///`read()` method returns [r10::R](r10::R) reader structure
    impl crate::Readable for R10 {}
    ///`write(|w| ..)` method takes [r10::W](r10::W) writer structure
    impl crate::Writable for R10 {}
    ///Semaphore 10 register
    pub mod r10 {
        ///Reader of register R10
        pub type R = crate::R<u32, super::R10>;
        ///Writer for register R10
        pub type W = crate::W<u32, super::R10>;
        ///Register R10 `reset()`'s with value 0
        impl crate::ResetValue for super::R10 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 11 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r11](r11) module
    pub type R11 = crate::Reg<u32, _R11>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R11;
    ///`read()` method returns [r11::R](r11::R) reader structure
    impl crate::Readable for R11 {}
    ///`write(|w| ..)` method takes [r11::W](r11::W) writer structure
    impl crate::Writable for R11 {}
    ///Semaphore 11 register
    pub mod r11 {
        ///Reader of register R11
        pub type R = crate::R<u32, super::R11>;
        ///Writer for register R11
        pub type W = crate::W<u32, super::R11>;
        ///Register R11 `reset()`'s with value 0
        impl crate::ResetValue for super::R11 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 12 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r12](r12) module
    pub type R12 = crate::Reg<u32, _R12>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R12;
    ///`read()` method returns [r12::R](r12::R) reader structure
    impl crate::Readable for R12 {}
    ///`write(|w| ..)` method takes [r12::W](r12::W) writer structure
    impl crate::Writable for R12 {}
    ///Semaphore 12 register
    pub mod r12 {
        ///Reader of register R12
        pub type R = crate::R<u32, super::R12>;
        ///Writer for register R12
        pub type W = crate::W<u32, super::R12>;
        ///Register R12 `reset()`'s with value 0
        impl crate::ResetValue for super::R12 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 13 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r13](r13) module
    pub type R13 = crate::Reg<u32, _R13>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R13;
    ///`read()` method returns [r13::R](r13::R) reader structure
    impl crate::Readable for R13 {}
    ///`write(|w| ..)` method takes [r13::W](r13::W) writer structure
    impl crate::Writable for R13 {}
    ///Semaphore 13 register
    pub mod r13 {
        ///Reader of register R13
        pub type R = crate::R<u32, super::R13>;
        ///Writer for register R13
        pub type W = crate::W<u32, super::R13>;
        ///Register R13 `reset()`'s with value 0
        impl crate::ResetValue for super::R13 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 14 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r14](r14) module
    pub type R14 = crate::Reg<u32, _R14>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R14;
    ///`read()` method returns [r14::R](r14::R) reader structure
    impl crate::Readable for R14 {}
    ///`write(|w| ..)` method takes [r14::W](r14::W) writer structure
    impl crate::Writable for R14 {}
    ///Semaphore 14 register
    pub mod r14 {
        ///Reader of register R14
        pub type R = crate::R<u32, super::R14>;
        ///Writer for register R14
        pub type W = crate::W<u32, super::R14>;
        ///Register R14 `reset()`'s with value 0
        impl crate::ResetValue for super::R14 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 15 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r15](r15) module
    pub type R15 = crate::Reg<u32, _R15>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R15;
    ///`read()` method returns [r15::R](r15::R) reader structure
    impl crate::Readable for R15 {}
    ///`write(|w| ..)` method takes [r15::W](r15::W) writer structure
    impl crate::Writable for R15 {}
    ///Semaphore 15 register
    pub mod r15 {
        ///Reader of register R15
        pub type R = crate::R<u32, super::R15>;
        ///Writer for register R15
        pub type W = crate::W<u32, super::R15>;
        ///Register R15 `reset()`'s with value 0
        impl crate::ResetValue for super::R15 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 16 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r16](r16) module
    pub type R16 = crate::Reg<u32, _R16>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R16;
    ///`read()` method returns [r16::R](r16::R) reader structure
    impl crate::Readable for R16 {}
    ///`write(|w| ..)` method takes [r16::W](r16::W) writer structure
    impl crate::Writable for R16 {}
    ///Semaphore 16 register
    pub mod r16 {
        ///Reader of register R16
        pub type R = crate::R<u32, super::R16>;
        ///Writer for register R16
        pub type W = crate::W<u32, super::R16>;
        ///Register R16 `reset()`'s with value 0
        impl crate::ResetValue for super::R16 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 17 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r17](r17) module
    pub type R17 = crate::Reg<u32, _R17>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R17;
    ///`read()` method returns [r17::R](r17::R) reader structure
    impl crate::Readable for R17 {}
    ///`write(|w| ..)` method takes [r17::W](r17::W) writer structure
    impl crate::Writable for R17 {}
    ///Semaphore 17 register
    pub mod r17 {
        ///Reader of register R17
        pub type R = crate::R<u32, super::R17>;
        ///Writer for register R17
        pub type W = crate::W<u32, super::R17>;
        ///Register R17 `reset()`'s with value 0
        impl crate::ResetValue for super::R17 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 18 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r18](r18) module
    pub type R18 = crate::Reg<u32, _R18>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R18;
    ///`read()` method returns [r18::R](r18::R) reader structure
    impl crate::Readable for R18 {}
    ///`write(|w| ..)` method takes [r18::W](r18::W) writer structure
    impl crate::Writable for R18 {}
    ///Semaphore 18 register
    pub mod r18 {
        ///Reader of register R18
        pub type R = crate::R<u32, super::R18>;
        ///Writer for register R18
        pub type W = crate::W<u32, super::R18>;
        ///Register R18 `reset()`'s with value 0
        impl crate::ResetValue for super::R18 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 19 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r19](r19) module
    pub type R19 = crate::Reg<u32, _R19>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R19;
    ///`read()` method returns [r19::R](r19::R) reader structure
    impl crate::Readable for R19 {}
    ///`write(|w| ..)` method takes [r19::W](r19::W) writer structure
    impl crate::Writable for R19 {}
    ///Semaphore 19 register
    pub mod r19 {
        ///Reader of register R19
        pub type R = crate::R<u32, super::R19>;
        ///Writer for register R19
        pub type W = crate::W<u32, super::R19>;
        ///Register R19 `reset()`'s with value 0
        impl crate::ResetValue for super::R19 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 20 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r20](r20) module
    pub type R20 = crate::Reg<u32, _R20>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R20;
    ///`read()` method returns [r20::R](r20::R) reader structure
    impl crate::Readable for R20 {}
    ///`write(|w| ..)` method takes [r20::W](r20::W) writer structure
    impl crate::Writable for R20 {}
    ///Semaphore 20 register
    pub mod r20 {
        ///Reader of register R20
        pub type R = crate::R<u32, super::R20>;
        ///Writer for register R20
        pub type W = crate::W<u32, super::R20>;
        ///Register R20 `reset()`'s with value 0
        impl crate::ResetValue for super::R20 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 21 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r21](r21) module
    pub type R21 = crate::Reg<u32, _R21>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R21;
    ///`read()` method returns [r21::R](r21::R) reader structure
    impl crate::Readable for R21 {}
    ///`write(|w| ..)` method takes [r21::W](r21::W) writer structure
    impl crate::Writable for R21 {}
    ///Semaphore 21 register
    pub mod r21 {
        ///Reader of register R21
        pub type R = crate::R<u32, super::R21>;
        ///Writer for register R21
        pub type W = crate::W<u32, super::R21>;
        ///Register R21 `reset()`'s with value 0
        impl crate::ResetValue for super::R21 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 22 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r22](r22) module
    pub type R22 = crate::Reg<u32, _R22>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R22;
    ///`read()` method returns [r22::R](r22::R) reader structure
    impl crate::Readable for R22 {}
    ///`write(|w| ..)` method takes [r22::W](r22::W) writer structure
    impl crate::Writable for R22 {}
    ///Semaphore 22 register
    pub mod r22 {
        ///Reader of register R22
        pub type R = crate::R<u32, super::R22>;
        ///Writer for register R22
        pub type W = crate::W<u32, super::R22>;
        ///Register R22 `reset()`'s with value 0
        impl crate::ResetValue for super::R22 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 23 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r23](r23) module
    pub type R23 = crate::Reg<u32, _R23>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R23;
    ///`read()` method returns [r23::R](r23::R) reader structure
    impl crate::Readable for R23 {}
    ///`write(|w| ..)` method takes [r23::W](r23::W) writer structure
    impl crate::Writable for R23 {}
    ///Semaphore 23 register
    pub mod r23 {
        ///Reader of register R23
        pub type R = crate::R<u32, super::R23>;
        ///Writer for register R23
        pub type W = crate::W<u32, super::R23>;
        ///Register R23 `reset()`'s with value 0
        impl crate::ResetValue for super::R23 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 24 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r24](r24) module
    pub type R24 = crate::Reg<u32, _R24>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R24;
    ///`read()` method returns [r24::R](r24::R) reader structure
    impl crate::Readable for R24 {}
    ///`write(|w| ..)` method takes [r24::W](r24::W) writer structure
    impl crate::Writable for R24 {}
    ///Semaphore 24 register
    pub mod r24 {
        ///Reader of register R24
        pub type R = crate::R<u32, super::R24>;
        ///Writer for register R24
        pub type W = crate::W<u32, super::R24>;
        ///Register R24 `reset()`'s with value 0
        impl crate::ResetValue for super::R24 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 25 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r25](r25) module
    pub type R25 = crate::Reg<u32, _R25>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R25;
    ///`read()` method returns [r25::R](r25::R) reader structure
    impl crate::Readable for R25 {}
    ///`write(|w| ..)` method takes [r25::W](r25::W) writer structure
    impl crate::Writable for R25 {}
    ///Semaphore 25 register
    pub mod r25 {
        ///Reader of register R25
        pub type R = crate::R<u32, super::R25>;
        ///Writer for register R25
        pub type W = crate::W<u32, super::R25>;
        ///Register R25 `reset()`'s with value 0
        impl crate::ResetValue for super::R25 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 26 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r26](r26) module
    pub type R26 = crate::Reg<u32, _R26>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R26;
    ///`read()` method returns [r26::R](r26::R) reader structure
    impl crate::Readable for R26 {}
    ///`write(|w| ..)` method takes [r26::W](r26::W) writer structure
    impl crate::Writable for R26 {}
    ///Semaphore 26 register
    pub mod r26 {
        ///Reader of register R26
        pub type R = crate::R<u32, super::R26>;
        ///Writer for register R26
        pub type W = crate::W<u32, super::R26>;
        ///Register R26 `reset()`'s with value 0
        impl crate::ResetValue for super::R26 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 27 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r27](r27) module
    pub type R27 = crate::Reg<u32, _R27>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R27;
    ///`read()` method returns [r27::R](r27::R) reader structure
    impl crate::Readable for R27 {}
    ///`write(|w| ..)` method takes [r27::W](r27::W) writer structure
    impl crate::Writable for R27 {}
    ///Semaphore 27 register
    pub mod r27 {
        ///Reader of register R27
        pub type R = crate::R<u32, super::R27>;
        ///Writer for register R27
        pub type W = crate::W<u32, super::R27>;
        ///Register R27 `reset()`'s with value 0
        impl crate::ResetValue for super::R27 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 28 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r28](r28) module
    pub type R28 = crate::Reg<u32, _R28>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R28;
    ///`read()` method returns [r28::R](r28::R) reader structure
    impl crate::Readable for R28 {}
    ///`write(|w| ..)` method takes [r28::W](r28::W) writer structure
    impl crate::Writable for R28 {}
    ///Semaphore 28 register
    pub mod r28 {
        ///Reader of register R28
        pub type R = crate::R<u32, super::R28>;
        ///Writer for register R28
        pub type W = crate::W<u32, super::R28>;
        ///Register R28 `reset()`'s with value 0
        impl crate::ResetValue for super::R28 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 29 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r29](r29) module
    pub type R29 = crate::Reg<u32, _R29>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R29;
    ///`read()` method returns [r29::R](r29::R) reader structure
    impl crate::Readable for R29 {}
    ///`write(|w| ..)` method takes [r29::W](r29::W) writer structure
    impl crate::Writable for R29 {}
    ///Semaphore 29 register
    pub mod r29 {
        ///Reader of register R29
        pub type R = crate::R<u32, super::R29>;
        ///Writer for register R29
        pub type W = crate::W<u32, super::R29>;
        ///Register R29 `reset()`'s with value 0
        impl crate::ResetValue for super::R29 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 30 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r30](r30) module
    pub type R30 = crate::Reg<u32, _R30>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R30;
    ///`read()` method returns [r30::R](r30::R) reader structure
    impl crate::Readable for R30 {}
    ///`write(|w| ..)` method takes [r30::W](r30::W) writer structure
    impl crate::Writable for R30 {}
    ///Semaphore 30 register
    pub mod r30 {
        ///Reader of register R30
        pub type R = crate::R<u32, super::R30>;
        ///Writer for register R30
        pub type W = crate::W<u32, super::R30>;
        ///Register R30 `reset()`'s with value 0
        impl crate::ResetValue for super::R30 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 31 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [r31](r31) module
    pub type R31 = crate::Reg<u32, _R31>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _R31;
    ///`read()` method returns [r31::R](r31::R) reader structure
    impl crate::Readable for R31 {}
    ///`write(|w| ..)` method takes [r31::W](r31::W) writer structure
    impl crate::Writable for R31 {}
    ///Semaphore 31 register
    pub mod r31 {
        ///Reader of register R31
        pub type R = crate::R<u32, super::R31>;
        ///Writer for register R31
        pub type W = crate::W<u32, super::R31>;
        ///Register R31 `reset()`'s with value 0
        impl crate::ResetValue for super::R31 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        ///Write proxy for field `PROCID`
        pub struct PROCID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&mut self) -> PROCID_W {
                PROCID_W { w: self }
            }
        }
    }
    ///Semaphore 0 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr0](rlr0) module
    pub type RLR0 = crate::Reg<u32, _RLR0>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR0;
    ///`read()` method returns [rlr0::R](rlr0::R) reader structure
    impl crate::Readable for RLR0 {}
    ///Semaphore 0 read lock register
    pub mod rlr0 {
        ///Reader of register RLR0
        pub type R = crate::R<u32, super::RLR0>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 1 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr1](rlr1) module
    pub type RLR1 = crate::Reg<u32, _RLR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR1;
    ///`read()` method returns [rlr1::R](rlr1::R) reader structure
    impl crate::Readable for RLR1 {}
    ///Semaphore 1 read lock register
    pub mod rlr1 {
        ///Reader of register RLR1
        pub type R = crate::R<u32, super::RLR1>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 2 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr2](rlr2) module
    pub type RLR2 = crate::Reg<u32, _RLR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR2;
    ///`read()` method returns [rlr2::R](rlr2::R) reader structure
    impl crate::Readable for RLR2 {}
    ///Semaphore 2 read lock register
    pub mod rlr2 {
        ///Reader of register RLR2
        pub type R = crate::R<u32, super::RLR2>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 3 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr3](rlr3) module
    pub type RLR3 = crate::Reg<u32, _RLR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR3;
    ///`read()` method returns [rlr3::R](rlr3::R) reader structure
    impl crate::Readable for RLR3 {}
    ///Semaphore 3 read lock register
    pub mod rlr3 {
        ///Reader of register RLR3
        pub type R = crate::R<u32, super::RLR3>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 4 read lock read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr4](rlr4) module
    pub type RLR4 = crate::Reg<u32, _RLR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR4;
    ///`read()` method returns [rlr4::R](rlr4::R) reader structure
    impl crate::Readable for RLR4 {}
    ///Semaphore 4 read lock read lock register
    pub mod rlr4 {
        ///Reader of register RLR4
        pub type R = crate::R<u32, super::RLR4>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 5 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr5](rlr5) module
    pub type RLR5 = crate::Reg<u32, _RLR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR5;
    ///`read()` method returns [rlr5::R](rlr5::R) reader structure
    impl crate::Readable for RLR5 {}
    ///Semaphore 5 read lock register
    pub mod rlr5 {
        ///Reader of register RLR5
        pub type R = crate::R<u32, super::RLR5>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 6 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr6](rlr6) module
    pub type RLR6 = crate::Reg<u32, _RLR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR6;
    ///`read()` method returns [rlr6::R](rlr6::R) reader structure
    impl crate::Readable for RLR6 {}
    ///Semaphore 6 read lock register
    pub mod rlr6 {
        ///Reader of register RLR6
        pub type R = crate::R<u32, super::RLR6>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 7 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr7](rlr7) module
    pub type RLR7 = crate::Reg<u32, _RLR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR7;
    ///`read()` method returns [rlr7::R](rlr7::R) reader structure
    impl crate::Readable for RLR7 {}
    ///Semaphore 7 read lock register
    pub mod rlr7 {
        ///Reader of register RLR7
        pub type R = crate::R<u32, super::RLR7>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 8 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr8](rlr8) module
    pub type RLR8 = crate::Reg<u32, _RLR8>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR8;
    ///`read()` method returns [rlr8::R](rlr8::R) reader structure
    impl crate::Readable for RLR8 {}
    ///Semaphore 8 read lock register
    pub mod rlr8 {
        ///Reader of register RLR8
        pub type R = crate::R<u32, super::RLR8>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 9 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr9](rlr9) module
    pub type RLR9 = crate::Reg<u32, _RLR9>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR9;
    ///`read()` method returns [rlr9::R](rlr9::R) reader structure
    impl crate::Readable for RLR9 {}
    ///Semaphore 9 read lock register
    pub mod rlr9 {
        ///Reader of register RLR9
        pub type R = crate::R<u32, super::RLR9>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 10 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr10](rlr10) module
    pub type RLR10 = crate::Reg<u32, _RLR10>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR10;
    ///`read()` method returns [rlr10::R](rlr10::R) reader structure
    impl crate::Readable for RLR10 {}
    ///Semaphore 10 read lock register
    pub mod rlr10 {
        ///Reader of register RLR10
        pub type R = crate::R<u32, super::RLR10>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 11 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr11](rlr11) module
    pub type RLR11 = crate::Reg<u32, _RLR11>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR11;
    ///`read()` method returns [rlr11::R](rlr11::R) reader structure
    impl crate::Readable for RLR11 {}
    ///Semaphore 11 read lock register
    pub mod rlr11 {
        ///Reader of register RLR11
        pub type R = crate::R<u32, super::RLR11>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 12 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr12](rlr12) module
    pub type RLR12 = crate::Reg<u32, _RLR12>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR12;
    ///`read()` method returns [rlr12::R](rlr12::R) reader structure
    impl crate::Readable for RLR12 {}
    ///Semaphore 12 read lock register
    pub mod rlr12 {
        ///Reader of register RLR12
        pub type R = crate::R<u32, super::RLR12>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 13 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr13](rlr13) module
    pub type RLR13 = crate::Reg<u32, _RLR13>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR13;
    ///`read()` method returns [rlr13::R](rlr13::R) reader structure
    impl crate::Readable for RLR13 {}
    ///Semaphore 13 read lock register
    pub mod rlr13 {
        ///Reader of register RLR13
        pub type R = crate::R<u32, super::RLR13>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 14 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr14](rlr14) module
    pub type RLR14 = crate::Reg<u32, _RLR14>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR14;
    ///`read()` method returns [rlr14::R](rlr14::R) reader structure
    impl crate::Readable for RLR14 {}
    ///Semaphore 14 read lock register
    pub mod rlr14 {
        ///Reader of register RLR14
        pub type R = crate::R<u32, super::RLR14>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 15 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr15](rlr15) module
    pub type RLR15 = crate::Reg<u32, _RLR15>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR15;
    ///`read()` method returns [rlr15::R](rlr15::R) reader structure
    impl crate::Readable for RLR15 {}
    ///Semaphore 15 read lock register
    pub mod rlr15 {
        ///Reader of register RLR15
        pub type R = crate::R<u32, super::RLR15>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 16 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr16](rlr16) module
    pub type RLR16 = crate::Reg<u32, _RLR16>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR16;
    ///`read()` method returns [rlr16::R](rlr16::R) reader structure
    impl crate::Readable for RLR16 {}
    ///Semaphore 16 read lock register
    pub mod rlr16 {
        ///Reader of register RLR16
        pub type R = crate::R<u32, super::RLR16>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 17 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr17](rlr17) module
    pub type RLR17 = crate::Reg<u32, _RLR17>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR17;
    ///`read()` method returns [rlr17::R](rlr17::R) reader structure
    impl crate::Readable for RLR17 {}
    ///Semaphore 17 read lock register
    pub mod rlr17 {
        ///Reader of register RLR17
        pub type R = crate::R<u32, super::RLR17>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 18 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr18](rlr18) module
    pub type RLR18 = crate::Reg<u32, _RLR18>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR18;
    ///`read()` method returns [rlr18::R](rlr18::R) reader structure
    impl crate::Readable for RLR18 {}
    ///Semaphore 18 read lock register
    pub mod rlr18 {
        ///Reader of register RLR18
        pub type R = crate::R<u32, super::RLR18>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 19 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr19](rlr19) module
    pub type RLR19 = crate::Reg<u32, _RLR19>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR19;
    ///`read()` method returns [rlr19::R](rlr19::R) reader structure
    impl crate::Readable for RLR19 {}
    ///Semaphore 19 read lock register
    pub mod rlr19 {
        ///Reader of register RLR19
        pub type R = crate::R<u32, super::RLR19>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 20 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr20](rlr20) module
    pub type RLR20 = crate::Reg<u32, _RLR20>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR20;
    ///`read()` method returns [rlr20::R](rlr20::R) reader structure
    impl crate::Readable for RLR20 {}
    ///Semaphore 20 read lock register
    pub mod rlr20 {
        ///Reader of register RLR20
        pub type R = crate::R<u32, super::RLR20>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 21 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr21](rlr21) module
    pub type RLR21 = crate::Reg<u32, _RLR21>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR21;
    ///`read()` method returns [rlr21::R](rlr21::R) reader structure
    impl crate::Readable for RLR21 {}
    ///Semaphore 21 read lock register
    pub mod rlr21 {
        ///Reader of register RLR21
        pub type R = crate::R<u32, super::RLR21>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 22 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr22](rlr22) module
    pub type RLR22 = crate::Reg<u32, _RLR22>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR22;
    ///`read()` method returns [rlr22::R](rlr22::R) reader structure
    impl crate::Readable for RLR22 {}
    ///Semaphore 22 read lock register
    pub mod rlr22 {
        ///Reader of register RLR22
        pub type R = crate::R<u32, super::RLR22>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 23 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr23](rlr23) module
    pub type RLR23 = crate::Reg<u32, _RLR23>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR23;
    ///`read()` method returns [rlr23::R](rlr23::R) reader structure
    impl crate::Readable for RLR23 {}
    ///Semaphore 23 read lock register
    pub mod rlr23 {
        ///Reader of register RLR23
        pub type R = crate::R<u32, super::RLR23>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 24 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr24](rlr24) module
    pub type RLR24 = crate::Reg<u32, _RLR24>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR24;
    ///`read()` method returns [rlr24::R](rlr24::R) reader structure
    impl crate::Readable for RLR24 {}
    ///Semaphore 24 read lock register
    pub mod rlr24 {
        ///Reader of register RLR24
        pub type R = crate::R<u32, super::RLR24>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 25 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr25](rlr25) module
    pub type RLR25 = crate::Reg<u32, _RLR25>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR25;
    ///`read()` method returns [rlr25::R](rlr25::R) reader structure
    impl crate::Readable for RLR25 {}
    ///Semaphore 25 read lock register
    pub mod rlr25 {
        ///Reader of register RLR25
        pub type R = crate::R<u32, super::RLR25>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 26 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr26](rlr26) module
    pub type RLR26 = crate::Reg<u32, _RLR26>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR26;
    ///`read()` method returns [rlr26::R](rlr26::R) reader structure
    impl crate::Readable for RLR26 {}
    ///Semaphore 26 read lock register
    pub mod rlr26 {
        ///Reader of register RLR26
        pub type R = crate::R<u32, super::RLR26>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 27 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr27](rlr27) module
    pub type RLR27 = crate::Reg<u32, _RLR27>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR27;
    ///`read()` method returns [rlr27::R](rlr27::R) reader structure
    impl crate::Readable for RLR27 {}
    ///Semaphore 27 read lock register
    pub mod rlr27 {
        ///Reader of register RLR27
        pub type R = crate::R<u32, super::RLR27>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 28 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr28](rlr28) module
    pub type RLR28 = crate::Reg<u32, _RLR28>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR28;
    ///`read()` method returns [rlr28::R](rlr28::R) reader structure
    impl crate::Readable for RLR28 {}
    ///Semaphore 28 read lock register
    pub mod rlr28 {
        ///Reader of register RLR28
        pub type R = crate::R<u32, super::RLR28>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 29 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr29](rlr29) module
    pub type RLR29 = crate::Reg<u32, _RLR29>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR29;
    ///`read()` method returns [rlr29::R](rlr29::R) reader structure
    impl crate::Readable for RLR29 {}
    ///Semaphore 29 read lock register
    pub mod rlr29 {
        ///Reader of register RLR29
        pub type R = crate::R<u32, super::RLR29>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 30 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr30](rlr30) module
    pub type RLR30 = crate::Reg<u32, _RLR30>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR30;
    ///`read()` method returns [rlr30::R](rlr30::R) reader structure
    impl crate::Readable for RLR30 {}
    ///Semaphore 30 read lock register
    pub mod rlr30 {
        ///Reader of register RLR30
        pub type R = crate::R<u32, super::RLR30>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore 31 read lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rlr31](rlr31) module
    pub type RLR31 = crate::Reg<u32, _RLR31>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RLR31;
    ///`read()` method returns [rlr31::R](rlr31::R) reader structure
    impl crate::Readable for RLR31 {}
    ///Semaphore 31 read lock register
    pub mod rlr31 {
        ///Reader of register RLR31
        pub type R = crate::R<u32, super::RLR31>;
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<bool, bool>;
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Reader of field `PROCID`
        pub type PROCID_R = crate::R<u8, u8>;
        impl R {
            ///Bit 31 - lock indication
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 8:11 - Semaphore CoreID
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Semaphore ProcessID
            #[inline(always)]
            pub fn procid(&self) -> PROCID_R {
                PROCID_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///Semaphore Clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Semaphore Clear register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `KEY`
        pub type KEY_R = crate::R<u16, u16>;
        ///Write proxy for field `KEY`
        pub struct KEY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                self.w
            }
        }
        ///Reader of field `COREID`
        pub type COREID_R = crate::R<u8, u8>;
        ///Write proxy for field `COREID`
        pub struct COREID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COREID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        impl R {
            ///Bits 16:31 - Semaphore clear Key
            #[inline(always)]
            pub fn key(&self) -> KEY_R {
                KEY_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
            ///Bits 8:11 - CoreID of semaphore to be cleared
            #[inline(always)]
            pub fn coreid(&self) -> COREID_R {
                COREID_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 16:31 - Semaphore clear Key
            #[inline(always)]
            pub fn key(&mut self) -> KEY_W {
                KEY_W { w: self }
            }
            ///Bits 8:11 - CoreID of semaphore to be cleared
            #[inline(always)]
            pub fn coreid(&mut self) -> COREID_W {
                COREID_W { w: self }
            }
        }
    }
    ///Interrupt clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [keyr](keyr) module
    pub type KEYR = crate::Reg<u32, _KEYR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _KEYR;
    ///`read()` method returns [keyr::R](keyr::R) reader structure
    impl crate::Readable for KEYR {}
    ///`write(|w| ..)` method takes [keyr::W](keyr::W) writer structure
    impl crate::Writable for KEYR {}
    ///Interrupt clear register
    pub mod keyr {
        ///Reader of register KEYR
        pub type R = crate::R<u32, super::KEYR>;
        ///Writer for register KEYR
        pub type W = crate::W<u32, super::KEYR>;
        ///Register KEYR `reset()`'s with value 0
        impl crate::ResetValue for super::KEYR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `KEY`
        pub type KEY_R = crate::R<u16, u16>;
        ///Write proxy for field `KEY`
        pub struct KEY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                self.w
            }
        }
        impl R {
            ///Bits 16:31 - Semaphore Clear Key
            #[inline(always)]
            pub fn key(&self) -> KEY_R {
                KEY_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 16:31 - Semaphore Clear Key
            #[inline(always)]
            pub fn key(&mut self) -> KEY_W {
                KEY_W { w: self }
            }
        }
    }
    ///Semaphore hardware configuration register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr2](hwcfgr2) module
    pub type HWCFGR2 = crate::Reg<u32, _HWCFGR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR2;
    ///`read()` method returns [hwcfgr2::R](hwcfgr2::R) reader structure
    impl crate::Readable for HWCFGR2 {}
    ///Semaphore hardware configuration register 2
    pub mod hwcfgr2 {
        ///Reader of register HWCFGR2
        pub type R = crate::R<u32, super::HWCFGR2>;
        ///Reader of field `MASTERID4`
        pub type MASTERID4_R = crate::R<u8, u8>;
        ///Reader of field `MASTERID3`
        pub type MASTERID3_R = crate::R<u8, u8>;
        ///Reader of field `MASTERID2`
        pub type MASTERID2_R = crate::R<u8, u8>;
        ///Reader of field `MASTERID1`
        pub type MASTERID1_R = crate::R<u8, u8>;
        impl R {
            ///Bits 12:15 - Hardware Configuration valid bus masters ID4
            #[inline(always)]
            pub fn masterid4(&self) -> MASTERID4_R {
                MASTERID4_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Hardware Configuration valid bus masters ID3
            #[inline(always)]
            pub fn masterid3(&self) -> MASTERID3_R {
                MASTERID3_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Hardware Configuration valid bus masters ID2
            #[inline(always)]
            pub fn masterid2(&self) -> MASTERID2_R {
                MASTERID2_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Hardware Configuration valid bus masters ID1
            #[inline(always)]
            pub fn masterid1(&self) -> MASTERID1_R {
                MASTERID1_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///Semaphore hardware configuration register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr1](hwcfgr1) module
    pub type HWCFGR1 = crate::Reg<u32, _HWCFGR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR1;
    ///`read()` method returns [hwcfgr1::R](hwcfgr1::R) reader structure
    impl crate::Readable for HWCFGR1 {}
    ///Semaphore hardware configuration register 1
    pub mod hwcfgr1 {
        ///Reader of register HWCFGR1
        pub type R = crate::R<u32, super::HWCFGR1>;
        ///Reader of field `NBINT`
        pub type NBINT_R = crate::R<u8, u8>;
        ///Reader of field `NBSEM`
        pub type NBSEM_R = crate::R<u8, u8>;
        impl R {
            ///Bits 8:11 - Hardware Configuration number of interrupts supported number of master IDs
            #[inline(always)]
            pub fn nbint(&self) -> NBINT_R {
                NBINT_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 0:7 - Hardware Configuration number of semaphores
            #[inline(always)]
            pub fn nbsem(&self) -> NBSEM_R {
                NBSEM_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///HSEM version register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [verr](verr) module
    pub type VERR = crate::Reg<u32, _VERR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _VERR;
    ///`read()` method returns [verr::R](verr::R) reader structure
    impl crate::Readable for VERR {}
    ///HSEM version register
    pub mod verr {
        ///Reader of register VERR
        pub type R = crate::R<u32, super::VERR>;
        ///Reader of field `MAJREV`
        pub type MAJREV_R = crate::R<u8, u8>;
        ///Reader of field `MINREV`
        pub type MINREV_R = crate::R<u8, u8>;
        impl R {
            ///Bits 4:7 - Major Revision
            #[inline(always)]
            pub fn majrev(&self) -> MAJREV_R {
                MAJREV_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Minor Revision
            #[inline(always)]
            pub fn minrev(&self) -> MINREV_R {
                MINREV_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///HSEM indentification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ipidr](ipidr) module
    pub type IPIDR = crate::Reg<u32, _IPIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IPIDR;
    ///`read()` method returns [ipidr::R](ipidr::R) reader structure
    impl crate::Readable for IPIDR {}
    ///HSEM indentification register
    pub mod ipidr {
        ///Reader of register IPIDR
        pub type R = crate::R<u32, super::IPIDR>;
        ///Reader of field `ID`
        pub type ID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Identification Code
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///HSEM size indentification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sidr](sidr) module
    pub type SIDR = crate::Reg<u32, _SIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SIDR;
    ///`read()` method returns [sidr::R](sidr::R) reader structure
    impl crate::Readable for SIDR {}
    ///HSEM size indentification register
    pub mod sidr {
        ///Reader of register SIDR
        pub type R = crate::R<u32, super::SIDR>;
        ///Reader of field `SID`
        pub type SID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Size Identification Code
            #[inline(always)]
            pub fn sid(&self) -> SID_R {
                SID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///HSEM Interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1ier](c1ier) module
    pub type C1IER = crate::Reg<u32, _C1IER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1IER;
    ///`read()` method returns [c1ier::R](c1ier::R) reader structure
    impl crate::Readable for C1IER {}
    ///`write(|w| ..)` method takes [c1ier::W](c1ier::W) writer structure
    impl crate::Writable for C1IER {}
    ///HSEM Interrupt enable register
    pub mod c1ier {
        ///Reader of register C1IER
        pub type R = crate::R<u32, super::C1IER>;
        ///Writer for register C1IER
        pub type W = crate::W<u32, super::C1IER>;
        ///Register C1IER `reset()`'s with value 0
        impl crate::ResetValue for super::C1IER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ISEm`
        pub type ISEM_R = crate::R<u32, u32>;
        ///Write proxy for field `ISEm`
        pub struct ISEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ISEM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - CPU(n) semaphore m enable bit
            #[inline(always)]
            pub fn isem(&self) -> ISEM_R {
                ISEM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - CPU(n) semaphore m enable bit
            #[inline(always)]
            pub fn isem(&mut self) -> ISEM_W {
                ISEM_W { w: self }
            }
        }
    }
    ///HSEM Interrupt clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1icr](c1icr) module
    pub type C1ICR = crate::Reg<u32, _C1ICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1ICR;
    ///`read()` method returns [c1icr::R](c1icr::R) reader structure
    impl crate::Readable for C1ICR {}
    ///`write(|w| ..)` method takes [c1icr::W](c1icr::W) writer structure
    impl crate::Writable for C1ICR {}
    ///HSEM Interrupt clear register
    pub mod c1icr {
        ///Reader of register C1ICR
        pub type R = crate::R<u32, super::C1ICR>;
        ///Writer for register C1ICR
        pub type W = crate::W<u32, super::C1ICR>;
        ///Register C1ICR `reset()`'s with value 0
        impl crate::ResetValue for super::C1ICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ISCm`
        pub type ISCM_R = crate::R<u32, u32>;
        ///Write proxy for field `ISCm`
        pub struct ISCM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ISCM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - CPU(n) semaphore m clear bit
            #[inline(always)]
            pub fn iscm(&self) -> ISCM_R {
                ISCM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - CPU(n) semaphore m clear bit
            #[inline(always)]
            pub fn iscm(&mut self) -> ISCM_W {
                ISCM_W { w: self }
            }
        }
    }
    ///HSEM Interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1isr](c1isr) module
    pub type C1ISR = crate::Reg<u32, _C1ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1ISR;
    ///`read()` method returns [c1isr::R](c1isr::R) reader structure
    impl crate::Readable for C1ISR {}
    ///HSEM Interrupt status register
    pub mod c1isr {
        ///Reader of register C1ISR
        pub type R = crate::R<u32, super::C1ISR>;
        ///Reader of field `ISFm`
        pub type ISFM_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - CPU(n) semaphore m status bit before enable (mask)
            #[inline(always)]
            pub fn isfm(&self) -> ISFM_R {
                ISFM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///HSEM Masked interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1misr](c1misr) module
    pub type C1MISR = crate::Reg<u32, _C1MISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1MISR;
    ///`read()` method returns [c1misr::R](c1misr::R) reader structure
    impl crate::Readable for C1MISR {}
    ///HSEM Masked interrupt status register
    pub mod c1misr {
        ///Reader of register C1MISR
        pub type R = crate::R<u32, super::C1MISR>;
        ///Reader of field `MISFm`
        pub type MISFM_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - masked CPU(n) semaphore m status bit after enable (mask).
            #[inline(always)]
            pub fn misfm(&self) -> MISFM_R {
                MISFM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///HSEM Interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ier](c2ier) module
    pub type C2IER = crate::Reg<u32, _C2IER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2IER;
    ///`read()` method returns [c2ier::R](c2ier::R) reader structure
    impl crate::Readable for C2IER {}
    ///`write(|w| ..)` method takes [c2ier::W](c2ier::W) writer structure
    impl crate::Writable for C2IER {}
    ///HSEM Interrupt enable register
    pub mod c2ier {
        ///Reader of register C2IER
        pub type R = crate::R<u32, super::C2IER>;
        ///Writer for register C2IER
        pub type W = crate::W<u32, super::C2IER>;
        ///Register C2IER `reset()`'s with value 0
        impl crate::ResetValue for super::C2IER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ISEm`
        pub type ISEM_R = crate::R<u32, u32>;
        ///Write proxy for field `ISEm`
        pub struct ISEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ISEM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - CPU(2) semaphore m enable bit.
            #[inline(always)]
            pub fn isem(&self) -> ISEM_R {
                ISEM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - CPU(2) semaphore m enable bit.
            #[inline(always)]
            pub fn isem(&mut self) -> ISEM_W {
                ISEM_W { w: self }
            }
        }
    }
    ///HSEM Interrupt clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2icr](c2icr) module
    pub type C2ICR = crate::Reg<u32, _C2ICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2ICR;
    ///`read()` method returns [c2icr::R](c2icr::R) reader structure
    impl crate::Readable for C2ICR {}
    ///`write(|w| ..)` method takes [c2icr::W](c2icr::W) writer structure
    impl crate::Writable for C2ICR {}
    ///HSEM Interrupt clear register
    pub mod c2icr {
        ///Reader of register C2ICR
        pub type R = crate::R<u32, super::C2ICR>;
        ///Writer for register C2ICR
        pub type W = crate::W<u32, super::C2ICR>;
        ///Register C2ICR `reset()`'s with value 0
        impl crate::ResetValue for super::C2ICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ISCm`
        pub type ISCM_R = crate::R<u32, u32>;
        ///Write proxy for field `ISCm`
        pub struct ISCM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ISCM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - CPU(2) semaphore m clear bit
            #[inline(always)]
            pub fn iscm(&self) -> ISCM_R {
                ISCM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - CPU(2) semaphore m clear bit
            #[inline(always)]
            pub fn iscm(&mut self) -> ISCM_W {
                ISCM_W { w: self }
            }
        }
    }
    ///HSEM Interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2isr](c2isr) module
    pub type C2ISR = crate::Reg<u32, _C2ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2ISR;
    ///`read()` method returns [c2isr::R](c2isr::R) reader structure
    impl crate::Readable for C2ISR {}
    ///HSEM Interrupt status register
    pub mod c2isr {
        ///Reader of register C2ISR
        pub type R = crate::R<u32, super::C2ISR>;
        ///Reader of field `ISFm`
        pub type ISFM_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - CPU(2) semaphore m status bit before enable (mask).
            #[inline(always)]
            pub fn isfm(&self) -> ISFM_R {
                ISFM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///HSEM Masked interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2misr](c2misr) module
    pub type C2MISR = crate::Reg<u32, _C2MISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2MISR;
    ///`read()` method returns [c2misr::R](c2misr::R) reader structure
    impl crate::Readable for C2MISR {}
    ///HSEM Masked interrupt status register
    pub mod c2misr {
        ///Reader of register C2MISR
        pub type R = crate::R<u32, super::C2MISR>;
        ///Reader of field `MISFm`
        pub type MISFM_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - masked CPU(2) semaphore m status bit after enable (mask).
            #[inline(always)]
            pub fn misfm(&self) -> MISFM_R {
                MISFM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
}
///Analog to Digital Converter instance 1
pub struct ADC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC {}
impl ADC {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const adc::RegisterBlock {
        0x5004_0000 as *const _
    }
}
impl Deref for ADC {
    type Target = adc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*ADC::ptr() }
    }
}
///Analog to Digital Converter instance 1
pub mod adc {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - ADC interrupt and status register
        pub isr: ISR,
        ///0x04 - ADC interrupt enable register
        pub ier: IER,
        ///0x08 - ADC control register
        pub cr: CR,
        ///0x0c - ADC configuration register 1
        pub cfgr: CFGR,
        ///0x10 - ADC configuration register 2
        pub cfgr2: CFGR2,
        ///0x14 - ADC sampling time register 1
        pub smpr1: SMPR1,
        ///0x18 - ADC sampling time register 2
        pub smpr2: SMPR2,
        _reserved7: [u8; 4usize],
        ///0x20 - ADC analog watchdog 1 threshold register
        pub tr1: TR1,
        ///0x24 - ADC analog watchdog 2 threshold register
        pub tr2: TR2,
        ///0x28 - ADC analog watchdog 3 threshold register
        pub tr3: TR3,
        _reserved10: [u8; 4usize],
        ///0x30 - ADC group regular sequencer ranks register 1
        pub sqr1: SQR1,
        ///0x34 - ADC group regular sequencer ranks register 2
        pub sqr2: SQR2,
        ///0x38 - ADC group regular sequencer ranks register 3
        pub sqr3: SQR3,
        ///0x3c - ADC group regular sequencer ranks register 4
        pub sqr4: SQR4,
        ///0x40 - ADC group regular conversion data register
        pub dr: DR,
        _reserved15: [u8; 8usize],
        ///0x4c - ADC group injected sequencer register
        pub jsqr: JSQR,
        _reserved16: [u8; 16usize],
        ///0x60 - ADC offset number 1 register
        pub ofr1: OFR1,
        ///0x64 - ADC offset number 2 register
        pub ofr2: OFR2,
        ///0x68 - ADC offset number 3 register
        pub ofr3: OFR3,
        ///0x6c - ADC offset number 4 register
        pub ofr4: OFR4,
        _reserved20: [u8; 16usize],
        ///0x80 - ADC group injected sequencer rank 1 register
        pub jdr1: JDR1,
        ///0x84 - ADC group injected sequencer rank 2 register
        pub jdr2: JDR2,
        ///0x88 - ADC group injected sequencer rank 3 register
        pub jdr3: JDR3,
        ///0x8c - ADC group injected sequencer rank 4 register
        pub jdr4: JDR4,
        _reserved24: [u8; 16usize],
        ///0xa0 - ADC analog watchdog 2 configuration register
        pub awd2cr: AWD2CR,
        ///0xa4 - ADC analog watchdog 3 configuration register
        pub awd3cr: AWD3CR,
        _reserved26: [u8; 8usize],
        ///0xb0 - ADC channel differential or single-ended mode selection register
        pub difsel: DIFSEL,
        ///0xb4 - ADC calibration factors register
        pub calfact: CALFACT,
        _reserved28: [u8; 592usize],
        ///0x308 - ADC common control register
        pub ccr: CCR,
    }
    ///ADC interrupt and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///`write(|w| ..)` method takes [isr::W](isr::W) writer structure
    impl crate::Writable for ISR {}
    ///ADC interrupt and status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Writer for register ISR
        pub type W = crate::W<u32, super::ISR>;
        ///Register ISR `reset()`'s with value 0
        impl crate::ResetValue for super::ISR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `JQOVF`
        pub type JQOVF_R = crate::R<bool, bool>;
        ///Write proxy for field `JQOVF`
        pub struct JQOVF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JQOVF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `AWD3`
        pub type AWD3_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD3`
        pub struct AWD3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `AWD2`
        pub type AWD2_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD2`
        pub struct AWD2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `AWD1`
        pub type AWD1_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD1`
        pub struct AWD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `JEOS`
        pub type JEOS_R = crate::R<bool, bool>;
        ///Write proxy for field `JEOS`
        pub struct JEOS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JEOS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `JEOC`
        pub type JEOC_R = crate::R<bool, bool>;
        ///Write proxy for field `JEOC`
        pub struct JEOC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JEOC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `OVR`
        pub type OVR_R = crate::R<bool, bool>;
        ///Write proxy for field `OVR`
        pub struct OVR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `EOS`
        pub type EOS_R = crate::R<bool, bool>;
        ///Write proxy for field `EOS`
        pub struct EOS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `EOC`
        pub type EOC_R = crate::R<bool, bool>;
        ///Write proxy for field `EOC`
        pub struct EOC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `EOSMP`
        pub type EOSMP_R = crate::R<bool, bool>;
        ///Write proxy for field `EOSMP`
        pub struct EOSMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOSMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ADRDY`
        pub type ADRDY_R = crate::R<bool, bool>;
        ///Write proxy for field `ADRDY`
        pub struct ADRDY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADRDY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 10 - ADC group injected contexts queue overflow flag
            #[inline(always)]
            pub fn jqovf(&self) -> JQOVF_R {
                JQOVF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - ADC analog watchdog 3 flag
            #[inline(always)]
            pub fn awd3(&self) -> AWD3_R {
                AWD3_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - ADC analog watchdog 2 flag
            #[inline(always)]
            pub fn awd2(&self) -> AWD2_R {
                AWD2_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - ADC analog watchdog 1 flag
            #[inline(always)]
            pub fn awd1(&self) -> AWD1_R {
                AWD1_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - ADC group injected end of sequence conversions flag
            #[inline(always)]
            pub fn jeos(&self) -> JEOS_R {
                JEOS_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - ADC group injected end of unitary conversion flag
            #[inline(always)]
            pub fn jeoc(&self) -> JEOC_R {
                JEOC_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - ADC group regular overrun flag
            #[inline(always)]
            pub fn ovr(&self) -> OVR_R {
                OVR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - ADC group regular end of sequence conversions flag
            #[inline(always)]
            pub fn eos(&self) -> EOS_R {
                EOS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - ADC group regular end of unitary conversion flag
            #[inline(always)]
            pub fn eoc(&self) -> EOC_R {
                EOC_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - ADC group regular end of sampling flag
            #[inline(always)]
            pub fn eosmp(&self) -> EOSMP_R {
                EOSMP_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - ADC ready flag
            #[inline(always)]
            pub fn adrdy(&self) -> ADRDY_R {
                ADRDY_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 10 - ADC group injected contexts queue overflow flag
            #[inline(always)]
            pub fn jqovf(&mut self) -> JQOVF_W {
                JQOVF_W { w: self }
            }
            ///Bit 9 - ADC analog watchdog 3 flag
            #[inline(always)]
            pub fn awd3(&mut self) -> AWD3_W {
                AWD3_W { w: self }
            }
            ///Bit 8 - ADC analog watchdog 2 flag
            #[inline(always)]
            pub fn awd2(&mut self) -> AWD2_W {
                AWD2_W { w: self }
            }
            ///Bit 7 - ADC analog watchdog 1 flag
            #[inline(always)]
            pub fn awd1(&mut self) -> AWD1_W {
                AWD1_W { w: self }
            }
            ///Bit 6 - ADC group injected end of sequence conversions flag
            #[inline(always)]
            pub fn jeos(&mut self) -> JEOS_W {
                JEOS_W { w: self }
            }
            ///Bit 5 - ADC group injected end of unitary conversion flag
            #[inline(always)]
            pub fn jeoc(&mut self) -> JEOC_W {
                JEOC_W { w: self }
            }
            ///Bit 4 - ADC group regular overrun flag
            #[inline(always)]
            pub fn ovr(&mut self) -> OVR_W {
                OVR_W { w: self }
            }
            ///Bit 3 - ADC group regular end of sequence conversions flag
            #[inline(always)]
            pub fn eos(&mut self) -> EOS_W {
                EOS_W { w: self }
            }
            ///Bit 2 - ADC group regular end of unitary conversion flag
            #[inline(always)]
            pub fn eoc(&mut self) -> EOC_W {
                EOC_W { w: self }
            }
            ///Bit 1 - ADC group regular end of sampling flag
            #[inline(always)]
            pub fn eosmp(&mut self) -> EOSMP_W {
                EOSMP_W { w: self }
            }
            ///Bit 0 - ADC ready flag
            #[inline(always)]
            pub fn adrdy(&mut self) -> ADRDY_W {
                ADRDY_W { w: self }
            }
        }
    }
    ///ADC interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ier](ier) module
    pub type IER = crate::Reg<u32, _IER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IER;
    ///`read()` method returns [ier::R](ier::R) reader structure
    impl crate::Readable for IER {}
    ///`write(|w| ..)` method takes [ier::W](ier::W) writer structure
    impl crate::Writable for IER {}
    ///ADC interrupt enable register
    pub mod ier {
        ///Reader of register IER
        pub type R = crate::R<u32, super::IER>;
        ///Writer for register IER
        pub type W = crate::W<u32, super::IER>;
        ///Register IER `reset()`'s with value 0
        impl crate::ResetValue for super::IER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `JQOVFIE`
        pub type JQOVFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `JQOVFIE`
        pub struct JQOVFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JQOVFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `AWD3IE`
        pub type AWD3IE_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD3IE`
        pub struct AWD3IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD3IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `AWD2IE`
        pub type AWD2IE_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD2IE`
        pub struct AWD2IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD2IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `AWD1IE`
        pub type AWD1IE_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD1IE`
        pub struct AWD1IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD1IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `JEOSIE`
        pub type JEOSIE_R = crate::R<bool, bool>;
        ///Write proxy for field `JEOSIE`
        pub struct JEOSIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JEOSIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `JEOCIE`
        pub type JEOCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `JEOCIE`
        pub struct JEOCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JEOCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `OVRIE`
        pub type OVRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `OVRIE`
        pub struct OVRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `EOSIE`
        pub type EOSIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EOSIE`
        pub struct EOSIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOSIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `EOCIE`
        pub type EOCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EOCIE`
        pub struct EOCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `EOSMPIE`
        pub type EOSMPIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EOSMPIE`
        pub struct EOSMPIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOSMPIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ADRDYIE`
        pub type ADRDYIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ADRDYIE`
        pub struct ADRDYIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADRDYIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 10 - ADC group injected contexts queue overflow interrupt
            #[inline(always)]
            pub fn jqovfie(&self) -> JQOVFIE_R {
                JQOVFIE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - ADC analog watchdog 3 interrupt
            #[inline(always)]
            pub fn awd3ie(&self) -> AWD3IE_R {
                AWD3IE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - ADC analog watchdog 2 interrupt
            #[inline(always)]
            pub fn awd2ie(&self) -> AWD2IE_R {
                AWD2IE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - ADC analog watchdog 1 interrupt
            #[inline(always)]
            pub fn awd1ie(&self) -> AWD1IE_R {
                AWD1IE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - ADC group injected end of sequence conversions interrupt
            #[inline(always)]
            pub fn jeosie(&self) -> JEOSIE_R {
                JEOSIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - ADC group injected end of unitary conversion interrupt
            #[inline(always)]
            pub fn jeocie(&self) -> JEOCIE_R {
                JEOCIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - ADC group regular overrun interrupt
            #[inline(always)]
            pub fn ovrie(&self) -> OVRIE_R {
                OVRIE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - ADC group regular end of sequence conversions interrupt
            #[inline(always)]
            pub fn eosie(&self) -> EOSIE_R {
                EOSIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - ADC group regular end of unitary conversion interrupt
            #[inline(always)]
            pub fn eocie(&self) -> EOCIE_R {
                EOCIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - ADC group regular end of sampling interrupt
            #[inline(always)]
            pub fn eosmpie(&self) -> EOSMPIE_R {
                EOSMPIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - ADC ready interrupt
            #[inline(always)]
            pub fn adrdyie(&self) -> ADRDYIE_R {
                ADRDYIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 10 - ADC group injected contexts queue overflow interrupt
            #[inline(always)]
            pub fn jqovfie(&mut self) -> JQOVFIE_W {
                JQOVFIE_W { w: self }
            }
            ///Bit 9 - ADC analog watchdog 3 interrupt
            #[inline(always)]
            pub fn awd3ie(&mut self) -> AWD3IE_W {
                AWD3IE_W { w: self }
            }
            ///Bit 8 - ADC analog watchdog 2 interrupt
            #[inline(always)]
            pub fn awd2ie(&mut self) -> AWD2IE_W {
                AWD2IE_W { w: self }
            }
            ///Bit 7 - ADC analog watchdog 1 interrupt
            #[inline(always)]
            pub fn awd1ie(&mut self) -> AWD1IE_W {
                AWD1IE_W { w: self }
            }
            ///Bit 6 - ADC group injected end of sequence conversions interrupt
            #[inline(always)]
            pub fn jeosie(&mut self) -> JEOSIE_W {
                JEOSIE_W { w: self }
            }
            ///Bit 5 - ADC group injected end of unitary conversion interrupt
            #[inline(always)]
            pub fn jeocie(&mut self) -> JEOCIE_W {
                JEOCIE_W { w: self }
            }
            ///Bit 4 - ADC group regular overrun interrupt
            #[inline(always)]
            pub fn ovrie(&mut self) -> OVRIE_W {
                OVRIE_W { w: self }
            }
            ///Bit 3 - ADC group regular end of sequence conversions interrupt
            #[inline(always)]
            pub fn eosie(&mut self) -> EOSIE_W {
                EOSIE_W { w: self }
            }
            ///Bit 2 - ADC group regular end of unitary conversion interrupt
            #[inline(always)]
            pub fn eocie(&mut self) -> EOCIE_W {
                EOCIE_W { w: self }
            }
            ///Bit 1 - ADC group regular end of sampling interrupt
            #[inline(always)]
            pub fn eosmpie(&mut self) -> EOSMPIE_W {
                EOSMPIE_W { w: self }
            }
            ///Bit 0 - ADC ready interrupt
            #[inline(always)]
            pub fn adrdyie(&mut self) -> ADRDYIE_W {
                ADRDYIE_W { w: self }
            }
        }
    }
    ///ADC control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///ADC control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADCAL`
        pub type ADCAL_R = crate::R<bool, bool>;
        ///Write proxy for field `ADCAL`
        pub struct ADCAL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCAL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `ADCALDIF`
        pub type ADCALDIF_R = crate::R<bool, bool>;
        ///Write proxy for field `ADCALDIF`
        pub struct ADCALDIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADCALDIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `DEEPPWD`
        pub type DEEPPWD_R = crate::R<bool, bool>;
        ///Write proxy for field `DEEPPWD`
        pub struct DEEPPWD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEEPPWD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `ADVREGEN`
        pub type ADVREGEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ADVREGEN`
        pub struct ADVREGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADVREGEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `JADSTP`
        pub type JADSTP_R = crate::R<bool, bool>;
        ///Write proxy for field `JADSTP`
        pub struct JADSTP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JADSTP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `ADSTP`
        pub type ADSTP_R = crate::R<bool, bool>;
        ///Write proxy for field `ADSTP`
        pub struct ADSTP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADSTP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `JADSTART`
        pub type JADSTART_R = crate::R<bool, bool>;
        ///Write proxy for field `JADSTART`
        pub struct JADSTART_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JADSTART_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ADSTART`
        pub type ADSTART_R = crate::R<bool, bool>;
        ///Write proxy for field `ADSTART`
        pub struct ADSTART_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADSTART_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ADDIS`
        pub type ADDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `ADDIS`
        pub struct ADDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ADEN`
        pub type ADEN_R = crate::R<bool, bool>;
        ///Write proxy for field `ADEN`
        pub struct ADEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - ADC calibration
            #[inline(always)]
            pub fn adcal(&self) -> ADCAL_R {
                ADCAL_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - ADC differential mode for calibration
            #[inline(always)]
            pub fn adcaldif(&self) -> ADCALDIF_R {
                ADCALDIF_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - ADC deep power down enable
            #[inline(always)]
            pub fn deeppwd(&self) -> DEEPPWD_R {
                DEEPPWD_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - ADC voltage regulator enable
            #[inline(always)]
            pub fn advregen(&self) -> ADVREGEN_R {
                ADVREGEN_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 5 - ADC group injected conversion stop
            #[inline(always)]
            pub fn jadstp(&self) -> JADSTP_R {
                JADSTP_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - ADC group regular conversion stop
            #[inline(always)]
            pub fn adstp(&self) -> ADSTP_R {
                ADSTP_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - ADC group injected conversion start
            #[inline(always)]
            pub fn jadstart(&self) -> JADSTART_R {
                JADSTART_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - ADC group regular conversion start
            #[inline(always)]
            pub fn adstart(&self) -> ADSTART_R {
                ADSTART_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - ADC disable
            #[inline(always)]
            pub fn addis(&self) -> ADDIS_R {
                ADDIS_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - ADC enable
            #[inline(always)]
            pub fn aden(&self) -> ADEN_R {
                ADEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - ADC calibration
            #[inline(always)]
            pub fn adcal(&mut self) -> ADCAL_W {
                ADCAL_W { w: self }
            }
            ///Bit 30 - ADC differential mode for calibration
            #[inline(always)]
            pub fn adcaldif(&mut self) -> ADCALDIF_W {
                ADCALDIF_W { w: self }
            }
            ///Bit 29 - ADC deep power down enable
            #[inline(always)]
            pub fn deeppwd(&mut self) -> DEEPPWD_W {
                DEEPPWD_W { w: self }
            }
            ///Bit 28 - ADC voltage regulator enable
            #[inline(always)]
            pub fn advregen(&mut self) -> ADVREGEN_W {
                ADVREGEN_W { w: self }
            }
            ///Bit 5 - ADC group injected conversion stop
            #[inline(always)]
            pub fn jadstp(&mut self) -> JADSTP_W {
                JADSTP_W { w: self }
            }
            ///Bit 4 - ADC group regular conversion stop
            #[inline(always)]
            pub fn adstp(&mut self) -> ADSTP_W {
                ADSTP_W { w: self }
            }
            ///Bit 3 - ADC group injected conversion start
            #[inline(always)]
            pub fn jadstart(&mut self) -> JADSTART_W {
                JADSTART_W { w: self }
            }
            ///Bit 2 - ADC group regular conversion start
            #[inline(always)]
            pub fn adstart(&mut self) -> ADSTART_W {
                ADSTART_W { w: self }
            }
            ///Bit 1 - ADC disable
            #[inline(always)]
            pub fn addis(&mut self) -> ADDIS_W {
                ADDIS_W { w: self }
            }
            ///Bit 0 - ADC enable
            #[inline(always)]
            pub fn aden(&mut self) -> ADEN_W {
                ADEN_W { w: self }
            }
        }
    }
    ///ADC configuration register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfgr](cfgr) module
    pub type CFGR = crate::Reg<u32, _CFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFGR;
    ///`read()` method returns [cfgr::R](cfgr::R) reader structure
    impl crate::Readable for CFGR {}
    ///`write(|w| ..)` method takes [cfgr::W](cfgr::W) writer structure
    impl crate::Writable for CFGR {}
    ///ADC configuration register 1
    pub mod cfgr {
        ///Reader of register CFGR
        pub type R = crate::R<u32, super::CFGR>;
        ///Writer for register CFGR
        pub type W = crate::W<u32, super::CFGR>;
        ///Register CFGR `reset()`'s with value 0x8000_0000
        impl crate::ResetValue for super::CFGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x8000_0000
            }
        }
        ///Reader of field `JQDIS`
        pub type JQDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `JQDIS`
        pub struct JQDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JQDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `AWDCH1CH`
        pub type AWDCH1CH_R = crate::R<u8, u8>;
        ///Write proxy for field `AWDCH1CH`
        pub struct AWDCH1CH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWDCH1CH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 26)) | (((value as u32) & 0x1f) << 26);
                self.w
            }
        }
        ///Reader of field `JAUTO`
        pub type JAUTO_R = crate::R<bool, bool>;
        ///Write proxy for field `JAUTO`
        pub struct JAUTO_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JAUTO_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `JAWD1EN`
        pub type JAWD1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `JAWD1EN`
        pub struct JAWD1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JAWD1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `AWD1EN`
        pub type AWD1EN_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD1EN`
        pub struct AWD1EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD1EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `AWD1SGL`
        pub type AWD1SGL_R = crate::R<bool, bool>;
        ///Write proxy for field `AWD1SGL`
        pub struct AWD1SGL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD1SGL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `JQM`
        pub type JQM_R = crate::R<bool, bool>;
        ///Write proxy for field `JQM`
        pub struct JQM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JQM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `JDISCEN`
        pub type JDISCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `JDISCEN`
        pub struct JDISCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JDISCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `DISCNUM`
        pub type DISCNUM_R = crate::R<u8, u8>;
        ///Write proxy for field `DISCNUM`
        pub struct DISCNUM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DISCNUM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 17)) | (((value as u32) & 0x07) << 17);
                self.w
            }
        }
        ///Reader of field `DISCEN`
        pub type DISCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DISCEN`
        pub struct DISCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DISCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `AUTDLY`
        pub type AUTDLY_R = crate::R<bool, bool>;
        ///Write proxy for field `AUTDLY`
        pub struct AUTDLY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AUTDLY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CONT`
        pub type CONT_R = crate::R<bool, bool>;
        ///Write proxy for field `CONT`
        pub struct CONT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CONT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `OVRMOD`
        pub type OVRMOD_R = crate::R<bool, bool>;
        ///Write proxy for field `OVRMOD`
        pub struct OVRMOD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVRMOD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `EXTEN`
        pub type EXTEN_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTEN`
        pub struct EXTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTEN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `EXTSEL`
        pub type EXTSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `EXTSEL`
        pub struct EXTSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 6)) | (((value as u32) & 0x0f) << 6);
                self.w
            }
        }
        ///Reader of field `ALIGN`
        pub type ALIGN_R = crate::R<bool, bool>;
        ///Write proxy for field `ALIGN`
        pub struct ALIGN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALIGN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `RES`
        pub type RES_R = crate::R<u8, u8>;
        ///Write proxy for field `RES`
        pub struct RES_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RES_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
                self.w
            }
        }
        ///Reader of field `DMACFG`
        pub type DMACFG_R = crate::R<bool, bool>;
        ///Write proxy for field `DMACFG`
        pub struct DMACFG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMACFG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DMAEN`
        pub type DMAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAEN`
        pub struct DMAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - ADC group injected contexts queue disable
            #[inline(always)]
            pub fn jqdis(&self) -> JQDIS_R {
                JQDIS_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 26:30 - ADC analog watchdog 1 monitored channel selection
            #[inline(always)]
            pub fn awdch1ch(&self) -> AWDCH1CH_R {
                AWDCH1CH_R::new(((self.bits >> 26) & 0x1f) as u8)
            }
            ///Bit 25 - ADC group injected automatic trigger mode
            #[inline(always)]
            pub fn jauto(&self) -> JAUTO_R {
                JAUTO_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected
            #[inline(always)]
            pub fn jawd1en(&self) -> JAWD1EN_R {
                JAWD1EN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular
            #[inline(always)]
            pub fn awd1en(&self) -> AWD1EN_R {
                AWD1EN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels
            #[inline(always)]
            pub fn awd1sgl(&self) -> AWD1SGL_R {
                AWD1SGL_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - ADC group injected contexts queue mode
            #[inline(always)]
            pub fn jqm(&self) -> JQM_R {
                JQM_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - ADC group injected sequencer discontinuous mode
            #[inline(always)]
            pub fn jdiscen(&self) -> JDISCEN_R {
                JDISCEN_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bits 17:19 - ADC group regular sequencer discontinuous number of ranks
            #[inline(always)]
            pub fn discnum(&self) -> DISCNUM_R {
                DISCNUM_R::new(((self.bits >> 17) & 0x07) as u8)
            }
            ///Bit 16 - ADC group regular sequencer discontinuous mode
            #[inline(always)]
            pub fn discen(&self) -> DISCEN_R {
                DISCEN_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 14 - ADC low power auto wait
            #[inline(always)]
            pub fn autdly(&self) -> AUTDLY_R {
                AUTDLY_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - ADC group regular continuous conversion mode
            #[inline(always)]
            pub fn cont(&self) -> CONT_R {
                CONT_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - ADC group regular overrun configuration
            #[inline(always)]
            pub fn ovrmod(&self) -> OVRMOD_R {
                OVRMOD_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bits 10:11 - ADC group regular external trigger polarity
            #[inline(always)]
            pub fn exten(&self) -> EXTEN_R {
                EXTEN_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 6:9 - ADC group regular external trigger source
            #[inline(always)]
            pub fn extsel(&self) -> EXTSEL_R {
                EXTSEL_R::new(((self.bits >> 6) & 0x0f) as u8)
            }
            ///Bit 5 - ADC data alignement
            #[inline(always)]
            pub fn align(&self) -> ALIGN_R {
                ALIGN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bits 3:4 - ADC data resolution
            #[inline(always)]
            pub fn res(&self) -> RES_R {
                RES_R::new(((self.bits >> 3) & 0x03) as u8)
            }
            ///Bit 1 - ADC DMA transfer configuration
            #[inline(always)]
            pub fn dmacfg(&self) -> DMACFG_R {
                DMACFG_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - ADC DMA transfer enable
            #[inline(always)]
            pub fn dmaen(&self) -> DMAEN_R {
                DMAEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - ADC group injected contexts queue disable
            #[inline(always)]
            pub fn jqdis(&mut self) -> JQDIS_W {
                JQDIS_W { w: self }
            }
            ///Bits 26:30 - ADC analog watchdog 1 monitored channel selection
            #[inline(always)]
            pub fn awdch1ch(&mut self) -> AWDCH1CH_W {
                AWDCH1CH_W { w: self }
            }
            ///Bit 25 - ADC group injected automatic trigger mode
            #[inline(always)]
            pub fn jauto(&mut self) -> JAUTO_W {
                JAUTO_W { w: self }
            }
            ///Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected
            #[inline(always)]
            pub fn jawd1en(&mut self) -> JAWD1EN_W {
                JAWD1EN_W { w: self }
            }
            ///Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular
            #[inline(always)]
            pub fn awd1en(&mut self) -> AWD1EN_W {
                AWD1EN_W { w: self }
            }
            ///Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels
            #[inline(always)]
            pub fn awd1sgl(&mut self) -> AWD1SGL_W {
                AWD1SGL_W { w: self }
            }
            ///Bit 21 - ADC group injected contexts queue mode
            #[inline(always)]
            pub fn jqm(&mut self) -> JQM_W {
                JQM_W { w: self }
            }
            ///Bit 20 - ADC group injected sequencer discontinuous mode
            #[inline(always)]
            pub fn jdiscen(&mut self) -> JDISCEN_W {
                JDISCEN_W { w: self }
            }
            ///Bits 17:19 - ADC group regular sequencer discontinuous number of ranks
            #[inline(always)]
            pub fn discnum(&mut self) -> DISCNUM_W {
                DISCNUM_W { w: self }
            }
            ///Bit 16 - ADC group regular sequencer discontinuous mode
            #[inline(always)]
            pub fn discen(&mut self) -> DISCEN_W {
                DISCEN_W { w: self }
            }
            ///Bit 14 - ADC low power auto wait
            #[inline(always)]
            pub fn autdly(&mut self) -> AUTDLY_W {
                AUTDLY_W { w: self }
            }
            ///Bit 13 - ADC group regular continuous conversion mode
            #[inline(always)]
            pub fn cont(&mut self) -> CONT_W {
                CONT_W { w: self }
            }
            ///Bit 12 - ADC group regular overrun configuration
            #[inline(always)]
            pub fn ovrmod(&mut self) -> OVRMOD_W {
                OVRMOD_W { w: self }
            }
            ///Bits 10:11 - ADC group regular external trigger polarity
            #[inline(always)]
            pub fn exten(&mut self) -> EXTEN_W {
                EXTEN_W { w: self }
            }
            ///Bits 6:9 - ADC group regular external trigger source
            #[inline(always)]
            pub fn extsel(&mut self) -> EXTSEL_W {
                EXTSEL_W { w: self }
            }
            ///Bit 5 - ADC data alignement
            #[inline(always)]
            pub fn align(&mut self) -> ALIGN_W {
                ALIGN_W { w: self }
            }
            ///Bits 3:4 - ADC data resolution
            #[inline(always)]
            pub fn res(&mut self) -> RES_W {
                RES_W { w: self }
            }
            ///Bit 1 - ADC DMA transfer configuration
            #[inline(always)]
            pub fn dmacfg(&mut self) -> DMACFG_W {
                DMACFG_W { w: self }
            }
            ///Bit 0 - ADC DMA transfer enable
            #[inline(always)]
            pub fn dmaen(&mut self) -> DMAEN_W {
                DMAEN_W { w: self }
            }
        }
    }
    ///ADC configuration register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfgr2](cfgr2) module
    pub type CFGR2 = crate::Reg<u32, _CFGR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFGR2;
    ///`read()` method returns [cfgr2::R](cfgr2::R) reader structure
    impl crate::Readable for CFGR2 {}
    ///`write(|w| ..)` method takes [cfgr2::W](cfgr2::W) writer structure
    impl crate::Writable for CFGR2 {}
    ///ADC configuration register 2
    pub mod cfgr2 {
        ///Reader of register CFGR2
        pub type R = crate::R<u32, super::CFGR2>;
        ///Writer for register CFGR2
        pub type W = crate::W<u32, super::CFGR2>;
        ///Register CFGR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CFGR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ROVSM`
        pub type ROVSM_R = crate::R<bool, bool>;
        ///Write proxy for field `ROVSM`
        pub struct ROVSM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ROVSM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `TOVS`
        pub type TOVS_R = crate::R<bool, bool>;
        ///Write proxy for field `TOVS`
        pub struct TOVS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TOVS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OVSS`
        pub type OVSS_R = crate::R<u8, u8>;
        ///Write proxy for field `OVSS`
        pub struct OVSS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVSS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 5)) | (((value as u32) & 0x0f) << 5);
                self.w
            }
        }
        ///Reader of field `OVSR`
        pub type OVSR_R = crate::R<u8, u8>;
        ///Write proxy for field `OVSR`
        pub struct OVSR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVSR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 2)) | (((value as u32) & 0x07) << 2);
                self.w
            }
        }
        ///Reader of field `JOVSE`
        pub type JOVSE_R = crate::R<bool, bool>;
        ///Write proxy for field `JOVSE`
        pub struct JOVSE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JOVSE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ROVSE`
        pub type ROVSE_R = crate::R<bool, bool>;
        ///Write proxy for field `ROVSE`
        pub struct ROVSE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ROVSE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 10 - ADC oversampling mode managing interlaced conversions of ADC group regular and group injected
            #[inline(always)]
            pub fn rovsm(&self) -> ROVSM_R {
                ROVSM_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular
            #[inline(always)]
            pub fn tovs(&self) -> TOVS_R {
                TOVS_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bits 5:8 - ADC oversampling shift
            #[inline(always)]
            pub fn ovss(&self) -> OVSS_R {
                OVSS_R::new(((self.bits >> 5) & 0x0f) as u8)
            }
            ///Bits 2:4 - ADC oversampling ratio
            #[inline(always)]
            pub fn ovsr(&self) -> OVSR_R {
                OVSR_R::new(((self.bits >> 2) & 0x07) as u8)
            }
            ///Bit 1 - ADC oversampler enable on scope ADC group injected
            #[inline(always)]
            pub fn jovse(&self) -> JOVSE_R {
                JOVSE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - ADC oversampler enable on scope ADC group regular
            #[inline(always)]
            pub fn rovse(&self) -> ROVSE_R {
                ROVSE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 10 - ADC oversampling mode managing interlaced conversions of ADC group regular and group injected
            #[inline(always)]
            pub fn rovsm(&mut self) -> ROVSM_W {
                ROVSM_W { w: self }
            }
            ///Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular
            #[inline(always)]
            pub fn tovs(&mut self) -> TOVS_W {
                TOVS_W { w: self }
            }
            ///Bits 5:8 - ADC oversampling shift
            #[inline(always)]
            pub fn ovss(&mut self) -> OVSS_W {
                OVSS_W { w: self }
            }
            ///Bits 2:4 - ADC oversampling ratio
            #[inline(always)]
            pub fn ovsr(&mut self) -> OVSR_W {
                OVSR_W { w: self }
            }
            ///Bit 1 - ADC oversampler enable on scope ADC group injected
            #[inline(always)]
            pub fn jovse(&mut self) -> JOVSE_W {
                JOVSE_W { w: self }
            }
            ///Bit 0 - ADC oversampler enable on scope ADC group regular
            #[inline(always)]
            pub fn rovse(&mut self) -> ROVSE_W {
                ROVSE_W { w: self }
            }
        }
    }
    ///ADC sampling time register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [smpr1](smpr1) module
    pub type SMPR1 = crate::Reg<u32, _SMPR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SMPR1;
    ///`read()` method returns [smpr1::R](smpr1::R) reader structure
    impl crate::Readable for SMPR1 {}
    ///`write(|w| ..)` method takes [smpr1::W](smpr1::W) writer structure
    impl crate::Writable for SMPR1 {}
    ///ADC sampling time register 1
    pub mod smpr1 {
        ///Reader of register SMPR1
        pub type R = crate::R<u32, super::SMPR1>;
        ///Writer for register SMPR1
        pub type W = crate::W<u32, super::SMPR1>;
        ///Register SMPR1 `reset()`'s with value 0
        impl crate::ResetValue for super::SMPR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SMP9`
        pub type SMP9_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP9`
        pub struct SMP9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 27)) | (((value as u32) & 0x07) << 27);
                self.w
            }
        }
        ///Reader of field `SMP8`
        pub type SMP8_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP8`
        pub struct SMP8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 24)) | (((value as u32) & 0x07) << 24);
                self.w
            }
        }
        ///Reader of field `SMP7`
        pub type SMP7_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP7`
        pub struct SMP7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 21)) | (((value as u32) & 0x07) << 21);
                self.w
            }
        }
        ///Reader of field `SMP6`
        pub type SMP6_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP6`
        pub struct SMP6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 18)) | (((value as u32) & 0x07) << 18);
                self.w
            }
        }
        ///Reader of field `SMP5`
        pub type SMP5_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP5`
        pub struct SMP5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 15)) | (((value as u32) & 0x07) << 15);
                self.w
            }
        }
        ///Reader of field `SMP4`
        pub type SMP4_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP4`
        pub struct SMP4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `SMP3`
        pub type SMP3_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP3`
        pub struct SMP3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 9)) | (((value as u32) & 0x07) << 9);
                self.w
            }
        }
        ///Reader of field `SMP2`
        pub type SMP2_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP2`
        pub struct SMP2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 6)) | (((value as u32) & 0x07) << 6);
                self.w
            }
        }
        ///Reader of field `SMP1`
        pub type SMP1_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP1`
        pub struct SMP1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 3)) | (((value as u32) & 0x07) << 3);
                self.w
            }
        }
        impl R {
            ///Bits 27:29 - ADC channel 9 sampling time selection
            #[inline(always)]
            pub fn smp9(&self) -> SMP9_R {
                SMP9_R::new(((self.bits >> 27) & 0x07) as u8)
            }
            ///Bits 24:26 - ADC channel 8 sampling time selection
            #[inline(always)]
            pub fn smp8(&self) -> SMP8_R {
                SMP8_R::new(((self.bits >> 24) & 0x07) as u8)
            }
            ///Bits 21:23 - ADC channel 7 sampling time selection
            #[inline(always)]
            pub fn smp7(&self) -> SMP7_R {
                SMP7_R::new(((self.bits >> 21) & 0x07) as u8)
            }
            ///Bits 18:20 - ADC channel 6 sampling time selection
            #[inline(always)]
            pub fn smp6(&self) -> SMP6_R {
                SMP6_R::new(((self.bits >> 18) & 0x07) as u8)
            }
            ///Bits 15:17 - ADC channel 5 sampling time selection
            #[inline(always)]
            pub fn smp5(&self) -> SMP5_R {
                SMP5_R::new(((self.bits >> 15) & 0x07) as u8)
            }
            ///Bits 12:14 - ADC channel 4 sampling time selection
            #[inline(always)]
            pub fn smp4(&self) -> SMP4_R {
                SMP4_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 9:11 - ADC channel 3 sampling time selection
            #[inline(always)]
            pub fn smp3(&self) -> SMP3_R {
                SMP3_R::new(((self.bits >> 9) & 0x07) as u8)
            }
            ///Bits 6:8 - ADC channel 2 sampling time selection
            #[inline(always)]
            pub fn smp2(&self) -> SMP2_R {
                SMP2_R::new(((self.bits >> 6) & 0x07) as u8)
            }
            ///Bits 3:5 - ADC channel 1 sampling time selection
            #[inline(always)]
            pub fn smp1(&self) -> SMP1_R {
                SMP1_R::new(((self.bits >> 3) & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 27:29 - ADC channel 9 sampling time selection
            #[inline(always)]
            pub fn smp9(&mut self) -> SMP9_W {
                SMP9_W { w: self }
            }
            ///Bits 24:26 - ADC channel 8 sampling time selection
            #[inline(always)]
            pub fn smp8(&mut self) -> SMP8_W {
                SMP8_W { w: self }
            }
            ///Bits 21:23 - ADC channel 7 sampling time selection
            #[inline(always)]
            pub fn smp7(&mut self) -> SMP7_W {
                SMP7_W { w: self }
            }
            ///Bits 18:20 - ADC channel 6 sampling time selection
            #[inline(always)]
            pub fn smp6(&mut self) -> SMP6_W {
                SMP6_W { w: self }
            }
            ///Bits 15:17 - ADC channel 5 sampling time selection
            #[inline(always)]
            pub fn smp5(&mut self) -> SMP5_W {
                SMP5_W { w: self }
            }
            ///Bits 12:14 - ADC channel 4 sampling time selection
            #[inline(always)]
            pub fn smp4(&mut self) -> SMP4_W {
                SMP4_W { w: self }
            }
            ///Bits 9:11 - ADC channel 3 sampling time selection
            #[inline(always)]
            pub fn smp3(&mut self) -> SMP3_W {
                SMP3_W { w: self }
            }
            ///Bits 6:8 - ADC channel 2 sampling time selection
            #[inline(always)]
            pub fn smp2(&mut self) -> SMP2_W {
                SMP2_W { w: self }
            }
            ///Bits 3:5 - ADC channel 1 sampling time selection
            #[inline(always)]
            pub fn smp1(&mut self) -> SMP1_W {
                SMP1_W { w: self }
            }
        }
    }
    ///ADC sampling time register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [smpr2](smpr2) module
    pub type SMPR2 = crate::Reg<u32, _SMPR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SMPR2;
    ///`read()` method returns [smpr2::R](smpr2::R) reader structure
    impl crate::Readable for SMPR2 {}
    ///`write(|w| ..)` method takes [smpr2::W](smpr2::W) writer structure
    impl crate::Writable for SMPR2 {}
    ///ADC sampling time register 2
    pub mod smpr2 {
        ///Reader of register SMPR2
        pub type R = crate::R<u32, super::SMPR2>;
        ///Writer for register SMPR2
        pub type W = crate::W<u32, super::SMPR2>;
        ///Register SMPR2 `reset()`'s with value 0
        impl crate::ResetValue for super::SMPR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SMP18`
        pub type SMP18_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP18`
        pub struct SMP18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP18_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 24)) | (((value as u32) & 0x07) << 24);
                self.w
            }
        }
        ///Reader of field `SMP17`
        pub type SMP17_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP17`
        pub struct SMP17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP17_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 21)) | (((value as u32) & 0x07) << 21);
                self.w
            }
        }
        ///Reader of field `SMP16`
        pub type SMP16_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP16`
        pub struct SMP16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP16_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 18)) | (((value as u32) & 0x07) << 18);
                self.w
            }
        }
        ///Reader of field `SMP15`
        pub type SMP15_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP15`
        pub struct SMP15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 15)) | (((value as u32) & 0x07) << 15);
                self.w
            }
        }
        ///Reader of field `SMP14`
        pub type SMP14_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP14`
        pub struct SMP14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `SMP13`
        pub type SMP13_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP13`
        pub struct SMP13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 9)) | (((value as u32) & 0x07) << 9);
                self.w
            }
        }
        ///Reader of field `SMP12`
        pub type SMP12_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP12`
        pub struct SMP12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 6)) | (((value as u32) & 0x07) << 6);
                self.w
            }
        }
        ///Reader of field `SMP11`
        pub type SMP11_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP11`
        pub struct SMP11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 3)) | (((value as u32) & 0x07) << 3);
                self.w
            }
        }
        ///Reader of field `SMP10`
        pub type SMP10_R = crate::R<u8, u8>;
        ///Write proxy for field `SMP10`
        pub struct SMP10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMP10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 24:26 - ADC channel 18 sampling time selection
            #[inline(always)]
            pub fn smp18(&self) -> SMP18_R {
                SMP18_R::new(((self.bits >> 24) & 0x07) as u8)
            }
            ///Bits 21:23 - ADC channel 17 sampling time selection
            #[inline(always)]
            pub fn smp17(&self) -> SMP17_R {
                SMP17_R::new(((self.bits >> 21) & 0x07) as u8)
            }
            ///Bits 18:20 - ADC channel 16 sampling time selection
            #[inline(always)]
            pub fn smp16(&self) -> SMP16_R {
                SMP16_R::new(((self.bits >> 18) & 0x07) as u8)
            }
            ///Bits 15:17 - ADC channel 15 sampling time selection
            #[inline(always)]
            pub fn smp15(&self) -> SMP15_R {
                SMP15_R::new(((self.bits >> 15) & 0x07) as u8)
            }
            ///Bits 12:14 - ADC channel 14 sampling time selection
            #[inline(always)]
            pub fn smp14(&self) -> SMP14_R {
                SMP14_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 9:11 - ADC channel 13 sampling time selection
            #[inline(always)]
            pub fn smp13(&self) -> SMP13_R {
                SMP13_R::new(((self.bits >> 9) & 0x07) as u8)
            }
            ///Bits 6:8 - ADC channel 12 sampling time selection
            #[inline(always)]
            pub fn smp12(&self) -> SMP12_R {
                SMP12_R::new(((self.bits >> 6) & 0x07) as u8)
            }
            ///Bits 3:5 - ADC channel 11 sampling time selection
            #[inline(always)]
            pub fn smp11(&self) -> SMP11_R {
                SMP11_R::new(((self.bits >> 3) & 0x07) as u8)
            }
            ///Bits 0:2 - ADC channel 10 sampling time selection
            #[inline(always)]
            pub fn smp10(&self) -> SMP10_R {
                SMP10_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 24:26 - ADC channel 18 sampling time selection
            #[inline(always)]
            pub fn smp18(&mut self) -> SMP18_W {
                SMP18_W { w: self }
            }
            ///Bits 21:23 - ADC channel 17 sampling time selection
            #[inline(always)]
            pub fn smp17(&mut self) -> SMP17_W {
                SMP17_W { w: self }
            }
            ///Bits 18:20 - ADC channel 16 sampling time selection
            #[inline(always)]
            pub fn smp16(&mut self) -> SMP16_W {
                SMP16_W { w: self }
            }
            ///Bits 15:17 - ADC channel 15 sampling time selection
            #[inline(always)]
            pub fn smp15(&mut self) -> SMP15_W {
                SMP15_W { w: self }
            }
            ///Bits 12:14 - ADC channel 14 sampling time selection
            #[inline(always)]
            pub fn smp14(&mut self) -> SMP14_W {
                SMP14_W { w: self }
            }
            ///Bits 9:11 - ADC channel 13 sampling time selection
            #[inline(always)]
            pub fn smp13(&mut self) -> SMP13_W {
                SMP13_W { w: self }
            }
            ///Bits 6:8 - ADC channel 12 sampling time selection
            #[inline(always)]
            pub fn smp12(&mut self) -> SMP12_W {
                SMP12_W { w: self }
            }
            ///Bits 3:5 - ADC channel 11 sampling time selection
            #[inline(always)]
            pub fn smp11(&mut self) -> SMP11_W {
                SMP11_W { w: self }
            }
            ///Bits 0:2 - ADC channel 10 sampling time selection
            #[inline(always)]
            pub fn smp10(&mut self) -> SMP10_W {
                SMP10_W { w: self }
            }
        }
    }
    ///ADC analog watchdog 1 threshold register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tr1](tr1) module
    pub type TR1 = crate::Reg<u32, _TR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TR1;
    ///`read()` method returns [tr1::R](tr1::R) reader structure
    impl crate::Readable for TR1 {}
    ///`write(|w| ..)` method takes [tr1::W](tr1::W) writer structure
    impl crate::Writable for TR1 {}
    ///ADC analog watchdog 1 threshold register
    pub mod tr1 {
        ///Reader of register TR1
        pub type R = crate::R<u32, super::TR1>;
        ///Writer for register TR1
        pub type W = crate::W<u32, super::TR1>;
        ///Register TR1 `reset()`'s with value 0x0fff_0000
        impl crate::ResetValue for super::TR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0fff_0000
            }
        }
        ///Reader of field `HT1`
        pub type HT1_R = crate::R<u16, u16>;
        ///Write proxy for field `HT1`
        pub struct HT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HT1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0fff << 16)) | (((value as u32) & 0x0fff) << 16);
                self.w
            }
        }
        ///Reader of field `LT1`
        pub type LT1_R = crate::R<u16, u16>;
        ///Write proxy for field `LT1`
        pub struct LT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LT1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        impl R {
            ///Bits 16:27 - ADC analog watchdog 1 threshold high
            #[inline(always)]
            pub fn ht1(&self) -> HT1_R {
                HT1_R::new(((self.bits >> 16) & 0x0fff) as u16)
            }
            ///Bits 0:11 - ADC analog watchdog 1 threshold low
            #[inline(always)]
            pub fn lt1(&self) -> LT1_R {
                LT1_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            ///Bits 16:27 - ADC analog watchdog 1 threshold high
            #[inline(always)]
            pub fn ht1(&mut self) -> HT1_W {
                HT1_W { w: self }
            }
            ///Bits 0:11 - ADC analog watchdog 1 threshold low
            #[inline(always)]
            pub fn lt1(&mut self) -> LT1_W {
                LT1_W { w: self }
            }
        }
    }
    ///ADC analog watchdog 2 threshold register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tr2](tr2) module
    pub type TR2 = crate::Reg<u32, _TR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TR2;
    ///`read()` method returns [tr2::R](tr2::R) reader structure
    impl crate::Readable for TR2 {}
    ///`write(|w| ..)` method takes [tr2::W](tr2::W) writer structure
    impl crate::Writable for TR2 {}
    ///ADC analog watchdog 2 threshold register
    pub mod tr2 {
        ///Reader of register TR2
        pub type R = crate::R<u32, super::TR2>;
        ///Writer for register TR2
        pub type W = crate::W<u32, super::TR2>;
        ///Register TR2 `reset()`'s with value 0x0fff_0000
        impl crate::ResetValue for super::TR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0fff_0000
            }
        }
        ///Reader of field `HT2`
        pub type HT2_R = crate::R<u8, u8>;
        ///Write proxy for field `HT2`
        pub struct HT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HT2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
                self.w
            }
        }
        ///Reader of field `LT2`
        pub type LT2_R = crate::R<u8, u8>;
        ///Write proxy for field `LT2`
        pub struct LT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LT2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 16:23 - ADC analog watchdog 2 threshold high
            #[inline(always)]
            pub fn ht2(&self) -> HT2_R {
                HT2_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            ///Bits 0:7 - ADC analog watchdog 2 threshold low
            #[inline(always)]
            pub fn lt2(&self) -> LT2_R {
                LT2_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 16:23 - ADC analog watchdog 2 threshold high
            #[inline(always)]
            pub fn ht2(&mut self) -> HT2_W {
                HT2_W { w: self }
            }
            ///Bits 0:7 - ADC analog watchdog 2 threshold low
            #[inline(always)]
            pub fn lt2(&mut self) -> LT2_W {
                LT2_W { w: self }
            }
        }
    }
    ///ADC analog watchdog 3 threshold register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tr3](tr3) module
    pub type TR3 = crate::Reg<u32, _TR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TR3;
    ///`read()` method returns [tr3::R](tr3::R) reader structure
    impl crate::Readable for TR3 {}
    ///`write(|w| ..)` method takes [tr3::W](tr3::W) writer structure
    impl crate::Writable for TR3 {}
    ///ADC analog watchdog 3 threshold register
    pub mod tr3 {
        ///Reader of register TR3
        pub type R = crate::R<u32, super::TR3>;
        ///Writer for register TR3
        pub type W = crate::W<u32, super::TR3>;
        ///Register TR3 `reset()`'s with value 0x0fff_0000
        impl crate::ResetValue for super::TR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0fff_0000
            }
        }
        ///Reader of field `HT3`
        pub type HT3_R = crate::R<u8, u8>;
        ///Write proxy for field `HT3`
        pub struct HT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HT3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
                self.w
            }
        }
        ///Reader of field `LT3`
        pub type LT3_R = crate::R<u8, u8>;
        ///Write proxy for field `LT3`
        pub struct LT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LT3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 16:23 - ADC analog watchdog 3 threshold high
            #[inline(always)]
            pub fn ht3(&self) -> HT3_R {
                HT3_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            ///Bits 0:7 - ADC analog watchdog 3 threshold low
            #[inline(always)]
            pub fn lt3(&self) -> LT3_R {
                LT3_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 16:23 - ADC analog watchdog 3 threshold high
            #[inline(always)]
            pub fn ht3(&mut self) -> HT3_W {
                HT3_W { w: self }
            }
            ///Bits 0:7 - ADC analog watchdog 3 threshold low
            #[inline(always)]
            pub fn lt3(&mut self) -> LT3_W {
                LT3_W { w: self }
            }
        }
    }
    ///ADC group regular sequencer ranks register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sqr1](sqr1) module
    pub type SQR1 = crate::Reg<u32, _SQR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SQR1;
    ///`read()` method returns [sqr1::R](sqr1::R) reader structure
    impl crate::Readable for SQR1 {}
    ///`write(|w| ..)` method takes [sqr1::W](sqr1::W) writer structure
    impl crate::Writable for SQR1 {}
    ///ADC group regular sequencer ranks register 1
    pub mod sqr1 {
        ///Reader of register SQR1
        pub type R = crate::R<u32, super::SQR1>;
        ///Writer for register SQR1
        pub type W = crate::W<u32, super::SQR1>;
        ///Register SQR1 `reset()`'s with value 0
        impl crate::ResetValue for super::SQR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SQ4`
        pub type SQ4_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ4`
        pub struct SQ4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `SQ3`
        pub type SQ3_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ3`
        pub struct SQ3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 18)) | (((value as u32) & 0x1f) << 18);
                self.w
            }
        }
        ///Reader of field `SQ2`
        pub type SQ2_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ2`
        pub struct SQ2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 12)) | (((value as u32) & 0x1f) << 12);
                self.w
            }
        }
        ///Reader of field `SQ1`
        pub type SQ1_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ1`
        pub struct SQ1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 6)) | (((value as u32) & 0x1f) << 6);
                self.w
            }
        }
        ///Reader of field `L`
        pub type L_R = crate::R<u8, u8>;
        ///Write proxy for field `L`
        pub struct L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - ADC group regular sequencer rank 4
            #[inline(always)]
            pub fn sq4(&self) -> SQ4_R {
                SQ4_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 18:22 - ADC group regular sequencer rank 3
            #[inline(always)]
            pub fn sq3(&self) -> SQ3_R {
                SQ3_R::new(((self.bits >> 18) & 0x1f) as u8)
            }
            ///Bits 12:16 - ADC group regular sequencer rank 2
            #[inline(always)]
            pub fn sq2(&self) -> SQ2_R {
                SQ2_R::new(((self.bits >> 12) & 0x1f) as u8)
            }
            ///Bits 6:10 - ADC group regular sequencer rank 1
            #[inline(always)]
            pub fn sq1(&self) -> SQ1_R {
                SQ1_R::new(((self.bits >> 6) & 0x1f) as u8)
            }
            ///Bits 0:3 - Regular channel sequence length
            #[inline(always)]
            pub fn l(&self) -> L_R {
                L_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - ADC group regular sequencer rank 4
            #[inline(always)]
            pub fn sq4(&mut self) -> SQ4_W {
                SQ4_W { w: self }
            }
            ///Bits 18:22 - ADC group regular sequencer rank 3
            #[inline(always)]
            pub fn sq3(&mut self) -> SQ3_W {
                SQ3_W { w: self }
            }
            ///Bits 12:16 - ADC group regular sequencer rank 2
            #[inline(always)]
            pub fn sq2(&mut self) -> SQ2_W {
                SQ2_W { w: self }
            }
            ///Bits 6:10 - ADC group regular sequencer rank 1
            #[inline(always)]
            pub fn sq1(&mut self) -> SQ1_W {
                SQ1_W { w: self }
            }
            ///Bits 0:3 - Regular channel sequence length
            #[inline(always)]
            pub fn l(&mut self) -> L_W {
                L_W { w: self }
            }
        }
    }
    ///ADC group regular sequencer ranks register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sqr2](sqr2) module
    pub type SQR2 = crate::Reg<u32, _SQR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SQR2;
    ///`read()` method returns [sqr2::R](sqr2::R) reader structure
    impl crate::Readable for SQR2 {}
    ///`write(|w| ..)` method takes [sqr2::W](sqr2::W) writer structure
    impl crate::Writable for SQR2 {}
    ///ADC group regular sequencer ranks register 2
    pub mod sqr2 {
        ///Reader of register SQR2
        pub type R = crate::R<u32, super::SQR2>;
        ///Writer for register SQR2
        pub type W = crate::W<u32, super::SQR2>;
        ///Register SQR2 `reset()`'s with value 0
        impl crate::ResetValue for super::SQR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SQ9`
        pub type SQ9_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ9`
        pub struct SQ9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `SQ8`
        pub type SQ8_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ8`
        pub struct SQ8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 18)) | (((value as u32) & 0x1f) << 18);
                self.w
            }
        }
        ///Reader of field `SQ7`
        pub type SQ7_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ7`
        pub struct SQ7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 12)) | (((value as u32) & 0x1f) << 12);
                self.w
            }
        }
        ///Reader of field `SQ6`
        pub type SQ6_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ6`
        pub struct SQ6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 6)) | (((value as u32) & 0x1f) << 6);
                self.w
            }
        }
        ///Reader of field `SQ5`
        pub type SQ5_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ5`
        pub struct SQ5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - ADC group regular sequencer rank 9
            #[inline(always)]
            pub fn sq9(&self) -> SQ9_R {
                SQ9_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 18:22 - ADC group regular sequencer rank 8
            #[inline(always)]
            pub fn sq8(&self) -> SQ8_R {
                SQ8_R::new(((self.bits >> 18) & 0x1f) as u8)
            }
            ///Bits 12:16 - ADC group regular sequencer rank 7
            #[inline(always)]
            pub fn sq7(&self) -> SQ7_R {
                SQ7_R::new(((self.bits >> 12) & 0x1f) as u8)
            }
            ///Bits 6:10 - ADC group regular sequencer rank 6
            #[inline(always)]
            pub fn sq6(&self) -> SQ6_R {
                SQ6_R::new(((self.bits >> 6) & 0x1f) as u8)
            }
            ///Bits 0:4 - ADC group regular sequencer rank 5
            #[inline(always)]
            pub fn sq5(&self) -> SQ5_R {
                SQ5_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - ADC group regular sequencer rank 9
            #[inline(always)]
            pub fn sq9(&mut self) -> SQ9_W {
                SQ9_W { w: self }
            }
            ///Bits 18:22 - ADC group regular sequencer rank 8
            #[inline(always)]
            pub fn sq8(&mut self) -> SQ8_W {
                SQ8_W { w: self }
            }
            ///Bits 12:16 - ADC group regular sequencer rank 7
            #[inline(always)]
            pub fn sq7(&mut self) -> SQ7_W {
                SQ7_W { w: self }
            }
            ///Bits 6:10 - ADC group regular sequencer rank 6
            #[inline(always)]
            pub fn sq6(&mut self) -> SQ6_W {
                SQ6_W { w: self }
            }
            ///Bits 0:4 - ADC group regular sequencer rank 5
            #[inline(always)]
            pub fn sq5(&mut self) -> SQ5_W {
                SQ5_W { w: self }
            }
        }
    }
    ///ADC group regular sequencer ranks register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sqr3](sqr3) module
    pub type SQR3 = crate::Reg<u32, _SQR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SQR3;
    ///`read()` method returns [sqr3::R](sqr3::R) reader structure
    impl crate::Readable for SQR3 {}
    ///`write(|w| ..)` method takes [sqr3::W](sqr3::W) writer structure
    impl crate::Writable for SQR3 {}
    ///ADC group regular sequencer ranks register 3
    pub mod sqr3 {
        ///Reader of register SQR3
        pub type R = crate::R<u32, super::SQR3>;
        ///Writer for register SQR3
        pub type W = crate::W<u32, super::SQR3>;
        ///Register SQR3 `reset()`'s with value 0
        impl crate::ResetValue for super::SQR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SQ14`
        pub type SQ14_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ14`
        pub struct SQ14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
                self.w
            }
        }
        ///Reader of field `SQ13`
        pub type SQ13_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ13`
        pub struct SQ13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 18)) | (((value as u32) & 0x1f) << 18);
                self.w
            }
        }
        ///Reader of field `SQ12`
        pub type SQ12_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ12`
        pub struct SQ12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 12)) | (((value as u32) & 0x1f) << 12);
                self.w
            }
        }
        ///Reader of field `SQ11`
        pub type SQ11_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ11`
        pub struct SQ11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 6)) | (((value as u32) & 0x1f) << 6);
                self.w
            }
        }
        ///Reader of field `SQ10`
        pub type SQ10_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ10`
        pub struct SQ10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 24:28 - ADC group regular sequencer rank 14
            #[inline(always)]
            pub fn sq14(&self) -> SQ14_R {
                SQ14_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            ///Bits 18:22 - ADC group regular sequencer rank 13
            #[inline(always)]
            pub fn sq13(&self) -> SQ13_R {
                SQ13_R::new(((self.bits >> 18) & 0x1f) as u8)
            }
            ///Bits 12:16 - ADC group regular sequencer rank 12
            #[inline(always)]
            pub fn sq12(&self) -> SQ12_R {
                SQ12_R::new(((self.bits >> 12) & 0x1f) as u8)
            }
            ///Bits 6:10 - ADC group regular sequencer rank 11
            #[inline(always)]
            pub fn sq11(&self) -> SQ11_R {
                SQ11_R::new(((self.bits >> 6) & 0x1f) as u8)
            }
            ///Bits 0:4 - ADC group regular sequencer rank 10
            #[inline(always)]
            pub fn sq10(&self) -> SQ10_R {
                SQ10_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 24:28 - ADC group regular sequencer rank 14
            #[inline(always)]
            pub fn sq14(&mut self) -> SQ14_W {
                SQ14_W { w: self }
            }
            ///Bits 18:22 - ADC group regular sequencer rank 13
            #[inline(always)]
            pub fn sq13(&mut self) -> SQ13_W {
                SQ13_W { w: self }
            }
            ///Bits 12:16 - ADC group regular sequencer rank 12
            #[inline(always)]
            pub fn sq12(&mut self) -> SQ12_W {
                SQ12_W { w: self }
            }
            ///Bits 6:10 - ADC group regular sequencer rank 11
            #[inline(always)]
            pub fn sq11(&mut self) -> SQ11_W {
                SQ11_W { w: self }
            }
            ///Bits 0:4 - ADC group regular sequencer rank 10
            #[inline(always)]
            pub fn sq10(&mut self) -> SQ10_W {
                SQ10_W { w: self }
            }
        }
    }
    ///ADC group regular sequencer ranks register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sqr4](sqr4) module
    pub type SQR4 = crate::Reg<u32, _SQR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SQR4;
    ///`read()` method returns [sqr4::R](sqr4::R) reader structure
    impl crate::Readable for SQR4 {}
    ///`write(|w| ..)` method takes [sqr4::W](sqr4::W) writer structure
    impl crate::Writable for SQR4 {}
    ///ADC group regular sequencer ranks register 4
    pub mod sqr4 {
        ///Reader of register SQR4
        pub type R = crate::R<u32, super::SQR4>;
        ///Writer for register SQR4
        pub type W = crate::W<u32, super::SQR4>;
        ///Register SQR4 `reset()`'s with value 0
        impl crate::ResetValue for super::SQR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SQ16`
        pub type SQ16_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ16`
        pub struct SQ16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ16_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 6)) | (((value as u32) & 0x1f) << 6);
                self.w
            }
        }
        ///Reader of field `SQ15`
        pub type SQ15_R = crate::R<u8, u8>;
        ///Write proxy for field `SQ15`
        pub struct SQ15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SQ15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 6:10 - ADC group regular sequencer rank 16
            #[inline(always)]
            pub fn sq16(&self) -> SQ16_R {
                SQ16_R::new(((self.bits >> 6) & 0x1f) as u8)
            }
            ///Bits 0:4 - ADC group regular sequencer rank 15
            #[inline(always)]
            pub fn sq15(&self) -> SQ15_R {
                SQ15_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 6:10 - ADC group regular sequencer rank 16
            #[inline(always)]
            pub fn sq16(&mut self) -> SQ16_W {
                SQ16_W { w: self }
            }
            ///Bits 0:4 - ADC group regular sequencer rank 15
            #[inline(always)]
            pub fn sq15(&mut self) -> SQ15_W {
                SQ15_W { w: self }
            }
        }
    }
    ///ADC group regular conversion data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dr](dr) module
    pub type DR = crate::Reg<u32, _DR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DR;
    ///`read()` method returns [dr::R](dr::R) reader structure
    impl crate::Readable for DR {}
    ///`write(|w| ..)` method takes [dr::W](dr::W) writer structure
    impl crate::Writable for DR {}
    ///ADC group regular conversion data register
    pub mod dr {
        ///Reader of register DR
        pub type R = crate::R<u32, super::DR>;
        ///Writer for register DR
        pub type W = crate::W<u32, super::DR>;
        ///Register DR `reset()`'s with value 0
        impl crate::ResetValue for super::DR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RDATA_0_6`
        pub type RDATA_0_6_R = crate::R<u8, u8>;
        ///Write proxy for field `RDATA_0_6`
        pub struct RDATA_0_6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RDATA_0_6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f);
                self.w
            }
        }
        ///Reader of field `RDATA_7_15`
        pub type RDATA_7_15_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:5 - Regular Data converted 0_6
            #[inline(always)]
            pub fn rdata_0_6(&self) -> RDATA_0_6_R {
                RDATA_0_6_R::new((self.bits & 0x3f) as u8)
            }
            ///Bits 7:15 - 15
            #[inline(always)]
            pub fn rdata_7_15(&self) -> RDATA_7_15_R {
                RDATA_7_15_R::new(((self.bits >> 7) & 0x01ff) as u16)
            }
        }
        impl W {
            ///Bits 0:5 - Regular Data converted 0_6
            #[inline(always)]
            pub fn rdata_0_6(&mut self) -> RDATA_0_6_W {
                RDATA_0_6_W { w: self }
            }
        }
    }
    ///ADC group injected sequencer register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [jsqr](jsqr) module
    pub type JSQR = crate::Reg<u32, _JSQR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _JSQR;
    ///`read()` method returns [jsqr::R](jsqr::R) reader structure
    impl crate::Readable for JSQR {}
    ///`write(|w| ..)` method takes [jsqr::W](jsqr::W) writer structure
    impl crate::Writable for JSQR {}
    ///ADC group injected sequencer register
    pub mod jsqr {
        ///Reader of register JSQR
        pub type R = crate::R<u32, super::JSQR>;
        ///Writer for register JSQR
        pub type W = crate::W<u32, super::JSQR>;
        ///Register JSQR `reset()`'s with value 0
        impl crate::ResetValue for super::JSQR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `JSQ4`
        pub type JSQ4_R = crate::R<u8, u8>;
        ///Write proxy for field `JSQ4`
        pub struct JSQ4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JSQ4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 26)) | (((value as u32) & 0x1f) << 26);
                self.w
            }
        }
        ///Reader of field `JSQ3`
        pub type JSQ3_R = crate::R<u8, u8>;
        ///Write proxy for field `JSQ3`
        pub struct JSQ3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JSQ3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 20)) | (((value as u32) & 0x1f) << 20);
                self.w
            }
        }
        ///Reader of field `JSQ2`
        pub type JSQ2_R = crate::R<u8, u8>;
        ///Write proxy for field `JSQ2`
        pub struct JSQ2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JSQ2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 14)) | (((value as u32) & 0x1f) << 14);
                self.w
            }
        }
        ///Reader of field `JSQ1`
        pub type JSQ1_R = crate::R<u8, u8>;
        ///Write proxy for field `JSQ1`
        pub struct JSQ1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JSQ1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8);
                self.w
            }
        }
        ///Reader of field `JEXTEN`
        pub type JEXTEN_R = crate::R<u8, u8>;
        ///Write proxy for field `JEXTEN`
        pub struct JEXTEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JEXTEN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `JEXTSEL`
        pub type JEXTSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `JEXTSEL`
        pub struct JEXTSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JEXTSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 2)) | (((value as u32) & 0x0f) << 2);
                self.w
            }
        }
        ///Reader of field `JL`
        pub type JL_R = crate::R<u8, u8>;
        ///Write proxy for field `JL`
        pub struct JL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> JL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 26:30 - ADC group injected sequencer rank 4
            #[inline(always)]
            pub fn jsq4(&self) -> JSQ4_R {
                JSQ4_R::new(((self.bits >> 26) & 0x1f) as u8)
            }
            ///Bits 20:24 - ADC group injected sequencer rank 3
            #[inline(always)]
            pub fn jsq3(&self) -> JSQ3_R {
                JSQ3_R::new(((self.bits >> 20) & 0x1f) as u8)
            }
            ///Bits 14:18 - ADC group injected sequencer rank 2
            #[inline(always)]
            pub fn jsq2(&self) -> JSQ2_R {
                JSQ2_R::new(((self.bits >> 14) & 0x1f) as u8)
            }
            ///Bits 8:12 - ADC group injected sequencer rank 1
            #[inline(always)]
            pub fn jsq1(&self) -> JSQ1_R {
                JSQ1_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            ///Bits 6:7 - ADC group injected external trigger polarity
            #[inline(always)]
            pub fn jexten(&self) -> JEXTEN_R {
                JEXTEN_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 2:5 - ADC group injected external trigger source
            #[inline(always)]
            pub fn jextsel(&self) -> JEXTSEL_R {
                JEXTSEL_R::new(((self.bits >> 2) & 0x0f) as u8)
            }
            ///Bits 0:1 - ADC group injected sequencer scan length
            #[inline(always)]
            pub fn jl(&self) -> JL_R {
                JL_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 26:30 - ADC group injected sequencer rank 4
            #[inline(always)]
            pub fn jsq4(&mut self) -> JSQ4_W {
                JSQ4_W { w: self }
            }
            ///Bits 20:24 - ADC group injected sequencer rank 3
            #[inline(always)]
            pub fn jsq3(&mut self) -> JSQ3_W {
                JSQ3_W { w: self }
            }
            ///Bits 14:18 - ADC group injected sequencer rank 2
            #[inline(always)]
            pub fn jsq2(&mut self) -> JSQ2_W {
                JSQ2_W { w: self }
            }
            ///Bits 8:12 - ADC group injected sequencer rank 1
            #[inline(always)]
            pub fn jsq1(&mut self) -> JSQ1_W {
                JSQ1_W { w: self }
            }
            ///Bits 6:7 - ADC group injected external trigger polarity
            #[inline(always)]
            pub fn jexten(&mut self) -> JEXTEN_W {
                JEXTEN_W { w: self }
            }
            ///Bits 2:5 - ADC group injected external trigger source
            #[inline(always)]
            pub fn jextsel(&mut self) -> JEXTSEL_W {
                JEXTSEL_W { w: self }
            }
            ///Bits 0:1 - ADC group injected sequencer scan length
            #[inline(always)]
            pub fn jl(&mut self) -> JL_W {
                JL_W { w: self }
            }
        }
    }
    ///ADC offset number 1 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ofr1](ofr1) module
    pub type OFR1 = crate::Reg<u32, _OFR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OFR1;
    ///`read()` method returns [ofr1::R](ofr1::R) reader structure
    impl crate::Readable for OFR1 {}
    ///`write(|w| ..)` method takes [ofr1::W](ofr1::W) writer structure
    impl crate::Writable for OFR1 {}
    ///ADC offset number 1 register
    pub mod ofr1 {
        ///Reader of register OFR1
        pub type R = crate::R<u32, super::OFR1>;
        ///Writer for register OFR1
        pub type W = crate::W<u32, super::OFR1>;
        ///Register OFR1 `reset()`'s with value 0
        impl crate::ResetValue for super::OFR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OFFSET1_EN`
        pub type OFFSET1_EN_R = crate::R<bool, bool>;
        ///Write proxy for field `OFFSET1_EN`
        pub struct OFFSET1_EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET1_EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `OFFSET1_CH`
        pub type OFFSET1_CH_R = crate::R<u8, u8>;
        ///Write proxy for field `OFFSET1_CH`
        pub struct OFFSET1_CH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET1_CH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 26)) | (((value as u32) & 0x1f) << 26);
                self.w
            }
        }
        ///Reader of field `OFFSET1`
        pub type OFFSET1_R = crate::R<u16, u16>;
        ///Write proxy for field `OFFSET1`
        pub struct OFFSET1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - ADC offset number 1 enable
            #[inline(always)]
            pub fn offset1_en(&self) -> OFFSET1_EN_R {
                OFFSET1_EN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 26:30 - ADC offset number 1 channel selection
            #[inline(always)]
            pub fn offset1_ch(&self) -> OFFSET1_CH_R {
                OFFSET1_CH_R::new(((self.bits >> 26) & 0x1f) as u8)
            }
            ///Bits 0:11 - ADC offset number 1 offset level
            #[inline(always)]
            pub fn offset1(&self) -> OFFSET1_R {
                OFFSET1_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            ///Bit 31 - ADC offset number 1 enable
            #[inline(always)]
            pub fn offset1_en(&mut self) -> OFFSET1_EN_W {
                OFFSET1_EN_W { w: self }
            }
            ///Bits 26:30 - ADC offset number 1 channel selection
            #[inline(always)]
            pub fn offset1_ch(&mut self) -> OFFSET1_CH_W {
                OFFSET1_CH_W { w: self }
            }
            ///Bits 0:11 - ADC offset number 1 offset level
            #[inline(always)]
            pub fn offset1(&mut self) -> OFFSET1_W {
                OFFSET1_W { w: self }
            }
        }
    }
    ///ADC offset number 2 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ofr2](ofr2) module
    pub type OFR2 = crate::Reg<u32, _OFR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OFR2;
    ///`read()` method returns [ofr2::R](ofr2::R) reader structure
    impl crate::Readable for OFR2 {}
    ///`write(|w| ..)` method takes [ofr2::W](ofr2::W) writer structure
    impl crate::Writable for OFR2 {}
    ///ADC offset number 2 register
    pub mod ofr2 {
        ///Reader of register OFR2
        pub type R = crate::R<u32, super::OFR2>;
        ///Writer for register OFR2
        pub type W = crate::W<u32, super::OFR2>;
        ///Register OFR2 `reset()`'s with value 0
        impl crate::ResetValue for super::OFR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OFFSET2_EN`
        pub type OFFSET2_EN_R = crate::R<bool, bool>;
        ///Write proxy for field `OFFSET2_EN`
        pub struct OFFSET2_EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET2_EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `OFFSET2_CH`
        pub type OFFSET2_CH_R = crate::R<u8, u8>;
        ///Write proxy for field `OFFSET2_CH`
        pub struct OFFSET2_CH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET2_CH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 26)) | (((value as u32) & 0x1f) << 26);
                self.w
            }
        }
        ///Reader of field `OFFSET2`
        pub type OFFSET2_R = crate::R<u16, u16>;
        ///Write proxy for field `OFFSET2`
        pub struct OFFSET2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - ADC offset number 2 enable
            #[inline(always)]
            pub fn offset2_en(&self) -> OFFSET2_EN_R {
                OFFSET2_EN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 26:30 - ADC offset number 2 channel selection
            #[inline(always)]
            pub fn offset2_ch(&self) -> OFFSET2_CH_R {
                OFFSET2_CH_R::new(((self.bits >> 26) & 0x1f) as u8)
            }
            ///Bits 0:11 - ADC offset number 2 offset level
            #[inline(always)]
            pub fn offset2(&self) -> OFFSET2_R {
                OFFSET2_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            ///Bit 31 - ADC offset number 2 enable
            #[inline(always)]
            pub fn offset2_en(&mut self) -> OFFSET2_EN_W {
                OFFSET2_EN_W { w: self }
            }
            ///Bits 26:30 - ADC offset number 2 channel selection
            #[inline(always)]
            pub fn offset2_ch(&mut self) -> OFFSET2_CH_W {
                OFFSET2_CH_W { w: self }
            }
            ///Bits 0:11 - ADC offset number 2 offset level
            #[inline(always)]
            pub fn offset2(&mut self) -> OFFSET2_W {
                OFFSET2_W { w: self }
            }
        }
    }
    ///ADC offset number 3 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ofr3](ofr3) module
    pub type OFR3 = crate::Reg<u32, _OFR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OFR3;
    ///`read()` method returns [ofr3::R](ofr3::R) reader structure
    impl crate::Readable for OFR3 {}
    ///`write(|w| ..)` method takes [ofr3::W](ofr3::W) writer structure
    impl crate::Writable for OFR3 {}
    ///ADC offset number 3 register
    pub mod ofr3 {
        ///Reader of register OFR3
        pub type R = crate::R<u32, super::OFR3>;
        ///Writer for register OFR3
        pub type W = crate::W<u32, super::OFR3>;
        ///Register OFR3 `reset()`'s with value 0
        impl crate::ResetValue for super::OFR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OFFSET3_EN`
        pub type OFFSET3_EN_R = crate::R<bool, bool>;
        ///Write proxy for field `OFFSET3_EN`
        pub struct OFFSET3_EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET3_EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `OFFSET3_CH`
        pub type OFFSET3_CH_R = crate::R<u8, u8>;
        ///Write proxy for field `OFFSET3_CH`
        pub struct OFFSET3_CH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET3_CH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 26)) | (((value as u32) & 0x1f) << 26);
                self.w
            }
        }
        ///Reader of field `OFFSET3`
        pub type OFFSET3_R = crate::R<u16, u16>;
        ///Write proxy for field `OFFSET3`
        pub struct OFFSET3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - ADC offset number 3 enable
            #[inline(always)]
            pub fn offset3_en(&self) -> OFFSET3_EN_R {
                OFFSET3_EN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 26:30 - ADC offset number 3 channel selection
            #[inline(always)]
            pub fn offset3_ch(&self) -> OFFSET3_CH_R {
                OFFSET3_CH_R::new(((self.bits >> 26) & 0x1f) as u8)
            }
            ///Bits 0:11 - ADC offset number 3 offset level
            #[inline(always)]
            pub fn offset3(&self) -> OFFSET3_R {
                OFFSET3_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            ///Bit 31 - ADC offset number 3 enable
            #[inline(always)]
            pub fn offset3_en(&mut self) -> OFFSET3_EN_W {
                OFFSET3_EN_W { w: self }
            }
            ///Bits 26:30 - ADC offset number 3 channel selection
            #[inline(always)]
            pub fn offset3_ch(&mut self) -> OFFSET3_CH_W {
                OFFSET3_CH_W { w: self }
            }
            ///Bits 0:11 - ADC offset number 3 offset level
            #[inline(always)]
            pub fn offset3(&mut self) -> OFFSET3_W {
                OFFSET3_W { w: self }
            }
        }
    }
    ///ADC offset number 4 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ofr4](ofr4) module
    pub type OFR4 = crate::Reg<u32, _OFR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OFR4;
    ///`read()` method returns [ofr4::R](ofr4::R) reader structure
    impl crate::Readable for OFR4 {}
    ///`write(|w| ..)` method takes [ofr4::W](ofr4::W) writer structure
    impl crate::Writable for OFR4 {}
    ///ADC offset number 4 register
    pub mod ofr4 {
        ///Reader of register OFR4
        pub type R = crate::R<u32, super::OFR4>;
        ///Writer for register OFR4
        pub type W = crate::W<u32, super::OFR4>;
        ///Register OFR4 `reset()`'s with value 0
        impl crate::ResetValue for super::OFR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OFFSET4_EN`
        pub type OFFSET4_EN_R = crate::R<bool, bool>;
        ///Write proxy for field `OFFSET4_EN`
        pub struct OFFSET4_EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET4_EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `OFFSET4_CH`
        pub type OFFSET4_CH_R = crate::R<u8, u8>;
        ///Write proxy for field `OFFSET4_CH`
        pub struct OFFSET4_CH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET4_CH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 26)) | (((value as u32) & 0x1f) << 26);
                self.w
            }
        }
        ///Reader of field `OFFSET4`
        pub type OFFSET4_R = crate::R<u16, u16>;
        ///Write proxy for field `OFFSET4`
        pub struct OFFSET4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OFFSET4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
                self.w
            }
        }
        impl R {
            ///Bit 31 - ADC offset number 4 enable
            #[inline(always)]
            pub fn offset4_en(&self) -> OFFSET4_EN_R {
                OFFSET4_EN_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bits 26:30 - ADC offset number 4 channel selection
            #[inline(always)]
            pub fn offset4_ch(&self) -> OFFSET4_CH_R {
                OFFSET4_CH_R::new(((self.bits >> 26) & 0x1f) as u8)
            }
            ///Bits 0:11 - ADC offset number 4 offset level
            #[inline(always)]
            pub fn offset4(&self) -> OFFSET4_R {
                OFFSET4_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            ///Bit 31 - ADC offset number 4 enable
            #[inline(always)]
            pub fn offset4_en(&mut self) -> OFFSET4_EN_W {
                OFFSET4_EN_W { w: self }
            }
            ///Bits 26:30 - ADC offset number 4 channel selection
            #[inline(always)]
            pub fn offset4_ch(&mut self) -> OFFSET4_CH_W {
                OFFSET4_CH_W { w: self }
            }
            ///Bits 0:11 - ADC offset number 4 offset level
            #[inline(always)]
            pub fn offset4(&mut self) -> OFFSET4_W {
                OFFSET4_W { w: self }
            }
        }
    }
    ///ADC group injected sequencer rank 1 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [jdr1](jdr1) module
    pub type JDR1 = crate::Reg<u32, _JDR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _JDR1;
    ///`read()` method returns [jdr1::R](jdr1::R) reader structure
    impl crate::Readable for JDR1 {}
    ///ADC group injected sequencer rank 1 register
    pub mod jdr1 {
        ///Reader of register JDR1
        pub type R = crate::R<u32, super::JDR1>;
        ///Reader of field `JDATA1`
        pub type JDATA1_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - ADC group injected sequencer rank 1 conversion data
            #[inline(always)]
            pub fn jdata1(&self) -> JDATA1_R {
                JDATA1_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///ADC group injected sequencer rank 2 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [jdr2](jdr2) module
    pub type JDR2 = crate::Reg<u32, _JDR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _JDR2;
    ///`read()` method returns [jdr2::R](jdr2::R) reader structure
    impl crate::Readable for JDR2 {}
    ///ADC group injected sequencer rank 2 register
    pub mod jdr2 {
        ///Reader of register JDR2
        pub type R = crate::R<u32, super::JDR2>;
        ///Reader of field `JDATA2`
        pub type JDATA2_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - ADC group injected sequencer rank 2 conversion data
            #[inline(always)]
            pub fn jdata2(&self) -> JDATA2_R {
                JDATA2_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///ADC group injected sequencer rank 3 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [jdr3](jdr3) module
    pub type JDR3 = crate::Reg<u32, _JDR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _JDR3;
    ///`read()` method returns [jdr3::R](jdr3::R) reader structure
    impl crate::Readable for JDR3 {}
    ///ADC group injected sequencer rank 3 register
    pub mod jdr3 {
        ///Reader of register JDR3
        pub type R = crate::R<u32, super::JDR3>;
        ///Reader of field `JDATA3`
        pub type JDATA3_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - ADC group injected sequencer rank 3 conversion data
            #[inline(always)]
            pub fn jdata3(&self) -> JDATA3_R {
                JDATA3_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///ADC group injected sequencer rank 4 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [jdr4](jdr4) module
    pub type JDR4 = crate::Reg<u32, _JDR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _JDR4;
    ///`read()` method returns [jdr4::R](jdr4::R) reader structure
    impl crate::Readable for JDR4 {}
    ///ADC group injected sequencer rank 4 register
    pub mod jdr4 {
        ///Reader of register JDR4
        pub type R = crate::R<u32, super::JDR4>;
        ///Reader of field `JDATA4`
        pub type JDATA4_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - ADC group injected sequencer rank 4 conversion data
            #[inline(always)]
            pub fn jdata4(&self) -> JDATA4_R {
                JDATA4_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///ADC analog watchdog 2 configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [awd2cr](awd2cr) module
    pub type AWD2CR = crate::Reg<u32, _AWD2CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AWD2CR;
    ///`read()` method returns [awd2cr::R](awd2cr::R) reader structure
    impl crate::Readable for AWD2CR {}
    ///`write(|w| ..)` method takes [awd2cr::W](awd2cr::W) writer structure
    impl crate::Writable for AWD2CR {}
    ///ADC analog watchdog 2 configuration register
    pub mod awd2cr {
        ///Reader of register AWD2CR
        pub type R = crate::R<u32, super::AWD2CR>;
        ///Writer for register AWD2CR
        pub type W = crate::W<u32, super::AWD2CR>;
        ///Register AWD2CR `reset()`'s with value 0
        impl crate::ResetValue for super::AWD2CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AWD2CH`
        pub type AWD2CH_R = crate::R<u32, u32>;
        ///Write proxy for field `AWD2CH`
        pub struct AWD2CH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD2CH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0007_ffff) | ((value as u32) & 0x0007_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:18 - ADC analog watchdog 2 monitored channel selection
            #[inline(always)]
            pub fn awd2ch(&self) -> AWD2CH_R {
                AWD2CH_R::new((self.bits & 0x0007_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:18 - ADC analog watchdog 2 monitored channel selection
            #[inline(always)]
            pub fn awd2ch(&mut self) -> AWD2CH_W {
                AWD2CH_W { w: self }
            }
        }
    }
    ///ADC analog watchdog 3 configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [awd3cr](awd3cr) module
    pub type AWD3CR = crate::Reg<u32, _AWD3CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AWD3CR;
    ///`read()` method returns [awd3cr::R](awd3cr::R) reader structure
    impl crate::Readable for AWD3CR {}
    ///`write(|w| ..)` method takes [awd3cr::W](awd3cr::W) writer structure
    impl crate::Writable for AWD3CR {}
    ///ADC analog watchdog 3 configuration register
    pub mod awd3cr {
        ///Reader of register AWD3CR
        pub type R = crate::R<u32, super::AWD3CR>;
        ///Writer for register AWD3CR
        pub type W = crate::W<u32, super::AWD3CR>;
        ///Register AWD3CR `reset()`'s with value 0
        impl crate::ResetValue for super::AWD3CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AWD3CH`
        pub type AWD3CH_R = crate::R<u32, u32>;
        ///Write proxy for field `AWD3CH`
        pub struct AWD3CH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AWD3CH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0007_ffff) | ((value as u32) & 0x0007_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:18 - ADC analog watchdog 3 monitored channel selection
            #[inline(always)]
            pub fn awd3ch(&self) -> AWD3CH_R {
                AWD3CH_R::new((self.bits & 0x0007_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:18 - ADC analog watchdog 3 monitored channel selection
            #[inline(always)]
            pub fn awd3ch(&mut self) -> AWD3CH_W {
                AWD3CH_W { w: self }
            }
        }
    }
    ///ADC channel differential or single-ended mode selection register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [difsel](difsel) module
    pub type DIFSEL = crate::Reg<u32, _DIFSEL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DIFSEL;
    ///`read()` method returns [difsel::R](difsel::R) reader structure
    impl crate::Readable for DIFSEL {}
    ///`write(|w| ..)` method takes [difsel::W](difsel::W) writer structure
    impl crate::Writable for DIFSEL {}
    ///ADC channel differential or single-ended mode selection register
    pub mod difsel {
        ///Reader of register DIFSEL
        pub type R = crate::R<u32, super::DIFSEL>;
        ///Writer for register DIFSEL
        pub type W = crate::W<u32, super::DIFSEL>;
        ///Register DIFSEL `reset()`'s with value 0
        impl crate::ResetValue for super::DIFSEL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DIFSEL_0`
        pub type DIFSEL_0_R = crate::R<bool, bool>;
        ///Reader of field `DIFSEL_1_15`
        pub type DIFSEL_1_15_R = crate::R<u16, u16>;
        ///Write proxy for field `DIFSEL_1_15`
        pub struct DIFSEL_1_15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIFSEL_1_15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u32) & 0x7fff) << 1);
                self.w
            }
        }
        ///Reader of field `DIFSEL_16_18`
        pub type DIFSEL_16_18_R = crate::R<u8, u8>;
        impl R {
            ///Bit 0 - ADC channel differential or single-ended mode for channel 0
            #[inline(always)]
            pub fn difsel_0(&self) -> DIFSEL_0_R {
                DIFSEL_0_R::new((self.bits & 0x01) != 0)
            }
            ///Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15
            #[inline(always)]
            pub fn difsel_1_15(&self) -> DIFSEL_1_15_R {
                DIFSEL_1_15_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
            ///Bits 16:18 - ADC channel differential or single-ended mode for channels 18 to 16
            #[inline(always)]
            pub fn difsel_16_18(&self) -> DIFSEL_16_18_R {
                DIFSEL_16_18_R::new(((self.bits >> 16) & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15
            #[inline(always)]
            pub fn difsel_1_15(&mut self) -> DIFSEL_1_15_W {
                DIFSEL_1_15_W { w: self }
            }
        }
    }
    ///ADC calibration factors register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [calfact](calfact) module
    pub type CALFACT = crate::Reg<u32, _CALFACT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CALFACT;
    ///`read()` method returns [calfact::R](calfact::R) reader structure
    impl crate::Readable for CALFACT {}
    ///`write(|w| ..)` method takes [calfact::W](calfact::W) writer structure
    impl crate::Writable for CALFACT {}
    ///ADC calibration factors register
    pub mod calfact {
        ///Reader of register CALFACT
        pub type R = crate::R<u32, super::CALFACT>;
        ///Writer for register CALFACT
        pub type W = crate::W<u32, super::CALFACT>;
        ///Register CALFACT `reset()`'s with value 0
        impl crate::ResetValue for super::CALFACT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CALFACT_D`
        pub type CALFACT_D_R = crate::R<u8, u8>;
        ///Write proxy for field `CALFACT_D`
        pub struct CALFACT_D_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CALFACT_D_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7f << 16)) | (((value as u32) & 0x7f) << 16);
                self.w
            }
        }
        ///Reader of field `CALFACT_S`
        pub type CALFACT_S_R = crate::R<u8, u8>;
        ///Write proxy for field `CALFACT_S`
        pub struct CALFACT_S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CALFACT_S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
                self.w
            }
        }
        impl R {
            ///Bits 16:22 - ADC calibration factor in differential mode
            #[inline(always)]
            pub fn calfact_d(&self) -> CALFACT_D_R {
                CALFACT_D_R::new(((self.bits >> 16) & 0x7f) as u8)
            }
            ///Bits 0:6 - ADC calibration factor in single-ended mode
            #[inline(always)]
            pub fn calfact_s(&self) -> CALFACT_S_R {
                CALFACT_S_R::new((self.bits & 0x7f) as u8)
            }
        }
        impl W {
            ///Bits 16:22 - ADC calibration factor in differential mode
            #[inline(always)]
            pub fn calfact_d(&mut self) -> CALFACT_D_W {
                CALFACT_D_W { w: self }
            }
            ///Bits 0:6 - ADC calibration factor in single-ended mode
            #[inline(always)]
            pub fn calfact_s(&mut self) -> CALFACT_S_W {
                CALFACT_S_W { w: self }
            }
        }
    }
    ///ADC common control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr](ccr) module
    pub type CCR = crate::Reg<u32, _CCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR;
    ///`read()` method returns [ccr::R](ccr::R) reader structure
    impl crate::Readable for CCR {}
    ///`write(|w| ..)` method takes [ccr::W](ccr::W) writer structure
    impl crate::Writable for CCR {}
    ///ADC common control register
    pub mod ccr {
        ///Reader of register CCR
        pub type R = crate::R<u32, super::CCR>;
        ///Writer for register CCR
        pub type W = crate::W<u32, super::CCR>;
        ///Register CCR `reset()`'s with value 0
        impl crate::ResetValue for super::CCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `VBATEN`
        pub type VBATEN_R = crate::R<bool, bool>;
        ///Write proxy for field `VBATEN`
        pub struct VBATEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> VBATEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `TSEN`
        pub type TSEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TSEN`
        pub struct TSEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `VREFEN`
        pub type VREFEN_R = crate::R<bool, bool>;
        ///Write proxy for field `VREFEN`
        pub struct VREFEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> VREFEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `PRESC`
        pub type PRESC_R = crate::R<u8, u8>;
        ///Write proxy for field `PRESC`
        pub struct PRESC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRESC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u32) & 0x0f) << 18);
                self.w
            }
        }
        ///Reader of field `CKMODE`
        pub type CKMODE_R = crate::R<u8, u8>;
        ///Write proxy for field `CKMODE`
        pub struct CKMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKMODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        impl R {
            ///Bit 24 - VBAT enable
            #[inline(always)]
            pub fn vbaten(&self) -> VBATEN_R {
                VBATEN_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - Temperature sensor enable
            #[inline(always)]
            pub fn tsen(&self) -> TSEN_R {
                TSEN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - VREFEN
            #[inline(always)]
            pub fn vrefen(&self) -> VREFEN_R {
                VREFEN_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bits 18:21 - ADC prescaler
            #[inline(always)]
            pub fn presc(&self) -> PRESC_R {
                PRESC_R::new(((self.bits >> 18) & 0x0f) as u8)
            }
            ///Bits 16:17 - ADC clock mode
            #[inline(always)]
            pub fn ckmode(&self) -> CKMODE_R {
                CKMODE_R::new(((self.bits >> 16) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 24 - VBAT enable
            #[inline(always)]
            pub fn vbaten(&mut self) -> VBATEN_W {
                VBATEN_W { w: self }
            }
            ///Bit 23 - Temperature sensor enable
            #[inline(always)]
            pub fn tsen(&mut self) -> TSEN_W {
                TSEN_W { w: self }
            }
            ///Bit 22 - VREFEN
            #[inline(always)]
            pub fn vrefen(&mut self) -> VREFEN_W {
                VREFEN_W { w: self }
            }
            ///Bits 18:21 - ADC prescaler
            #[inline(always)]
            pub fn presc(&mut self) -> PRESC_W {
                PRESC_W { w: self }
            }
            ///Bits 16:17 - ADC clock mode
            #[inline(always)]
            pub fn ckmode(&mut self) -> CKMODE_W {
                CKMODE_W { w: self }
            }
        }
    }
}
///General-purpose I/Os
pub struct GPIOA {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOA {}
impl GPIOA {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const gpioa::RegisterBlock {
        0x4800_0000 as *const _
    }
}
impl Deref for GPIOA {
    type Target = gpioa::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*GPIOA::ptr() }
    }
}
///General-purpose I/Os
pub mod gpioa {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - GPIO port mode register
        pub moder: MODER,
        ///0x04 - GPIO port output type register
        pub otyper: OTYPER,
        ///0x08 - GPIO port output speed register
        pub ospeedr: OSPEEDR,
        ///0x0c - GPIO port pull-up/pull-down register
        pub pupdr: PUPDR,
        ///0x10 - GPIO port input data register
        pub idr: IDR,
        ///0x14 - GPIO port output data register
        pub odr: ODR,
        ///0x18 - GPIO port bit set/reset register
        pub bsrr: BSRR,
        ///0x1c - GPIO port configuration lock register
        pub lckr: LCKR,
        ///0x20 - GPIO alternate function low register
        pub afrl: AFRL,
        ///0x24 - GPIO alternate function high register
        pub afrh: AFRH,
        ///0x28 - port bit reset register
        pub brr: BRR,
    }
    ///GPIO port mode register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [moder](moder) module
    pub type MODER = crate::Reg<u32, _MODER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _MODER;
    ///`read()` method returns [moder::R](moder::R) reader structure
    impl crate::Readable for MODER {}
    ///`write(|w| ..)` method takes [moder::W](moder::W) writer structure
    impl crate::Writable for MODER {}
    ///GPIO port mode register
    pub mod moder {
        ///Reader of register MODER
        pub type R = crate::R<u32, super::MODER>;
        ///Writer for register MODER
        pub type W = crate::W<u32, super::MODER>;
        ///Register MODER `reset()`'s with value 0xabff_ffff
        impl crate::ResetValue for super::MODER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xabff_ffff
            }
        }
        ///Reader of field `MODER15`
        pub type MODER15_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER15`
        pub struct MODER15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `MODER14`
        pub type MODER14_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER14`
        pub struct MODER14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `MODER13`
        pub type MODER13_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER13`
        pub struct MODER13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `MODER12`
        pub type MODER12_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER12`
        pub struct MODER12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `MODER11`
        pub type MODER11_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER11`
        pub struct MODER11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `MODER10`
        pub type MODER10_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER10`
        pub struct MODER10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `MODER9`
        pub type MODER9_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER9`
        pub struct MODER9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `MODER8`
        pub type MODER8_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER8`
        pub struct MODER8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `MODER7`
        pub type MODER7_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER7`
        pub struct MODER7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `MODER6`
        pub type MODER6_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER6`
        pub struct MODER6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MODER5`
        pub type MODER5_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER5`
        pub struct MODER5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `MODER4`
        pub type MODER4_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER4`
        pub struct MODER4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MODER3`
        pub type MODER3_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER3`
        pub struct MODER3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `MODER2`
        pub type MODER2_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER2`
        pub struct MODER2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `MODER1`
        pub type MODER1_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER1`
        pub struct MODER1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `MODER0`
        pub type MODER0_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER0`
        pub struct MODER0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder15(&self) -> MODER15_R {
                MODER15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder14(&self) -> MODER14_R {
                MODER14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder13(&self) -> MODER13_R {
                MODER13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder12(&self) -> MODER12_R {
                MODER12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder11(&self) -> MODER11_R {
                MODER11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder10(&self) -> MODER10_R {
                MODER10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder9(&self) -> MODER9_R {
                MODER9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder8(&self) -> MODER8_R {
                MODER8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder7(&self) -> MODER7_R {
                MODER7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder6(&self) -> MODER6_R {
                MODER6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder5(&self) -> MODER5_R {
                MODER5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&self) -> MODER4_R {
                MODER4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&self) -> MODER3_R {
                MODER3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&self) -> MODER2_R {
                MODER2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&self) -> MODER1_R {
                MODER1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&self) -> MODER0_R {
                MODER0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder15(&mut self) -> MODER15_W {
                MODER15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder14(&mut self) -> MODER14_W {
                MODER14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder13(&mut self) -> MODER13_W {
                MODER13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder12(&mut self) -> MODER12_W {
                MODER12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder11(&mut self) -> MODER11_W {
                MODER11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder10(&mut self) -> MODER10_W {
                MODER10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder9(&mut self) -> MODER9_W {
                MODER9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder8(&mut self) -> MODER8_W {
                MODER8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder7(&mut self) -> MODER7_W {
                MODER7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder6(&mut self) -> MODER6_W {
                MODER6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder5(&mut self) -> MODER5_W {
                MODER5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&mut self) -> MODER4_W {
                MODER4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&mut self) -> MODER3_W {
                MODER3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&mut self) -> MODER2_W {
                MODER2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&mut self) -> MODER1_W {
                MODER1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&mut self) -> MODER0_W {
                MODER0_W { w: self }
            }
        }
    }
    ///GPIO port output type register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [otyper](otyper) module
    pub type OTYPER = crate::Reg<u32, _OTYPER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OTYPER;
    ///`read()` method returns [otyper::R](otyper::R) reader structure
    impl crate::Readable for OTYPER {}
    ///`write(|w| ..)` method takes [otyper::W](otyper::W) writer structure
    impl crate::Writable for OTYPER {}
    ///GPIO port output type register
    pub mod otyper {
        ///Reader of register OTYPER
        pub type R = crate::R<u32, super::OTYPER>;
        ///Writer for register OTYPER
        pub type W = crate::W<u32, super::OTYPER>;
        ///Register OTYPER `reset()`'s with value 0
        impl crate::ResetValue for super::OTYPER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OT15`
        pub type OT15_R = crate::R<bool, bool>;
        ///Write proxy for field `OT15`
        pub struct OT15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OT14`
        pub type OT14_R = crate::R<bool, bool>;
        ///Write proxy for field `OT14`
        pub struct OT14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `OT13`
        pub type OT13_R = crate::R<bool, bool>;
        ///Write proxy for field `OT13`
        pub struct OT13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `OT12`
        pub type OT12_R = crate::R<bool, bool>;
        ///Write proxy for field `OT12`
        pub struct OT12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `OT11`
        pub type OT11_R = crate::R<bool, bool>;
        ///Write proxy for field `OT11`
        pub struct OT11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OT10`
        pub type OT10_R = crate::R<bool, bool>;
        ///Write proxy for field `OT10`
        pub struct OT10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OT9`
        pub type OT9_R = crate::R<bool, bool>;
        ///Write proxy for field `OT9`
        pub struct OT9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OT8`
        pub type OT8_R = crate::R<bool, bool>;
        ///Write proxy for field `OT8`
        pub struct OT8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `OT7`
        pub type OT7_R = crate::R<bool, bool>;
        ///Write proxy for field `OT7`
        pub struct OT7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `OT6`
        pub type OT6_R = crate::R<bool, bool>;
        ///Write proxy for field `OT6`
        pub struct OT6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `OT5`
        pub type OT5_R = crate::R<bool, bool>;
        ///Write proxy for field `OT5`
        pub struct OT5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `OT4`
        pub type OT4_R = crate::R<bool, bool>;
        ///Write proxy for field `OT4`
        pub struct OT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `OT3`
        pub type OT3_R = crate::R<bool, bool>;
        ///Write proxy for field `OT3`
        pub struct OT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OT2`
        pub type OT2_R = crate::R<bool, bool>;
        ///Write proxy for field `OT2`
        pub struct OT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OT1`
        pub type OT1_R = crate::R<bool, bool>;
        ///Write proxy for field `OT1`
        pub struct OT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `OT0`
        pub type OT0_R = crate::R<bool, bool>;
        ///Write proxy for field `OT0`
        pub struct OT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot15(&self) -> OT15_R {
                OT15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot14(&self) -> OT14_R {
                OT14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot13(&self) -> OT13_R {
                OT13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot12(&self) -> OT12_R {
                OT12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot11(&self) -> OT11_R {
                OT11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot10(&self) -> OT10_R {
                OT10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot9(&self) -> OT9_R {
                OT9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot8(&self) -> OT8_R {
                OT8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot7(&self) -> OT7_R {
                OT7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot6(&self) -> OT6_R {
                OT6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot5(&self) -> OT5_R {
                OT5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&self) -> OT4_R {
                OT4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&self) -> OT3_R {
                OT3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&self) -> OT2_R {
                OT2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&self) -> OT1_R {
                OT1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&self) -> OT0_R {
                OT0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot15(&mut self) -> OT15_W {
                OT15_W { w: self }
            }
            ///Bit 14 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot14(&mut self) -> OT14_W {
                OT14_W { w: self }
            }
            ///Bit 13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot13(&mut self) -> OT13_W {
                OT13_W { w: self }
            }
            ///Bit 12 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot12(&mut self) -> OT12_W {
                OT12_W { w: self }
            }
            ///Bit 11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot11(&mut self) -> OT11_W {
                OT11_W { w: self }
            }
            ///Bit 10 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot10(&mut self) -> OT10_W {
                OT10_W { w: self }
            }
            ///Bit 9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot9(&mut self) -> OT9_W {
                OT9_W { w: self }
            }
            ///Bit 8 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot8(&mut self) -> OT8_W {
                OT8_W { w: self }
            }
            ///Bit 7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot7(&mut self) -> OT7_W {
                OT7_W { w: self }
            }
            ///Bit 6 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot6(&mut self) -> OT6_W {
                OT6_W { w: self }
            }
            ///Bit 5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot5(&mut self) -> OT5_W {
                OT5_W { w: self }
            }
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&mut self) -> OT4_W {
                OT4_W { w: self }
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&mut self) -> OT3_W {
                OT3_W { w: self }
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&mut self) -> OT2_W {
                OT2_W { w: self }
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&mut self) -> OT1_W {
                OT1_W { w: self }
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&mut self) -> OT0_W {
                OT0_W { w: self }
            }
        }
    }
    ///GPIO port output speed register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ospeedr](ospeedr) module
    pub type OSPEEDR = crate::Reg<u32, _OSPEEDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OSPEEDR;
    ///`read()` method returns [ospeedr::R](ospeedr::R) reader structure
    impl crate::Readable for OSPEEDR {}
    ///`write(|w| ..)` method takes [ospeedr::W](ospeedr::W) writer structure
    impl crate::Writable for OSPEEDR {}
    ///GPIO port output speed register
    pub mod ospeedr {
        ///Reader of register OSPEEDR
        pub type R = crate::R<u32, super::OSPEEDR>;
        ///Writer for register OSPEEDR
        pub type W = crate::W<u32, super::OSPEEDR>;
        ///Register OSPEEDR `reset()`'s with value 0x0c00_0000
        impl crate::ResetValue for super::OSPEEDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0c00_0000
            }
        }
        ///Reader of field `OSPEEDR15`
        pub type OSPEEDR15_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR15`
        pub struct OSPEEDR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `OSPEEDR14`
        pub type OSPEEDR14_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR14`
        pub struct OSPEEDR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `OSPEEDR13`
        pub type OSPEEDR13_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR13`
        pub struct OSPEEDR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `OSPEEDR12`
        pub type OSPEEDR12_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR12`
        pub struct OSPEEDR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `OSPEEDR11`
        pub type OSPEEDR11_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR11`
        pub struct OSPEEDR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `OSPEEDR10`
        pub type OSPEEDR10_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR10`
        pub struct OSPEEDR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `OSPEEDR9`
        pub type OSPEEDR9_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR9`
        pub struct OSPEEDR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `OSPEEDR8`
        pub type OSPEEDR8_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR8`
        pub struct OSPEEDR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `OSPEEDR7`
        pub type OSPEEDR7_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR7`
        pub struct OSPEEDR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `OSPEEDR6`
        pub type OSPEEDR6_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR6`
        pub struct OSPEEDR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `OSPEEDR5`
        pub type OSPEEDR5_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR5`
        pub struct OSPEEDR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `OSPEEDR4`
        pub type OSPEEDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR4`
        pub struct OSPEEDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OSPEEDR3`
        pub type OSPEEDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR3`
        pub struct OSPEEDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `OSPEEDR2`
        pub type OSPEEDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR2`
        pub struct OSPEEDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `OSPEEDR1`
        pub type OSPEEDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR1`
        pub struct OSPEEDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `OSPEEDR0`
        pub type OSPEEDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR0`
        pub struct OSPEEDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr15(&self) -> OSPEEDR15_R {
                OSPEEDR15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr14(&self) -> OSPEEDR14_R {
                OSPEEDR14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr13(&self) -> OSPEEDR13_R {
                OSPEEDR13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr12(&self) -> OSPEEDR12_R {
                OSPEEDR12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr11(&self) -> OSPEEDR11_R {
                OSPEEDR11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr10(&self) -> OSPEEDR10_R {
                OSPEEDR10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr9(&self) -> OSPEEDR9_R {
                OSPEEDR9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr8(&self) -> OSPEEDR8_R {
                OSPEEDR8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr7(&self) -> OSPEEDR7_R {
                OSPEEDR7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr6(&self) -> OSPEEDR6_R {
                OSPEEDR6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr5(&self) -> OSPEEDR5_R {
                OSPEEDR5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&self) -> OSPEEDR4_R {
                OSPEEDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&self) -> OSPEEDR3_R {
                OSPEEDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&self) -> OSPEEDR2_R {
                OSPEEDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&self) -> OSPEEDR1_R {
                OSPEEDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&self) -> OSPEEDR0_R {
                OSPEEDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr15(&mut self) -> OSPEEDR15_W {
                OSPEEDR15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr14(&mut self) -> OSPEEDR14_W {
                OSPEEDR14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr13(&mut self) -> OSPEEDR13_W {
                OSPEEDR13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr12(&mut self) -> OSPEEDR12_W {
                OSPEEDR12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr11(&mut self) -> OSPEEDR11_W {
                OSPEEDR11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr10(&mut self) -> OSPEEDR10_W {
                OSPEEDR10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr9(&mut self) -> OSPEEDR9_W {
                OSPEEDR9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr8(&mut self) -> OSPEEDR8_W {
                OSPEEDR8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr7(&mut self) -> OSPEEDR7_W {
                OSPEEDR7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr6(&mut self) -> OSPEEDR6_W {
                OSPEEDR6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr5(&mut self) -> OSPEEDR5_W {
                OSPEEDR5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&mut self) -> OSPEEDR4_W {
                OSPEEDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&mut self) -> OSPEEDR3_W {
                OSPEEDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&mut self) -> OSPEEDR2_W {
                OSPEEDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&mut self) -> OSPEEDR1_W {
                OSPEEDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&mut self) -> OSPEEDR0_W {
                OSPEEDR0_W { w: self }
            }
        }
    }
    ///GPIO port pull-up/pull-down register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pupdr](pupdr) module
    pub type PUPDR = crate::Reg<u32, _PUPDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUPDR;
    ///`read()` method returns [pupdr::R](pupdr::R) reader structure
    impl crate::Readable for PUPDR {}
    ///`write(|w| ..)` method takes [pupdr::W](pupdr::W) writer structure
    impl crate::Writable for PUPDR {}
    ///GPIO port pull-up/pull-down register
    pub mod pupdr {
        ///Reader of register PUPDR
        pub type R = crate::R<u32, super::PUPDR>;
        ///Writer for register PUPDR
        pub type W = crate::W<u32, super::PUPDR>;
        ///Register PUPDR `reset()`'s with value 0x6400_0000
        impl crate::ResetValue for super::PUPDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x6400_0000
            }
        }
        ///Reader of field `PUPDR15`
        pub type PUPDR15_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR15`
        pub struct PUPDR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `PUPDR14`
        pub type PUPDR14_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR14`
        pub struct PUPDR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `PUPDR13`
        pub type PUPDR13_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR13`
        pub struct PUPDR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `PUPDR12`
        pub type PUPDR12_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR12`
        pub struct PUPDR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `PUPDR11`
        pub type PUPDR11_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR11`
        pub struct PUPDR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `PUPDR10`
        pub type PUPDR10_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR10`
        pub struct PUPDR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `PUPDR9`
        pub type PUPDR9_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR9`
        pub struct PUPDR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `PUPDR8`
        pub type PUPDR8_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR8`
        pub struct PUPDR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `PUPDR7`
        pub type PUPDR7_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR7`
        pub struct PUPDR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `PUPDR6`
        pub type PUPDR6_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR6`
        pub struct PUPDR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `PUPDR5`
        pub type PUPDR5_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR5`
        pub struct PUPDR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PUPDR4`
        pub type PUPDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR4`
        pub struct PUPDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `PUPDR3`
        pub type PUPDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR3`
        pub struct PUPDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `PUPDR2`
        pub type PUPDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR2`
        pub struct PUPDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `PUPDR1`
        pub type PUPDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR1`
        pub struct PUPDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `PUPDR0`
        pub type PUPDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR0`
        pub struct PUPDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr15(&self) -> PUPDR15_R {
                PUPDR15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr14(&self) -> PUPDR14_R {
                PUPDR14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr13(&self) -> PUPDR13_R {
                PUPDR13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr12(&self) -> PUPDR12_R {
                PUPDR12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr11(&self) -> PUPDR11_R {
                PUPDR11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr10(&self) -> PUPDR10_R {
                PUPDR10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr9(&self) -> PUPDR9_R {
                PUPDR9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr8(&self) -> PUPDR8_R {
                PUPDR8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr7(&self) -> PUPDR7_R {
                PUPDR7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr6(&self) -> PUPDR6_R {
                PUPDR6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr5(&self) -> PUPDR5_R {
                PUPDR5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&self) -> PUPDR4_R {
                PUPDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&self) -> PUPDR3_R {
                PUPDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&self) -> PUPDR2_R {
                PUPDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&self) -> PUPDR1_R {
                PUPDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&self) -> PUPDR0_R {
                PUPDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr15(&mut self) -> PUPDR15_W {
                PUPDR15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr14(&mut self) -> PUPDR14_W {
                PUPDR14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr13(&mut self) -> PUPDR13_W {
                PUPDR13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr12(&mut self) -> PUPDR12_W {
                PUPDR12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr11(&mut self) -> PUPDR11_W {
                PUPDR11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr10(&mut self) -> PUPDR10_W {
                PUPDR10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr9(&mut self) -> PUPDR9_W {
                PUPDR9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr8(&mut self) -> PUPDR8_W {
                PUPDR8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr7(&mut self) -> PUPDR7_W {
                PUPDR7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr6(&mut self) -> PUPDR6_W {
                PUPDR6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr5(&mut self) -> PUPDR5_W {
                PUPDR5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&mut self) -> PUPDR4_W {
                PUPDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&mut self) -> PUPDR3_W {
                PUPDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&mut self) -> PUPDR2_W {
                PUPDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&mut self) -> PUPDR1_W {
                PUPDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&mut self) -> PUPDR0_W {
                PUPDR0_W { w: self }
            }
        }
    }
    ///GPIO port input data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [idr](idr) module
    pub type IDR = crate::Reg<u32, _IDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IDR;
    ///`read()` method returns [idr::R](idr::R) reader structure
    impl crate::Readable for IDR {}
    ///GPIO port input data register
    pub mod idr {
        ///Reader of register IDR
        pub type R = crate::R<u32, super::IDR>;
        ///Reader of field `IDR15`
        pub type IDR15_R = crate::R<bool, bool>;
        ///Reader of field `IDR14`
        pub type IDR14_R = crate::R<bool, bool>;
        ///Reader of field `IDR13`
        pub type IDR13_R = crate::R<bool, bool>;
        ///Reader of field `IDR12`
        pub type IDR12_R = crate::R<bool, bool>;
        ///Reader of field `IDR11`
        pub type IDR11_R = crate::R<bool, bool>;
        ///Reader of field `IDR10`
        pub type IDR10_R = crate::R<bool, bool>;
        ///Reader of field `IDR9`
        pub type IDR9_R = crate::R<bool, bool>;
        ///Reader of field `IDR8`
        pub type IDR8_R = crate::R<bool, bool>;
        ///Reader of field `IDR7`
        pub type IDR7_R = crate::R<bool, bool>;
        ///Reader of field `IDR6`
        pub type IDR6_R = crate::R<bool, bool>;
        ///Reader of field `IDR5`
        pub type IDR5_R = crate::R<bool, bool>;
        ///Reader of field `IDR4`
        pub type IDR4_R = crate::R<bool, bool>;
        ///Reader of field `IDR3`
        pub type IDR3_R = crate::R<bool, bool>;
        ///Reader of field `IDR2`
        pub type IDR2_R = crate::R<bool, bool>;
        ///Reader of field `IDR1`
        pub type IDR1_R = crate::R<bool, bool>;
        ///Reader of field `IDR0`
        pub type IDR0_R = crate::R<bool, bool>;
        impl R {
            ///Bit 15 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr15(&self) -> IDR15_R {
                IDR15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr14(&self) -> IDR14_R {
                IDR14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr13(&self) -> IDR13_R {
                IDR13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr12(&self) -> IDR12_R {
                IDR12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr11(&self) -> IDR11_R {
                IDR11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr10(&self) -> IDR10_R {
                IDR10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr9(&self) -> IDR9_R {
                IDR9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr8(&self) -> IDR8_R {
                IDR8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr7(&self) -> IDR7_R {
                IDR7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr6(&self) -> IDR6_R {
                IDR6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr5(&self) -> IDR5_R {
                IDR5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr4(&self) -> IDR4_R {
                IDR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr3(&self) -> IDR3_R {
                IDR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr2(&self) -> IDR2_R {
                IDR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr1(&self) -> IDR1_R {
                IDR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr0(&self) -> IDR0_R {
                IDR0_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///GPIO port output data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [odr](odr) module
    pub type ODR = crate::Reg<u32, _ODR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ODR;
    ///`read()` method returns [odr::R](odr::R) reader structure
    impl crate::Readable for ODR {}
    ///`write(|w| ..)` method takes [odr::W](odr::W) writer structure
    impl crate::Writable for ODR {}
    ///GPIO port output data register
    pub mod odr {
        ///Reader of register ODR
        pub type R = crate::R<u32, super::ODR>;
        ///Writer for register ODR
        pub type W = crate::W<u32, super::ODR>;
        ///Register ODR `reset()`'s with value 0
        impl crate::ResetValue for super::ODR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ODR15`
        pub type ODR15_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR15`
        pub struct ODR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `ODR14`
        pub type ODR14_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR14`
        pub struct ODR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `ODR13`
        pub type ODR13_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR13`
        pub struct ODR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `ODR12`
        pub type ODR12_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR12`
        pub struct ODR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ODR11`
        pub type ODR11_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR11`
        pub struct ODR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ODR10`
        pub type ODR10_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR10`
        pub struct ODR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `ODR9`
        pub type ODR9_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR9`
        pub struct ODR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `ODR8`
        pub type ODR8_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR8`
        pub struct ODR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `ODR7`
        pub type ODR7_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR7`
        pub struct ODR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ODR6`
        pub type ODR6_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR6`
        pub struct ODR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `ODR5`
        pub type ODR5_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR5`
        pub struct ODR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `ODR4`
        pub type ODR4_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR4`
        pub struct ODR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `ODR3`
        pub type ODR3_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR3`
        pub struct ODR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ODR2`
        pub type ODR2_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR2`
        pub struct ODR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ODR1`
        pub type ODR1_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR1`
        pub struct ODR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ODR0`
        pub type ODR0_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR0`
        pub struct ODR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr15(&self) -> ODR15_R {
                ODR15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr14(&self) -> ODR14_R {
                ODR14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr13(&self) -> ODR13_R {
                ODR13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr12(&self) -> ODR12_R {
                ODR12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr11(&self) -> ODR11_R {
                ODR11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr10(&self) -> ODR10_R {
                ODR10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr9(&self) -> ODR9_R {
                ODR9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr8(&self) -> ODR8_R {
                ODR8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr7(&self) -> ODR7_R {
                ODR7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr6(&self) -> ODR6_R {
                ODR6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr5(&self) -> ODR5_R {
                ODR5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&self) -> ODR4_R {
                ODR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&self) -> ODR3_R {
                ODR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&self) -> ODR2_R {
                ODR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&self) -> ODR1_R {
                ODR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&self) -> ODR0_R {
                ODR0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr15(&mut self) -> ODR15_W {
                ODR15_W { w: self }
            }
            ///Bit 14 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr14(&mut self) -> ODR14_W {
                ODR14_W { w: self }
            }
            ///Bit 13 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr13(&mut self) -> ODR13_W {
                ODR13_W { w: self }
            }
            ///Bit 12 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr12(&mut self) -> ODR12_W {
                ODR12_W { w: self }
            }
            ///Bit 11 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr11(&mut self) -> ODR11_W {
                ODR11_W { w: self }
            }
            ///Bit 10 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr10(&mut self) -> ODR10_W {
                ODR10_W { w: self }
            }
            ///Bit 9 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr9(&mut self) -> ODR9_W {
                ODR9_W { w: self }
            }
            ///Bit 8 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr8(&mut self) -> ODR8_W {
                ODR8_W { w: self }
            }
            ///Bit 7 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr7(&mut self) -> ODR7_W {
                ODR7_W { w: self }
            }
            ///Bit 6 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr6(&mut self) -> ODR6_W {
                ODR6_W { w: self }
            }
            ///Bit 5 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr5(&mut self) -> ODR5_W {
                ODR5_W { w: self }
            }
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&mut self) -> ODR4_W {
                ODR4_W { w: self }
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&mut self) -> ODR3_W {
                ODR3_W { w: self }
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&mut self) -> ODR2_W {
                ODR2_W { w: self }
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&mut self) -> ODR1_W {
                ODR1_W { w: self }
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&mut self) -> ODR0_W {
                ODR0_W { w: self }
            }
        }
    }
    ///GPIO port bit set/reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bsrr](bsrr) module
    pub type BSRR = crate::Reg<u32, _BSRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BSRR;
    ///`write(|w| ..)` method takes [bsrr::W](bsrr::W) writer structure
    impl crate::Writable for BSRR {}
    ///GPIO port bit set/reset register
    pub mod bsrr {
        ///Writer for register BSRR
        pub type W = crate::W<u32, super::BSRR>;
        ///Register BSRR `reset()`'s with value 0
        impl crate::ResetValue for super::BSRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR15`
        pub struct BR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Write proxy for field `BR14`
        pub struct BR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Write proxy for field `BR13`
        pub struct BR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Write proxy for field `BR12`
        pub struct BR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Write proxy for field `BR11`
        pub struct BR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Write proxy for field `BR10`
        pub struct BR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Write proxy for field `BR9`
        pub struct BR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Write proxy for field `BR8`
        pub struct BR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Write proxy for field `BR7`
        pub struct BR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Write proxy for field `BR6`
        pub struct BR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Write proxy for field `BR5`
        pub struct BR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `BS15`
        pub struct BS15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Write proxy for field `BS14`
        pub struct BS14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `BS13`
        pub struct BS13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `BS12`
        pub struct BS12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `BS11`
        pub struct BS11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `BS10`
        pub struct BS10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `BS9`
        pub struct BS9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `BS8`
        pub struct BS8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `BS7`
        pub struct BS7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `BS6`
        pub struct BS6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `BS5`
        pub struct BS5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `BS4`
        pub struct BS4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `BS3`
        pub struct BS3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BS2`
        pub struct BS2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BS1`
        pub struct BS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BS0`
        pub struct BS0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 31 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br15(&mut self) -> BR15_W {
                BR15_W { w: self }
            }
            ///Bit 30 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br14(&mut self) -> BR14_W {
                BR14_W { w: self }
            }
            ///Bit 29 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br13(&mut self) -> BR13_W {
                BR13_W { w: self }
            }
            ///Bit 28 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br12(&mut self) -> BR12_W {
                BR12_W { w: self }
            }
            ///Bit 27 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br11(&mut self) -> BR11_W {
                BR11_W { w: self }
            }
            ///Bit 26 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br10(&mut self) -> BR10_W {
                BR10_W { w: self }
            }
            ///Bit 25 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br9(&mut self) -> BR9_W {
                BR9_W { w: self }
            }
            ///Bit 24 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br8(&mut self) -> BR8_W {
                BR8_W { w: self }
            }
            ///Bit 23 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br7(&mut self) -> BR7_W {
                BR7_W { w: self }
            }
            ///Bit 22 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br6(&mut self) -> BR6_W {
                BR6_W { w: self }
            }
            ///Bit 21 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br5(&mut self) -> BR5_W {
                BR5_W { w: self }
            }
            ///Bit 20 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
            ///Bit 19 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 18 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 17 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 16 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 15 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs15(&mut self) -> BS15_W {
                BS15_W { w: self }
            }
            ///Bit 14 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs14(&mut self) -> BS14_W {
                BS14_W { w: self }
            }
            ///Bit 13 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs13(&mut self) -> BS13_W {
                BS13_W { w: self }
            }
            ///Bit 12 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs12(&mut self) -> BS12_W {
                BS12_W { w: self }
            }
            ///Bit 11 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs11(&mut self) -> BS11_W {
                BS11_W { w: self }
            }
            ///Bit 10 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs10(&mut self) -> BS10_W {
                BS10_W { w: self }
            }
            ///Bit 9 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs9(&mut self) -> BS9_W {
                BS9_W { w: self }
            }
            ///Bit 8 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs8(&mut self) -> BS8_W {
                BS8_W { w: self }
            }
            ///Bit 7 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs7(&mut self) -> BS7_W {
                BS7_W { w: self }
            }
            ///Bit 6 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs6(&mut self) -> BS6_W {
                BS6_W { w: self }
            }
            ///Bit 5 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs5(&mut self) -> BS5_W {
                BS5_W { w: self }
            }
            ///Bit 4 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs4(&mut self) -> BS4_W {
                BS4_W { w: self }
            }
            ///Bit 3 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs3(&mut self) -> BS3_W {
                BS3_W { w: self }
            }
            ///Bit 2 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs2(&mut self) -> BS2_W {
                BS2_W { w: self }
            }
            ///Bit 1 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs1(&mut self) -> BS1_W {
                BS1_W { w: self }
            }
            ///Bit 0 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs0(&mut self) -> BS0_W {
                BS0_W { w: self }
            }
        }
    }
    ///GPIO port configuration lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [lckr](lckr) module
    pub type LCKR = crate::Reg<u32, _LCKR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LCKR;
    ///`read()` method returns [lckr::R](lckr::R) reader structure
    impl crate::Readable for LCKR {}
    ///`write(|w| ..)` method takes [lckr::W](lckr::W) writer structure
    impl crate::Writable for LCKR {}
    ///GPIO port configuration lock register
    pub mod lckr {
        ///Reader of register LCKR
        pub type R = crate::R<u32, super::LCKR>;
        ///Writer for register LCKR
        pub type W = crate::W<u32, super::LCKR>;
        ///Register LCKR `reset()`'s with value 0
        impl crate::ResetValue for super::LCKR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LCKK`
        pub type LCKK_R = crate::R<bool, bool>;
        ///Write proxy for field `LCKK`
        pub struct LCKK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCKK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `LCK15`
        pub type LCK15_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK15`
        pub struct LCK15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `LCK14`
        pub type LCK14_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK14`
        pub struct LCK14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `LCK13`
        pub type LCK13_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK13`
        pub struct LCK13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `LCK12`
        pub type LCK12_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK12`
        pub struct LCK12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `LCK11`
        pub type LCK11_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK11`
        pub struct LCK11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `LCK10`
        pub type LCK10_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK10`
        pub struct LCK10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LCK9`
        pub type LCK9_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK9`
        pub struct LCK9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `LCK8`
        pub type LCK8_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK8`
        pub struct LCK8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `LCK7`
        pub type LCK7_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK7`
        pub struct LCK7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `LCK6`
        pub type LCK6_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK6`
        pub struct LCK6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `LCK5`
        pub type LCK5_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK5`
        pub struct LCK5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LCK4`
        pub type LCK4_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK4`
        pub struct LCK4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `LCK3`
        pub type LCK3_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK3`
        pub struct LCK3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `LCK2`
        pub type LCK2_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK2`
        pub struct LCK2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `LCK1`
        pub type LCK1_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK1`
        pub struct LCK1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LCK0`
        pub type LCK0_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK0`
        pub struct LCK0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&self) -> LCKK_R {
                LCKK_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck15(&self) -> LCK15_R {
                LCK15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck14(&self) -> LCK14_R {
                LCK14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck13(&self) -> LCK13_R {
                LCK13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck12(&self) -> LCK12_R {
                LCK12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck11(&self) -> LCK11_R {
                LCK11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck10(&self) -> LCK10_R {
                LCK10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck9(&self) -> LCK9_R {
                LCK9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck8(&self) -> LCK8_R {
                LCK8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck7(&self) -> LCK7_R {
                LCK7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck6(&self) -> LCK6_R {
                LCK6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck5(&self) -> LCK5_R {
                LCK5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&self) -> LCK4_R {
                LCK4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&self) -> LCK3_R {
                LCK3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&self) -> LCK2_R {
                LCK2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&self) -> LCK1_R {
                LCK1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&self) -> LCK0_R {
                LCK0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&mut self) -> LCKK_W {
                LCKK_W { w: self }
            }
            ///Bit 15 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck15(&mut self) -> LCK15_W {
                LCK15_W { w: self }
            }
            ///Bit 14 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck14(&mut self) -> LCK14_W {
                LCK14_W { w: self }
            }
            ///Bit 13 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck13(&mut self) -> LCK13_W {
                LCK13_W { w: self }
            }
            ///Bit 12 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck12(&mut self) -> LCK12_W {
                LCK12_W { w: self }
            }
            ///Bit 11 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck11(&mut self) -> LCK11_W {
                LCK11_W { w: self }
            }
            ///Bit 10 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck10(&mut self) -> LCK10_W {
                LCK10_W { w: self }
            }
            ///Bit 9 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck9(&mut self) -> LCK9_W {
                LCK9_W { w: self }
            }
            ///Bit 8 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck8(&mut self) -> LCK8_W {
                LCK8_W { w: self }
            }
            ///Bit 7 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck7(&mut self) -> LCK7_W {
                LCK7_W { w: self }
            }
            ///Bit 6 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck6(&mut self) -> LCK6_W {
                LCK6_W { w: self }
            }
            ///Bit 5 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck5(&mut self) -> LCK5_W {
                LCK5_W { w: self }
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&mut self) -> LCK4_W {
                LCK4_W { w: self }
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&mut self) -> LCK3_W {
                LCK3_W { w: self }
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&mut self) -> LCK2_W {
                LCK2_W { w: self }
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&mut self) -> LCK1_W {
                LCK1_W { w: self }
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&mut self) -> LCK0_W {
                LCK0_W { w: self }
            }
        }
    }
    ///GPIO alternate function low register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrl](afrl) module
    pub type AFRL = crate::Reg<u32, _AFRL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRL;
    ///`read()` method returns [afrl::R](afrl::R) reader structure
    impl crate::Readable for AFRL {}
    ///`write(|w| ..)` method takes [afrl::W](afrl::W) writer structure
    impl crate::Writable for AFRL {}
    ///GPIO alternate function low register
    pub mod afrl {
        ///Reader of register AFRL
        pub type R = crate::R<u32, super::AFRL>;
        ///Writer for register AFRL
        pub type W = crate::W<u32, super::AFRL>;
        ///Register AFRL `reset()`'s with value 0
        impl crate::ResetValue for super::AFRL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL7`
        pub type AFSEL7_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL7`
        pub struct AFSEL7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL6`
        pub type AFSEL6_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL6`
        pub struct AFSEL6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL5`
        pub type AFSEL5_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL5`
        pub struct AFSEL5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL4`
        pub type AFSEL4_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL4`
        pub struct AFSEL4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL3`
        pub type AFSEL3_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL3`
        pub struct AFSEL3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL2`
        pub type AFSEL2_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL2`
        pub struct AFSEL2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL1`
        pub type AFSEL1_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL1`
        pub struct AFSEL1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL0`
        pub type AFSEL0_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL0`
        pub struct AFSEL0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel7(&self) -> AFSEL7_R {
                AFSEL7_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel6(&self) -> AFSEL6_R {
                AFSEL6_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel5(&self) -> AFSEL5_R {
                AFSEL5_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&self) -> AFSEL4_R {
                AFSEL4_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&self) -> AFSEL3_R {
                AFSEL3_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&self) -> AFSEL2_R {
                AFSEL2_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&self) -> AFSEL1_R {
                AFSEL1_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&self) -> AFSEL0_R {
                AFSEL0_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel7(&mut self) -> AFSEL7_W {
                AFSEL7_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel6(&mut self) -> AFSEL6_W {
                AFSEL6_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel5(&mut self) -> AFSEL5_W {
                AFSEL5_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&mut self) -> AFSEL4_W {
                AFSEL4_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&mut self) -> AFSEL3_W {
                AFSEL3_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&mut self) -> AFSEL2_W {
                AFSEL2_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&mut self) -> AFSEL1_W {
                AFSEL1_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&mut self) -> AFSEL0_W {
                AFSEL0_W { w: self }
            }
        }
    }
    ///GPIO alternate function high register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrh](afrh) module
    pub type AFRH = crate::Reg<u32, _AFRH>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRH;
    ///`read()` method returns [afrh::R](afrh::R) reader structure
    impl crate::Readable for AFRH {}
    ///`write(|w| ..)` method takes [afrh::W](afrh::W) writer structure
    impl crate::Writable for AFRH {}
    ///GPIO alternate function high register
    pub mod afrh {
        ///Reader of register AFRH
        pub type R = crate::R<u32, super::AFRH>;
        ///Writer for register AFRH
        pub type W = crate::W<u32, super::AFRH>;
        ///Register AFRH `reset()`'s with value 0
        impl crate::ResetValue for super::AFRH {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL15`
        pub type AFSEL15_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL15`
        pub struct AFSEL15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL14`
        pub type AFSEL14_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL14`
        pub struct AFSEL14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL13`
        pub type AFSEL13_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL13`
        pub struct AFSEL13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL12`
        pub type AFSEL12_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL12`
        pub struct AFSEL12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL11`
        pub type AFSEL11_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL11`
        pub struct AFSEL11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL10`
        pub type AFSEL10_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL10`
        pub struct AFSEL10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL9`
        pub type AFSEL9_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL9`
        pub struct AFSEL9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL8`
        pub type AFSEL8_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL8`
        pub struct AFSEL8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&self) -> AFSEL15_R {
                AFSEL15_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&self) -> AFSEL14_R {
                AFSEL14_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&self) -> AFSEL13_R {
                AFSEL13_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&self) -> AFSEL12_R {
                AFSEL12_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&self) -> AFSEL11_R {
                AFSEL11_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&self) -> AFSEL10_R {
                AFSEL10_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&self) -> AFSEL9_R {
                AFSEL9_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&self) -> AFSEL8_R {
                AFSEL8_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&mut self) -> AFSEL15_W {
                AFSEL15_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&mut self) -> AFSEL14_W {
                AFSEL14_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&mut self) -> AFSEL13_W {
                AFSEL13_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&mut self) -> AFSEL12_W {
                AFSEL12_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&mut self) -> AFSEL11_W {
                AFSEL11_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&mut self) -> AFSEL10_W {
                AFSEL10_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&mut self) -> AFSEL9_W {
                AFSEL9_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&mut self) -> AFSEL8_W {
                AFSEL8_W { w: self }
            }
        }
    }
    ///port bit reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [brr](brr) module
    pub type BRR = crate::Reg<u32, _BRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BRR;
    ///`write(|w| ..)` method takes [brr::W](brr::W) writer structure
    impl crate::Writable for BRR {}
    ///port bit reset register
    pub mod brr {
        ///Writer for register BRR
        pub type W = crate::W<u32, super::BRR>;
        ///Register BRR `reset()`'s with value 0
        impl crate::ResetValue for super::BRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `BR5`
        pub struct BR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `BR6`
        pub struct BR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `BR7`
        pub struct BR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `BR8`
        pub struct BR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `BR9`
        pub struct BR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `BR10`
        pub struct BR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `BR11`
        pub struct BR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `BR12`
        pub struct BR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `BR13`
        pub struct BR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `BR14`
        pub struct BR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `BR15`
        pub struct BR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        impl W {
            ///Bit 0 - Port Reset bit
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 1 - Port Reset bit
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 2 - Port Reset bit
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 3 - Port Reset bit
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 4 - Port Reset bit
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
            ///Bit 5 - Port Reset bit
            #[inline(always)]
            pub fn br5(&mut self) -> BR5_W {
                BR5_W { w: self }
            }
            ///Bit 6 - Port Reset bit
            #[inline(always)]
            pub fn br6(&mut self) -> BR6_W {
                BR6_W { w: self }
            }
            ///Bit 7 - Port Reset bit
            #[inline(always)]
            pub fn br7(&mut self) -> BR7_W {
                BR7_W { w: self }
            }
            ///Bit 8 - Port Reset bit
            #[inline(always)]
            pub fn br8(&mut self) -> BR8_W {
                BR8_W { w: self }
            }
            ///Bit 9 - Port Reset bit
            #[inline(always)]
            pub fn br9(&mut self) -> BR9_W {
                BR9_W { w: self }
            }
            ///Bit 10 - Port Reset bit
            #[inline(always)]
            pub fn br10(&mut self) -> BR10_W {
                BR10_W { w: self }
            }
            ///Bit 11 - Port Reset bit
            #[inline(always)]
            pub fn br11(&mut self) -> BR11_W {
                BR11_W { w: self }
            }
            ///Bit 12 - Port Reset bit
            #[inline(always)]
            pub fn br12(&mut self) -> BR12_W {
                BR12_W { w: self }
            }
            ///Bit 13 - Port Reset bit
            #[inline(always)]
            pub fn br13(&mut self) -> BR13_W {
                BR13_W { w: self }
            }
            ///Bit 14 - Port Reset bit
            #[inline(always)]
            pub fn br14(&mut self) -> BR14_W {
                BR14_W { w: self }
            }
            ///Bit 15 - Port Reset bit
            #[inline(always)]
            pub fn br15(&mut self) -> BR15_W {
                BR15_W { w: self }
            }
        }
    }
}
///General-purpose I/Os
pub struct GPIOB {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOB {}
impl GPIOB {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const gpiob::RegisterBlock {
        0x4800_0400 as *const _
    }
}
impl Deref for GPIOB {
    type Target = gpiob::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*GPIOB::ptr() }
    }
}
///General-purpose I/Os
pub mod gpiob {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - GPIO port mode register
        pub moder: MODER,
        ///0x04 - GPIO port output type register
        pub otyper: OTYPER,
        ///0x08 - GPIO port output speed register
        pub ospeedr: OSPEEDR,
        ///0x0c - GPIO port pull-up/pull-down register
        pub pupdr: PUPDR,
        ///0x10 - GPIO port input data register
        pub idr: IDR,
        ///0x14 - GPIO port output data register
        pub odr: ODR,
        ///0x18 - GPIO port bit set/reset register
        pub bsrr: BSRR,
        ///0x1c - GPIO port configuration lock register
        pub lckr: LCKR,
        ///0x20 - GPIO alternate function low register
        pub afrl: AFRL,
        ///0x24 - GPIO alternate function high register
        pub afrh: AFRH,
        ///0x28 - port bit reset register
        pub brr: BRR,
    }
    ///GPIO port mode register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [moder](moder) module
    pub type MODER = crate::Reg<u32, _MODER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _MODER;
    ///`read()` method returns [moder::R](moder::R) reader structure
    impl crate::Readable for MODER {}
    ///`write(|w| ..)` method takes [moder::W](moder::W) writer structure
    impl crate::Writable for MODER {}
    ///GPIO port mode register
    pub mod moder {
        ///Reader of register MODER
        pub type R = crate::R<u32, super::MODER>;
        ///Writer for register MODER
        pub type W = crate::W<u32, super::MODER>;
        ///Register MODER `reset()`'s with value 0xffff_febf
        impl crate::ResetValue for super::MODER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_febf
            }
        }
        ///Reader of field `MODER15`
        pub type MODER15_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER15`
        pub struct MODER15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `MODER14`
        pub type MODER14_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER14`
        pub struct MODER14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `MODER13`
        pub type MODER13_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER13`
        pub struct MODER13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `MODER12`
        pub type MODER12_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER12`
        pub struct MODER12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `MODER11`
        pub type MODER11_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER11`
        pub struct MODER11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `MODER10`
        pub type MODER10_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER10`
        pub struct MODER10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `MODER9`
        pub type MODER9_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER9`
        pub struct MODER9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `MODER8`
        pub type MODER8_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER8`
        pub struct MODER8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `MODER7`
        pub type MODER7_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER7`
        pub struct MODER7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `MODER6`
        pub type MODER6_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER6`
        pub struct MODER6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MODER5`
        pub type MODER5_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER5`
        pub struct MODER5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `MODER4`
        pub type MODER4_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER4`
        pub struct MODER4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MODER3`
        pub type MODER3_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER3`
        pub struct MODER3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `MODER2`
        pub type MODER2_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER2`
        pub struct MODER2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `MODER1`
        pub type MODER1_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER1`
        pub struct MODER1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `MODER0`
        pub type MODER0_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER0`
        pub struct MODER0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder15(&self) -> MODER15_R {
                MODER15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder14(&self) -> MODER14_R {
                MODER14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder13(&self) -> MODER13_R {
                MODER13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder12(&self) -> MODER12_R {
                MODER12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder11(&self) -> MODER11_R {
                MODER11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder10(&self) -> MODER10_R {
                MODER10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder9(&self) -> MODER9_R {
                MODER9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder8(&self) -> MODER8_R {
                MODER8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder7(&self) -> MODER7_R {
                MODER7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder6(&self) -> MODER6_R {
                MODER6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder5(&self) -> MODER5_R {
                MODER5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&self) -> MODER4_R {
                MODER4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&self) -> MODER3_R {
                MODER3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&self) -> MODER2_R {
                MODER2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&self) -> MODER1_R {
                MODER1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&self) -> MODER0_R {
                MODER0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder15(&mut self) -> MODER15_W {
                MODER15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder14(&mut self) -> MODER14_W {
                MODER14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder13(&mut self) -> MODER13_W {
                MODER13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder12(&mut self) -> MODER12_W {
                MODER12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder11(&mut self) -> MODER11_W {
                MODER11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder10(&mut self) -> MODER10_W {
                MODER10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder9(&mut self) -> MODER9_W {
                MODER9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder8(&mut self) -> MODER8_W {
                MODER8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder7(&mut self) -> MODER7_W {
                MODER7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder6(&mut self) -> MODER6_W {
                MODER6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder5(&mut self) -> MODER5_W {
                MODER5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&mut self) -> MODER4_W {
                MODER4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&mut self) -> MODER3_W {
                MODER3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&mut self) -> MODER2_W {
                MODER2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&mut self) -> MODER1_W {
                MODER1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&mut self) -> MODER0_W {
                MODER0_W { w: self }
            }
        }
    }
    ///GPIO port output type register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [otyper](otyper) module
    pub type OTYPER = crate::Reg<u32, _OTYPER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OTYPER;
    ///`read()` method returns [otyper::R](otyper::R) reader structure
    impl crate::Readable for OTYPER {}
    ///`write(|w| ..)` method takes [otyper::W](otyper::W) writer structure
    impl crate::Writable for OTYPER {}
    ///GPIO port output type register
    pub mod otyper {
        ///Reader of register OTYPER
        pub type R = crate::R<u32, super::OTYPER>;
        ///Writer for register OTYPER
        pub type W = crate::W<u32, super::OTYPER>;
        ///Register OTYPER `reset()`'s with value 0
        impl crate::ResetValue for super::OTYPER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OT15`
        pub type OT15_R = crate::R<bool, bool>;
        ///Write proxy for field `OT15`
        pub struct OT15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OT14`
        pub type OT14_R = crate::R<bool, bool>;
        ///Write proxy for field `OT14`
        pub struct OT14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `OT13`
        pub type OT13_R = crate::R<bool, bool>;
        ///Write proxy for field `OT13`
        pub struct OT13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `OT12`
        pub type OT12_R = crate::R<bool, bool>;
        ///Write proxy for field `OT12`
        pub struct OT12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `OT11`
        pub type OT11_R = crate::R<bool, bool>;
        ///Write proxy for field `OT11`
        pub struct OT11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OT10`
        pub type OT10_R = crate::R<bool, bool>;
        ///Write proxy for field `OT10`
        pub struct OT10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OT9`
        pub type OT9_R = crate::R<bool, bool>;
        ///Write proxy for field `OT9`
        pub struct OT9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OT8`
        pub type OT8_R = crate::R<bool, bool>;
        ///Write proxy for field `OT8`
        pub struct OT8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `OT7`
        pub type OT7_R = crate::R<bool, bool>;
        ///Write proxy for field `OT7`
        pub struct OT7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `OT6`
        pub type OT6_R = crate::R<bool, bool>;
        ///Write proxy for field `OT6`
        pub struct OT6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `OT5`
        pub type OT5_R = crate::R<bool, bool>;
        ///Write proxy for field `OT5`
        pub struct OT5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `OT4`
        pub type OT4_R = crate::R<bool, bool>;
        ///Write proxy for field `OT4`
        pub struct OT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `OT3`
        pub type OT3_R = crate::R<bool, bool>;
        ///Write proxy for field `OT3`
        pub struct OT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OT2`
        pub type OT2_R = crate::R<bool, bool>;
        ///Write proxy for field `OT2`
        pub struct OT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OT1`
        pub type OT1_R = crate::R<bool, bool>;
        ///Write proxy for field `OT1`
        pub struct OT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `OT0`
        pub type OT0_R = crate::R<bool, bool>;
        ///Write proxy for field `OT0`
        pub struct OT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot15(&self) -> OT15_R {
                OT15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot14(&self) -> OT14_R {
                OT14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot13(&self) -> OT13_R {
                OT13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot12(&self) -> OT12_R {
                OT12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot11(&self) -> OT11_R {
                OT11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot10(&self) -> OT10_R {
                OT10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot9(&self) -> OT9_R {
                OT9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot8(&self) -> OT8_R {
                OT8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot7(&self) -> OT7_R {
                OT7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot6(&self) -> OT6_R {
                OT6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot5(&self) -> OT5_R {
                OT5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&self) -> OT4_R {
                OT4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&self) -> OT3_R {
                OT3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&self) -> OT2_R {
                OT2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&self) -> OT1_R {
                OT1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&self) -> OT0_R {
                OT0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot15(&mut self) -> OT15_W {
                OT15_W { w: self }
            }
            ///Bit 14 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot14(&mut self) -> OT14_W {
                OT14_W { w: self }
            }
            ///Bit 13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot13(&mut self) -> OT13_W {
                OT13_W { w: self }
            }
            ///Bit 12 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot12(&mut self) -> OT12_W {
                OT12_W { w: self }
            }
            ///Bit 11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot11(&mut self) -> OT11_W {
                OT11_W { w: self }
            }
            ///Bit 10 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot10(&mut self) -> OT10_W {
                OT10_W { w: self }
            }
            ///Bit 9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot9(&mut self) -> OT9_W {
                OT9_W { w: self }
            }
            ///Bit 8 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot8(&mut self) -> OT8_W {
                OT8_W { w: self }
            }
            ///Bit 7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot7(&mut self) -> OT7_W {
                OT7_W { w: self }
            }
            ///Bit 6 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot6(&mut self) -> OT6_W {
                OT6_W { w: self }
            }
            ///Bit 5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot5(&mut self) -> OT5_W {
                OT5_W { w: self }
            }
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&mut self) -> OT4_W {
                OT4_W { w: self }
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&mut self) -> OT3_W {
                OT3_W { w: self }
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&mut self) -> OT2_W {
                OT2_W { w: self }
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&mut self) -> OT1_W {
                OT1_W { w: self }
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&mut self) -> OT0_W {
                OT0_W { w: self }
            }
        }
    }
    ///GPIO port output speed register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ospeedr](ospeedr) module
    pub type OSPEEDR = crate::Reg<u32, _OSPEEDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OSPEEDR;
    ///`read()` method returns [ospeedr::R](ospeedr::R) reader structure
    impl crate::Readable for OSPEEDR {}
    ///`write(|w| ..)` method takes [ospeedr::W](ospeedr::W) writer structure
    impl crate::Writable for OSPEEDR {}
    ///GPIO port output speed register
    pub mod ospeedr {
        ///Reader of register OSPEEDR
        pub type R = crate::R<u32, super::OSPEEDR>;
        ///Writer for register OSPEEDR
        pub type W = crate::W<u32, super::OSPEEDR>;
        ///Register OSPEEDR `reset()`'s with value 0xc0
        impl crate::ResetValue for super::OSPEEDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xc0
            }
        }
        ///Reader of field `OSPEEDR15`
        pub type OSPEEDR15_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR15`
        pub struct OSPEEDR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `OSPEEDR14`
        pub type OSPEEDR14_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR14`
        pub struct OSPEEDR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `OSPEEDR13`
        pub type OSPEEDR13_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR13`
        pub struct OSPEEDR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `OSPEEDR12`
        pub type OSPEEDR12_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR12`
        pub struct OSPEEDR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `OSPEEDR11`
        pub type OSPEEDR11_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR11`
        pub struct OSPEEDR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `OSPEEDR10`
        pub type OSPEEDR10_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR10`
        pub struct OSPEEDR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `OSPEEDR9`
        pub type OSPEEDR9_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR9`
        pub struct OSPEEDR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `OSPEEDR8`
        pub type OSPEEDR8_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR8`
        pub struct OSPEEDR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `OSPEEDR7`
        pub type OSPEEDR7_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR7`
        pub struct OSPEEDR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `OSPEEDR6`
        pub type OSPEEDR6_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR6`
        pub struct OSPEEDR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `OSPEEDR5`
        pub type OSPEEDR5_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR5`
        pub struct OSPEEDR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `OSPEEDR4`
        pub type OSPEEDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR4`
        pub struct OSPEEDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OSPEEDR3`
        pub type OSPEEDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR3`
        pub struct OSPEEDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `OSPEEDR2`
        pub type OSPEEDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR2`
        pub struct OSPEEDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `OSPEEDR1`
        pub type OSPEEDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR1`
        pub struct OSPEEDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `OSPEEDR0`
        pub type OSPEEDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR0`
        pub struct OSPEEDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr15(&self) -> OSPEEDR15_R {
                OSPEEDR15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr14(&self) -> OSPEEDR14_R {
                OSPEEDR14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr13(&self) -> OSPEEDR13_R {
                OSPEEDR13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr12(&self) -> OSPEEDR12_R {
                OSPEEDR12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr11(&self) -> OSPEEDR11_R {
                OSPEEDR11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr10(&self) -> OSPEEDR10_R {
                OSPEEDR10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr9(&self) -> OSPEEDR9_R {
                OSPEEDR9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr8(&self) -> OSPEEDR8_R {
                OSPEEDR8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr7(&self) -> OSPEEDR7_R {
                OSPEEDR7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr6(&self) -> OSPEEDR6_R {
                OSPEEDR6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr5(&self) -> OSPEEDR5_R {
                OSPEEDR5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&self) -> OSPEEDR4_R {
                OSPEEDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&self) -> OSPEEDR3_R {
                OSPEEDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&self) -> OSPEEDR2_R {
                OSPEEDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&self) -> OSPEEDR1_R {
                OSPEEDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&self) -> OSPEEDR0_R {
                OSPEEDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr15(&mut self) -> OSPEEDR15_W {
                OSPEEDR15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr14(&mut self) -> OSPEEDR14_W {
                OSPEEDR14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr13(&mut self) -> OSPEEDR13_W {
                OSPEEDR13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr12(&mut self) -> OSPEEDR12_W {
                OSPEEDR12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr11(&mut self) -> OSPEEDR11_W {
                OSPEEDR11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr10(&mut self) -> OSPEEDR10_W {
                OSPEEDR10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr9(&mut self) -> OSPEEDR9_W {
                OSPEEDR9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr8(&mut self) -> OSPEEDR8_W {
                OSPEEDR8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr7(&mut self) -> OSPEEDR7_W {
                OSPEEDR7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr6(&mut self) -> OSPEEDR6_W {
                OSPEEDR6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr5(&mut self) -> OSPEEDR5_W {
                OSPEEDR5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&mut self) -> OSPEEDR4_W {
                OSPEEDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&mut self) -> OSPEEDR3_W {
                OSPEEDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&mut self) -> OSPEEDR2_W {
                OSPEEDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&mut self) -> OSPEEDR1_W {
                OSPEEDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&mut self) -> OSPEEDR0_W {
                OSPEEDR0_W { w: self }
            }
        }
    }
    ///GPIO port pull-up/pull-down register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pupdr](pupdr) module
    pub type PUPDR = crate::Reg<u32, _PUPDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUPDR;
    ///`read()` method returns [pupdr::R](pupdr::R) reader structure
    impl crate::Readable for PUPDR {}
    ///`write(|w| ..)` method takes [pupdr::W](pupdr::W) writer structure
    impl crate::Writable for PUPDR {}
    ///GPIO port pull-up/pull-down register
    pub mod pupdr {
        ///Reader of register PUPDR
        pub type R = crate::R<u32, super::PUPDR>;
        ///Writer for register PUPDR
        pub type W = crate::W<u32, super::PUPDR>;
        ///Register PUPDR `reset()`'s with value 0x0100
        impl crate::ResetValue for super::PUPDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0100
            }
        }
        ///Reader of field `PUPDR15`
        pub type PUPDR15_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR15`
        pub struct PUPDR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `PUPDR14`
        pub type PUPDR14_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR14`
        pub struct PUPDR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `PUPDR13`
        pub type PUPDR13_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR13`
        pub struct PUPDR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `PUPDR12`
        pub type PUPDR12_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR12`
        pub struct PUPDR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `PUPDR11`
        pub type PUPDR11_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR11`
        pub struct PUPDR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `PUPDR10`
        pub type PUPDR10_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR10`
        pub struct PUPDR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `PUPDR9`
        pub type PUPDR9_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR9`
        pub struct PUPDR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `PUPDR8`
        pub type PUPDR8_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR8`
        pub struct PUPDR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `PUPDR7`
        pub type PUPDR7_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR7`
        pub struct PUPDR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `PUPDR6`
        pub type PUPDR6_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR6`
        pub struct PUPDR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `PUPDR5`
        pub type PUPDR5_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR5`
        pub struct PUPDR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PUPDR4`
        pub type PUPDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR4`
        pub struct PUPDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `PUPDR3`
        pub type PUPDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR3`
        pub struct PUPDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `PUPDR2`
        pub type PUPDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR2`
        pub struct PUPDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `PUPDR1`
        pub type PUPDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR1`
        pub struct PUPDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `PUPDR0`
        pub type PUPDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR0`
        pub struct PUPDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr15(&self) -> PUPDR15_R {
                PUPDR15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr14(&self) -> PUPDR14_R {
                PUPDR14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr13(&self) -> PUPDR13_R {
                PUPDR13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr12(&self) -> PUPDR12_R {
                PUPDR12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr11(&self) -> PUPDR11_R {
                PUPDR11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr10(&self) -> PUPDR10_R {
                PUPDR10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr9(&self) -> PUPDR9_R {
                PUPDR9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr8(&self) -> PUPDR8_R {
                PUPDR8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr7(&self) -> PUPDR7_R {
                PUPDR7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr6(&self) -> PUPDR6_R {
                PUPDR6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr5(&self) -> PUPDR5_R {
                PUPDR5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&self) -> PUPDR4_R {
                PUPDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&self) -> PUPDR3_R {
                PUPDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&self) -> PUPDR2_R {
                PUPDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&self) -> PUPDR1_R {
                PUPDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&self) -> PUPDR0_R {
                PUPDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr15(&mut self) -> PUPDR15_W {
                PUPDR15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr14(&mut self) -> PUPDR14_W {
                PUPDR14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr13(&mut self) -> PUPDR13_W {
                PUPDR13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr12(&mut self) -> PUPDR12_W {
                PUPDR12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr11(&mut self) -> PUPDR11_W {
                PUPDR11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr10(&mut self) -> PUPDR10_W {
                PUPDR10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr9(&mut self) -> PUPDR9_W {
                PUPDR9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr8(&mut self) -> PUPDR8_W {
                PUPDR8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr7(&mut self) -> PUPDR7_W {
                PUPDR7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr6(&mut self) -> PUPDR6_W {
                PUPDR6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr5(&mut self) -> PUPDR5_W {
                PUPDR5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&mut self) -> PUPDR4_W {
                PUPDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&mut self) -> PUPDR3_W {
                PUPDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&mut self) -> PUPDR2_W {
                PUPDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&mut self) -> PUPDR1_W {
                PUPDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&mut self) -> PUPDR0_W {
                PUPDR0_W { w: self }
            }
        }
    }
    ///GPIO port input data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [idr](idr) module
    pub type IDR = crate::Reg<u32, _IDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IDR;
    ///`read()` method returns [idr::R](idr::R) reader structure
    impl crate::Readable for IDR {}
    ///GPIO port input data register
    pub mod idr {
        ///Reader of register IDR
        pub type R = crate::R<u32, super::IDR>;
        ///Reader of field `IDR15`
        pub type IDR15_R = crate::R<bool, bool>;
        ///Reader of field `IDR14`
        pub type IDR14_R = crate::R<bool, bool>;
        ///Reader of field `IDR13`
        pub type IDR13_R = crate::R<bool, bool>;
        ///Reader of field `IDR12`
        pub type IDR12_R = crate::R<bool, bool>;
        ///Reader of field `IDR11`
        pub type IDR11_R = crate::R<bool, bool>;
        ///Reader of field `IDR10`
        pub type IDR10_R = crate::R<bool, bool>;
        ///Reader of field `IDR9`
        pub type IDR9_R = crate::R<bool, bool>;
        ///Reader of field `IDR8`
        pub type IDR8_R = crate::R<bool, bool>;
        ///Reader of field `IDR7`
        pub type IDR7_R = crate::R<bool, bool>;
        ///Reader of field `IDR6`
        pub type IDR6_R = crate::R<bool, bool>;
        ///Reader of field `IDR5`
        pub type IDR5_R = crate::R<bool, bool>;
        ///Reader of field `IDR4`
        pub type IDR4_R = crate::R<bool, bool>;
        ///Reader of field `IDR3`
        pub type IDR3_R = crate::R<bool, bool>;
        ///Reader of field `IDR2`
        pub type IDR2_R = crate::R<bool, bool>;
        ///Reader of field `IDR1`
        pub type IDR1_R = crate::R<bool, bool>;
        ///Reader of field `IDR0`
        pub type IDR0_R = crate::R<bool, bool>;
        impl R {
            ///Bit 15 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr15(&self) -> IDR15_R {
                IDR15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr14(&self) -> IDR14_R {
                IDR14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr13(&self) -> IDR13_R {
                IDR13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr12(&self) -> IDR12_R {
                IDR12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr11(&self) -> IDR11_R {
                IDR11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr10(&self) -> IDR10_R {
                IDR10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr9(&self) -> IDR9_R {
                IDR9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr8(&self) -> IDR8_R {
                IDR8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr7(&self) -> IDR7_R {
                IDR7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr6(&self) -> IDR6_R {
                IDR6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr5(&self) -> IDR5_R {
                IDR5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr4(&self) -> IDR4_R {
                IDR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr3(&self) -> IDR3_R {
                IDR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr2(&self) -> IDR2_R {
                IDR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr1(&self) -> IDR1_R {
                IDR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr0(&self) -> IDR0_R {
                IDR0_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///GPIO port output data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [odr](odr) module
    pub type ODR = crate::Reg<u32, _ODR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ODR;
    ///`read()` method returns [odr::R](odr::R) reader structure
    impl crate::Readable for ODR {}
    ///`write(|w| ..)` method takes [odr::W](odr::W) writer structure
    impl crate::Writable for ODR {}
    ///GPIO port output data register
    pub mod odr {
        ///Reader of register ODR
        pub type R = crate::R<u32, super::ODR>;
        ///Writer for register ODR
        pub type W = crate::W<u32, super::ODR>;
        ///Register ODR `reset()`'s with value 0
        impl crate::ResetValue for super::ODR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ODR15`
        pub type ODR15_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR15`
        pub struct ODR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `ODR14`
        pub type ODR14_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR14`
        pub struct ODR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `ODR13`
        pub type ODR13_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR13`
        pub struct ODR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `ODR12`
        pub type ODR12_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR12`
        pub struct ODR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ODR11`
        pub type ODR11_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR11`
        pub struct ODR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ODR10`
        pub type ODR10_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR10`
        pub struct ODR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `ODR9`
        pub type ODR9_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR9`
        pub struct ODR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `ODR8`
        pub type ODR8_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR8`
        pub struct ODR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `ODR7`
        pub type ODR7_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR7`
        pub struct ODR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ODR6`
        pub type ODR6_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR6`
        pub struct ODR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `ODR5`
        pub type ODR5_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR5`
        pub struct ODR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `ODR4`
        pub type ODR4_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR4`
        pub struct ODR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `ODR3`
        pub type ODR3_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR3`
        pub struct ODR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ODR2`
        pub type ODR2_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR2`
        pub struct ODR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ODR1`
        pub type ODR1_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR1`
        pub struct ODR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ODR0`
        pub type ODR0_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR0`
        pub struct ODR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr15(&self) -> ODR15_R {
                ODR15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr14(&self) -> ODR14_R {
                ODR14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr13(&self) -> ODR13_R {
                ODR13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr12(&self) -> ODR12_R {
                ODR12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr11(&self) -> ODR11_R {
                ODR11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr10(&self) -> ODR10_R {
                ODR10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr9(&self) -> ODR9_R {
                ODR9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr8(&self) -> ODR8_R {
                ODR8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr7(&self) -> ODR7_R {
                ODR7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr6(&self) -> ODR6_R {
                ODR6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr5(&self) -> ODR5_R {
                ODR5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&self) -> ODR4_R {
                ODR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&self) -> ODR3_R {
                ODR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&self) -> ODR2_R {
                ODR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&self) -> ODR1_R {
                ODR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&self) -> ODR0_R {
                ODR0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr15(&mut self) -> ODR15_W {
                ODR15_W { w: self }
            }
            ///Bit 14 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr14(&mut self) -> ODR14_W {
                ODR14_W { w: self }
            }
            ///Bit 13 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr13(&mut self) -> ODR13_W {
                ODR13_W { w: self }
            }
            ///Bit 12 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr12(&mut self) -> ODR12_W {
                ODR12_W { w: self }
            }
            ///Bit 11 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr11(&mut self) -> ODR11_W {
                ODR11_W { w: self }
            }
            ///Bit 10 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr10(&mut self) -> ODR10_W {
                ODR10_W { w: self }
            }
            ///Bit 9 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr9(&mut self) -> ODR9_W {
                ODR9_W { w: self }
            }
            ///Bit 8 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr8(&mut self) -> ODR8_W {
                ODR8_W { w: self }
            }
            ///Bit 7 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr7(&mut self) -> ODR7_W {
                ODR7_W { w: self }
            }
            ///Bit 6 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr6(&mut self) -> ODR6_W {
                ODR6_W { w: self }
            }
            ///Bit 5 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr5(&mut self) -> ODR5_W {
                ODR5_W { w: self }
            }
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&mut self) -> ODR4_W {
                ODR4_W { w: self }
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&mut self) -> ODR3_W {
                ODR3_W { w: self }
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&mut self) -> ODR2_W {
                ODR2_W { w: self }
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&mut self) -> ODR1_W {
                ODR1_W { w: self }
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&mut self) -> ODR0_W {
                ODR0_W { w: self }
            }
        }
    }
    ///GPIO port bit set/reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bsrr](bsrr) module
    pub type BSRR = crate::Reg<u32, _BSRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BSRR;
    ///`write(|w| ..)` method takes [bsrr::W](bsrr::W) writer structure
    impl crate::Writable for BSRR {}
    ///GPIO port bit set/reset register
    pub mod bsrr {
        ///Writer for register BSRR
        pub type W = crate::W<u32, super::BSRR>;
        ///Register BSRR `reset()`'s with value 0
        impl crate::ResetValue for super::BSRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR15`
        pub struct BR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Write proxy for field `BR14`
        pub struct BR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Write proxy for field `BR13`
        pub struct BR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Write proxy for field `BR12`
        pub struct BR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Write proxy for field `BR11`
        pub struct BR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Write proxy for field `BR10`
        pub struct BR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Write proxy for field `BR9`
        pub struct BR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Write proxy for field `BR8`
        pub struct BR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Write proxy for field `BR7`
        pub struct BR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Write proxy for field `BR6`
        pub struct BR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Write proxy for field `BR5`
        pub struct BR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `BS15`
        pub struct BS15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Write proxy for field `BS14`
        pub struct BS14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `BS13`
        pub struct BS13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `BS12`
        pub struct BS12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `BS11`
        pub struct BS11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `BS10`
        pub struct BS10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `BS9`
        pub struct BS9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `BS8`
        pub struct BS8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `BS7`
        pub struct BS7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `BS6`
        pub struct BS6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `BS5`
        pub struct BS5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `BS4`
        pub struct BS4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `BS3`
        pub struct BS3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BS2`
        pub struct BS2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BS1`
        pub struct BS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BS0`
        pub struct BS0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 31 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br15(&mut self) -> BR15_W {
                BR15_W { w: self }
            }
            ///Bit 30 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br14(&mut self) -> BR14_W {
                BR14_W { w: self }
            }
            ///Bit 29 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br13(&mut self) -> BR13_W {
                BR13_W { w: self }
            }
            ///Bit 28 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br12(&mut self) -> BR12_W {
                BR12_W { w: self }
            }
            ///Bit 27 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br11(&mut self) -> BR11_W {
                BR11_W { w: self }
            }
            ///Bit 26 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br10(&mut self) -> BR10_W {
                BR10_W { w: self }
            }
            ///Bit 25 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br9(&mut self) -> BR9_W {
                BR9_W { w: self }
            }
            ///Bit 24 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br8(&mut self) -> BR8_W {
                BR8_W { w: self }
            }
            ///Bit 23 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br7(&mut self) -> BR7_W {
                BR7_W { w: self }
            }
            ///Bit 22 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br6(&mut self) -> BR6_W {
                BR6_W { w: self }
            }
            ///Bit 21 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br5(&mut self) -> BR5_W {
                BR5_W { w: self }
            }
            ///Bit 20 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
            ///Bit 19 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 18 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 17 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 16 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 15 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs15(&mut self) -> BS15_W {
                BS15_W { w: self }
            }
            ///Bit 14 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs14(&mut self) -> BS14_W {
                BS14_W { w: self }
            }
            ///Bit 13 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs13(&mut self) -> BS13_W {
                BS13_W { w: self }
            }
            ///Bit 12 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs12(&mut self) -> BS12_W {
                BS12_W { w: self }
            }
            ///Bit 11 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs11(&mut self) -> BS11_W {
                BS11_W { w: self }
            }
            ///Bit 10 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs10(&mut self) -> BS10_W {
                BS10_W { w: self }
            }
            ///Bit 9 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs9(&mut self) -> BS9_W {
                BS9_W { w: self }
            }
            ///Bit 8 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs8(&mut self) -> BS8_W {
                BS8_W { w: self }
            }
            ///Bit 7 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs7(&mut self) -> BS7_W {
                BS7_W { w: self }
            }
            ///Bit 6 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs6(&mut self) -> BS6_W {
                BS6_W { w: self }
            }
            ///Bit 5 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs5(&mut self) -> BS5_W {
                BS5_W { w: self }
            }
            ///Bit 4 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs4(&mut self) -> BS4_W {
                BS4_W { w: self }
            }
            ///Bit 3 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs3(&mut self) -> BS3_W {
                BS3_W { w: self }
            }
            ///Bit 2 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs2(&mut self) -> BS2_W {
                BS2_W { w: self }
            }
            ///Bit 1 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs1(&mut self) -> BS1_W {
                BS1_W { w: self }
            }
            ///Bit 0 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs0(&mut self) -> BS0_W {
                BS0_W { w: self }
            }
        }
    }
    ///GPIO port configuration lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [lckr](lckr) module
    pub type LCKR = crate::Reg<u32, _LCKR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LCKR;
    ///`read()` method returns [lckr::R](lckr::R) reader structure
    impl crate::Readable for LCKR {}
    ///`write(|w| ..)` method takes [lckr::W](lckr::W) writer structure
    impl crate::Writable for LCKR {}
    ///GPIO port configuration lock register
    pub mod lckr {
        ///Reader of register LCKR
        pub type R = crate::R<u32, super::LCKR>;
        ///Writer for register LCKR
        pub type W = crate::W<u32, super::LCKR>;
        ///Register LCKR `reset()`'s with value 0
        impl crate::ResetValue for super::LCKR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LCKK`
        pub type LCKK_R = crate::R<bool, bool>;
        ///Write proxy for field `LCKK`
        pub struct LCKK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCKK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `LCK15`
        pub type LCK15_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK15`
        pub struct LCK15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `LCK14`
        pub type LCK14_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK14`
        pub struct LCK14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `LCK13`
        pub type LCK13_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK13`
        pub struct LCK13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `LCK12`
        pub type LCK12_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK12`
        pub struct LCK12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `LCK11`
        pub type LCK11_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK11`
        pub struct LCK11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `LCK10`
        pub type LCK10_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK10`
        pub struct LCK10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LCK9`
        pub type LCK9_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK9`
        pub struct LCK9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `LCK8`
        pub type LCK8_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK8`
        pub struct LCK8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `LCK7`
        pub type LCK7_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK7`
        pub struct LCK7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `LCK6`
        pub type LCK6_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK6`
        pub struct LCK6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `LCK5`
        pub type LCK5_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK5`
        pub struct LCK5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LCK4`
        pub type LCK4_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK4`
        pub struct LCK4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `LCK3`
        pub type LCK3_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK3`
        pub struct LCK3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `LCK2`
        pub type LCK2_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK2`
        pub struct LCK2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `LCK1`
        pub type LCK1_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK1`
        pub struct LCK1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LCK0`
        pub type LCK0_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK0`
        pub struct LCK0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&self) -> LCKK_R {
                LCKK_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck15(&self) -> LCK15_R {
                LCK15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck14(&self) -> LCK14_R {
                LCK14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck13(&self) -> LCK13_R {
                LCK13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck12(&self) -> LCK12_R {
                LCK12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck11(&self) -> LCK11_R {
                LCK11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck10(&self) -> LCK10_R {
                LCK10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck9(&self) -> LCK9_R {
                LCK9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck8(&self) -> LCK8_R {
                LCK8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck7(&self) -> LCK7_R {
                LCK7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck6(&self) -> LCK6_R {
                LCK6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck5(&self) -> LCK5_R {
                LCK5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&self) -> LCK4_R {
                LCK4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&self) -> LCK3_R {
                LCK3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&self) -> LCK2_R {
                LCK2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&self) -> LCK1_R {
                LCK1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&self) -> LCK0_R {
                LCK0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&mut self) -> LCKK_W {
                LCKK_W { w: self }
            }
            ///Bit 15 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck15(&mut self) -> LCK15_W {
                LCK15_W { w: self }
            }
            ///Bit 14 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck14(&mut self) -> LCK14_W {
                LCK14_W { w: self }
            }
            ///Bit 13 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck13(&mut self) -> LCK13_W {
                LCK13_W { w: self }
            }
            ///Bit 12 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck12(&mut self) -> LCK12_W {
                LCK12_W { w: self }
            }
            ///Bit 11 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck11(&mut self) -> LCK11_W {
                LCK11_W { w: self }
            }
            ///Bit 10 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck10(&mut self) -> LCK10_W {
                LCK10_W { w: self }
            }
            ///Bit 9 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck9(&mut self) -> LCK9_W {
                LCK9_W { w: self }
            }
            ///Bit 8 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck8(&mut self) -> LCK8_W {
                LCK8_W { w: self }
            }
            ///Bit 7 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck7(&mut self) -> LCK7_W {
                LCK7_W { w: self }
            }
            ///Bit 6 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck6(&mut self) -> LCK6_W {
                LCK6_W { w: self }
            }
            ///Bit 5 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck5(&mut self) -> LCK5_W {
                LCK5_W { w: self }
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&mut self) -> LCK4_W {
                LCK4_W { w: self }
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&mut self) -> LCK3_W {
                LCK3_W { w: self }
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&mut self) -> LCK2_W {
                LCK2_W { w: self }
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&mut self) -> LCK1_W {
                LCK1_W { w: self }
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&mut self) -> LCK0_W {
                LCK0_W { w: self }
            }
        }
    }
    ///GPIO alternate function low register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrl](afrl) module
    pub type AFRL = crate::Reg<u32, _AFRL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRL;
    ///`read()` method returns [afrl::R](afrl::R) reader structure
    impl crate::Readable for AFRL {}
    ///`write(|w| ..)` method takes [afrl::W](afrl::W) writer structure
    impl crate::Writable for AFRL {}
    ///GPIO alternate function low register
    pub mod afrl {
        ///Reader of register AFRL
        pub type R = crate::R<u32, super::AFRL>;
        ///Writer for register AFRL
        pub type W = crate::W<u32, super::AFRL>;
        ///Register AFRL `reset()`'s with value 0
        impl crate::ResetValue for super::AFRL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL7`
        pub type AFSEL7_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL7`
        pub struct AFSEL7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL6`
        pub type AFSEL6_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL6`
        pub struct AFSEL6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL5`
        pub type AFSEL5_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL5`
        pub struct AFSEL5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL4`
        pub type AFSEL4_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL4`
        pub struct AFSEL4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL3`
        pub type AFSEL3_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL3`
        pub struct AFSEL3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL2`
        pub type AFSEL2_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL2`
        pub struct AFSEL2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL1`
        pub type AFSEL1_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL1`
        pub struct AFSEL1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL0`
        pub type AFSEL0_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL0`
        pub struct AFSEL0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel7(&self) -> AFSEL7_R {
                AFSEL7_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel6(&self) -> AFSEL6_R {
                AFSEL6_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel5(&self) -> AFSEL5_R {
                AFSEL5_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&self) -> AFSEL4_R {
                AFSEL4_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&self) -> AFSEL3_R {
                AFSEL3_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&self) -> AFSEL2_R {
                AFSEL2_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&self) -> AFSEL1_R {
                AFSEL1_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&self) -> AFSEL0_R {
                AFSEL0_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel7(&mut self) -> AFSEL7_W {
                AFSEL7_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel6(&mut self) -> AFSEL6_W {
                AFSEL6_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel5(&mut self) -> AFSEL5_W {
                AFSEL5_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&mut self) -> AFSEL4_W {
                AFSEL4_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&mut self) -> AFSEL3_W {
                AFSEL3_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&mut self) -> AFSEL2_W {
                AFSEL2_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&mut self) -> AFSEL1_W {
                AFSEL1_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&mut self) -> AFSEL0_W {
                AFSEL0_W { w: self }
            }
        }
    }
    ///GPIO alternate function high register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrh](afrh) module
    pub type AFRH = crate::Reg<u32, _AFRH>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRH;
    ///`read()` method returns [afrh::R](afrh::R) reader structure
    impl crate::Readable for AFRH {}
    ///`write(|w| ..)` method takes [afrh::W](afrh::W) writer structure
    impl crate::Writable for AFRH {}
    ///GPIO alternate function high register
    pub mod afrh {
        ///Reader of register AFRH
        pub type R = crate::R<u32, super::AFRH>;
        ///Writer for register AFRH
        pub type W = crate::W<u32, super::AFRH>;
        ///Register AFRH `reset()`'s with value 0
        impl crate::ResetValue for super::AFRH {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL15`
        pub type AFSEL15_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL15`
        pub struct AFSEL15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL14`
        pub type AFSEL14_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL14`
        pub struct AFSEL14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL13`
        pub type AFSEL13_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL13`
        pub struct AFSEL13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL12`
        pub type AFSEL12_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL12`
        pub struct AFSEL12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL11`
        pub type AFSEL11_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL11`
        pub struct AFSEL11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL10`
        pub type AFSEL10_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL10`
        pub struct AFSEL10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL9`
        pub type AFSEL9_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL9`
        pub struct AFSEL9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL8`
        pub type AFSEL8_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL8`
        pub struct AFSEL8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&self) -> AFSEL15_R {
                AFSEL15_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&self) -> AFSEL14_R {
                AFSEL14_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&self) -> AFSEL13_R {
                AFSEL13_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&self) -> AFSEL12_R {
                AFSEL12_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&self) -> AFSEL11_R {
                AFSEL11_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&self) -> AFSEL10_R {
                AFSEL10_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&self) -> AFSEL9_R {
                AFSEL9_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&self) -> AFSEL8_R {
                AFSEL8_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&mut self) -> AFSEL15_W {
                AFSEL15_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&mut self) -> AFSEL14_W {
                AFSEL14_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&mut self) -> AFSEL13_W {
                AFSEL13_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&mut self) -> AFSEL12_W {
                AFSEL12_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&mut self) -> AFSEL11_W {
                AFSEL11_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&mut self) -> AFSEL10_W {
                AFSEL10_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&mut self) -> AFSEL9_W {
                AFSEL9_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&mut self) -> AFSEL8_W {
                AFSEL8_W { w: self }
            }
        }
    }
    ///port bit reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [brr](brr) module
    pub type BRR = crate::Reg<u32, _BRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BRR;
    ///`write(|w| ..)` method takes [brr::W](brr::W) writer structure
    impl crate::Writable for BRR {}
    ///port bit reset register
    pub mod brr {
        ///Writer for register BRR
        pub type W = crate::W<u32, super::BRR>;
        ///Register BRR `reset()`'s with value 0
        impl crate::ResetValue for super::BRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `BR5`
        pub struct BR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `BR6`
        pub struct BR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `BR7`
        pub struct BR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `BR8`
        pub struct BR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `BR9`
        pub struct BR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `BR10`
        pub struct BR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `BR11`
        pub struct BR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `BR12`
        pub struct BR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `BR13`
        pub struct BR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `BR14`
        pub struct BR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `BR15`
        pub struct BR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        impl W {
            ///Bit 0 - Port Reset bit
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 1 - Port Reset bit
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 2 - Port Reset bit
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 3 - Port Reset bit
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 4 - Port Reset bit
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
            ///Bit 5 - Port Reset bit
            #[inline(always)]
            pub fn br5(&mut self) -> BR5_W {
                BR5_W { w: self }
            }
            ///Bit 6 - Port Reset bit
            #[inline(always)]
            pub fn br6(&mut self) -> BR6_W {
                BR6_W { w: self }
            }
            ///Bit 7 - Port Reset bit
            #[inline(always)]
            pub fn br7(&mut self) -> BR7_W {
                BR7_W { w: self }
            }
            ///Bit 8 - Port Reset bit
            #[inline(always)]
            pub fn br8(&mut self) -> BR8_W {
                BR8_W { w: self }
            }
            ///Bit 9 - Port Reset bit
            #[inline(always)]
            pub fn br9(&mut self) -> BR9_W {
                BR9_W { w: self }
            }
            ///Bit 10 - Port Reset bit
            #[inline(always)]
            pub fn br10(&mut self) -> BR10_W {
                BR10_W { w: self }
            }
            ///Bit 11 - Port Reset bit
            #[inline(always)]
            pub fn br11(&mut self) -> BR11_W {
                BR11_W { w: self }
            }
            ///Bit 12 - Port Reset bit
            #[inline(always)]
            pub fn br12(&mut self) -> BR12_W {
                BR12_W { w: self }
            }
            ///Bit 13 - Port Reset bit
            #[inline(always)]
            pub fn br13(&mut self) -> BR13_W {
                BR13_W { w: self }
            }
            ///Bit 14 - Port Reset bit
            #[inline(always)]
            pub fn br14(&mut self) -> BR14_W {
                BR14_W { w: self }
            }
            ///Bit 15 - Port Reset bit
            #[inline(always)]
            pub fn br15(&mut self) -> BR15_W {
                BR15_W { w: self }
            }
        }
    }
}
///General-purpose I/Os
pub struct GPIOC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOC {}
impl GPIOC {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const gpioc::RegisterBlock {
        0x4800_0800 as *const _
    }
}
impl Deref for GPIOC {
    type Target = gpioc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*GPIOC::ptr() }
    }
}
///General-purpose I/Os
pub mod gpioc {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - GPIO port mode register
        pub moder: MODER,
        ///0x04 - GPIO port output type register
        pub otyper: OTYPER,
        ///0x08 - GPIO port output speed register
        pub ospeedr: OSPEEDR,
        ///0x0c - GPIO port pull-up/pull-down register
        pub pupdr: PUPDR,
        ///0x10 - GPIO port input data register
        pub idr: IDR,
        ///0x14 - GPIO port output data register
        pub odr: ODR,
        ///0x18 - GPIO port bit set/reset register
        pub bsrr: BSRR,
        ///0x1c - GPIO port configuration lock register
        pub lckr: LCKR,
        ///0x20 - GPIO alternate function low register
        pub afrl: AFRL,
        ///0x24 - GPIO alternate function high register
        pub afrh: AFRH,
        ///0x28 - port bit reset register
        pub brr: BRR,
    }
    ///GPIO port mode register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [moder](moder) module
    pub type MODER = crate::Reg<u32, _MODER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _MODER;
    ///`read()` method returns [moder::R](moder::R) reader structure
    impl crate::Readable for MODER {}
    ///`write(|w| ..)` method takes [moder::W](moder::W) writer structure
    impl crate::Writable for MODER {}
    ///GPIO port mode register
    pub mod moder {
        ///Reader of register MODER
        pub type R = crate::R<u32, super::MODER>;
        ///Writer for register MODER
        pub type W = crate::W<u32, super::MODER>;
        ///Register MODER `reset()`'s with value 0xffff_ffff
        impl crate::ResetValue for super::MODER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_ffff
            }
        }
        ///Reader of field `MODER15`
        pub type MODER15_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER15`
        pub struct MODER15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `MODER14`
        pub type MODER14_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER14`
        pub struct MODER14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `MODER13`
        pub type MODER13_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER13`
        pub struct MODER13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `MODER12`
        pub type MODER12_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER12`
        pub struct MODER12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `MODER11`
        pub type MODER11_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER11`
        pub struct MODER11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `MODER10`
        pub type MODER10_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER10`
        pub struct MODER10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `MODER9`
        pub type MODER9_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER9`
        pub struct MODER9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `MODER8`
        pub type MODER8_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER8`
        pub struct MODER8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `MODER7`
        pub type MODER7_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER7`
        pub struct MODER7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `MODER6`
        pub type MODER6_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER6`
        pub struct MODER6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `MODER5`
        pub type MODER5_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER5`
        pub struct MODER5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `MODER4`
        pub type MODER4_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER4`
        pub struct MODER4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MODER3`
        pub type MODER3_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER3`
        pub struct MODER3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `MODER2`
        pub type MODER2_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER2`
        pub struct MODER2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `MODER1`
        pub type MODER1_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER1`
        pub struct MODER1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `MODER0`
        pub type MODER0_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER0`
        pub struct MODER0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder15(&self) -> MODER15_R {
                MODER15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder14(&self) -> MODER14_R {
                MODER14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder13(&self) -> MODER13_R {
                MODER13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder12(&self) -> MODER12_R {
                MODER12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder11(&self) -> MODER11_R {
                MODER11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder10(&self) -> MODER10_R {
                MODER10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder9(&self) -> MODER9_R {
                MODER9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder8(&self) -> MODER8_R {
                MODER8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder7(&self) -> MODER7_R {
                MODER7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder6(&self) -> MODER6_R {
                MODER6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder5(&self) -> MODER5_R {
                MODER5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&self) -> MODER4_R {
                MODER4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&self) -> MODER3_R {
                MODER3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&self) -> MODER2_R {
                MODER2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&self) -> MODER1_R {
                MODER1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&self) -> MODER0_R {
                MODER0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder15(&mut self) -> MODER15_W {
                MODER15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder14(&mut self) -> MODER14_W {
                MODER14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder13(&mut self) -> MODER13_W {
                MODER13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder12(&mut self) -> MODER12_W {
                MODER12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder11(&mut self) -> MODER11_W {
                MODER11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder10(&mut self) -> MODER10_W {
                MODER10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder9(&mut self) -> MODER9_W {
                MODER9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder8(&mut self) -> MODER8_W {
                MODER8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder7(&mut self) -> MODER7_W {
                MODER7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder6(&mut self) -> MODER6_W {
                MODER6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder5(&mut self) -> MODER5_W {
                MODER5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&mut self) -> MODER4_W {
                MODER4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&mut self) -> MODER3_W {
                MODER3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&mut self) -> MODER2_W {
                MODER2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&mut self) -> MODER1_W {
                MODER1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&mut self) -> MODER0_W {
                MODER0_W { w: self }
            }
        }
    }
    ///GPIO port output type register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [otyper](otyper) module
    pub type OTYPER = crate::Reg<u32, _OTYPER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OTYPER;
    ///`read()` method returns [otyper::R](otyper::R) reader structure
    impl crate::Readable for OTYPER {}
    ///`write(|w| ..)` method takes [otyper::W](otyper::W) writer structure
    impl crate::Writable for OTYPER {}
    ///GPIO port output type register
    pub mod otyper {
        ///Reader of register OTYPER
        pub type R = crate::R<u32, super::OTYPER>;
        ///Writer for register OTYPER
        pub type W = crate::W<u32, super::OTYPER>;
        ///Register OTYPER `reset()`'s with value 0
        impl crate::ResetValue for super::OTYPER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OT15`
        pub type OT15_R = crate::R<bool, bool>;
        ///Write proxy for field `OT15`
        pub struct OT15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OT14`
        pub type OT14_R = crate::R<bool, bool>;
        ///Write proxy for field `OT14`
        pub struct OT14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `OT13`
        pub type OT13_R = crate::R<bool, bool>;
        ///Write proxy for field `OT13`
        pub struct OT13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `OT12`
        pub type OT12_R = crate::R<bool, bool>;
        ///Write proxy for field `OT12`
        pub struct OT12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `OT11`
        pub type OT11_R = crate::R<bool, bool>;
        ///Write proxy for field `OT11`
        pub struct OT11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OT10`
        pub type OT10_R = crate::R<bool, bool>;
        ///Write proxy for field `OT10`
        pub struct OT10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OT9`
        pub type OT9_R = crate::R<bool, bool>;
        ///Write proxy for field `OT9`
        pub struct OT9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OT8`
        pub type OT8_R = crate::R<bool, bool>;
        ///Write proxy for field `OT8`
        pub struct OT8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `OT7`
        pub type OT7_R = crate::R<bool, bool>;
        ///Write proxy for field `OT7`
        pub struct OT7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `OT6`
        pub type OT6_R = crate::R<bool, bool>;
        ///Write proxy for field `OT6`
        pub struct OT6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `OT5`
        pub type OT5_R = crate::R<bool, bool>;
        ///Write proxy for field `OT5`
        pub struct OT5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `OT4`
        pub type OT4_R = crate::R<bool, bool>;
        ///Write proxy for field `OT4`
        pub struct OT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `OT3`
        pub type OT3_R = crate::R<bool, bool>;
        ///Write proxy for field `OT3`
        pub struct OT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OT2`
        pub type OT2_R = crate::R<bool, bool>;
        ///Write proxy for field `OT2`
        pub struct OT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OT1`
        pub type OT1_R = crate::R<bool, bool>;
        ///Write proxy for field `OT1`
        pub struct OT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `OT0`
        pub type OT0_R = crate::R<bool, bool>;
        ///Write proxy for field `OT0`
        pub struct OT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot15(&self) -> OT15_R {
                OT15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot14(&self) -> OT14_R {
                OT14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot13(&self) -> OT13_R {
                OT13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot12(&self) -> OT12_R {
                OT12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot11(&self) -> OT11_R {
                OT11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot10(&self) -> OT10_R {
                OT10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot9(&self) -> OT9_R {
                OT9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot8(&self) -> OT8_R {
                OT8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot7(&self) -> OT7_R {
                OT7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot6(&self) -> OT6_R {
                OT6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot5(&self) -> OT5_R {
                OT5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&self) -> OT4_R {
                OT4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&self) -> OT3_R {
                OT3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&self) -> OT2_R {
                OT2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&self) -> OT1_R {
                OT1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&self) -> OT0_R {
                OT0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot15(&mut self) -> OT15_W {
                OT15_W { w: self }
            }
            ///Bit 14 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot14(&mut self) -> OT14_W {
                OT14_W { w: self }
            }
            ///Bit 13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot13(&mut self) -> OT13_W {
                OT13_W { w: self }
            }
            ///Bit 12 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot12(&mut self) -> OT12_W {
                OT12_W { w: self }
            }
            ///Bit 11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot11(&mut self) -> OT11_W {
                OT11_W { w: self }
            }
            ///Bit 10 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot10(&mut self) -> OT10_W {
                OT10_W { w: self }
            }
            ///Bit 9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot9(&mut self) -> OT9_W {
                OT9_W { w: self }
            }
            ///Bit 8 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot8(&mut self) -> OT8_W {
                OT8_W { w: self }
            }
            ///Bit 7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot7(&mut self) -> OT7_W {
                OT7_W { w: self }
            }
            ///Bit 6 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot6(&mut self) -> OT6_W {
                OT6_W { w: self }
            }
            ///Bit 5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot5(&mut self) -> OT5_W {
                OT5_W { w: self }
            }
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&mut self) -> OT4_W {
                OT4_W { w: self }
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&mut self) -> OT3_W {
                OT3_W { w: self }
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&mut self) -> OT2_W {
                OT2_W { w: self }
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&mut self) -> OT1_W {
                OT1_W { w: self }
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&mut self) -> OT0_W {
                OT0_W { w: self }
            }
        }
    }
    ///GPIO port output speed register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ospeedr](ospeedr) module
    pub type OSPEEDR = crate::Reg<u32, _OSPEEDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OSPEEDR;
    ///`read()` method returns [ospeedr::R](ospeedr::R) reader structure
    impl crate::Readable for OSPEEDR {}
    ///`write(|w| ..)` method takes [ospeedr::W](ospeedr::W) writer structure
    impl crate::Writable for OSPEEDR {}
    ///GPIO port output speed register
    pub mod ospeedr {
        ///Reader of register OSPEEDR
        pub type R = crate::R<u32, super::OSPEEDR>;
        ///Writer for register OSPEEDR
        pub type W = crate::W<u32, super::OSPEEDR>;
        ///Register OSPEEDR `reset()`'s with value 0xc0
        impl crate::ResetValue for super::OSPEEDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xc0
            }
        }
        ///Reader of field `OSPEEDR15`
        pub type OSPEEDR15_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR15`
        pub struct OSPEEDR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `OSPEEDR14`
        pub type OSPEEDR14_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR14`
        pub struct OSPEEDR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `OSPEEDR13`
        pub type OSPEEDR13_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR13`
        pub struct OSPEEDR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `OSPEEDR12`
        pub type OSPEEDR12_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR12`
        pub struct OSPEEDR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `OSPEEDR11`
        pub type OSPEEDR11_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR11`
        pub struct OSPEEDR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `OSPEEDR10`
        pub type OSPEEDR10_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR10`
        pub struct OSPEEDR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `OSPEEDR9`
        pub type OSPEEDR9_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR9`
        pub struct OSPEEDR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `OSPEEDR8`
        pub type OSPEEDR8_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR8`
        pub struct OSPEEDR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `OSPEEDR7`
        pub type OSPEEDR7_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR7`
        pub struct OSPEEDR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `OSPEEDR6`
        pub type OSPEEDR6_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR6`
        pub struct OSPEEDR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `OSPEEDR5`
        pub type OSPEEDR5_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR5`
        pub struct OSPEEDR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `OSPEEDR4`
        pub type OSPEEDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR4`
        pub struct OSPEEDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OSPEEDR3`
        pub type OSPEEDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR3`
        pub struct OSPEEDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `OSPEEDR2`
        pub type OSPEEDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR2`
        pub struct OSPEEDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `OSPEEDR1`
        pub type OSPEEDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR1`
        pub struct OSPEEDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `OSPEEDR0`
        pub type OSPEEDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR0`
        pub struct OSPEEDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr15(&self) -> OSPEEDR15_R {
                OSPEEDR15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr14(&self) -> OSPEEDR14_R {
                OSPEEDR14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr13(&self) -> OSPEEDR13_R {
                OSPEEDR13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr12(&self) -> OSPEEDR12_R {
                OSPEEDR12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr11(&self) -> OSPEEDR11_R {
                OSPEEDR11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr10(&self) -> OSPEEDR10_R {
                OSPEEDR10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr9(&self) -> OSPEEDR9_R {
                OSPEEDR9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr8(&self) -> OSPEEDR8_R {
                OSPEEDR8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr7(&self) -> OSPEEDR7_R {
                OSPEEDR7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr6(&self) -> OSPEEDR6_R {
                OSPEEDR6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr5(&self) -> OSPEEDR5_R {
                OSPEEDR5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&self) -> OSPEEDR4_R {
                OSPEEDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&self) -> OSPEEDR3_R {
                OSPEEDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&self) -> OSPEEDR2_R {
                OSPEEDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&self) -> OSPEEDR1_R {
                OSPEEDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&self) -> OSPEEDR0_R {
                OSPEEDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr15(&mut self) -> OSPEEDR15_W {
                OSPEEDR15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr14(&mut self) -> OSPEEDR14_W {
                OSPEEDR14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr13(&mut self) -> OSPEEDR13_W {
                OSPEEDR13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr12(&mut self) -> OSPEEDR12_W {
                OSPEEDR12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr11(&mut self) -> OSPEEDR11_W {
                OSPEEDR11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr10(&mut self) -> OSPEEDR10_W {
                OSPEEDR10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr9(&mut self) -> OSPEEDR9_W {
                OSPEEDR9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr8(&mut self) -> OSPEEDR8_W {
                OSPEEDR8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr7(&mut self) -> OSPEEDR7_W {
                OSPEEDR7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr6(&mut self) -> OSPEEDR6_W {
                OSPEEDR6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr5(&mut self) -> OSPEEDR5_W {
                OSPEEDR5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&mut self) -> OSPEEDR4_W {
                OSPEEDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&mut self) -> OSPEEDR3_W {
                OSPEEDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&mut self) -> OSPEEDR2_W {
                OSPEEDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&mut self) -> OSPEEDR1_W {
                OSPEEDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&mut self) -> OSPEEDR0_W {
                OSPEEDR0_W { w: self }
            }
        }
    }
    ///GPIO port pull-up/pull-down register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pupdr](pupdr) module
    pub type PUPDR = crate::Reg<u32, _PUPDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUPDR;
    ///`read()` method returns [pupdr::R](pupdr::R) reader structure
    impl crate::Readable for PUPDR {}
    ///`write(|w| ..)` method takes [pupdr::W](pupdr::W) writer structure
    impl crate::Writable for PUPDR {}
    ///GPIO port pull-up/pull-down register
    pub mod pupdr {
        ///Reader of register PUPDR
        pub type R = crate::R<u32, super::PUPDR>;
        ///Writer for register PUPDR
        pub type W = crate::W<u32, super::PUPDR>;
        ///Register PUPDR `reset()`'s with value 0x0100
        impl crate::ResetValue for super::PUPDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0100
            }
        }
        ///Reader of field `PUPDR15`
        pub type PUPDR15_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR15`
        pub struct PUPDR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
                self.w
            }
        }
        ///Reader of field `PUPDR14`
        pub type PUPDR14_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR14`
        pub struct PUPDR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `PUPDR13`
        pub type PUPDR13_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR13`
        pub struct PUPDR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
                self.w
            }
        }
        ///Reader of field `PUPDR12`
        pub type PUPDR12_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR12`
        pub struct PUPDR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
                self.w
            }
        }
        ///Reader of field `PUPDR11`
        pub type PUPDR11_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR11`
        pub struct PUPDR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
                self.w
            }
        }
        ///Reader of field `PUPDR10`
        pub type PUPDR10_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR10`
        pub struct PUPDR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `PUPDR9`
        pub type PUPDR9_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR9`
        pub struct PUPDR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
                self.w
            }
        }
        ///Reader of field `PUPDR8`
        pub type PUPDR8_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR8`
        pub struct PUPDR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
                self.w
            }
        }
        ///Reader of field `PUPDR7`
        pub type PUPDR7_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR7`
        pub struct PUPDR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                self.w
            }
        }
        ///Reader of field `PUPDR6`
        pub type PUPDR6_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR6`
        pub struct PUPDR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `PUPDR5`
        pub type PUPDR5_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR5`
        pub struct PUPDR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `PUPDR4`
        pub type PUPDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR4`
        pub struct PUPDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `PUPDR3`
        pub type PUPDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR3`
        pub struct PUPDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `PUPDR2`
        pub type PUPDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR2`
        pub struct PUPDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `PUPDR1`
        pub type PUPDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR1`
        pub struct PUPDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `PUPDR0`
        pub type PUPDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR0`
        pub struct PUPDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr15(&self) -> PUPDR15_R {
                PUPDR15_R::new(((self.bits >> 30) & 0x03) as u8)
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr14(&self) -> PUPDR14_R {
                PUPDR14_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr13(&self) -> PUPDR13_R {
                PUPDR13_R::new(((self.bits >> 26) & 0x03) as u8)
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr12(&self) -> PUPDR12_R {
                PUPDR12_R::new(((self.bits >> 24) & 0x03) as u8)
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr11(&self) -> PUPDR11_R {
                PUPDR11_R::new(((self.bits >> 22) & 0x03) as u8)
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr10(&self) -> PUPDR10_R {
                PUPDR10_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr9(&self) -> PUPDR9_R {
                PUPDR9_R::new(((self.bits >> 18) & 0x03) as u8)
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr8(&self) -> PUPDR8_R {
                PUPDR8_R::new(((self.bits >> 16) & 0x03) as u8)
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr7(&self) -> PUPDR7_R {
                PUPDR7_R::new(((self.bits >> 14) & 0x03) as u8)
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr6(&self) -> PUPDR6_R {
                PUPDR6_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr5(&self) -> PUPDR5_R {
                PUPDR5_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&self) -> PUPDR4_R {
                PUPDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&self) -> PUPDR3_R {
                PUPDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&self) -> PUPDR2_R {
                PUPDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&self) -> PUPDR1_R {
                PUPDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&self) -> PUPDR0_R {
                PUPDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 30:31 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr15(&mut self) -> PUPDR15_W {
                PUPDR15_W { w: self }
            }
            ///Bits 28:29 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr14(&mut self) -> PUPDR14_W {
                PUPDR14_W { w: self }
            }
            ///Bits 26:27 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr13(&mut self) -> PUPDR13_W {
                PUPDR13_W { w: self }
            }
            ///Bits 24:25 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr12(&mut self) -> PUPDR12_W {
                PUPDR12_W { w: self }
            }
            ///Bits 22:23 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr11(&mut self) -> PUPDR11_W {
                PUPDR11_W { w: self }
            }
            ///Bits 20:21 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr10(&mut self) -> PUPDR10_W {
                PUPDR10_W { w: self }
            }
            ///Bits 18:19 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr9(&mut self) -> PUPDR9_W {
                PUPDR9_W { w: self }
            }
            ///Bits 16:17 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr8(&mut self) -> PUPDR8_W {
                PUPDR8_W { w: self }
            }
            ///Bits 14:15 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr7(&mut self) -> PUPDR7_W {
                PUPDR7_W { w: self }
            }
            ///Bits 12:13 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr6(&mut self) -> PUPDR6_W {
                PUPDR6_W { w: self }
            }
            ///Bits 10:11 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr5(&mut self) -> PUPDR5_W {
                PUPDR5_W { w: self }
            }
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&mut self) -> PUPDR4_W {
                PUPDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&mut self) -> PUPDR3_W {
                PUPDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&mut self) -> PUPDR2_W {
                PUPDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&mut self) -> PUPDR1_W {
                PUPDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&mut self) -> PUPDR0_W {
                PUPDR0_W { w: self }
            }
        }
    }
    ///GPIO port input data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [idr](idr) module
    pub type IDR = crate::Reg<u32, _IDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IDR;
    ///`read()` method returns [idr::R](idr::R) reader structure
    impl crate::Readable for IDR {}
    ///GPIO port input data register
    pub mod idr {
        ///Reader of register IDR
        pub type R = crate::R<u32, super::IDR>;
        ///Reader of field `IDR15`
        pub type IDR15_R = crate::R<bool, bool>;
        ///Reader of field `IDR14`
        pub type IDR14_R = crate::R<bool, bool>;
        ///Reader of field `IDR13`
        pub type IDR13_R = crate::R<bool, bool>;
        ///Reader of field `IDR12`
        pub type IDR12_R = crate::R<bool, bool>;
        ///Reader of field `IDR11`
        pub type IDR11_R = crate::R<bool, bool>;
        ///Reader of field `IDR10`
        pub type IDR10_R = crate::R<bool, bool>;
        ///Reader of field `IDR9`
        pub type IDR9_R = crate::R<bool, bool>;
        ///Reader of field `IDR8`
        pub type IDR8_R = crate::R<bool, bool>;
        ///Reader of field `IDR7`
        pub type IDR7_R = crate::R<bool, bool>;
        ///Reader of field `IDR6`
        pub type IDR6_R = crate::R<bool, bool>;
        ///Reader of field `IDR5`
        pub type IDR5_R = crate::R<bool, bool>;
        ///Reader of field `IDR4`
        pub type IDR4_R = crate::R<bool, bool>;
        ///Reader of field `IDR3`
        pub type IDR3_R = crate::R<bool, bool>;
        ///Reader of field `IDR2`
        pub type IDR2_R = crate::R<bool, bool>;
        ///Reader of field `IDR1`
        pub type IDR1_R = crate::R<bool, bool>;
        ///Reader of field `IDR0`
        pub type IDR0_R = crate::R<bool, bool>;
        impl R {
            ///Bit 15 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr15(&self) -> IDR15_R {
                IDR15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr14(&self) -> IDR14_R {
                IDR14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr13(&self) -> IDR13_R {
                IDR13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr12(&self) -> IDR12_R {
                IDR12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr11(&self) -> IDR11_R {
                IDR11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr10(&self) -> IDR10_R {
                IDR10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr9(&self) -> IDR9_R {
                IDR9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr8(&self) -> IDR8_R {
                IDR8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr7(&self) -> IDR7_R {
                IDR7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr6(&self) -> IDR6_R {
                IDR6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr5(&self) -> IDR5_R {
                IDR5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr4(&self) -> IDR4_R {
                IDR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr3(&self) -> IDR3_R {
                IDR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr2(&self) -> IDR2_R {
                IDR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr1(&self) -> IDR1_R {
                IDR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr0(&self) -> IDR0_R {
                IDR0_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///GPIO port output data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [odr](odr) module
    pub type ODR = crate::Reg<u32, _ODR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ODR;
    ///`read()` method returns [odr::R](odr::R) reader structure
    impl crate::Readable for ODR {}
    ///`write(|w| ..)` method takes [odr::W](odr::W) writer structure
    impl crate::Writable for ODR {}
    ///GPIO port output data register
    pub mod odr {
        ///Reader of register ODR
        pub type R = crate::R<u32, super::ODR>;
        ///Writer for register ODR
        pub type W = crate::W<u32, super::ODR>;
        ///Register ODR `reset()`'s with value 0
        impl crate::ResetValue for super::ODR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ODR15`
        pub type ODR15_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR15`
        pub struct ODR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `ODR14`
        pub type ODR14_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR14`
        pub struct ODR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `ODR13`
        pub type ODR13_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR13`
        pub struct ODR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `ODR12`
        pub type ODR12_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR12`
        pub struct ODR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ODR11`
        pub type ODR11_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR11`
        pub struct ODR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ODR10`
        pub type ODR10_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR10`
        pub struct ODR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `ODR9`
        pub type ODR9_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR9`
        pub struct ODR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `ODR8`
        pub type ODR8_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR8`
        pub struct ODR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `ODR7`
        pub type ODR7_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR7`
        pub struct ODR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ODR6`
        pub type ODR6_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR6`
        pub struct ODR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `ODR5`
        pub type ODR5_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR5`
        pub struct ODR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `ODR4`
        pub type ODR4_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR4`
        pub struct ODR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `ODR3`
        pub type ODR3_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR3`
        pub struct ODR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ODR2`
        pub type ODR2_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR2`
        pub struct ODR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ODR1`
        pub type ODR1_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR1`
        pub struct ODR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ODR0`
        pub type ODR0_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR0`
        pub struct ODR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr15(&self) -> ODR15_R {
                ODR15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr14(&self) -> ODR14_R {
                ODR14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr13(&self) -> ODR13_R {
                ODR13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr12(&self) -> ODR12_R {
                ODR12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr11(&self) -> ODR11_R {
                ODR11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr10(&self) -> ODR10_R {
                ODR10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr9(&self) -> ODR9_R {
                ODR9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr8(&self) -> ODR8_R {
                ODR8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr7(&self) -> ODR7_R {
                ODR7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr6(&self) -> ODR6_R {
                ODR6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr5(&self) -> ODR5_R {
                ODR5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&self) -> ODR4_R {
                ODR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&self) -> ODR3_R {
                ODR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&self) -> ODR2_R {
                ODR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&self) -> ODR1_R {
                ODR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&self) -> ODR0_R {
                ODR0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr15(&mut self) -> ODR15_W {
                ODR15_W { w: self }
            }
            ///Bit 14 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr14(&mut self) -> ODR14_W {
                ODR14_W { w: self }
            }
            ///Bit 13 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr13(&mut self) -> ODR13_W {
                ODR13_W { w: self }
            }
            ///Bit 12 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr12(&mut self) -> ODR12_W {
                ODR12_W { w: self }
            }
            ///Bit 11 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr11(&mut self) -> ODR11_W {
                ODR11_W { w: self }
            }
            ///Bit 10 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr10(&mut self) -> ODR10_W {
                ODR10_W { w: self }
            }
            ///Bit 9 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr9(&mut self) -> ODR9_W {
                ODR9_W { w: self }
            }
            ///Bit 8 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr8(&mut self) -> ODR8_W {
                ODR8_W { w: self }
            }
            ///Bit 7 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr7(&mut self) -> ODR7_W {
                ODR7_W { w: self }
            }
            ///Bit 6 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr6(&mut self) -> ODR6_W {
                ODR6_W { w: self }
            }
            ///Bit 5 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr5(&mut self) -> ODR5_W {
                ODR5_W { w: self }
            }
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&mut self) -> ODR4_W {
                ODR4_W { w: self }
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&mut self) -> ODR3_W {
                ODR3_W { w: self }
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&mut self) -> ODR2_W {
                ODR2_W { w: self }
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&mut self) -> ODR1_W {
                ODR1_W { w: self }
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&mut self) -> ODR0_W {
                ODR0_W { w: self }
            }
        }
    }
    ///GPIO port bit set/reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bsrr](bsrr) module
    pub type BSRR = crate::Reg<u32, _BSRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BSRR;
    ///`write(|w| ..)` method takes [bsrr::W](bsrr::W) writer structure
    impl crate::Writable for BSRR {}
    ///GPIO port bit set/reset register
    pub mod bsrr {
        ///Writer for register BSRR
        pub type W = crate::W<u32, super::BSRR>;
        ///Register BSRR `reset()`'s with value 0
        impl crate::ResetValue for super::BSRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR15`
        pub struct BR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Write proxy for field `BR14`
        pub struct BR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Write proxy for field `BR13`
        pub struct BR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Write proxy for field `BR12`
        pub struct BR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Write proxy for field `BR11`
        pub struct BR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Write proxy for field `BR10`
        pub struct BR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Write proxy for field `BR9`
        pub struct BR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Write proxy for field `BR8`
        pub struct BR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Write proxy for field `BR7`
        pub struct BR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Write proxy for field `BR6`
        pub struct BR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Write proxy for field `BR5`
        pub struct BR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `BS15`
        pub struct BS15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Write proxy for field `BS14`
        pub struct BS14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `BS13`
        pub struct BS13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `BS12`
        pub struct BS12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `BS11`
        pub struct BS11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `BS10`
        pub struct BS10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `BS9`
        pub struct BS9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `BS8`
        pub struct BS8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `BS7`
        pub struct BS7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `BS6`
        pub struct BS6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `BS5`
        pub struct BS5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `BS4`
        pub struct BS4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `BS3`
        pub struct BS3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BS2`
        pub struct BS2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BS1`
        pub struct BS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BS0`
        pub struct BS0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 31 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br15(&mut self) -> BR15_W {
                BR15_W { w: self }
            }
            ///Bit 30 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br14(&mut self) -> BR14_W {
                BR14_W { w: self }
            }
            ///Bit 29 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br13(&mut self) -> BR13_W {
                BR13_W { w: self }
            }
            ///Bit 28 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br12(&mut self) -> BR12_W {
                BR12_W { w: self }
            }
            ///Bit 27 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br11(&mut self) -> BR11_W {
                BR11_W { w: self }
            }
            ///Bit 26 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br10(&mut self) -> BR10_W {
                BR10_W { w: self }
            }
            ///Bit 25 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br9(&mut self) -> BR9_W {
                BR9_W { w: self }
            }
            ///Bit 24 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br8(&mut self) -> BR8_W {
                BR8_W { w: self }
            }
            ///Bit 23 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br7(&mut self) -> BR7_W {
                BR7_W { w: self }
            }
            ///Bit 22 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br6(&mut self) -> BR6_W {
                BR6_W { w: self }
            }
            ///Bit 21 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br5(&mut self) -> BR5_W {
                BR5_W { w: self }
            }
            ///Bit 20 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
            ///Bit 19 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 18 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 17 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 16 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 15 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs15(&mut self) -> BS15_W {
                BS15_W { w: self }
            }
            ///Bit 14 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs14(&mut self) -> BS14_W {
                BS14_W { w: self }
            }
            ///Bit 13 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs13(&mut self) -> BS13_W {
                BS13_W { w: self }
            }
            ///Bit 12 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs12(&mut self) -> BS12_W {
                BS12_W { w: self }
            }
            ///Bit 11 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs11(&mut self) -> BS11_W {
                BS11_W { w: self }
            }
            ///Bit 10 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs10(&mut self) -> BS10_W {
                BS10_W { w: self }
            }
            ///Bit 9 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs9(&mut self) -> BS9_W {
                BS9_W { w: self }
            }
            ///Bit 8 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs8(&mut self) -> BS8_W {
                BS8_W { w: self }
            }
            ///Bit 7 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs7(&mut self) -> BS7_W {
                BS7_W { w: self }
            }
            ///Bit 6 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs6(&mut self) -> BS6_W {
                BS6_W { w: self }
            }
            ///Bit 5 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs5(&mut self) -> BS5_W {
                BS5_W { w: self }
            }
            ///Bit 4 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs4(&mut self) -> BS4_W {
                BS4_W { w: self }
            }
            ///Bit 3 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs3(&mut self) -> BS3_W {
                BS3_W { w: self }
            }
            ///Bit 2 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs2(&mut self) -> BS2_W {
                BS2_W { w: self }
            }
            ///Bit 1 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs1(&mut self) -> BS1_W {
                BS1_W { w: self }
            }
            ///Bit 0 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs0(&mut self) -> BS0_W {
                BS0_W { w: self }
            }
        }
    }
    ///GPIO port configuration lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [lckr](lckr) module
    pub type LCKR = crate::Reg<u32, _LCKR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LCKR;
    ///`read()` method returns [lckr::R](lckr::R) reader structure
    impl crate::Readable for LCKR {}
    ///`write(|w| ..)` method takes [lckr::W](lckr::W) writer structure
    impl crate::Writable for LCKR {}
    ///GPIO port configuration lock register
    pub mod lckr {
        ///Reader of register LCKR
        pub type R = crate::R<u32, super::LCKR>;
        ///Writer for register LCKR
        pub type W = crate::W<u32, super::LCKR>;
        ///Register LCKR `reset()`'s with value 0
        impl crate::ResetValue for super::LCKR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LCKK`
        pub type LCKK_R = crate::R<bool, bool>;
        ///Write proxy for field `LCKK`
        pub struct LCKK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCKK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `LCK15`
        pub type LCK15_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK15`
        pub struct LCK15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `LCK14`
        pub type LCK14_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK14`
        pub struct LCK14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `LCK13`
        pub type LCK13_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK13`
        pub struct LCK13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `LCK12`
        pub type LCK12_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK12`
        pub struct LCK12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `LCK11`
        pub type LCK11_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK11`
        pub struct LCK11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `LCK10`
        pub type LCK10_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK10`
        pub struct LCK10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `LCK9`
        pub type LCK9_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK9`
        pub struct LCK9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `LCK8`
        pub type LCK8_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK8`
        pub struct LCK8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `LCK7`
        pub type LCK7_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK7`
        pub struct LCK7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `LCK6`
        pub type LCK6_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK6`
        pub struct LCK6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `LCK5`
        pub type LCK5_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK5`
        pub struct LCK5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `LCK4`
        pub type LCK4_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK4`
        pub struct LCK4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `LCK3`
        pub type LCK3_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK3`
        pub struct LCK3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `LCK2`
        pub type LCK2_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK2`
        pub struct LCK2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `LCK1`
        pub type LCK1_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK1`
        pub struct LCK1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LCK0`
        pub type LCK0_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK0`
        pub struct LCK0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&self) -> LCKK_R {
                LCKK_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck15(&self) -> LCK15_R {
                LCK15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck14(&self) -> LCK14_R {
                LCK14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck13(&self) -> LCK13_R {
                LCK13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck12(&self) -> LCK12_R {
                LCK12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck11(&self) -> LCK11_R {
                LCK11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck10(&self) -> LCK10_R {
                LCK10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck9(&self) -> LCK9_R {
                LCK9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck8(&self) -> LCK8_R {
                LCK8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck7(&self) -> LCK7_R {
                LCK7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck6(&self) -> LCK6_R {
                LCK6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck5(&self) -> LCK5_R {
                LCK5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&self) -> LCK4_R {
                LCK4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&self) -> LCK3_R {
                LCK3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&self) -> LCK2_R {
                LCK2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&self) -> LCK1_R {
                LCK1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&self) -> LCK0_R {
                LCK0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&mut self) -> LCKK_W {
                LCKK_W { w: self }
            }
            ///Bit 15 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck15(&mut self) -> LCK15_W {
                LCK15_W { w: self }
            }
            ///Bit 14 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck14(&mut self) -> LCK14_W {
                LCK14_W { w: self }
            }
            ///Bit 13 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck13(&mut self) -> LCK13_W {
                LCK13_W { w: self }
            }
            ///Bit 12 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck12(&mut self) -> LCK12_W {
                LCK12_W { w: self }
            }
            ///Bit 11 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck11(&mut self) -> LCK11_W {
                LCK11_W { w: self }
            }
            ///Bit 10 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck10(&mut self) -> LCK10_W {
                LCK10_W { w: self }
            }
            ///Bit 9 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck9(&mut self) -> LCK9_W {
                LCK9_W { w: self }
            }
            ///Bit 8 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck8(&mut self) -> LCK8_W {
                LCK8_W { w: self }
            }
            ///Bit 7 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck7(&mut self) -> LCK7_W {
                LCK7_W { w: self }
            }
            ///Bit 6 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck6(&mut self) -> LCK6_W {
                LCK6_W { w: self }
            }
            ///Bit 5 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck5(&mut self) -> LCK5_W {
                LCK5_W { w: self }
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&mut self) -> LCK4_W {
                LCK4_W { w: self }
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&mut self) -> LCK3_W {
                LCK3_W { w: self }
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&mut self) -> LCK2_W {
                LCK2_W { w: self }
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&mut self) -> LCK1_W {
                LCK1_W { w: self }
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&mut self) -> LCK0_W {
                LCK0_W { w: self }
            }
        }
    }
    ///GPIO alternate function low register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrl](afrl) module
    pub type AFRL = crate::Reg<u32, _AFRL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRL;
    ///`read()` method returns [afrl::R](afrl::R) reader structure
    impl crate::Readable for AFRL {}
    ///`write(|w| ..)` method takes [afrl::W](afrl::W) writer structure
    impl crate::Writable for AFRL {}
    ///GPIO alternate function low register
    pub mod afrl {
        ///Reader of register AFRL
        pub type R = crate::R<u32, super::AFRL>;
        ///Writer for register AFRL
        pub type W = crate::W<u32, super::AFRL>;
        ///Register AFRL `reset()`'s with value 0
        impl crate::ResetValue for super::AFRL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL7`
        pub type AFSEL7_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL7`
        pub struct AFSEL7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL6`
        pub type AFSEL6_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL6`
        pub struct AFSEL6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL5`
        pub type AFSEL5_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL5`
        pub struct AFSEL5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL4`
        pub type AFSEL4_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL4`
        pub struct AFSEL4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL3`
        pub type AFSEL3_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL3`
        pub struct AFSEL3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL2`
        pub type AFSEL2_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL2`
        pub struct AFSEL2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL1`
        pub type AFSEL1_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL1`
        pub struct AFSEL1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL0`
        pub type AFSEL0_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL0`
        pub struct AFSEL0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel7(&self) -> AFSEL7_R {
                AFSEL7_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel6(&self) -> AFSEL6_R {
                AFSEL6_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel5(&self) -> AFSEL5_R {
                AFSEL5_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&self) -> AFSEL4_R {
                AFSEL4_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&self) -> AFSEL3_R {
                AFSEL3_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&self) -> AFSEL2_R {
                AFSEL2_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&self) -> AFSEL1_R {
                AFSEL1_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&self) -> AFSEL0_R {
                AFSEL0_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel7(&mut self) -> AFSEL7_W {
                AFSEL7_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel6(&mut self) -> AFSEL6_W {
                AFSEL6_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel5(&mut self) -> AFSEL5_W {
                AFSEL5_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&mut self) -> AFSEL4_W {
                AFSEL4_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&mut self) -> AFSEL3_W {
                AFSEL3_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&mut self) -> AFSEL2_W {
                AFSEL2_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&mut self) -> AFSEL1_W {
                AFSEL1_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&mut self) -> AFSEL0_W {
                AFSEL0_W { w: self }
            }
        }
    }
    ///GPIO alternate function high register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrh](afrh) module
    pub type AFRH = crate::Reg<u32, _AFRH>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRH;
    ///`read()` method returns [afrh::R](afrh::R) reader structure
    impl crate::Readable for AFRH {}
    ///`write(|w| ..)` method takes [afrh::W](afrh::W) writer structure
    impl crate::Writable for AFRH {}
    ///GPIO alternate function high register
    pub mod afrh {
        ///Reader of register AFRH
        pub type R = crate::R<u32, super::AFRH>;
        ///Writer for register AFRH
        pub type W = crate::W<u32, super::AFRH>;
        ///Register AFRH `reset()`'s with value 0
        impl crate::ResetValue for super::AFRH {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL15`
        pub type AFSEL15_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL15`
        pub struct AFSEL15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL14`
        pub type AFSEL14_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL14`
        pub struct AFSEL14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL13`
        pub type AFSEL13_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL13`
        pub struct AFSEL13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL12`
        pub type AFSEL12_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL12`
        pub struct AFSEL12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL11`
        pub type AFSEL11_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL11`
        pub struct AFSEL11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL10`
        pub type AFSEL10_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL10`
        pub struct AFSEL10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL9`
        pub type AFSEL9_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL9`
        pub struct AFSEL9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL8`
        pub type AFSEL8_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL8`
        pub struct AFSEL8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&self) -> AFSEL15_R {
                AFSEL15_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&self) -> AFSEL14_R {
                AFSEL14_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&self) -> AFSEL13_R {
                AFSEL13_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&self) -> AFSEL12_R {
                AFSEL12_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&self) -> AFSEL11_R {
                AFSEL11_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&self) -> AFSEL10_R {
                AFSEL10_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&self) -> AFSEL9_R {
                AFSEL9_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&self) -> AFSEL8_R {
                AFSEL8_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&mut self) -> AFSEL15_W {
                AFSEL15_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&mut self) -> AFSEL14_W {
                AFSEL14_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&mut self) -> AFSEL13_W {
                AFSEL13_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&mut self) -> AFSEL12_W {
                AFSEL12_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&mut self) -> AFSEL11_W {
                AFSEL11_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&mut self) -> AFSEL10_W {
                AFSEL10_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&mut self) -> AFSEL9_W {
                AFSEL9_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&mut self) -> AFSEL8_W {
                AFSEL8_W { w: self }
            }
        }
    }
    ///port bit reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [brr](brr) module
    pub type BRR = crate::Reg<u32, _BRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BRR;
    ///`write(|w| ..)` method takes [brr::W](brr::W) writer structure
    impl crate::Writable for BRR {}
    ///port bit reset register
    pub mod brr {
        ///Writer for register BRR
        pub type W = crate::W<u32, super::BRR>;
        ///Register BRR `reset()`'s with value 0
        impl crate::ResetValue for super::BRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `BR5`
        pub struct BR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `BR6`
        pub struct BR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `BR7`
        pub struct BR7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `BR8`
        pub struct BR8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `BR9`
        pub struct BR9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `BR10`
        pub struct BR10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Write proxy for field `BR11`
        pub struct BR11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `BR12`
        pub struct BR12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `BR13`
        pub struct BR13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `BR14`
        pub struct BR14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Write proxy for field `BR15`
        pub struct BR15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        impl W {
            ///Bit 0 - Port Reset bit
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 1 - Port Reset bit
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 2 - Port Reset bit
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 3 - Port Reset bit
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 4 - Port Reset bit
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
            ///Bit 5 - Port Reset bit
            #[inline(always)]
            pub fn br5(&mut self) -> BR5_W {
                BR5_W { w: self }
            }
            ///Bit 6 - Port Reset bit
            #[inline(always)]
            pub fn br6(&mut self) -> BR6_W {
                BR6_W { w: self }
            }
            ///Bit 7 - Port Reset bit
            #[inline(always)]
            pub fn br7(&mut self) -> BR7_W {
                BR7_W { w: self }
            }
            ///Bit 8 - Port Reset bit
            #[inline(always)]
            pub fn br8(&mut self) -> BR8_W {
                BR8_W { w: self }
            }
            ///Bit 9 - Port Reset bit
            #[inline(always)]
            pub fn br9(&mut self) -> BR9_W {
                BR9_W { w: self }
            }
            ///Bit 10 - Port Reset bit
            #[inline(always)]
            pub fn br10(&mut self) -> BR10_W {
                BR10_W { w: self }
            }
            ///Bit 11 - Port Reset bit
            #[inline(always)]
            pub fn br11(&mut self) -> BR11_W {
                BR11_W { w: self }
            }
            ///Bit 12 - Port Reset bit
            #[inline(always)]
            pub fn br12(&mut self) -> BR12_W {
                BR12_W { w: self }
            }
            ///Bit 13 - Port Reset bit
            #[inline(always)]
            pub fn br13(&mut self) -> BR13_W {
                BR13_W { w: self }
            }
            ///Bit 14 - Port Reset bit
            #[inline(always)]
            pub fn br14(&mut self) -> BR14_W {
                BR14_W { w: self }
            }
            ///Bit 15 - Port Reset bit
            #[inline(always)]
            pub fn br15(&mut self) -> BR15_W {
                BR15_W { w: self }
            }
        }
    }
}
///General-purpose I/Os
pub struct GPIOD {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOD {}
impl GPIOD {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const gpioc::RegisterBlock {
        0x4800_0c00 as *const _
    }
}
impl Deref for GPIOD {
    type Target = gpioc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*GPIOD::ptr() }
    }
}
///General-purpose I/Os
pub struct GPIOE {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOE {}
impl GPIOE {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const gpioe::RegisterBlock {
        0x4800_1000 as *const _
    }
}
impl Deref for GPIOE {
    type Target = gpioe::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*GPIOE::ptr() }
    }
}
///General-purpose I/Os
pub mod gpioe {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - GPIO port mode register
        pub moder: MODER,
        ///0x04 - GPIO port output type register
        pub otyper: OTYPER,
        ///0x08 - GPIO port output speed register
        pub ospeedr: OSPEEDR,
        ///0x0c - GPIO port pull-up/pull-down register
        pub pupdr: PUPDR,
        ///0x10 - GPIO port input data register
        pub idr: IDR,
        ///0x14 - GPIO port output data register
        pub odr: ODR,
        ///0x18 - GPIO port bit set/reset register
        pub bsrr: BSRR,
        ///0x1c - GPIO port configuration lock register
        pub lckr: LCKR,
        ///0x20 - GPIO alternate function low register
        pub afrl: AFRL,
        ///0x24 - GPIO alternate function high register
        pub afrh: AFRH,
        ///0x28 - port bit reset register
        pub brr: BRR,
    }
    ///GPIO port mode register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [moder](moder) module
    pub type MODER = crate::Reg<u32, _MODER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _MODER;
    ///`read()` method returns [moder::R](moder::R) reader structure
    impl crate::Readable for MODER {}
    ///`write(|w| ..)` method takes [moder::W](moder::W) writer structure
    impl crate::Writable for MODER {}
    ///GPIO port mode register
    pub mod moder {
        ///Reader of register MODER
        pub type R = crate::R<u32, super::MODER>;
        ///Writer for register MODER
        pub type W = crate::W<u32, super::MODER>;
        ///Register MODER `reset()`'s with value 0x03ff
        impl crate::ResetValue for super::MODER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x03ff
            }
        }
        ///Reader of field `MODER4`
        pub type MODER4_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER4`
        pub struct MODER4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `MODER3`
        pub type MODER3_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER3`
        pub struct MODER3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `MODER2`
        pub type MODER2_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER2`
        pub struct MODER2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `MODER1`
        pub type MODER1_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER1`
        pub struct MODER1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `MODER0`
        pub type MODER0_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER0`
        pub struct MODER0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&self) -> MODER4_R {
                MODER4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&self) -> MODER3_R {
                MODER3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&self) -> MODER2_R {
                MODER2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&self) -> MODER1_R {
                MODER1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&self) -> MODER0_R {
                MODER0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder4(&mut self) -> MODER4_W {
                MODER4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&mut self) -> MODER3_W {
                MODER3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder2(&mut self) -> MODER2_W {
                MODER2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&mut self) -> MODER1_W {
                MODER1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&mut self) -> MODER0_W {
                MODER0_W { w: self }
            }
        }
    }
    ///GPIO port output type register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [otyper](otyper) module
    pub type OTYPER = crate::Reg<u32, _OTYPER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OTYPER;
    ///`read()` method returns [otyper::R](otyper::R) reader structure
    impl crate::Readable for OTYPER {}
    ///`write(|w| ..)` method takes [otyper::W](otyper::W) writer structure
    impl crate::Writable for OTYPER {}
    ///GPIO port output type register
    pub mod otyper {
        ///Reader of register OTYPER
        pub type R = crate::R<u32, super::OTYPER>;
        ///Writer for register OTYPER
        pub type W = crate::W<u32, super::OTYPER>;
        ///Register OTYPER `reset()`'s with value 0
        impl crate::ResetValue for super::OTYPER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OT4`
        pub type OT4_R = crate::R<bool, bool>;
        ///Write proxy for field `OT4`
        pub struct OT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `OT3`
        pub type OT3_R = crate::R<bool, bool>;
        ///Write proxy for field `OT3`
        pub struct OT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OT2`
        pub type OT2_R = crate::R<bool, bool>;
        ///Write proxy for field `OT2`
        pub struct OT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OT1`
        pub type OT1_R = crate::R<bool, bool>;
        ///Write proxy for field `OT1`
        pub struct OT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `OT0`
        pub type OT0_R = crate::R<bool, bool>;
        ///Write proxy for field `OT0`
        pub struct OT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&self) -> OT4_R {
                OT4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&self) -> OT3_R {
                OT3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&self) -> OT2_R {
                OT2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&self) -> OT1_R {
                OT1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&self) -> OT0_R {
                OT0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 4 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot4(&mut self) -> OT4_W {
                OT4_W { w: self }
            }
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&mut self) -> OT3_W {
                OT3_W { w: self }
            }
            ///Bit 2 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot2(&mut self) -> OT2_W {
                OT2_W { w: self }
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&mut self) -> OT1_W {
                OT1_W { w: self }
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&mut self) -> OT0_W {
                OT0_W { w: self }
            }
        }
    }
    ///GPIO port output speed register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ospeedr](ospeedr) module
    pub type OSPEEDR = crate::Reg<u32, _OSPEEDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OSPEEDR;
    ///`read()` method returns [ospeedr::R](ospeedr::R) reader structure
    impl crate::Readable for OSPEEDR {}
    ///`write(|w| ..)` method takes [ospeedr::W](ospeedr::W) writer structure
    impl crate::Writable for OSPEEDR {}
    ///GPIO port output speed register
    pub mod ospeedr {
        ///Reader of register OSPEEDR
        pub type R = crate::R<u32, super::OSPEEDR>;
        ///Writer for register OSPEEDR
        pub type W = crate::W<u32, super::OSPEEDR>;
        ///Register OSPEEDR `reset()`'s with value 0xc0
        impl crate::ResetValue for super::OSPEEDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xc0
            }
        }
        ///Reader of field `OSPEEDR4`
        pub type OSPEEDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR4`
        pub struct OSPEEDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OSPEEDR3`
        pub type OSPEEDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR3`
        pub struct OSPEEDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `OSPEEDR2`
        pub type OSPEEDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR2`
        pub struct OSPEEDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `OSPEEDR1`
        pub type OSPEEDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR1`
        pub struct OSPEEDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `OSPEEDR0`
        pub type OSPEEDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR0`
        pub struct OSPEEDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&self) -> OSPEEDR4_R {
                OSPEEDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&self) -> OSPEEDR3_R {
                OSPEEDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&self) -> OSPEEDR2_R {
                OSPEEDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&self) -> OSPEEDR1_R {
                OSPEEDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&self) -> OSPEEDR0_R {
                OSPEEDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr4(&mut self) -> OSPEEDR4_W {
                OSPEEDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&mut self) -> OSPEEDR3_W {
                OSPEEDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr2(&mut self) -> OSPEEDR2_W {
                OSPEEDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&mut self) -> OSPEEDR1_W {
                OSPEEDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&mut self) -> OSPEEDR0_W {
                OSPEEDR0_W { w: self }
            }
        }
    }
    ///GPIO port pull-up/pull-down register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pupdr](pupdr) module
    pub type PUPDR = crate::Reg<u32, _PUPDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUPDR;
    ///`read()` method returns [pupdr::R](pupdr::R) reader structure
    impl crate::Readable for PUPDR {}
    ///`write(|w| ..)` method takes [pupdr::W](pupdr::W) writer structure
    impl crate::Writable for PUPDR {}
    ///GPIO port pull-up/pull-down register
    pub mod pupdr {
        ///Reader of register PUPDR
        pub type R = crate::R<u32, super::PUPDR>;
        ///Writer for register PUPDR
        pub type W = crate::W<u32, super::PUPDR>;
        ///Register PUPDR `reset()`'s with value 0
        impl crate::ResetValue for super::PUPDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PUPDR4`
        pub type PUPDR4_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR4`
        pub struct PUPDR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `PUPDR3`
        pub type PUPDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR3`
        pub struct PUPDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `PUPDR2`
        pub type PUPDR2_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR2`
        pub struct PUPDR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `PUPDR1`
        pub type PUPDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR1`
        pub struct PUPDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `PUPDR0`
        pub type PUPDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR0`
        pub struct PUPDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&self) -> PUPDR4_R {
                PUPDR4_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&self) -> PUPDR3_R {
                PUPDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&self) -> PUPDR2_R {
                PUPDR2_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&self) -> PUPDR1_R {
                PUPDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&self) -> PUPDR0_R {
                PUPDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 8:9 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr4(&mut self) -> PUPDR4_W {
                PUPDR4_W { w: self }
            }
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&mut self) -> PUPDR3_W {
                PUPDR3_W { w: self }
            }
            ///Bits 4:5 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr2(&mut self) -> PUPDR2_W {
                PUPDR2_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&mut self) -> PUPDR1_W {
                PUPDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&mut self) -> PUPDR0_W {
                PUPDR0_W { w: self }
            }
        }
    }
    ///GPIO port input data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [idr](idr) module
    pub type IDR = crate::Reg<u32, _IDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IDR;
    ///`read()` method returns [idr::R](idr::R) reader structure
    impl crate::Readable for IDR {}
    ///GPIO port input data register
    pub mod idr {
        ///Reader of register IDR
        pub type R = crate::R<u32, super::IDR>;
        ///Reader of field `IDR4`
        pub type IDR4_R = crate::R<bool, bool>;
        ///Reader of field `IDR3`
        pub type IDR3_R = crate::R<bool, bool>;
        ///Reader of field `IDR2`
        pub type IDR2_R = crate::R<bool, bool>;
        ///Reader of field `IDR1`
        pub type IDR1_R = crate::R<bool, bool>;
        ///Reader of field `IDR0`
        pub type IDR0_R = crate::R<bool, bool>;
        impl R {
            ///Bit 4 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr4(&self) -> IDR4_R {
                IDR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr3(&self) -> IDR3_R {
                IDR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr2(&self) -> IDR2_R {
                IDR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr1(&self) -> IDR1_R {
                IDR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr0(&self) -> IDR0_R {
                IDR0_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///GPIO port output data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [odr](odr) module
    pub type ODR = crate::Reg<u32, _ODR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ODR;
    ///`read()` method returns [odr::R](odr::R) reader structure
    impl crate::Readable for ODR {}
    ///`write(|w| ..)` method takes [odr::W](odr::W) writer structure
    impl crate::Writable for ODR {}
    ///GPIO port output data register
    pub mod odr {
        ///Reader of register ODR
        pub type R = crate::R<u32, super::ODR>;
        ///Writer for register ODR
        pub type W = crate::W<u32, super::ODR>;
        ///Register ODR `reset()`'s with value 0
        impl crate::ResetValue for super::ODR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ODR4`
        pub type ODR4_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR4`
        pub struct ODR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `ODR3`
        pub type ODR3_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR3`
        pub struct ODR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ODR2`
        pub type ODR2_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR2`
        pub struct ODR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ODR1`
        pub type ODR1_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR1`
        pub struct ODR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ODR0`
        pub type ODR0_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR0`
        pub struct ODR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&self) -> ODR4_R {
                ODR4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&self) -> ODR3_R {
                ODR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&self) -> ODR2_R {
                ODR2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&self) -> ODR1_R {
                ODR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&self) -> ODR0_R {
                ODR0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 4 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr4(&mut self) -> ODR4_W {
                ODR4_W { w: self }
            }
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&mut self) -> ODR3_W {
                ODR3_W { w: self }
            }
            ///Bit 2 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr2(&mut self) -> ODR2_W {
                ODR2_W { w: self }
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&mut self) -> ODR1_W {
                ODR1_W { w: self }
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&mut self) -> ODR0_W {
                ODR0_W { w: self }
            }
        }
    }
    ///GPIO port bit set/reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bsrr](bsrr) module
    pub type BSRR = crate::Reg<u32, _BSRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BSRR;
    ///`write(|w| ..)` method takes [bsrr::W](bsrr::W) writer structure
    impl crate::Writable for BSRR {}
    ///GPIO port bit set/reset register
    pub mod bsrr {
        ///Writer for register BSRR
        pub type W = crate::W<u32, super::BSRR>;
        ///Register BSRR `reset()`'s with value 0
        impl crate::ResetValue for super::BSRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `BS4`
        pub struct BS4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `BS3`
        pub struct BS3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BS2`
        pub struct BS2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BS1`
        pub struct BS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BS0`
        pub struct BS0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 20 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
            ///Bit 19 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 18 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 17 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 16 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 4 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs4(&mut self) -> BS4_W {
                BS4_W { w: self }
            }
            ///Bit 3 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs3(&mut self) -> BS3_W {
                BS3_W { w: self }
            }
            ///Bit 2 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs2(&mut self) -> BS2_W {
                BS2_W { w: self }
            }
            ///Bit 1 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs1(&mut self) -> BS1_W {
                BS1_W { w: self }
            }
            ///Bit 0 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs0(&mut self) -> BS0_W {
                BS0_W { w: self }
            }
        }
    }
    ///GPIO port configuration lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [lckr](lckr) module
    pub type LCKR = crate::Reg<u32, _LCKR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LCKR;
    ///`read()` method returns [lckr::R](lckr::R) reader structure
    impl crate::Readable for LCKR {}
    ///`write(|w| ..)` method takes [lckr::W](lckr::W) writer structure
    impl crate::Writable for LCKR {}
    ///GPIO port configuration lock register
    pub mod lckr {
        ///Reader of register LCKR
        pub type R = crate::R<u32, super::LCKR>;
        ///Writer for register LCKR
        pub type W = crate::W<u32, super::LCKR>;
        ///Register LCKR `reset()`'s with value 0
        impl crate::ResetValue for super::LCKR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LCKK`
        pub type LCKK_R = crate::R<bool, bool>;
        ///Write proxy for field `LCKK`
        pub struct LCKK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCKK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `LCK4`
        pub type LCK4_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK4`
        pub struct LCK4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `LCK3`
        pub type LCK3_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK3`
        pub struct LCK3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `LCK2`
        pub type LCK2_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK2`
        pub struct LCK2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `LCK1`
        pub type LCK1_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK1`
        pub struct LCK1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LCK0`
        pub type LCK0_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK0`
        pub struct LCK0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&self) -> LCKK_R {
                LCKK_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&self) -> LCK4_R {
                LCK4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&self) -> LCK3_R {
                LCK3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&self) -> LCK2_R {
                LCK2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&self) -> LCK1_R {
                LCK1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&self) -> LCK0_R {
                LCK0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&mut self) -> LCKK_W {
                LCKK_W { w: self }
            }
            ///Bit 4 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck4(&mut self) -> LCK4_W {
                LCK4_W { w: self }
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&mut self) -> LCK3_W {
                LCK3_W { w: self }
            }
            ///Bit 2 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck2(&mut self) -> LCK2_W {
                LCK2_W { w: self }
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&mut self) -> LCK1_W {
                LCK1_W { w: self }
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&mut self) -> LCK0_W {
                LCK0_W { w: self }
            }
        }
    }
    ///GPIO alternate function low register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrl](afrl) module
    pub type AFRL = crate::Reg<u32, _AFRL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRL;
    ///`read()` method returns [afrl::R](afrl::R) reader structure
    impl crate::Readable for AFRL {}
    ///`write(|w| ..)` method takes [afrl::W](afrl::W) writer structure
    impl crate::Writable for AFRL {}
    ///GPIO alternate function low register
    pub mod afrl {
        ///Reader of register AFRL
        pub type R = crate::R<u32, super::AFRL>;
        ///Writer for register AFRL
        pub type W = crate::W<u32, super::AFRL>;
        ///Register AFRL `reset()`'s with value 0
        impl crate::ResetValue for super::AFRL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL4`
        pub type AFSEL4_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL4`
        pub struct AFSEL4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL3`
        pub type AFSEL3_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL3`
        pub struct AFSEL3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL2`
        pub type AFSEL2_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL2`
        pub struct AFSEL2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL1`
        pub type AFSEL1_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL1`
        pub struct AFSEL1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL0`
        pub type AFSEL0_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL0`
        pub struct AFSEL0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&self) -> AFSEL4_R {
                AFSEL4_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&self) -> AFSEL3_R {
                AFSEL3_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&self) -> AFSEL2_R {
                AFSEL2_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&self) -> AFSEL1_R {
                AFSEL1_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&self) -> AFSEL0_R {
                AFSEL0_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel4(&mut self) -> AFSEL4_W {
                AFSEL4_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&mut self) -> AFSEL3_W {
                AFSEL3_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel2(&mut self) -> AFSEL2_W {
                AFSEL2_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&mut self) -> AFSEL1_W {
                AFSEL1_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&mut self) -> AFSEL0_W {
                AFSEL0_W { w: self }
            }
        }
    }
    ///GPIO alternate function high register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrh](afrh) module
    pub type AFRH = crate::Reg<u32, _AFRH>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRH;
    ///`read()` method returns [afrh::R](afrh::R) reader structure
    impl crate::Readable for AFRH {}
    ///`write(|w| ..)` method takes [afrh::W](afrh::W) writer structure
    impl crate::Writable for AFRH {}
    ///GPIO alternate function high register
    pub mod afrh {
        ///Reader of register AFRH
        pub type R = crate::R<u32, super::AFRH>;
        ///Writer for register AFRH
        pub type W = crate::W<u32, super::AFRH>;
        ///Register AFRH `reset()`'s with value 0
        impl crate::ResetValue for super::AFRH {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL15`
        pub type AFSEL15_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL15`
        pub struct AFSEL15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL14`
        pub type AFSEL14_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL14`
        pub struct AFSEL14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL13`
        pub type AFSEL13_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL13`
        pub struct AFSEL13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL12`
        pub type AFSEL12_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL12`
        pub struct AFSEL12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL11`
        pub type AFSEL11_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL11`
        pub struct AFSEL11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL10`
        pub type AFSEL10_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL10`
        pub struct AFSEL10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL9`
        pub type AFSEL9_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL9`
        pub struct AFSEL9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL8`
        pub type AFSEL8_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL8`
        pub struct AFSEL8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&self) -> AFSEL15_R {
                AFSEL15_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&self) -> AFSEL14_R {
                AFSEL14_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&self) -> AFSEL13_R {
                AFSEL13_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&self) -> AFSEL12_R {
                AFSEL12_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&self) -> AFSEL11_R {
                AFSEL11_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&self) -> AFSEL10_R {
                AFSEL10_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&self) -> AFSEL9_R {
                AFSEL9_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&self) -> AFSEL8_R {
                AFSEL8_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&mut self) -> AFSEL15_W {
                AFSEL15_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&mut self) -> AFSEL14_W {
                AFSEL14_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&mut self) -> AFSEL13_W {
                AFSEL13_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&mut self) -> AFSEL12_W {
                AFSEL12_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&mut self) -> AFSEL11_W {
                AFSEL11_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&mut self) -> AFSEL10_W {
                AFSEL10_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&mut self) -> AFSEL9_W {
                AFSEL9_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&mut self) -> AFSEL8_W {
                AFSEL8_W { w: self }
            }
        }
    }
    ///port bit reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [brr](brr) module
    pub type BRR = crate::Reg<u32, _BRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BRR;
    ///`write(|w| ..)` method takes [brr::W](brr::W) writer structure
    impl crate::Writable for BRR {}
    ///port bit reset register
    pub mod brr {
        ///Writer for register BRR
        pub type W = crate::W<u32, super::BRR>;
        ///Register BRR `reset()`'s with value 0
        impl crate::ResetValue for super::BRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BR2`
        pub struct BR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BR4`
        pub struct BR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        impl W {
            ///Bit 0 - Port Reset bit
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 1 - Port Reset bit
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 2 - Port Reset bit
            #[inline(always)]
            pub fn br2(&mut self) -> BR2_W {
                BR2_W { w: self }
            }
            ///Bit 3 - Port Reset bit
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 4 - Port Reset bit
            #[inline(always)]
            pub fn br4(&mut self) -> BR4_W {
                BR4_W { w: self }
            }
        }
    }
}
///General-purpose I/Os
pub struct GPIOH {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOH {}
impl GPIOH {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const gpioh::RegisterBlock {
        0x4800_1c00 as *const _
    }
}
impl Deref for GPIOH {
    type Target = gpioh::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*GPIOH::ptr() }
    }
}
///General-purpose I/Os
pub mod gpioh {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - GPIO port mode register
        pub moder: MODER,
        ///0x04 - GPIO port output type register
        pub otyper: OTYPER,
        ///0x08 - GPIO port output speed register
        pub ospeedr: OSPEEDR,
        ///0x0c - GPIO port pull-up/pull-down register
        pub pupdr: PUPDR,
        ///0x10 - GPIO port input data register
        pub idr: IDR,
        ///0x14 - GPIO port output data register
        pub odr: ODR,
        ///0x18 - GPIO port bit set/reset register
        pub bsrr: BSRR,
        ///0x1c - GPIO port configuration lock register
        pub lckr: LCKR,
        ///0x20 - GPIO alternate function low register
        pub afrl: AFRL,
        ///0x24 - GPIO alternate function high register
        pub afrh: AFRH,
        ///0x28 - port bit reset register
        pub brr: BRR,
    }
    ///GPIO port mode register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [moder](moder) module
    pub type MODER = crate::Reg<u32, _MODER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _MODER;
    ///`read()` method returns [moder::R](moder::R) reader structure
    impl crate::Readable for MODER {}
    ///`write(|w| ..)` method takes [moder::W](moder::W) writer structure
    impl crate::Writable for MODER {}
    ///GPIO port mode register
    pub mod moder {
        ///Reader of register MODER
        pub type R = crate::R<u32, super::MODER>;
        ///Writer for register MODER
        pub type W = crate::W<u32, super::MODER>;
        ///Register MODER `reset()`'s with value 0xcf
        impl crate::ResetValue for super::MODER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xcf
            }
        }
        ///Reader of field `MODER3`
        pub type MODER3_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER3`
        pub struct MODER3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `MODER1`
        pub type MODER1_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER1`
        pub struct MODER1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `MODER0`
        pub type MODER0_R = crate::R<u8, u8>;
        ///Write proxy for field `MODER0`
        pub struct MODER0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODER0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&self) -> MODER3_R {
                MODER3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&self) -> MODER1_R {
                MODER1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&self) -> MODER0_R {
                MODER0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder3(&mut self) -> MODER3_W {
                MODER3_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder1(&mut self) -> MODER1_W {
                MODER1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn moder0(&mut self) -> MODER0_W {
                MODER0_W { w: self }
            }
        }
    }
    ///GPIO port output type register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [otyper](otyper) module
    pub type OTYPER = crate::Reg<u32, _OTYPER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OTYPER;
    ///`read()` method returns [otyper::R](otyper::R) reader structure
    impl crate::Readable for OTYPER {}
    ///`write(|w| ..)` method takes [otyper::W](otyper::W) writer structure
    impl crate::Writable for OTYPER {}
    ///GPIO port output type register
    pub mod otyper {
        ///Reader of register OTYPER
        pub type R = crate::R<u32, super::OTYPER>;
        ///Writer for register OTYPER
        pub type W = crate::W<u32, super::OTYPER>;
        ///Register OTYPER `reset()`'s with value 0
        impl crate::ResetValue for super::OTYPER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OT3`
        pub type OT3_R = crate::R<bool, bool>;
        ///Write proxy for field `OT3`
        pub struct OT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OT1`
        pub type OT1_R = crate::R<bool, bool>;
        ///Write proxy for field `OT1`
        pub struct OT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `OT0`
        pub type OT0_R = crate::R<bool, bool>;
        ///Write proxy for field `OT0`
        pub struct OT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&self) -> OT3_R {
                OT3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&self) -> OT1_R {
                OT1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&self) -> OT0_R {
                OT0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot3(&mut self) -> OT3_W {
                OT3_W { w: self }
            }
            ///Bit 1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot1(&mut self) -> OT1_W {
                OT1_W { w: self }
            }
            ///Bit 0 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ot0(&mut self) -> OT0_W {
                OT0_W { w: self }
            }
        }
    }
    ///GPIO port output speed register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ospeedr](ospeedr) module
    pub type OSPEEDR = crate::Reg<u32, _OSPEEDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OSPEEDR;
    ///`read()` method returns [ospeedr::R](ospeedr::R) reader structure
    impl crate::Readable for OSPEEDR {}
    ///`write(|w| ..)` method takes [ospeedr::W](ospeedr::W) writer structure
    impl crate::Writable for OSPEEDR {}
    ///GPIO port output speed register
    pub mod ospeedr {
        ///Reader of register OSPEEDR
        pub type R = crate::R<u32, super::OSPEEDR>;
        ///Writer for register OSPEEDR
        pub type W = crate::W<u32, super::OSPEEDR>;
        ///Register OSPEEDR `reset()`'s with value 0
        impl crate::ResetValue for super::OSPEEDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OSPEEDR3`
        pub type OSPEEDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR3`
        pub struct OSPEEDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `OSPEEDR1`
        pub type OSPEEDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR1`
        pub struct OSPEEDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `OSPEEDR0`
        pub type OSPEEDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `OSPEEDR0`
        pub struct OSPEEDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSPEEDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&self) -> OSPEEDR3_R {
                OSPEEDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&self) -> OSPEEDR1_R {
                OSPEEDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&self) -> OSPEEDR0_R {
                OSPEEDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr3(&mut self) -> OSPEEDR3_W {
                OSPEEDR3_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr1(&mut self) -> OSPEEDR1_W {
                OSPEEDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn ospeedr0(&mut self) -> OSPEEDR0_W {
                OSPEEDR0_W { w: self }
            }
        }
    }
    ///GPIO port pull-up/pull-down register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pupdr](pupdr) module
    pub type PUPDR = crate::Reg<u32, _PUPDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PUPDR;
    ///`read()` method returns [pupdr::R](pupdr::R) reader structure
    impl crate::Readable for PUPDR {}
    ///`write(|w| ..)` method takes [pupdr::W](pupdr::W) writer structure
    impl crate::Writable for PUPDR {}
    ///GPIO port pull-up/pull-down register
    pub mod pupdr {
        ///Reader of register PUPDR
        pub type R = crate::R<u32, super::PUPDR>;
        ///Writer for register PUPDR
        pub type W = crate::W<u32, super::PUPDR>;
        ///Register PUPDR `reset()`'s with value 0
        impl crate::ResetValue for super::PUPDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PUPDR3`
        pub type PUPDR3_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR3`
        pub struct PUPDR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `PUPDR1`
        pub type PUPDR1_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR1`
        pub struct PUPDR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `PUPDR0`
        pub type PUPDR0_R = crate::R<u8, u8>;
        ///Write proxy for field `PUPDR0`
        pub struct PUPDR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PUPDR0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&self) -> PUPDR3_R {
                PUPDR3_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&self) -> PUPDR1_R {
                PUPDR1_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&self) -> PUPDR0_R {
                PUPDR0_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 6:7 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr3(&mut self) -> PUPDR3_W {
                PUPDR3_W { w: self }
            }
            ///Bits 2:3 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr1(&mut self) -> PUPDR1_W {
                PUPDR1_W { w: self }
            }
            ///Bits 0:1 - Port x configuration bits (y = 0..15)
            #[inline(always)]
            pub fn pupdr0(&mut self) -> PUPDR0_W {
                PUPDR0_W { w: self }
            }
        }
    }
    ///GPIO port input data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [idr](idr) module
    pub type IDR = crate::Reg<u32, _IDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IDR;
    ///`read()` method returns [idr::R](idr::R) reader structure
    impl crate::Readable for IDR {}
    ///GPIO port input data register
    pub mod idr {
        ///Reader of register IDR
        pub type R = crate::R<u32, super::IDR>;
        ///Reader of field `IDR3`
        pub type IDR3_R = crate::R<bool, bool>;
        ///Reader of field `IDR1`
        pub type IDR1_R = crate::R<bool, bool>;
        ///Reader of field `IDR0`
        pub type IDR0_R = crate::R<bool, bool>;
        impl R {
            ///Bit 3 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr3(&self) -> IDR3_R {
                IDR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr1(&self) -> IDR1_R {
                IDR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port input data (y = 0..15)
            #[inline(always)]
            pub fn idr0(&self) -> IDR0_R {
                IDR0_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///GPIO port output data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [odr](odr) module
    pub type ODR = crate::Reg<u32, _ODR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ODR;
    ///`read()` method returns [odr::R](odr::R) reader structure
    impl crate::Readable for ODR {}
    ///`write(|w| ..)` method takes [odr::W](odr::W) writer structure
    impl crate::Writable for ODR {}
    ///GPIO port output data register
    pub mod odr {
        ///Reader of register ODR
        pub type R = crate::R<u32, super::ODR>;
        ///Writer for register ODR
        pub type W = crate::W<u32, super::ODR>;
        ///Register ODR `reset()`'s with value 0
        impl crate::ResetValue for super::ODR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ODR3`
        pub type ODR3_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR3`
        pub struct ODR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ODR1`
        pub type ODR1_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR1`
        pub struct ODR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ODR0`
        pub type ODR0_R = crate::R<bool, bool>;
        ///Write proxy for field `ODR0`
        pub struct ODR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ODR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&self) -> ODR3_R {
                ODR3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&self) -> ODR1_R {
                ODR1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&self) -> ODR0_R {
                ODR0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 3 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr3(&mut self) -> ODR3_W {
                ODR3_W { w: self }
            }
            ///Bit 1 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr1(&mut self) -> ODR1_W {
                ODR1_W { w: self }
            }
            ///Bit 0 - Port output data (y = 0..15)
            #[inline(always)]
            pub fn odr0(&mut self) -> ODR0_W {
                ODR0_W { w: self }
            }
        }
    }
    ///GPIO port bit set/reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bsrr](bsrr) module
    pub type BSRR = crate::Reg<u32, _BSRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BSRR;
    ///`write(|w| ..)` method takes [bsrr::W](bsrr::W) writer structure
    impl crate::Writable for BSRR {}
    ///GPIO port bit set/reset register
    pub mod bsrr {
        ///Writer for register BSRR
        pub type W = crate::W<u32, super::BSRR>;
        ///Register BSRR `reset()`'s with value 0
        impl crate::ResetValue for super::BSRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `BS3`
        pub struct BS3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `BS1`
        pub struct BS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BS0`
        pub struct BS0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BS0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 19 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
            ///Bit 17 - Port x reset bit y (y = 0..15)
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 16 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 3 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs3(&mut self) -> BS3_W {
                BS3_W { w: self }
            }
            ///Bit 1 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs1(&mut self) -> BS1_W {
                BS1_W { w: self }
            }
            ///Bit 0 - Port x set bit y (y= 0..15)
            #[inline(always)]
            pub fn bs0(&mut self) -> BS0_W {
                BS0_W { w: self }
            }
        }
    }
    ///GPIO port configuration lock register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [lckr](lckr) module
    pub type LCKR = crate::Reg<u32, _LCKR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LCKR;
    ///`read()` method returns [lckr::R](lckr::R) reader structure
    impl crate::Readable for LCKR {}
    ///`write(|w| ..)` method takes [lckr::W](lckr::W) writer structure
    impl crate::Writable for LCKR {}
    ///GPIO port configuration lock register
    pub mod lckr {
        ///Reader of register LCKR
        pub type R = crate::R<u32, super::LCKR>;
        ///Writer for register LCKR
        pub type W = crate::W<u32, super::LCKR>;
        ///Register LCKR `reset()`'s with value 0
        impl crate::ResetValue for super::LCKR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LCKK`
        pub type LCKK_R = crate::R<bool, bool>;
        ///Write proxy for field `LCKK`
        pub struct LCKK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCKK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `LCK3`
        pub type LCK3_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK3`
        pub struct LCK3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `LCK1`
        pub type LCK1_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK1`
        pub struct LCK1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LCK0`
        pub type LCK0_R = crate::R<bool, bool>;
        ///Write proxy for field `LCK0`
        pub struct LCK0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LCK0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&self) -> LCKK_R {
                LCKK_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&self) -> LCK3_R {
                LCK3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&self) -> LCK1_R {
                LCK1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&self) -> LCK0_R {
                LCK0_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lckk(&mut self) -> LCKK_W {
                LCKK_W { w: self }
            }
            ///Bit 3 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck3(&mut self) -> LCK3_W {
                LCK3_W { w: self }
            }
            ///Bit 1 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck1(&mut self) -> LCK1_W {
                LCK1_W { w: self }
            }
            ///Bit 0 - Port x lock bit y (y= 0..15)
            #[inline(always)]
            pub fn lck0(&mut self) -> LCK0_W {
                LCK0_W { w: self }
            }
        }
    }
    ///GPIO alternate function low register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrl](afrl) module
    pub type AFRL = crate::Reg<u32, _AFRL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRL;
    ///`read()` method returns [afrl::R](afrl::R) reader structure
    impl crate::Readable for AFRL {}
    ///`write(|w| ..)` method takes [afrl::W](afrl::W) writer structure
    impl crate::Writable for AFRL {}
    ///GPIO alternate function low register
    pub mod afrl {
        ///Reader of register AFRL
        pub type R = crate::R<u32, super::AFRL>;
        ///Writer for register AFRL
        pub type W = crate::W<u32, super::AFRL>;
        ///Register AFRL `reset()`'s with value 0
        impl crate::ResetValue for super::AFRL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL3`
        pub type AFSEL3_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL3`
        pub struct AFSEL3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL1`
        pub type AFSEL1_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL1`
        pub struct AFSEL1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL0`
        pub type AFSEL0_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL0`
        pub struct AFSEL0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL0_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&self) -> AFSEL3_R {
                AFSEL3_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&self) -> AFSEL1_R {
                AFSEL1_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&self) -> AFSEL0_R {
                AFSEL0_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel3(&mut self) -> AFSEL3_W {
                AFSEL3_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel1(&mut self) -> AFSEL1_W {
                AFSEL1_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
            #[inline(always)]
            pub fn afsel0(&mut self) -> AFSEL0_W {
                AFSEL0_W { w: self }
            }
        }
    }
    ///GPIO alternate function high register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [afrh](afrh) module
    pub type AFRH = crate::Reg<u32, _AFRH>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AFRH;
    ///`read()` method returns [afrh::R](afrh::R) reader structure
    impl crate::Readable for AFRH {}
    ///`write(|w| ..)` method takes [afrh::W](afrh::W) writer structure
    impl crate::Writable for AFRH {}
    ///GPIO alternate function high register
    pub mod afrh {
        ///Reader of register AFRH
        pub type R = crate::R<u32, super::AFRH>;
        ///Writer for register AFRH
        pub type W = crate::W<u32, super::AFRH>;
        ///Register AFRH `reset()`'s with value 0
        impl crate::ResetValue for super::AFRH {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `AFSEL15`
        pub type AFSEL15_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL15`
        pub struct AFSEL15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `AFSEL14`
        pub type AFSEL14_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL14`
        pub struct AFSEL14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL14_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `AFSEL13`
        pub type AFSEL13_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL13`
        pub struct AFSEL13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL13_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `AFSEL12`
        pub type AFSEL12_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL12`
        pub struct AFSEL12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL12_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `AFSEL11`
        pub type AFSEL11_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL11`
        pub struct AFSEL11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL11_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `AFSEL10`
        pub type AFSEL10_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL10`
        pub struct AFSEL10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL10_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `AFSEL9`
        pub type AFSEL9_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL9`
        pub struct AFSEL9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL9_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `AFSEL8`
        pub type AFSEL8_R = crate::R<u8, u8>;
        ///Write proxy for field `AFSEL8`
        pub struct AFSEL8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AFSEL8_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&self) -> AFSEL15_R {
                AFSEL15_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&self) -> AFSEL14_R {
                AFSEL14_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&self) -> AFSEL13_R {
                AFSEL13_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&self) -> AFSEL12_R {
                AFSEL12_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&self) -> AFSEL11_R {
                AFSEL11_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&self) -> AFSEL10_R {
                AFSEL10_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&self) -> AFSEL9_R {
                AFSEL9_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&self) -> AFSEL8_R {
                AFSEL8_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel15(&mut self) -> AFSEL15_W {
                AFSEL15_W { w: self }
            }
            ///Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel14(&mut self) -> AFSEL14_W {
                AFSEL14_W { w: self }
            }
            ///Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel13(&mut self) -> AFSEL13_W {
                AFSEL13_W { w: self }
            }
            ///Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel12(&mut self) -> AFSEL12_W {
                AFSEL12_W { w: self }
            }
            ///Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel11(&mut self) -> AFSEL11_W {
                AFSEL11_W { w: self }
            }
            ///Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel10(&mut self) -> AFSEL10_W {
                AFSEL10_W { w: self }
            }
            ///Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel9(&mut self) -> AFSEL9_W {
                AFSEL9_W { w: self }
            }
            ///Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
            #[inline(always)]
            pub fn afsel8(&mut self) -> AFSEL8_W {
                AFSEL8_W { w: self }
            }
        }
    }
    ///port bit reset register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [brr](brr) module
    pub type BRR = crate::Reg<u32, _BRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BRR;
    ///`write(|w| ..)` method takes [brr::W](brr::W) writer structure
    impl crate::Writable for BRR {}
    ///port bit reset register
    pub mod brr {
        ///Writer for register BRR
        pub type W = crate::W<u32, super::BRR>;
        ///Register BRR `reset()`'s with value 0
        impl crate::ResetValue for super::BRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BR0`
        pub struct BR0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Write proxy for field `BR1`
        pub struct BR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `BR3`
        pub struct BR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        impl W {
            ///Bit 0 - Port Reset bit
            #[inline(always)]
            pub fn br0(&mut self) -> BR0_W {
                BR0_W { w: self }
            }
            ///Bit 1 - Port Reset bit
            #[inline(always)]
            pub fn br1(&mut self) -> BR1_W {
                BR1_W { w: self }
            }
            ///Bit 3 - Port Reset bit
            #[inline(always)]
            pub fn br3(&mut self) -> BR3_W {
                BR3_W { w: self }
            }
        }
    }
}
///Serial audio interface
pub struct SAI1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SAI1 {}
impl SAI1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const sai1::RegisterBlock {
        0x4001_5400 as *const _
    }
}
impl Deref for SAI1 {
    type Target = sai1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*SAI1::ptr() }
    }
}
///Serial audio interface
pub mod sai1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Global configuration register
        pub gcr: GCR,
        ///0x04 - Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR
        pub cha: CH,
        ///0x24 - Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR
        pub chb: CH,
        ///0x44 - PDM control register
        pub pdmcr: PDMCR,
        ///0x48 - PDM delay register
        pub pdmdly: PDMDLY,
    }
    ///Register block
    #[repr(C)]
    pub struct CH {
        ///0x00 - AConfiguration register 1
        pub cr1: self::ch::CR1,
        ///0x04 - AConfiguration register 2
        pub cr2: self::ch::CR2,
        ///0x08 - AFRCR
        pub frcr: self::ch::FRCR,
        ///0x0c - ASlot register
        pub slotr: self::ch::SLOTR,
        ///0x10 - AInterrupt mask register2
        pub im: self::ch::IM,
        ///0x14 - AStatus register
        pub sr: self::ch::SR,
        ///0x18 - AClear flag register
        pub clrfr: self::ch::CLRFR,
        ///0x1c - AData register
        pub dr: self::ch::DR,
    }
    ///Register block
    ///Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR
    pub mod ch {
        ///AConfiguration register 1
        ///
        ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [cr1](cr1) module
        pub type CR1 = crate::Reg<u32, _CR1>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _CR1;
        ///`read()` method returns [cr1::R](cr1::R) reader structure
        impl crate::Readable for CR1 {}
        ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
        impl crate::Writable for CR1 {}
        ///AConfiguration register 1
        pub mod cr1 {
            ///Reader of register CR1
            pub type R = crate::R<u32, super::CR1>;
            ///Writer for register CR1
            pub type W = crate::W<u32, super::CR1>;
            ///Register CR1 `reset()`'s with value 0x40
            impl crate::ResetValue for super::CR1 {
                type Type = u32;
                #[inline(always)]
                fn reset_value() -> Self::Type {
                    0x40
                }
            }
            ///Reader of field `MCKEN`
            pub type MCKEN_R = crate::R<bool, bool>;
            ///Write proxy for field `MCKEN`
            pub struct MCKEN_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MCKEN_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                    self.w
                }
            }
            ///Reader of field `OSR`
            pub type OSR_R = crate::R<bool, bool>;
            ///Write proxy for field `OSR`
            pub struct OSR_W<'a> {
                w: &'a mut W,
            }
            impl<'a> OSR_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                    self.w
                }
            }
            ///Reader of field `MCKDIV`
            pub type MCKDIV_R = crate::R<u8, u8>;
            ///Write proxy for field `MCKDIV`
            pub struct MCKDIV_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MCKDIV_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x3f << 20)) | (((value as u32) & 0x3f) << 20);
                    self.w
                }
            }
            ///Reader of field `NODIV`
            pub type NODIV_R = crate::R<bool, bool>;
            ///Write proxy for field `NODIV`
            pub struct NODIV_W<'a> {
                w: &'a mut W,
            }
            impl<'a> NODIV_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                    self.w
                }
            }
            ///Reader of field `DMAEN`
            pub type DMAEN_R = crate::R<bool, bool>;
            ///Write proxy for field `DMAEN`
            pub struct DMAEN_W<'a> {
                w: &'a mut W,
            }
            impl<'a> DMAEN_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                    self.w
                }
            }
            ///Reader of field `SAIEN`
            pub type SAIEN_R = crate::R<bool, bool>;
            ///Write proxy for field `SAIEN`
            pub struct SAIEN_W<'a> {
                w: &'a mut W,
            }
            impl<'a> SAIEN_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                    self.w
                }
            }
            ///Reader of field `OUTDRIV`
            pub type OUTDRIV_R = crate::R<bool, bool>;
            ///Write proxy for field `OUTDRIV`
            pub struct OUTDRIV_W<'a> {
                w: &'a mut W,
            }
            impl<'a> OUTDRIV_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                    self.w
                }
            }
            ///Reader of field `MONO`
            pub type MONO_R = crate::R<bool, bool>;
            ///Write proxy for field `MONO`
            pub struct MONO_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MONO_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                    self.w
                }
            }
            ///Reader of field `SYNCEN`
            pub type SYNCEN_R = crate::R<u8, u8>;
            ///Write proxy for field `SYNCEN`
            pub struct SYNCEN_W<'a> {
                w: &'a mut W,
            }
            impl<'a> SYNCEN_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                    self.w
                }
            }
            ///Reader of field `CKSTR`
            pub type CKSTR_R = crate::R<bool, bool>;
            ///Write proxy for field `CKSTR`
            pub struct CKSTR_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CKSTR_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                    self.w
                }
            }
            ///Reader of field `LSBFIRST`
            pub type LSBFIRST_R = crate::R<bool, bool>;
            ///Write proxy for field `LSBFIRST`
            pub struct LSBFIRST_W<'a> {
                w: &'a mut W,
            }
            impl<'a> LSBFIRST_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                    self.w
                }
            }
            ///Reader of field `DS`
            pub type DS_R = crate::R<u8, u8>;
            ///Write proxy for field `DS`
            pub struct DS_W<'a> {
                w: &'a mut W,
            }
            impl<'a> DS_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5);
                    self.w
                }
            }
            ///Reader of field `PRTCFG`
            pub type PRTCFG_R = crate::R<u8, u8>;
            ///Write proxy for field `PRTCFG`
            pub struct PRTCFG_W<'a> {
                w: &'a mut W,
            }
            impl<'a> PRTCFG_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                    self.w
                }
            }
            ///Reader of field `MODE`
            pub type MODE_R = crate::R<u8, u8>;
            ///Write proxy for field `MODE`
            pub struct MODE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MODE_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                    self.w
                }
            }
            impl R {
                ///Bit 27 - Master clock generation enable
                #[inline(always)]
                pub fn mcken(&self) -> MCKEN_R {
                    MCKEN_R::new(((self.bits >> 27) & 0x01) != 0)
                }
                ///Bit 26 - Oversampling ratio for master clock
                #[inline(always)]
                pub fn osr(&self) -> OSR_R {
                    OSR_R::new(((self.bits >> 26) & 0x01) != 0)
                }
                ///Bits 20:25 - Master clock divider
                #[inline(always)]
                pub fn mckdiv(&self) -> MCKDIV_R {
                    MCKDIV_R::new(((self.bits >> 20) & 0x3f) as u8)
                }
                ///Bit 19 - No divider
                #[inline(always)]
                pub fn nodiv(&self) -> NODIV_R {
                    NODIV_R::new(((self.bits >> 19) & 0x01) != 0)
                }
                ///Bit 17 - DMA enable
                #[inline(always)]
                pub fn dmaen(&self) -> DMAEN_R {
                    DMAEN_R::new(((self.bits >> 17) & 0x01) != 0)
                }
                ///Bit 16 - Audio block B enable
                #[inline(always)]
                pub fn saien(&self) -> SAIEN_R {
                    SAIEN_R::new(((self.bits >> 16) & 0x01) != 0)
                }
                ///Bit 13 - Output drive
                #[inline(always)]
                pub fn outdriv(&self) -> OUTDRIV_R {
                    OUTDRIV_R::new(((self.bits >> 13) & 0x01) != 0)
                }
                ///Bit 12 - Mono mode
                #[inline(always)]
                pub fn mono(&self) -> MONO_R {
                    MONO_R::new(((self.bits >> 12) & 0x01) != 0)
                }
                ///Bits 10:11 - Synchronization enable
                #[inline(always)]
                pub fn syncen(&self) -> SYNCEN_R {
                    SYNCEN_R::new(((self.bits >> 10) & 0x03) as u8)
                }
                ///Bit 9 - Clock strobing edge
                #[inline(always)]
                pub fn ckstr(&self) -> CKSTR_R {
                    CKSTR_R::new(((self.bits >> 9) & 0x01) != 0)
                }
                ///Bit 8 - Least significant bit first
                #[inline(always)]
                pub fn lsbfirst(&self) -> LSBFIRST_R {
                    LSBFIRST_R::new(((self.bits >> 8) & 0x01) != 0)
                }
                ///Bits 5:7 - Data size
                #[inline(always)]
                pub fn ds(&self) -> DS_R {
                    DS_R::new(((self.bits >> 5) & 0x07) as u8)
                }
                ///Bits 2:3 - Protocol configuration
                #[inline(always)]
                pub fn prtcfg(&self) -> PRTCFG_R {
                    PRTCFG_R::new(((self.bits >> 2) & 0x03) as u8)
                }
                ///Bits 0:1 - Audio block mode
                #[inline(always)]
                pub fn mode(&self) -> MODE_R {
                    MODE_R::new((self.bits & 0x03) as u8)
                }
            }
            impl W {
                ///Bit 27 - Master clock generation enable
                #[inline(always)]
                pub fn mcken(&mut self) -> MCKEN_W {
                    MCKEN_W { w: self }
                }
                ///Bit 26 - Oversampling ratio for master clock
                #[inline(always)]
                pub fn osr(&mut self) -> OSR_W {
                    OSR_W { w: self }
                }
                ///Bits 20:25 - Master clock divider
                #[inline(always)]
                pub fn mckdiv(&mut self) -> MCKDIV_W {
                    MCKDIV_W { w: self }
                }
                ///Bit 19 - No divider
                #[inline(always)]
                pub fn nodiv(&mut self) -> NODIV_W {
                    NODIV_W { w: self }
                }
                ///Bit 17 - DMA enable
                #[inline(always)]
                pub fn dmaen(&mut self) -> DMAEN_W {
                    DMAEN_W { w: self }
                }
                ///Bit 16 - Audio block B enable
                #[inline(always)]
                pub fn saien(&mut self) -> SAIEN_W {
                    SAIEN_W { w: self }
                }
                ///Bit 13 - Output drive
                #[inline(always)]
                pub fn outdriv(&mut self) -> OUTDRIV_W {
                    OUTDRIV_W { w: self }
                }
                ///Bit 12 - Mono mode
                #[inline(always)]
                pub fn mono(&mut self) -> MONO_W {
                    MONO_W { w: self }
                }
                ///Bits 10:11 - Synchronization enable
                #[inline(always)]
                pub fn syncen(&mut self) -> SYNCEN_W {
                    SYNCEN_W { w: self }
                }
                ///Bit 9 - Clock strobing edge
                #[inline(always)]
                pub fn ckstr(&mut self) -> CKSTR_W {
                    CKSTR_W { w: self }
                }
                ///Bit 8 - Least significant bit first
                #[inline(always)]
                pub fn lsbfirst(&mut self) -> LSBFIRST_W {
                    LSBFIRST_W { w: self }
                }
                ///Bits 5:7 - Data size
                #[inline(always)]
                pub fn ds(&mut self) -> DS_W {
                    DS_W { w: self }
                }
                ///Bits 2:3 - Protocol configuration
                #[inline(always)]
                pub fn prtcfg(&mut self) -> PRTCFG_W {
                    PRTCFG_W { w: self }
                }
                ///Bits 0:1 - Audio block mode
                #[inline(always)]
                pub fn mode(&mut self) -> MODE_W {
                    MODE_W { w: self }
                }
            }
        }
        ///AConfiguration register 2
        ///
        ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [cr2](cr2) module
        pub type CR2 = crate::Reg<u32, _CR2>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _CR2;
        ///`read()` method returns [cr2::R](cr2::R) reader structure
        impl crate::Readable for CR2 {}
        ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
        impl crate::Writable for CR2 {}
        ///AConfiguration register 2
        pub mod cr2 {
            ///Reader of register CR2
            pub type R = crate::R<u32, super::CR2>;
            ///Writer for register CR2
            pub type W = crate::W<u32, super::CR2>;
            ///Register CR2 `reset()`'s with value 0
            impl crate::ResetValue for super::CR2 {
                type Type = u32;
                #[inline(always)]
                fn reset_value() -> Self::Type {
                    0
                }
            }
            ///Reader of field `COMP`
            pub type COMP_R = crate::R<u8, u8>;
            ///Write proxy for field `COMP`
            pub struct COMP_W<'a> {
                w: &'a mut W,
            }
            impl<'a> COMP_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
                    self.w
                }
            }
            ///Reader of field `CPL`
            pub type CPL_R = crate::R<bool, bool>;
            ///Write proxy for field `CPL`
            pub struct CPL_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CPL_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                    self.w
                }
            }
            ///Reader of field `MUTECN`
            pub type MUTECN_R = crate::R<u8, u8>;
            ///Write proxy for field `MUTECN`
            pub struct MUTECN_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MUTECN_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x3f << 7)) | (((value as u32) & 0x3f) << 7);
                    self.w
                }
            }
            ///Reader of field `MUTEVAL`
            pub type MUTEVAL_R = crate::R<bool, bool>;
            ///Write proxy for field `MUTEVAL`
            pub struct MUTEVAL_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MUTEVAL_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                    self.w
                }
            }
            ///Reader of field `MUTE`
            pub type MUTE_R = crate::R<bool, bool>;
            ///Write proxy for field `MUTE`
            pub struct MUTE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MUTE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                    self.w
                }
            }
            ///Reader of field `TRIS`
            pub type TRIS_R = crate::R<bool, bool>;
            ///Write proxy for field `TRIS`
            pub struct TRIS_W<'a> {
                w: &'a mut W,
            }
            impl<'a> TRIS_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                    self.w
                }
            }
            ///Reader of field `FFLUSH`
            pub type FFLUSH_R = crate::R<bool, bool>;
            ///Write proxy for field `FFLUSH`
            pub struct FFLUSH_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FFLUSH_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                    self.w
                }
            }
            ///Reader of field `FTH`
            pub type FTH_R = crate::R<u8, u8>;
            ///Write proxy for field `FTH`
            pub struct FTH_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FTH_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                    self.w
                }
            }
            impl R {
                ///Bits 14:15 - Companding mode
                #[inline(always)]
                pub fn comp(&self) -> COMP_R {
                    COMP_R::new(((self.bits >> 14) & 0x03) as u8)
                }
                ///Bit 13 - Complement bit
                #[inline(always)]
                pub fn cpl(&self) -> CPL_R {
                    CPL_R::new(((self.bits >> 13) & 0x01) != 0)
                }
                ///Bits 7:12 - Mute counter
                #[inline(always)]
                pub fn mutecn(&self) -> MUTECN_R {
                    MUTECN_R::new(((self.bits >> 7) & 0x3f) as u8)
                }
                ///Bit 6 - Mute value
                #[inline(always)]
                pub fn muteval(&self) -> MUTEVAL_R {
                    MUTEVAL_R::new(((self.bits >> 6) & 0x01) != 0)
                }
                ///Bit 5 - Mute
                #[inline(always)]
                pub fn mute(&self) -> MUTE_R {
                    MUTE_R::new(((self.bits >> 5) & 0x01) != 0)
                }
                ///Bit 4 - Tristate management on data line
                #[inline(always)]
                pub fn tris(&self) -> TRIS_R {
                    TRIS_R::new(((self.bits >> 4) & 0x01) != 0)
                }
                ///Bit 3 - FIFO flush
                #[inline(always)]
                pub fn fflush(&self) -> FFLUSH_R {
                    FFLUSH_R::new(((self.bits >> 3) & 0x01) != 0)
                }
                ///Bits 0:2 - FIFO threshold
                #[inline(always)]
                pub fn fth(&self) -> FTH_R {
                    FTH_R::new((self.bits & 0x07) as u8)
                }
            }
            impl W {
                ///Bits 14:15 - Companding mode
                #[inline(always)]
                pub fn comp(&mut self) -> COMP_W {
                    COMP_W { w: self }
                }
                ///Bit 13 - Complement bit
                #[inline(always)]
                pub fn cpl(&mut self) -> CPL_W {
                    CPL_W { w: self }
                }
                ///Bits 7:12 - Mute counter
                #[inline(always)]
                pub fn mutecn(&mut self) -> MUTECN_W {
                    MUTECN_W { w: self }
                }
                ///Bit 6 - Mute value
                #[inline(always)]
                pub fn muteval(&mut self) -> MUTEVAL_W {
                    MUTEVAL_W { w: self }
                }
                ///Bit 5 - Mute
                #[inline(always)]
                pub fn mute(&mut self) -> MUTE_W {
                    MUTE_W { w: self }
                }
                ///Bit 4 - Tristate management on data line
                #[inline(always)]
                pub fn tris(&mut self) -> TRIS_W {
                    TRIS_W { w: self }
                }
                ///Bit 3 - FIFO flush
                #[inline(always)]
                pub fn fflush(&mut self) -> FFLUSH_W {
                    FFLUSH_W { w: self }
                }
                ///Bits 0:2 - FIFO threshold
                #[inline(always)]
                pub fn fth(&mut self) -> FTH_W {
                    FTH_W { w: self }
                }
            }
        }
        ///AFRCR
        ///
        ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [frcr](frcr) module
        pub type FRCR = crate::Reg<u32, _FRCR>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _FRCR;
        ///`read()` method returns [frcr::R](frcr::R) reader structure
        impl crate::Readable for FRCR {}
        ///`write(|w| ..)` method takes [frcr::W](frcr::W) writer structure
        impl crate::Writable for FRCR {}
        ///AFRCR
        pub mod frcr {
            ///Reader of register FRCR
            pub type R = crate::R<u32, super::FRCR>;
            ///Writer for register FRCR
            pub type W = crate::W<u32, super::FRCR>;
            ///Register FRCR `reset()`'s with value 0x07
            impl crate::ResetValue for super::FRCR {
                type Type = u32;
                #[inline(always)]
                fn reset_value() -> Self::Type {
                    0x07
                }
            }
            ///Reader of field `FSOFF`
            pub type FSOFF_R = crate::R<bool, bool>;
            ///Write proxy for field `FSOFF`
            pub struct FSOFF_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FSOFF_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                    self.w
                }
            }
            ///Reader of field `FSPOL`
            pub type FSPOL_R = crate::R<bool, bool>;
            ///Write proxy for field `FSPOL`
            pub struct FSPOL_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FSPOL_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                    self.w
                }
            }
            ///Reader of field `FSDEF`
            pub type FSDEF_R = crate::R<bool, bool>;
            ///Write proxy for field `FSDEF`
            pub struct FSDEF_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FSDEF_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                    self.w
                }
            }
            ///Reader of field `FSALL`
            pub type FSALL_R = crate::R<u8, u8>;
            ///Write proxy for field `FSALL`
            pub struct FSALL_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FSALL_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
                    self.w
                }
            }
            ///Reader of field `FRL`
            pub type FRL_R = crate::R<u8, u8>;
            ///Write proxy for field `FRL`
            pub struct FRL_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FRL_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                    self.w
                }
            }
            impl R {
                ///Bit 18 - Frame synchronization offset
                #[inline(always)]
                pub fn fsoff(&self) -> FSOFF_R {
                    FSOFF_R::new(((self.bits >> 18) & 0x01) != 0)
                }
                ///Bit 17 - Frame synchronization polarity
                #[inline(always)]
                pub fn fspol(&self) -> FSPOL_R {
                    FSPOL_R::new(((self.bits >> 17) & 0x01) != 0)
                }
                ///Bit 16 - Frame synchronization definition
                #[inline(always)]
                pub fn fsdef(&self) -> FSDEF_R {
                    FSDEF_R::new(((self.bits >> 16) & 0x01) != 0)
                }
                ///Bits 8:14 - Frame synchronization active level length
                #[inline(always)]
                pub fn fsall(&self) -> FSALL_R {
                    FSALL_R::new(((self.bits >> 8) & 0x7f) as u8)
                }
                ///Bits 0:7 - Frame length
                #[inline(always)]
                pub fn frl(&self) -> FRL_R {
                    FRL_R::new((self.bits & 0xff) as u8)
                }
            }
            impl W {
                ///Bit 18 - Frame synchronization offset
                #[inline(always)]
                pub fn fsoff(&mut self) -> FSOFF_W {
                    FSOFF_W { w: self }
                }
                ///Bit 17 - Frame synchronization polarity
                #[inline(always)]
                pub fn fspol(&mut self) -> FSPOL_W {
                    FSPOL_W { w: self }
                }
                ///Bit 16 - Frame synchronization definition
                #[inline(always)]
                pub fn fsdef(&mut self) -> FSDEF_W {
                    FSDEF_W { w: self }
                }
                ///Bits 8:14 - Frame synchronization active level length
                #[inline(always)]
                pub fn fsall(&mut self) -> FSALL_W {
                    FSALL_W { w: self }
                }
                ///Bits 0:7 - Frame length
                #[inline(always)]
                pub fn frl(&mut self) -> FRL_W {
                    FRL_W { w: self }
                }
            }
        }
        ///ASlot register
        ///
        ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [slotr](slotr) module
        pub type SLOTR = crate::Reg<u32, _SLOTR>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _SLOTR;
        ///`read()` method returns [slotr::R](slotr::R) reader structure
        impl crate::Readable for SLOTR {}
        ///`write(|w| ..)` method takes [slotr::W](slotr::W) writer structure
        impl crate::Writable for SLOTR {}
        ///ASlot register
        pub mod slotr {
            ///Reader of register SLOTR
            pub type R = crate::R<u32, super::SLOTR>;
            ///Writer for register SLOTR
            pub type W = crate::W<u32, super::SLOTR>;
            ///Register SLOTR `reset()`'s with value 0
            impl crate::ResetValue for super::SLOTR {
                type Type = u32;
                #[inline(always)]
                fn reset_value() -> Self::Type {
                    0
                }
            }
            ///Reader of field `SLOTEN`
            pub type SLOTEN_R = crate::R<u16, u16>;
            ///Write proxy for field `SLOTEN`
            pub struct SLOTEN_W<'a> {
                w: &'a mut W,
            }
            impl<'a> SLOTEN_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u16) -> &'a mut W {
                    self.w.bits =
                        (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                    self.w
                }
            }
            ///Reader of field `NBSLOT`
            pub type NBSLOT_R = crate::R<u8, u8>;
            ///Write proxy for field `NBSLOT`
            pub struct NBSLOT_W<'a> {
                w: &'a mut W,
            }
            impl<'a> NBSLOT_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                    self.w
                }
            }
            ///Reader of field `SLOTSZ`
            pub type SLOTSZ_R = crate::R<u8, u8>;
            ///Write proxy for field `SLOTSZ`
            pub struct SLOTSZ_W<'a> {
                w: &'a mut W,
            }
            impl<'a> SLOTSZ_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                    self.w
                }
            }
            ///Reader of field `FBOFF`
            pub type FBOFF_R = crate::R<u8, u8>;
            ///Write proxy for field `FBOFF`
            pub struct FBOFF_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FBOFF_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u8) -> &'a mut W {
                    self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                    self.w
                }
            }
            impl R {
                ///Bits 16:31 - Slot enable
                #[inline(always)]
                pub fn sloten(&self) -> SLOTEN_R {
                    SLOTEN_R::new(((self.bits >> 16) & 0xffff) as u16)
                }
                ///Bits 8:11 - Number of slots in an audio frame
                #[inline(always)]
                pub fn nbslot(&self) -> NBSLOT_R {
                    NBSLOT_R::new(((self.bits >> 8) & 0x0f) as u8)
                }
                ///Bits 6:7 - Slot size
                #[inline(always)]
                pub fn slotsz(&self) -> SLOTSZ_R {
                    SLOTSZ_R::new(((self.bits >> 6) & 0x03) as u8)
                }
                ///Bits 0:4 - First bit offset
                #[inline(always)]
                pub fn fboff(&self) -> FBOFF_R {
                    FBOFF_R::new((self.bits & 0x1f) as u8)
                }
            }
            impl W {
                ///Bits 16:31 - Slot enable
                #[inline(always)]
                pub fn sloten(&mut self) -> SLOTEN_W {
                    SLOTEN_W { w: self }
                }
                ///Bits 8:11 - Number of slots in an audio frame
                #[inline(always)]
                pub fn nbslot(&mut self) -> NBSLOT_W {
                    NBSLOT_W { w: self }
                }
                ///Bits 6:7 - Slot size
                #[inline(always)]
                pub fn slotsz(&mut self) -> SLOTSZ_W {
                    SLOTSZ_W { w: self }
                }
                ///Bits 0:4 - First bit offset
                #[inline(always)]
                pub fn fboff(&mut self) -> FBOFF_W {
                    FBOFF_W { w: self }
                }
            }
        }
        ///AInterrupt mask register2
        ///
        ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [im](im) module
        pub type IM = crate::Reg<u32, _IM>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _IM;
        ///`read()` method returns [im::R](im::R) reader structure
        impl crate::Readable for IM {}
        ///`write(|w| ..)` method takes [im::W](im::W) writer structure
        impl crate::Writable for IM {}
        ///AInterrupt mask register2
        pub mod im {
            ///Reader of register IM
            pub type R = crate::R<u32, super::IM>;
            ///Writer for register IM
            pub type W = crate::W<u32, super::IM>;
            ///Register IM `reset()`'s with value 0
            impl crate::ResetValue for super::IM {
                type Type = u32;
                #[inline(always)]
                fn reset_value() -> Self::Type {
                    0
                }
            }
            ///Reader of field `LFSDETIE`
            pub type LFSDETIE_R = crate::R<bool, bool>;
            ///Write proxy for field `LFSDETIE`
            pub struct LFSDETIE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> LFSDETIE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                    self.w
                }
            }
            ///Reader of field `AFSDETIE`
            pub type AFSDETIE_R = crate::R<bool, bool>;
            ///Write proxy for field `AFSDETIE`
            pub struct AFSDETIE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> AFSDETIE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                    self.w
                }
            }
            ///Reader of field `CNRDYIE`
            pub type CNRDYIE_R = crate::R<bool, bool>;
            ///Write proxy for field `CNRDYIE`
            pub struct CNRDYIE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CNRDYIE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                    self.w
                }
            }
            ///Reader of field `FREQIE`
            pub type FREQIE_R = crate::R<bool, bool>;
            ///Write proxy for field `FREQIE`
            pub struct FREQIE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> FREQIE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                    self.w
                }
            }
            ///Reader of field `WCKCFGIE`
            pub type WCKCFGIE_R = crate::R<bool, bool>;
            ///Write proxy for field `WCKCFGIE`
            pub struct WCKCFGIE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> WCKCFGIE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                    self.w
                }
            }
            ///Reader of field `MUTEDETIE`
            pub type MUTEDETIE_R = crate::R<bool, bool>;
            ///Write proxy for field `MUTEDETIE`
            pub struct MUTEDETIE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> MUTEDETIE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                    self.w
                }
            }
            ///Reader of field `OVRUDRIE`
            pub type OVRUDRIE_R = crate::R<bool, bool>;
            ///Write proxy for field `OVRUDRIE`
            pub struct OVRUDRIE_W<'a> {
                w: &'a mut W,
            }
            impl<'a> OVRUDRIE_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                    self.w
                }
            }
            impl R {
                ///Bit 6 - Late frame synchronization detection interrupt enable
                #[inline(always)]
                pub fn lfsdetie(&self) -> LFSDETIE_R {
                    LFSDETIE_R::new(((self.bits >> 6) & 0x01) != 0)
                }
                ///Bit 5 - Anticipated frame synchronization detection interrupt enable
                #[inline(always)]
                pub fn afsdetie(&self) -> AFSDETIE_R {
                    AFSDETIE_R::new(((self.bits >> 5) & 0x01) != 0)
                }
                ///Bit 4 - Codec not ready interrupt enable
                #[inline(always)]
                pub fn cnrdyie(&self) -> CNRDYIE_R {
                    CNRDYIE_R::new(((self.bits >> 4) & 0x01) != 0)
                }
                ///Bit 3 - FIFO request interrupt enable
                #[inline(always)]
                pub fn freqie(&self) -> FREQIE_R {
                    FREQIE_R::new(((self.bits >> 3) & 0x01) != 0)
                }
                ///Bit 2 - Wrong clock configuration interrupt enable
                #[inline(always)]
                pub fn wckcfgie(&self) -> WCKCFGIE_R {
                    WCKCFGIE_R::new(((self.bits >> 2) & 0x01) != 0)
                }
                ///Bit 1 - Mute detection interrupt enable
                #[inline(always)]
                pub fn mutedetie(&self) -> MUTEDETIE_R {
                    MUTEDETIE_R::new(((self.bits >> 1) & 0x01) != 0)
                }
                ///Bit 0 - Overrun/underrun interrupt enable
                #[inline(always)]
                pub fn ovrudrie(&self) -> OVRUDRIE_R {
                    OVRUDRIE_R::new((self.bits & 0x01) != 0)
                }
            }
            impl W {
                ///Bit 6 - Late frame synchronization detection interrupt enable
                #[inline(always)]
                pub fn lfsdetie(&mut self) -> LFSDETIE_W {
                    LFSDETIE_W { w: self }
                }
                ///Bit 5 - Anticipated frame synchronization detection interrupt enable
                #[inline(always)]
                pub fn afsdetie(&mut self) -> AFSDETIE_W {
                    AFSDETIE_W { w: self }
                }
                ///Bit 4 - Codec not ready interrupt enable
                #[inline(always)]
                pub fn cnrdyie(&mut self) -> CNRDYIE_W {
                    CNRDYIE_W { w: self }
                }
                ///Bit 3 - FIFO request interrupt enable
                #[inline(always)]
                pub fn freqie(&mut self) -> FREQIE_W {
                    FREQIE_W { w: self }
                }
                ///Bit 2 - Wrong clock configuration interrupt enable
                #[inline(always)]
                pub fn wckcfgie(&mut self) -> WCKCFGIE_W {
                    WCKCFGIE_W { w: self }
                }
                ///Bit 1 - Mute detection interrupt enable
                #[inline(always)]
                pub fn mutedetie(&mut self) -> MUTEDETIE_W {
                    MUTEDETIE_W { w: self }
                }
                ///Bit 0 - Overrun/underrun interrupt enable
                #[inline(always)]
                pub fn ovrudrie(&mut self) -> OVRUDRIE_W {
                    OVRUDRIE_W { w: self }
                }
            }
        }
        ///AStatus register
        ///
        ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [sr](sr) module
        pub type SR = crate::Reg<u32, _SR>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _SR;
        ///`read()` method returns [sr::R](sr::R) reader structure
        impl crate::Readable for SR {}
        ///AStatus register
        pub mod sr {
            ///Reader of register SR
            pub type R = crate::R<u32, super::SR>;
            ///Reader of field `FLVL`
            pub type FLVL_R = crate::R<u8, u8>;
            ///Reader of field `LFSDET`
            pub type LFSDET_R = crate::R<bool, bool>;
            ///Reader of field `AFSDET`
            pub type AFSDET_R = crate::R<bool, bool>;
            ///Reader of field `CNRDY`
            pub type CNRDY_R = crate::R<bool, bool>;
            ///Reader of field `FREQ`
            pub type FREQ_R = crate::R<bool, bool>;
            ///Reader of field `WCKCFG`
            pub type WCKCFG_R = crate::R<bool, bool>;
            ///Reader of field `MUTEDET`
            pub type MUTEDET_R = crate::R<bool, bool>;
            ///Reader of field `OVRUDR`
            pub type OVRUDR_R = crate::R<bool, bool>;
            impl R {
                ///Bits 16:18 - FIFO level threshold
                #[inline(always)]
                pub fn flvl(&self) -> FLVL_R {
                    FLVL_R::new(((self.bits >> 16) & 0x07) as u8)
                }
                ///Bit 6 - Late frame synchronization detection
                #[inline(always)]
                pub fn lfsdet(&self) -> LFSDET_R {
                    LFSDET_R::new(((self.bits >> 6) & 0x01) != 0)
                }
                ///Bit 5 - Anticipated frame synchronization detection
                #[inline(always)]
                pub fn afsdet(&self) -> AFSDET_R {
                    AFSDET_R::new(((self.bits >> 5) & 0x01) != 0)
                }
                ///Bit 4 - Codec not ready
                #[inline(always)]
                pub fn cnrdy(&self) -> CNRDY_R {
                    CNRDY_R::new(((self.bits >> 4) & 0x01) != 0)
                }
                ///Bit 3 - FIFO request
                #[inline(always)]
                pub fn freq(&self) -> FREQ_R {
                    FREQ_R::new(((self.bits >> 3) & 0x01) != 0)
                }
                ///Bit 2 - Wrong clock configuration flag. This bit is read only
                #[inline(always)]
                pub fn wckcfg(&self) -> WCKCFG_R {
                    WCKCFG_R::new(((self.bits >> 2) & 0x01) != 0)
                }
                ///Bit 1 - Mute detection
                #[inline(always)]
                pub fn mutedet(&self) -> MUTEDET_R {
                    MUTEDET_R::new(((self.bits >> 1) & 0x01) != 0)
                }
                ///Bit 0 - Overrun / underrun
                #[inline(always)]
                pub fn ovrudr(&self) -> OVRUDR_R {
                    OVRUDR_R::new((self.bits & 0x01) != 0)
                }
            }
        }
        ///AClear flag register
        ///
        ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [clrfr](clrfr) module
        pub type CLRFR = crate::Reg<u32, _CLRFR>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _CLRFR;
        ///`write(|w| ..)` method takes [clrfr::W](clrfr::W) writer structure
        impl crate::Writable for CLRFR {}
        ///AClear flag register
        pub mod clrfr {
            ///Writer for register CLRFR
            pub type W = crate::W<u32, super::CLRFR>;
            ///Register CLRFR `reset()`'s with value 0
            impl crate::ResetValue for super::CLRFR {
                type Type = u32;
                #[inline(always)]
                fn reset_value() -> Self::Type {
                    0
                }
            }
            ///Write proxy for field `CLFSDET`
            pub struct CLFSDET_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CLFSDET_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                    self.w
                }
            }
            ///Write proxy for field `CAFSDET`
            pub struct CAFSDET_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CAFSDET_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                    self.w
                }
            }
            ///Write proxy for field `CCNRDY`
            pub struct CCNRDY_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CCNRDY_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                    self.w
                }
            }
            ///Write proxy for field `CWCKCFG`
            pub struct CWCKCFG_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CWCKCFG_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                    self.w
                }
            }
            ///Write proxy for field `CMUTEDET`
            pub struct CMUTEDET_W<'a> {
                w: &'a mut W,
            }
            impl<'a> CMUTEDET_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                    self.w
                }
            }
            ///Write proxy for field `COVRUDR`
            pub struct COVRUDR_W<'a> {
                w: &'a mut W,
            }
            impl<'a> COVRUDR_W<'a> {
                ///Sets the field bit
                #[inline(always)]
                pub fn set_bit(self) -> &'a mut W {
                    self.bit(true)
                }
                ///Clears the field bit
                #[inline(always)]
                pub fn clear_bit(self) -> &'a mut W {
                    self.bit(false)
                }
                ///Writes raw bits to the field
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W {
                    self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                    self.w
                }
            }
            impl W {
                ///Bit 6 - Clear late frame synchronization detection flag
                #[inline(always)]
                pub fn clfsdet(&mut self) -> CLFSDET_W {
                    CLFSDET_W { w: self }
                }
                ///Bit 5 - Clear anticipated frame synchronization detection flag
                #[inline(always)]
                pub fn cafsdet(&mut self) -> CAFSDET_W {
                    CAFSDET_W { w: self }
                }
                ///Bit 4 - Clear codec not ready flag
                #[inline(always)]
                pub fn ccnrdy(&mut self) -> CCNRDY_W {
                    CCNRDY_W { w: self }
                }
                ///Bit 2 - Clear wrong clock configuration flag
                #[inline(always)]
                pub fn cwckcfg(&mut self) -> CWCKCFG_W {
                    CWCKCFG_W { w: self }
                }
                ///Bit 1 - Mute detection flag
                #[inline(always)]
                pub fn cmutedet(&mut self) -> CMUTEDET_W {
                    CMUTEDET_W { w: self }
                }
                ///Bit 0 - Clear overrun / underrun
                #[inline(always)]
                pub fn covrudr(&mut self) -> COVRUDR_W {
                    COVRUDR_W { w: self }
                }
            }
        }
        ///AData register
        ///
        ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
        ///
        ///For information about available fields see [dr](dr) module
        pub type DR = crate::Reg<u32, _DR>;
        #[allow(missing_docs)]
        #[doc(hidden)]
        pub struct _DR;
        ///`read()` method returns [dr::R](dr::R) reader structure
        impl crate::Readable for DR {}
        ///`write(|w| ..)` method takes [dr::W](dr::W) writer structure
        impl crate::Writable for DR {}
        ///AData register
        pub mod dr {
            ///Reader of register DR
            pub type R = crate::R<u32, super::DR>;
            ///Writer for register DR
            pub type W = crate::W<u32, super::DR>;
            ///Register DR `reset()`'s with value 0
            impl crate::ResetValue for super::DR {
                type Type = u32;
                #[inline(always)]
                fn reset_value() -> Self::Type {
                    0
                }
            }
            ///Reader of field `DATA`
            pub type DATA_R = crate::R<u32, u32>;
            ///Write proxy for field `DATA`
            pub struct DATA_W<'a> {
                w: &'a mut W,
            }
            impl<'a> DATA_W<'a> {
                ///Writes raw bits to the field
                #[inline(always)]
                pub unsafe fn bits(self, value: u32) -> &'a mut W {
                    self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                    self.w
                }
            }
            impl R {
                ///Bits 0:31 - Data
                #[inline(always)]
                pub fn data(&self) -> DATA_R {
                    DATA_R::new((self.bits & 0xffff_ffff) as u32)
                }
            }
            impl W {
                ///Bits 0:31 - Data
                #[inline(always)]
                pub fn data(&mut self) -> DATA_W {
                    DATA_W { w: self }
                }
            }
        }
    }
    ///Global configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [gcr](gcr) module
    pub type GCR = crate::Reg<u32, _GCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _GCR;
    ///`read()` method returns [gcr::R](gcr::R) reader structure
    impl crate::Readable for GCR {}
    ///`write(|w| ..)` method takes [gcr::W](gcr::W) writer structure
    impl crate::Writable for GCR {}
    ///Global configuration register
    pub mod gcr {
        ///Reader of register GCR
        pub type R = crate::R<u32, super::GCR>;
        ///Writer for register GCR
        pub type W = crate::W<u32, super::GCR>;
        ///Register GCR `reset()`'s with value 0
        impl crate::ResetValue for super::GCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNCOUT`
        pub type SYNCOUT_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNCOUT`
        pub struct SYNCOUT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCOUT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `SYNCIN`
        pub type SYNCIN_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNCIN`
        pub struct SYNCIN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCIN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 4:5 - Synchronization outputs
            #[inline(always)]
            pub fn syncout(&self) -> SYNCOUT_R {
                SYNCOUT_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 0:1 - Synchronization inputs
            #[inline(always)]
            pub fn syncin(&self) -> SYNCIN_R {
                SYNCIN_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 4:5 - Synchronization outputs
            #[inline(always)]
            pub fn syncout(&mut self) -> SYNCOUT_W {
                SYNCOUT_W { w: self }
            }
            ///Bits 0:1 - Synchronization inputs
            #[inline(always)]
            pub fn syncin(&mut self) -> SYNCIN_W {
                SYNCIN_W { w: self }
            }
        }
    }
    ///PDM control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdmcr](pdmcr) module
    pub type PDMCR = crate::Reg<u32, _PDMCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDMCR;
    ///`read()` method returns [pdmcr::R](pdmcr::R) reader structure
    impl crate::Readable for PDMCR {}
    ///`write(|w| ..)` method takes [pdmcr::W](pdmcr::W) writer structure
    impl crate::Writable for PDMCR {}
    ///PDM control register
    pub mod pdmcr {
        ///Reader of register PDMCR
        pub type R = crate::R<u32, super::PDMCR>;
        ///Writer for register PDMCR
        pub type W = crate::W<u32, super::PDMCR>;
        ///Register PDMCR `reset()`'s with value 0
        impl crate::ResetValue for super::PDMCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CKEN4`
        pub type CKEN4_R = crate::R<bool, bool>;
        ///Write proxy for field `CKEN4`
        pub struct CKEN4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKEN4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CKEN3`
        pub type CKEN3_R = crate::R<bool, bool>;
        ///Write proxy for field `CKEN3`
        pub struct CKEN3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKEN3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CKEN2`
        pub type CKEN2_R = crate::R<bool, bool>;
        ///Write proxy for field `CKEN2`
        pub struct CKEN2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKEN2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `CKEN1`
        pub type CKEN1_R = crate::R<bool, bool>;
        ///Write proxy for field `CKEN1`
        pub struct CKEN1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKEN1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `MICNBR`
        pub type MICNBR_R = crate::R<u8, u8>;
        ///Write proxy for field `MICNBR`
        pub struct MICNBR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MICNBR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `PDMEN`
        pub type PDMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PDMEN`
        pub struct PDMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PDMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 11 - Clock enable of bitstream clock number 4
            #[inline(always)]
            pub fn cken4(&self) -> CKEN4_R {
                CKEN4_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Clock enable of bitstream clock number 3
            #[inline(always)]
            pub fn cken3(&self) -> CKEN3_R {
                CKEN3_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Clock enable of bitstream clock number 2
            #[inline(always)]
            pub fn cken2(&self) -> CKEN2_R {
                CKEN2_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Clock enable of bitstream clock number 1
            #[inline(always)]
            pub fn cken1(&self) -> CKEN1_R {
                CKEN1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 4:5 - Number of microphones
            #[inline(always)]
            pub fn micnbr(&self) -> MICNBR_R {
                MICNBR_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 0 - PDM enable
            #[inline(always)]
            pub fn pdmen(&self) -> PDMEN_R {
                PDMEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 11 - Clock enable of bitstream clock number 4
            #[inline(always)]
            pub fn cken4(&mut self) -> CKEN4_W {
                CKEN4_W { w: self }
            }
            ///Bit 10 - Clock enable of bitstream clock number 3
            #[inline(always)]
            pub fn cken3(&mut self) -> CKEN3_W {
                CKEN3_W { w: self }
            }
            ///Bit 9 - Clock enable of bitstream clock number 2
            #[inline(always)]
            pub fn cken2(&mut self) -> CKEN2_W {
                CKEN2_W { w: self }
            }
            ///Bit 8 - Clock enable of bitstream clock number 1
            #[inline(always)]
            pub fn cken1(&mut self) -> CKEN1_W {
                CKEN1_W { w: self }
            }
            ///Bits 4:5 - Number of microphones
            #[inline(always)]
            pub fn micnbr(&mut self) -> MICNBR_W {
                MICNBR_W { w: self }
            }
            ///Bit 0 - PDM enable
            #[inline(always)]
            pub fn pdmen(&mut self) -> PDMEN_W {
                PDMEN_W { w: self }
            }
        }
    }
    ///PDM delay register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pdmdly](pdmdly) module
    pub type PDMDLY = crate::Reg<u32, _PDMDLY>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PDMDLY;
    ///`read()` method returns [pdmdly::R](pdmdly::R) reader structure
    impl crate::Readable for PDMDLY {}
    ///`write(|w| ..)` method takes [pdmdly::W](pdmdly::W) writer structure
    impl crate::Writable for PDMDLY {}
    ///PDM delay register
    pub mod pdmdly {
        ///Reader of register PDMDLY
        pub type R = crate::R<u32, super::PDMDLY>;
        ///Writer for register PDMDLY
        pub type W = crate::W<u32, super::PDMDLY>;
        ///Register PDMDLY `reset()`'s with value 0
        impl crate::ResetValue for super::PDMDLY {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DLYM4R`
        pub type DLYM4R_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM4R`
        pub struct DLYM4R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM4R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 28)) | (((value as u32) & 0x07) << 28);
                self.w
            }
        }
        ///Reader of field `DLYM4L`
        pub type DLYM4L_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM4L`
        pub struct DLYM4L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM4L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 24)) | (((value as u32) & 0x07) << 24);
                self.w
            }
        }
        ///Reader of field `DLYM3R`
        pub type DLYM3R_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM3R`
        pub struct DLYM3R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM3R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 20)) | (((value as u32) & 0x07) << 20);
                self.w
            }
        }
        ///Reader of field `DLYM3L`
        pub type DLYM3L_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM3L`
        pub struct DLYM3L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM3L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 16)) | (((value as u32) & 0x07) << 16);
                self.w
            }
        }
        ///Reader of field `DLYM2R`
        pub type DLYM2R_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM2R`
        pub struct DLYM2R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM2R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `DLYM2L`
        pub type DLYM2L_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM2L`
        pub struct DLYM2L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM2L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `DLYM1R`
        pub type DLYM1R_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM1R`
        pub struct DLYM1R_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM1R_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `DLYM1L`
        pub type DLYM1L_R = crate::R<u8, u8>;
        ///Write proxy for field `DLYM1L`
        pub struct DLYM1L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DLYM1L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bits 28:30 - Delay line for second microphone of pair 4
            #[inline(always)]
            pub fn dlym4r(&self) -> DLYM4R_R {
                DLYM4R_R::new(((self.bits >> 28) & 0x07) as u8)
            }
            ///Bits 24:26 - Delay line for first microphone of pair 4
            #[inline(always)]
            pub fn dlym4l(&self) -> DLYM4L_R {
                DLYM4L_R::new(((self.bits >> 24) & 0x07) as u8)
            }
            ///Bits 20:22 - Delay line for second microphone of pair 3
            #[inline(always)]
            pub fn dlym3r(&self) -> DLYM3R_R {
                DLYM3R_R::new(((self.bits >> 20) & 0x07) as u8)
            }
            ///Bits 16:18 - Delay line for first microphone of pair 3
            #[inline(always)]
            pub fn dlym3l(&self) -> DLYM3L_R {
                DLYM3L_R::new(((self.bits >> 16) & 0x07) as u8)
            }
            ///Bits 12:14 - Delay line for second microphone of pair 2
            #[inline(always)]
            pub fn dlym2r(&self) -> DLYM2R_R {
                DLYM2R_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:10 - Delay line for first microphone of pair 2
            #[inline(always)]
            pub fn dlym2l(&self) -> DLYM2L_R {
                DLYM2L_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bits 4:6 - Delay line for second microphone of pair 1
            #[inline(always)]
            pub fn dlym1r(&self) -> DLYM1R_R {
                DLYM1R_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:2 - Delay line for first microphone of pair 1
            #[inline(always)]
            pub fn dlym1l(&self) -> DLYM1L_R {
                DLYM1L_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 28:30 - Delay line for second microphone of pair 4
            #[inline(always)]
            pub fn dlym4r(&mut self) -> DLYM4R_W {
                DLYM4R_W { w: self }
            }
            ///Bits 24:26 - Delay line for first microphone of pair 4
            #[inline(always)]
            pub fn dlym4l(&mut self) -> DLYM4L_W {
                DLYM4L_W { w: self }
            }
            ///Bits 20:22 - Delay line for second microphone of pair 3
            #[inline(always)]
            pub fn dlym3r(&mut self) -> DLYM3R_W {
                DLYM3R_W { w: self }
            }
            ///Bits 16:18 - Delay line for first microphone of pair 3
            #[inline(always)]
            pub fn dlym3l(&mut self) -> DLYM3L_W {
                DLYM3L_W { w: self }
            }
            ///Bits 12:14 - Delay line for second microphone of pair 2
            #[inline(always)]
            pub fn dlym2r(&mut self) -> DLYM2R_W {
                DLYM2R_W { w: self }
            }
            ///Bits 8:10 - Delay line for first microphone of pair 2
            #[inline(always)]
            pub fn dlym2l(&mut self) -> DLYM2L_W {
                DLYM2L_W { w: self }
            }
            ///Bits 4:6 - Delay line for second microphone of pair 1
            #[inline(always)]
            pub fn dlym1r(&mut self) -> DLYM1R_W {
                DLYM1R_W { w: self }
            }
            ///Bits 0:2 - Delay line for first microphone of pair 1
            #[inline(always)]
            pub fn dlym1l(&mut self) -> DLYM1L_W {
                DLYM1L_W { w: self }
            }
        }
    }
}
///General-purpose-timers
pub struct TIM2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM2 {}
impl TIM2 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const tim2::RegisterBlock {
        0x4000_0000 as *const _
    }
}
impl Deref for TIM2 {
    type Target = tim2::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*TIM2::ptr() }
    }
}
///General-purpose-timers
pub mod tim2 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register 1
        pub cr1: CR1,
        ///0x04 - control register 2
        pub cr2: CR2,
        ///0x08 - slave mode control register
        pub smcr: SMCR,
        ///0x0c - DMA/Interrupt enable register
        pub dier: DIER,
        ///0x10 - status register
        pub sr: SR,
        ///0x14 - event generation register
        pub egr: EGR,
        _reserved_6_ccmr1: [u8; 4usize],
        _reserved_7_ccmr2: [u8; 4usize],
        ///0x20 - capture/compare enable register
        pub ccer: CCER,
        ///0x24 - counter
        pub cnt: CNT,
        ///0x28 - prescaler
        pub psc: PSC,
        ///0x2c - auto-reload register
        pub arr: ARR,
        _reserved12: [u8; 4usize],
        ///0x34 - capture/compare register 1
        pub ccr1: CCR1,
        ///0x38 - capture/compare register 2
        pub ccr2: CCR2,
        ///0x3c - capture/compare register 3
        pub ccr3: CCR3,
        ///0x40 - capture/compare register 4
        pub ccr4: CCR4,
        _reserved16: [u8; 4usize],
        ///0x48 - DMA control register
        pub dcr: DCR,
        ///0x4c - DMA address for full transfer
        pub dmar: DMAR,
        ///0x50 - TIM2 option register
        pub or: OR,
        _reserved19: [u8; 12usize],
        ///0x60 - TIM2 alternate function option register 1
        pub af: AF,
    }
    impl RegisterBlock {
        ///0x18 - capture/compare mode register 1 (input mode)
        #[inline(always)]
        pub fn ccmr1_input(&self) -> &CCMR1_INPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_INPUT) }
        }
        ///0x18 - capture/compare mode register 1 (input mode)
        #[inline(always)]
        pub fn ccmr1_input_mut(&self) -> &mut CCMR1_INPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CCMR1_INPUT) }
        }
        ///0x18 - capture/compare mode register 1 (output mode)
        #[inline(always)]
        pub fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_OUTPUT) }
        }
        ///0x18 - capture/compare mode register 1 (output mode)
        #[inline(always)]
        pub fn ccmr1_output_mut(&self) -> &mut CCMR1_OUTPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CCMR1_OUTPUT) }
        }
        ///0x1c - capture/compare mode register 2 (input mode)
        #[inline(always)]
        pub fn ccmr2_input(&self) -> &CCMR2_INPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(28usize) as *const CCMR2_INPUT) }
        }
        ///0x1c - capture/compare mode register 2 (input mode)
        #[inline(always)]
        pub fn ccmr2_input_mut(&self) -> &mut CCMR2_INPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(28usize) as *mut CCMR2_INPUT) }
        }
        ///0x1c - capture/compare mode register 2 (output mode)
        #[inline(always)]
        pub fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(28usize) as *const CCMR2_OUTPUT) }
        }
        ///0x1c - capture/compare mode register 2 (output mode)
        #[inline(always)]
        pub fn ccmr2_output_mut(&self) -> &mut CCMR2_OUTPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(28usize) as *mut CCMR2_OUTPUT) }
        }
    }
    ///control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `UIFREMAP`
        pub type UIFREMAP_R = crate::R<bool, bool>;
        ///Write proxy for field `UIFREMAP`
        pub struct UIFREMAP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIFREMAP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CKD`
        pub type CKD_R = crate::R<u8, u8>;
        ///Write proxy for field `CKD`
        pub struct CKD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `ARPE`
        pub type ARPE_R = crate::R<bool, bool>;
        ///Write proxy for field `ARPE`
        pub struct ARPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARPE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CMS`
        pub type CMS_R = crate::R<u8, u8>;
        ///Write proxy for field `CMS`
        pub struct CMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `OPM`
        pub type OPM_R = crate::R<bool, bool>;
        ///Write proxy for field `OPM`
        pub struct OPM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `URS`
        pub type URS_R = crate::R<bool, bool>;
        ///Write proxy for field `URS`
        pub struct URS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> URS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `UDIS`
        pub type UDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `UDIS`
        pub struct UDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CEN`
        pub type CEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CEN`
        pub struct CEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 11 - UIF status bit remapping
            #[inline(always)]
            pub fn uifremap(&self) -> UIFREMAP_R {
                UIFREMAP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 8:9 - Clock division
            #[inline(always)]
            pub fn ckd(&self) -> CKD_R {
                CKD_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Auto-reload preload enable
            #[inline(always)]
            pub fn arpe(&self) -> ARPE_R {
                ARPE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 5:6 - Center-aligned mode selection
            #[inline(always)]
            pub fn cms(&self) -> CMS_R {
                CMS_R::new(((self.bits >> 5) & 0x03) as u8)
            }
            ///Bit 4 - Direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - One-pulse mode
            #[inline(always)]
            pub fn opm(&self) -> OPM_R {
                OPM_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Update request source
            #[inline(always)]
            pub fn urs(&self) -> URS_R {
                URS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Update disable
            #[inline(always)]
            pub fn udis(&self) -> UDIS_R {
                UDIS_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn cen(&self) -> CEN_R {
                CEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 11 - UIF status bit remapping
            #[inline(always)]
            pub fn uifremap(&mut self) -> UIFREMAP_W {
                UIFREMAP_W { w: self }
            }
            ///Bits 8:9 - Clock division
            #[inline(always)]
            pub fn ckd(&mut self) -> CKD_W {
                CKD_W { w: self }
            }
            ///Bit 7 - Auto-reload preload enable
            #[inline(always)]
            pub fn arpe(&mut self) -> ARPE_W {
                ARPE_W { w: self }
            }
            ///Bits 5:6 - Center-aligned mode selection
            #[inline(always)]
            pub fn cms(&mut self) -> CMS_W {
                CMS_W { w: self }
            }
            ///Bit 4 - Direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bit 3 - One-pulse mode
            #[inline(always)]
            pub fn opm(&mut self) -> OPM_W {
                OPM_W { w: self }
            }
            ///Bit 2 - Update request source
            #[inline(always)]
            pub fn urs(&mut self) -> URS_W {
                URS_W { w: self }
            }
            ///Bit 1 - Update disable
            #[inline(always)]
            pub fn udis(&mut self) -> UDIS_W {
                UDIS_W { w: self }
            }
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn cen(&mut self) -> CEN_W {
                CEN_W { w: self }
            }
        }
    }
    ///control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TI1S`
        pub type TI1S_R = crate::R<bool, bool>;
        ///Write proxy for field `TI1S`
        pub struct TI1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TI1S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `MMS`
        pub type MMS_R = crate::R<u8, u8>;
        ///Write proxy for field `MMS`
        pub struct MMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `CCDS`
        pub type CCDS_R = crate::R<bool, bool>;
        ///Write proxy for field `CCDS`
        pub struct CCDS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCDS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        impl R {
            ///Bit 7 - TI1 selection
            #[inline(always)]
            pub fn ti1s(&self) -> TI1S_R {
                TI1S_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Master mode selection
            #[inline(always)]
            pub fn mms(&self) -> MMS_R {
                MMS_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&self) -> CCDS_R {
                CCDS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 7 - TI1 selection
            #[inline(always)]
            pub fn ti1s(&mut self) -> TI1S_W {
                TI1S_W { w: self }
            }
            ///Bits 4:6 - Master mode selection
            #[inline(always)]
            pub fn mms(&mut self) -> MMS_W {
                MMS_W { w: self }
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&mut self) -> CCDS_W {
                CCDS_W { w: self }
            }
        }
    }
    ///slave mode control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [smcr](smcr) module
    pub type SMCR = crate::Reg<u32, _SMCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SMCR;
    ///`read()` method returns [smcr::R](smcr::R) reader structure
    impl crate::Readable for SMCR {}
    ///`write(|w| ..)` method takes [smcr::W](smcr::W) writer structure
    impl crate::Writable for SMCR {}
    ///slave mode control register
    pub mod smcr {
        ///Reader of register SMCR
        pub type R = crate::R<u32, super::SMCR>;
        ///Writer for register SMCR
        pub type W = crate::W<u32, super::SMCR>;
        ///Register SMCR `reset()`'s with value 0
        impl crate::ResetValue for super::SMCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SMS_3`
        pub type SMS_3_R = crate::R<bool, bool>;
        ///Write proxy for field `SMS_3`
        pub struct SMS_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMS_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `ETP`
        pub type ETP_R = crate::R<bool, bool>;
        ///Write proxy for field `ETP`
        pub struct ETP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `ECE`
        pub type ECE_R = crate::R<bool, bool>;
        ///Write proxy for field `ECE`
        pub struct ECE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ECE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `ETPS`
        pub type ETPS_R = crate::R<u8, u8>;
        ///Write proxy for field `ETPS`
        pub struct ETPS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETPS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `ETF`
        pub type ETF_R = crate::R<u8, u8>;
        ///Write proxy for field `ETF`
        pub struct ETF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `MSM`
        pub type MSM_R = crate::R<bool, bool>;
        ///Write proxy for field `MSM`
        pub struct MSM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `TS`
        pub type TS_R = crate::R<u8, u8>;
        ///Write proxy for field `TS`
        pub struct TS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OCCS`
        pub type OCCS_R = crate::R<bool, bool>;
        ///Write proxy for field `OCCS`
        pub struct OCCS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OCCS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `SMS`
        pub type SMS_R = crate::R<u8, u8>;
        ///Write proxy for field `SMS`
        pub struct SMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Slave mode selection - bit 3
            #[inline(always)]
            pub fn sms_3(&self) -> SMS_3_R {
                SMS_3_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - External trigger polarity
            #[inline(always)]
            pub fn etp(&self) -> ETP_R {
                ETP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - External clock enable
            #[inline(always)]
            pub fn ece(&self) -> ECE_R {
                ECE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - External trigger prescaler
            #[inline(always)]
            pub fn etps(&self) -> ETPS_R {
                ETPS_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bits 8:11 - External trigger filter
            #[inline(always)]
            pub fn etf(&self) -> ETF_R {
                ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bit 7 - Master/Slave mode
            #[inline(always)]
            pub fn msm(&self) -> MSM_R {
                MSM_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Trigger selection
            #[inline(always)]
            pub fn ts(&self) -> TS_R {
                TS_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - OCREF clear selection
            #[inline(always)]
            pub fn occs(&self) -> OCCS_R {
                OCCS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bits 0:2 - Slave mode selection
            #[inline(always)]
            pub fn sms(&self) -> SMS_R {
                SMS_R::new((self.bits & 0x07) as u8)
            }
        }
        impl W {
            ///Bit 16 - Slave mode selection - bit 3
            #[inline(always)]
            pub fn sms_3(&mut self) -> SMS_3_W {
                SMS_3_W { w: self }
            }
            ///Bit 15 - External trigger polarity
            #[inline(always)]
            pub fn etp(&mut self) -> ETP_W {
                ETP_W { w: self }
            }
            ///Bit 14 - External clock enable
            #[inline(always)]
            pub fn ece(&mut self) -> ECE_W {
                ECE_W { w: self }
            }
            ///Bits 12:13 - External trigger prescaler
            #[inline(always)]
            pub fn etps(&mut self) -> ETPS_W {
                ETPS_W { w: self }
            }
            ///Bits 8:11 - External trigger filter
            #[inline(always)]
            pub fn etf(&mut self) -> ETF_W {
                ETF_W { w: self }
            }
            ///Bit 7 - Master/Slave mode
            #[inline(always)]
            pub fn msm(&mut self) -> MSM_W {
                MSM_W { w: self }
            }
            ///Bits 4:6 - Trigger selection
            #[inline(always)]
            pub fn ts(&mut self) -> TS_W {
                TS_W { w: self }
            }
            ///Bit 3 - OCREF clear selection
            #[inline(always)]
            pub fn occs(&mut self) -> OCCS_W {
                OCCS_W { w: self }
            }
            ///Bits 0:2 - Slave mode selection
            #[inline(always)]
            pub fn sms(&mut self) -> SMS_W {
                SMS_W { w: self }
            }
        }
    }
    ///DMA/Interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dier](dier) module
    pub type DIER = crate::Reg<u32, _DIER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DIER;
    ///`read()` method returns [dier::R](dier::R) reader structure
    impl crate::Readable for DIER {}
    ///`write(|w| ..)` method takes [dier::W](dier::W) writer structure
    impl crate::Writable for DIER {}
    ///DMA/Interrupt enable register
    pub mod dier {
        ///Reader of register DIER
        pub type R = crate::R<u32, super::DIER>;
        ///Writer for register DIER
        pub type W = crate::W<u32, super::DIER>;
        ///Register DIER `reset()`'s with value 0
        impl crate::ResetValue for super::DIER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC4DE`
        pub type CC4DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4DE`
        pub struct CC4DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `CC3DE`
        pub type CC3DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3DE`
        pub struct CC3DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CC2DE`
        pub type CC2DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2DE`
        pub struct CC2DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CC1DE`
        pub type CC1DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1DE`
        pub struct CC1DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `UDE`
        pub type UDE_R = crate::R<bool, bool>;
        ///Write proxy for field `UDE`
        pub struct UDE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `TIE`
        pub type TIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TIE`
        pub struct TIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CC4IE`
        pub type CC4IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4IE`
        pub struct CC4IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CC3IE`
        pub type CC3IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3IE`
        pub struct CC3IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC2IE`
        pub type CC2IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2IE`
        pub struct CC2IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1IE`
        pub type CC1IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IE`
        pub struct CC1IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `UIE`
        pub type UIE_R = crate::R<bool, bool>;
        ///Write proxy for field `UIE`
        pub struct UIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 12 - Capture/Compare 4 DMA request enable
            #[inline(always)]
            pub fn cc4de(&self) -> CC4DE_R {
                CC4DE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Capture/Compare 3 DMA request enable
            #[inline(always)]
            pub fn cc3de(&self) -> CC3DE_R {
                CC3DE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Capture/Compare 2 DMA request enable
            #[inline(always)]
            pub fn cc2de(&self) -> CC2DE_R {
                CC2DE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Capture/Compare 1 DMA request enable
            #[inline(always)]
            pub fn cc1de(&self) -> CC1DE_R {
                CC1DE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Update DMA request enable
            #[inline(always)]
            pub fn ude(&self) -> UDE_R {
                UDE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 6 - Trigger interrupt enable
            #[inline(always)]
            pub fn tie(&self) -> TIE_R {
                TIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 4 - Capture/Compare 4 interrupt enable
            #[inline(always)]
            pub fn cc4ie(&self) -> CC4IE_R {
                CC4IE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Capture/Compare 3 interrupt enable
            #[inline(always)]
            pub fn cc3ie(&self) -> CC3IE_R {
                CC3IE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Capture/Compare 2 interrupt enable
            #[inline(always)]
            pub fn cc2ie(&self) -> CC2IE_R {
                CC2IE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable
            #[inline(always)]
            pub fn cc1ie(&self) -> CC1IE_R {
                CC1IE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Update interrupt enable
            #[inline(always)]
            pub fn uie(&self) -> UIE_R {
                UIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 12 - Capture/Compare 4 DMA request enable
            #[inline(always)]
            pub fn cc4de(&mut self) -> CC4DE_W {
                CC4DE_W { w: self }
            }
            ///Bit 11 - Capture/Compare 3 DMA request enable
            #[inline(always)]
            pub fn cc3de(&mut self) -> CC3DE_W {
                CC3DE_W { w: self }
            }
            ///Bit 10 - Capture/Compare 2 DMA request enable
            #[inline(always)]
            pub fn cc2de(&mut self) -> CC2DE_W {
                CC2DE_W { w: self }
            }
            ///Bit 9 - Capture/Compare 1 DMA request enable
            #[inline(always)]
            pub fn cc1de(&mut self) -> CC1DE_W {
                CC1DE_W { w: self }
            }
            ///Bit 8 - Update DMA request enable
            #[inline(always)]
            pub fn ude(&mut self) -> UDE_W {
                UDE_W { w: self }
            }
            ///Bit 6 - Trigger interrupt enable
            #[inline(always)]
            pub fn tie(&mut self) -> TIE_W {
                TIE_W { w: self }
            }
            ///Bit 4 - Capture/Compare 4 interrupt enable
            #[inline(always)]
            pub fn cc4ie(&mut self) -> CC4IE_W {
                CC4IE_W { w: self }
            }
            ///Bit 3 - Capture/Compare 3 interrupt enable
            #[inline(always)]
            pub fn cc3ie(&mut self) -> CC3IE_W {
                CC3IE_W { w: self }
            }
            ///Bit 2 - Capture/Compare 2 interrupt enable
            #[inline(always)]
            pub fn cc2ie(&mut self) -> CC2IE_W {
                CC2IE_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable
            #[inline(always)]
            pub fn cc1ie(&mut self) -> CC1IE_W {
                CC1IE_W { w: self }
            }
            ///Bit 0 - Update interrupt enable
            #[inline(always)]
            pub fn uie(&mut self) -> UIE_W {
                UIE_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC4OF`
        pub type CC4OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4OF`
        pub struct CC4OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `CC3OF`
        pub type CC3OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3OF`
        pub struct CC3OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CC2OF`
        pub type CC2OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2OF`
        pub struct CC2OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CC1OF`
        pub type CC1OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1OF`
        pub struct CC1OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `TIF`
        pub type TIF_R = crate::R<bool, bool>;
        ///Write proxy for field `TIF`
        pub struct TIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CC4IF`
        pub type CC4IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4IF`
        pub struct CC4IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CC3IF`
        pub type CC3IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3IF`
        pub struct CC3IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC2IF`
        pub type CC2IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2IF`
        pub struct CC2IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1IF`
        pub type CC1IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IF`
        pub struct CC1IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `UIF`
        pub type UIF_R = crate::R<bool, bool>;
        ///Write proxy for field `UIF`
        pub struct UIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 12 - Capture/Compare 4 overcapture flag
            #[inline(always)]
            pub fn cc4of(&self) -> CC4OF_R {
                CC4OF_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Capture/Compare 3 overcapture flag
            #[inline(always)]
            pub fn cc3of(&self) -> CC3OF_R {
                CC3OF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Capture/compare 2 overcapture flag
            #[inline(always)]
            pub fn cc2of(&self) -> CC2OF_R {
                CC2OF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&self) -> CC1OF_R {
                CC1OF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&self) -> TIF_R {
                TIF_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 4 - Capture/Compare 4 interrupt flag
            #[inline(always)]
            pub fn cc4if(&self) -> CC4IF_R {
                CC4IF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Capture/Compare 3 interrupt flag
            #[inline(always)]
            pub fn cc3if(&self) -> CC3IF_R {
                CC3IF_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Capture/Compare 2 interrupt flag
            #[inline(always)]
            pub fn cc2if(&self) -> CC2IF_R {
                CC2IF_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&self) -> CC1IF_R {
                CC1IF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&self) -> UIF_R {
                UIF_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 12 - Capture/Compare 4 overcapture flag
            #[inline(always)]
            pub fn cc4of(&mut self) -> CC4OF_W {
                CC4OF_W { w: self }
            }
            ///Bit 11 - Capture/Compare 3 overcapture flag
            #[inline(always)]
            pub fn cc3of(&mut self) -> CC3OF_W {
                CC3OF_W { w: self }
            }
            ///Bit 10 - Capture/compare 2 overcapture flag
            #[inline(always)]
            pub fn cc2of(&mut self) -> CC2OF_W {
                CC2OF_W { w: self }
            }
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&mut self) -> CC1OF_W {
                CC1OF_W { w: self }
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&mut self) -> TIF_W {
                TIF_W { w: self }
            }
            ///Bit 4 - Capture/Compare 4 interrupt flag
            #[inline(always)]
            pub fn cc4if(&mut self) -> CC4IF_W {
                CC4IF_W { w: self }
            }
            ///Bit 3 - Capture/Compare 3 interrupt flag
            #[inline(always)]
            pub fn cc3if(&mut self) -> CC3IF_W {
                CC3IF_W { w: self }
            }
            ///Bit 2 - Capture/Compare 2 interrupt flag
            #[inline(always)]
            pub fn cc2if(&mut self) -> CC2IF_W {
                CC2IF_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&mut self) -> CC1IF_W {
                CC1IF_W { w: self }
            }
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&mut self) -> UIF_W {
                UIF_W { w: self }
            }
        }
    }
    ///event generation register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [egr](egr) module
    pub type EGR = crate::Reg<u32, _EGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EGR;
    ///`write(|w| ..)` method takes [egr::W](egr::W) writer structure
    impl crate::Writable for EGR {}
    ///event generation register
    pub mod egr {
        ///Writer for register EGR
        pub type W = crate::W<u32, super::EGR>;
        ///Register EGR `reset()`'s with value 0
        impl crate::ResetValue for super::EGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `TG`
        pub struct TG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `CC4G`
        pub struct CC4G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CC3G`
        pub struct CC3G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CC2G`
        pub struct CC2G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CC1G`
        pub struct CC1G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `UG`
        pub struct UG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 6 - Trigger generation
            #[inline(always)]
            pub fn tg(&mut self) -> TG_W {
                TG_W { w: self }
            }
            ///Bit 4 - Capture/compare 4 generation
            #[inline(always)]
            pub fn cc4g(&mut self) -> CC4G_W {
                CC4G_W { w: self }
            }
            ///Bit 3 - Capture/compare 3 generation
            #[inline(always)]
            pub fn cc3g(&mut self) -> CC3G_W {
                CC3G_W { w: self }
            }
            ///Bit 2 - Capture/compare 2 generation
            #[inline(always)]
            pub fn cc2g(&mut self) -> CC2G_W {
                CC2G_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 generation
            #[inline(always)]
            pub fn cc1g(&mut self) -> CC1G_W {
                CC1G_W { w: self }
            }
            ///Bit 0 - Update generation
            #[inline(always)]
            pub fn ug(&mut self) -> UG_W {
                UG_W { w: self }
            }
        }
    }
    ///capture/compare mode register 1 (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_output](ccmr1_output) module
    pub type CCMR1_OUTPUT = crate::Reg<u32, _CCMR1_OUTPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_OUTPUT;
    ///`read()` method returns [ccmr1_output::R](ccmr1_output::R) reader structure
    impl crate::Readable for CCMR1_OUTPUT {}
    ///`write(|w| ..)` method takes [ccmr1_output::W](ccmr1_output::W) writer structure
    impl crate::Writable for CCMR1_OUTPUT {}
    ///capture/compare mode register 1 (output mode)
    pub mod ccmr1_output {
        ///Reader of register CCMR1_Output
        pub type R = crate::R<u32, super::CCMR1_OUTPUT>;
        ///Writer for register CCMR1_Output
        pub type W = crate::W<u32, super::CCMR1_OUTPUT>;
        ///Register CCMR1_Output `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_OUTPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OC2M_3`
        pub type OC2M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2M_3`
        pub struct OC2M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `OC1M_3`
        pub type OC1M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1M_3`
        pub struct OC1M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OC2CE`
        pub type OC2CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2CE`
        pub struct OC2CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OC2M`
        pub type OC2M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC2M`
        pub struct OC2M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `OC2PE`
        pub type OC2PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2PE`
        pub struct OC2PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OC2FE`
        pub type OC2FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2FE`
        pub struct OC2FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CC2S`
        pub type CC2S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC2S`
        pub struct CC2S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OC1CE`
        pub type OC1CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1CE`
        pub struct OC1CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `OC1M`
        pub type OC1M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC1M`
        pub struct OC1M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OC1PE`
        pub type OC1PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1PE`
        pub struct OC1PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OC1FE`
        pub type OC1FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1FE`
        pub struct OC1FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bit 24 - Output Compare 2 mode - bit 3
            #[inline(always)]
            pub fn oc2m_3(&self) -> OC2M_3_R {
                OC2M_3_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 16 - Output Compare 1 mode - bit 3
            #[inline(always)]
            pub fn oc1m_3(&self) -> OC1M_3_R {
                OC1M_3_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Output compare 2 clear enable
            #[inline(always)]
            pub fn oc2ce(&self) -> OC2CE_R {
                OC2CE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 12:14 - Output compare 2 mode
            #[inline(always)]
            pub fn oc2m(&self) -> OC2M_R {
                OC2M_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bit 11 - Output compare 2 preload enable
            #[inline(always)]
            pub fn oc2pe(&self) -> OC2PE_R {
                OC2PE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Output compare 2 fast enable
            #[inline(always)]
            pub fn oc2fe(&self) -> OC2FE_R {
                OC2FE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bits 8:9 - Capture/Compare 2 selection
            #[inline(always)]
            pub fn cc2s(&self) -> CC2S_R {
                CC2S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Output compare 1 clear enable
            #[inline(always)]
            pub fn oc1ce(&self) -> OC1CE_R {
                OC1CE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Output compare 1 mode
            #[inline(always)]
            pub fn oc1m(&self) -> OC1M_R {
                OC1M_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Output compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&self) -> OC1PE_R {
                OC1PE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Output compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&self) -> OC1FE_R {
                OC1FE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 24 - Output Compare 2 mode - bit 3
            #[inline(always)]
            pub fn oc2m_3(&mut self) -> OC2M_3_W {
                OC2M_3_W { w: self }
            }
            ///Bit 16 - Output Compare 1 mode - bit 3
            #[inline(always)]
            pub fn oc1m_3(&mut self) -> OC1M_3_W {
                OC1M_3_W { w: self }
            }
            ///Bit 15 - Output compare 2 clear enable
            #[inline(always)]
            pub fn oc2ce(&mut self) -> OC2CE_W {
                OC2CE_W { w: self }
            }
            ///Bits 12:14 - Output compare 2 mode
            #[inline(always)]
            pub fn oc2m(&mut self) -> OC2M_W {
                OC2M_W { w: self }
            }
            ///Bit 11 - Output compare 2 preload enable
            #[inline(always)]
            pub fn oc2pe(&mut self) -> OC2PE_W {
                OC2PE_W { w: self }
            }
            ///Bit 10 - Output compare 2 fast enable
            #[inline(always)]
            pub fn oc2fe(&mut self) -> OC2FE_W {
                OC2FE_W { w: self }
            }
            ///Bits 8:9 - Capture/Compare 2 selection
            #[inline(always)]
            pub fn cc2s(&mut self) -> CC2S_W {
                CC2S_W { w: self }
            }
            ///Bit 7 - Output compare 1 clear enable
            #[inline(always)]
            pub fn oc1ce(&mut self) -> OC1CE_W {
                OC1CE_W { w: self }
            }
            ///Bits 4:6 - Output compare 1 mode
            #[inline(always)]
            pub fn oc1m(&mut self) -> OC1M_W {
                OC1M_W { w: self }
            }
            ///Bit 3 - Output compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&mut self) -> OC1PE_W {
                OC1PE_W { w: self }
            }
            ///Bit 2 - Output compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&mut self) -> OC1FE_W {
                OC1FE_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
        }
    }
    ///capture/compare mode register 1 (input mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_input](ccmr1_input) module
    pub type CCMR1_INPUT = crate::Reg<u32, _CCMR1_INPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_INPUT;
    ///`read()` method returns [ccmr1_input::R](ccmr1_input::R) reader structure
    impl crate::Readable for CCMR1_INPUT {}
    ///`write(|w| ..)` method takes [ccmr1_input::W](ccmr1_input::W) writer structure
    impl crate::Writable for CCMR1_INPUT {}
    ///capture/compare mode register 1 (input mode)
    pub mod ccmr1_input {
        ///Reader of register CCMR1_Input
        pub type R = crate::R<u32, super::CCMR1_INPUT>;
        ///Writer for register CCMR1_Input
        pub type W = crate::W<u32, super::CCMR1_INPUT>;
        ///Register CCMR1_Input `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_INPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `IC2F`
        pub type IC2F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC2F`
        pub struct IC2F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC2F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `IC2PSC`
        pub type IC2PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC2PSC`
        pub struct IC2PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC2PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `CC2S`
        pub type CC2S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC2S`
        pub struct CC2S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `IC1F`
        pub type IC1F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC1F`
        pub struct IC1F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC1F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `IC1PSC`
        pub type IC1PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC1PSC`
        pub struct IC1PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC1PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 12:15 - Input capture 2 filter
            #[inline(always)]
            pub fn ic2f(&self) -> IC2F_R {
                IC2F_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 10:11 - Input capture 2 prescaler
            #[inline(always)]
            pub fn ic2psc(&self) -> IC2PSC_R {
                IC2PSC_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Capture/compare 2 selection
            #[inline(always)]
            pub fn cc2s(&self) -> CC2S_R {
                CC2S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn ic1f(&self) -> IC1F_R {
                IC1F_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&self) -> IC1PSC_R {
                IC1PSC_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 12:15 - Input capture 2 filter
            #[inline(always)]
            pub fn ic2f(&mut self) -> IC2F_W {
                IC2F_W { w: self }
            }
            ///Bits 10:11 - Input capture 2 prescaler
            #[inline(always)]
            pub fn ic2psc(&mut self) -> IC2PSC_W {
                IC2PSC_W { w: self }
            }
            ///Bits 8:9 - Capture/compare 2 selection
            #[inline(always)]
            pub fn cc2s(&mut self) -> CC2S_W {
                CC2S_W { w: self }
            }
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn ic1f(&mut self) -> IC1F_W {
                IC1F_W { w: self }
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&mut self) -> IC1PSC_W {
                IC1PSC_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
        }
    }
    ///capture/compare mode register 2 (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr2_output](ccmr2_output) module
    pub type CCMR2_OUTPUT = crate::Reg<u32, _CCMR2_OUTPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR2_OUTPUT;
    ///`read()` method returns [ccmr2_output::R](ccmr2_output::R) reader structure
    impl crate::Readable for CCMR2_OUTPUT {}
    ///`write(|w| ..)` method takes [ccmr2_output::W](ccmr2_output::W) writer structure
    impl crate::Writable for CCMR2_OUTPUT {}
    ///capture/compare mode register 2 (output mode)
    pub mod ccmr2_output {
        ///Reader of register CCMR2_Output
        pub type R = crate::R<u32, super::CCMR2_OUTPUT>;
        ///Writer for register CCMR2_Output
        pub type W = crate::W<u32, super::CCMR2_OUTPUT>;
        ///Register CCMR2_Output `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR2_OUTPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OC4M_3`
        pub type OC4M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4M_3`
        pub struct OC4M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `OC3M_3`
        pub type OC3M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3M_3`
        pub struct OC3M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OC4CE`
        pub type OC4CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4CE`
        pub struct OC4CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OC4M`
        pub type OC4M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC4M`
        pub struct OC4M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `OC4PE`
        pub type OC4PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4PE`
        pub struct OC4PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OC4FE`
        pub type OC4FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4FE`
        pub struct OC4FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CC4S`
        pub type CC4S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC4S`
        pub struct CC4S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OC3CE`
        pub type OC3CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3CE`
        pub struct OC3CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `OC3M`
        pub type OC3M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC3M`
        pub struct OC3M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OC3PE`
        pub type OC3PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3PE`
        pub struct OC3PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OC3FE`
        pub type OC3FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3FE`
        pub struct OC3FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC3S`
        pub type CC3S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC3S`
        pub struct CC3S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bit 24 - Output Compare 4 mode - bit 3
            #[inline(always)]
            pub fn oc4m_3(&self) -> OC4M_3_R {
                OC4M_3_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 16 - Output Compare 3 mode - bit 3
            #[inline(always)]
            pub fn oc3m_3(&self) -> OC3M_3_R {
                OC3M_3_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Output compare 4 clear enable
            #[inline(always)]
            pub fn oc4ce(&self) -> OC4CE_R {
                OC4CE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 12:14 - Output compare 4 mode
            #[inline(always)]
            pub fn oc4m(&self) -> OC4M_R {
                OC4M_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bit 11 - Output compare 4 preload enable
            #[inline(always)]
            pub fn oc4pe(&self) -> OC4PE_R {
                OC4PE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Output compare 4 fast enable
            #[inline(always)]
            pub fn oc4fe(&self) -> OC4FE_R {
                OC4FE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&self) -> CC4S_R {
                CC4S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 7 - Output compare 3 clear enable
            #[inline(always)]
            pub fn oc3ce(&self) -> OC3CE_R {
                OC3CE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Output compare 3 mode
            #[inline(always)]
            pub fn oc3m(&self) -> OC3M_R {
                OC3M_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Output compare 3 preload enable
            #[inline(always)]
            pub fn oc3pe(&self) -> OC3PE_R {
                OC3PE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Output compare 3 fast enable
            #[inline(always)]
            pub fn oc3fe(&self) -> OC3FE_R {
                OC3FE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&self) -> CC3S_R {
                CC3S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 24 - Output Compare 4 mode - bit 3
            #[inline(always)]
            pub fn oc4m_3(&mut self) -> OC4M_3_W {
                OC4M_3_W { w: self }
            }
            ///Bit 16 - Output Compare 3 mode - bit 3
            #[inline(always)]
            pub fn oc3m_3(&mut self) -> OC3M_3_W {
                OC3M_3_W { w: self }
            }
            ///Bit 15 - Output compare 4 clear enable
            #[inline(always)]
            pub fn oc4ce(&mut self) -> OC4CE_W {
                OC4CE_W { w: self }
            }
            ///Bits 12:14 - Output compare 4 mode
            #[inline(always)]
            pub fn oc4m(&mut self) -> OC4M_W {
                OC4M_W { w: self }
            }
            ///Bit 11 - Output compare 4 preload enable
            #[inline(always)]
            pub fn oc4pe(&mut self) -> OC4PE_W {
                OC4PE_W { w: self }
            }
            ///Bit 10 - Output compare 4 fast enable
            #[inline(always)]
            pub fn oc4fe(&mut self) -> OC4FE_W {
                OC4FE_W { w: self }
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&mut self) -> CC4S_W {
                CC4S_W { w: self }
            }
            ///Bit 7 - Output compare 3 clear enable
            #[inline(always)]
            pub fn oc3ce(&mut self) -> OC3CE_W {
                OC3CE_W { w: self }
            }
            ///Bits 4:6 - Output compare 3 mode
            #[inline(always)]
            pub fn oc3m(&mut self) -> OC3M_W {
                OC3M_W { w: self }
            }
            ///Bit 3 - Output compare 3 preload enable
            #[inline(always)]
            pub fn oc3pe(&mut self) -> OC3PE_W {
                OC3PE_W { w: self }
            }
            ///Bit 2 - Output compare 3 fast enable
            #[inline(always)]
            pub fn oc3fe(&mut self) -> OC3FE_W {
                OC3FE_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&mut self) -> CC3S_W {
                CC3S_W { w: self }
            }
        }
    }
    ///capture/compare mode register 2 (input mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr2_input](ccmr2_input) module
    pub type CCMR2_INPUT = crate::Reg<u32, _CCMR2_INPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR2_INPUT;
    ///`read()` method returns [ccmr2_input::R](ccmr2_input::R) reader structure
    impl crate::Readable for CCMR2_INPUT {}
    ///`write(|w| ..)` method takes [ccmr2_input::W](ccmr2_input::W) writer structure
    impl crate::Writable for CCMR2_INPUT {}
    ///capture/compare mode register 2 (input mode)
    pub mod ccmr2_input {
        ///Reader of register CCMR2_Input
        pub type R = crate::R<u32, super::CCMR2_INPUT>;
        ///Writer for register CCMR2_Input
        pub type W = crate::W<u32, super::CCMR2_INPUT>;
        ///Register CCMR2_Input `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR2_INPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `IC4F`
        pub type IC4F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC4F`
        pub struct IC4F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC4F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        ///Reader of field `IC4PSC`
        pub type IC4PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC4PSC`
        pub struct IC4PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC4PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `CC4S`
        pub type CC4S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC4S`
        pub struct CC4S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `IC3F`
        pub type IC3F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC3F`
        pub struct IC3F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC3F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `IC3PSC`
        pub type IC3PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC3PSC`
        pub struct IC3PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC3PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `CC3S`
        pub type CC3S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC3S`
        pub struct CC3S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 12:15 - Input capture 4 filter
            #[inline(always)]
            pub fn ic4f(&self) -> IC4F_R {
                IC4F_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            ///Bits 10:11 - Input capture 4 prescaler
            #[inline(always)]
            pub fn ic4psc(&self) -> IC4PSC_R {
                IC4PSC_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&self) -> CC4S_R {
                CC4S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 4:7 - Input capture 3 filter
            #[inline(always)]
            pub fn ic3f(&self) -> IC3F_R {
                IC3F_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 2:3 - Input capture 3 prescaler
            #[inline(always)]
            pub fn ic3psc(&self) -> IC3PSC_R {
                IC3PSC_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&self) -> CC3S_R {
                CC3S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 12:15 - Input capture 4 filter
            #[inline(always)]
            pub fn ic4f(&mut self) -> IC4F_W {
                IC4F_W { w: self }
            }
            ///Bits 10:11 - Input capture 4 prescaler
            #[inline(always)]
            pub fn ic4psc(&mut self) -> IC4PSC_W {
                IC4PSC_W { w: self }
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&mut self) -> CC4S_W {
                CC4S_W { w: self }
            }
            ///Bits 4:7 - Input capture 3 filter
            #[inline(always)]
            pub fn ic3f(&mut self) -> IC3F_W {
                IC3F_W { w: self }
            }
            ///Bits 2:3 - Input capture 3 prescaler
            #[inline(always)]
            pub fn ic3psc(&mut self) -> IC3PSC_W {
                IC3PSC_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&mut self) -> CC3S_W {
                CC3S_W { w: self }
            }
        }
    }
    ///capture/compare enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccer](ccer) module
    pub type CCER = crate::Reg<u32, _CCER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCER;
    ///`read()` method returns [ccer::R](ccer::R) reader structure
    impl crate::Readable for CCER {}
    ///`write(|w| ..)` method takes [ccer::W](ccer::W) writer structure
    impl crate::Writable for CCER {}
    ///capture/compare enable register
    pub mod ccer {
        ///Reader of register CCER
        pub type R = crate::R<u32, super::CCER>;
        ///Writer for register CCER
        pub type W = crate::W<u32, super::CCER>;
        ///Register CCER `reset()`'s with value 0
        impl crate::ResetValue for super::CCER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC4NP`
        pub type CC4NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4NP`
        pub struct CC4NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `CC4P`
        pub type CC4P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4P`
        pub struct CC4P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `CC4E`
        pub type CC4E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4E`
        pub struct CC4E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `CC3NP`
        pub type CC3NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3NP`
        pub struct CC3NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CC3P`
        pub type CC3P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3P`
        pub struct CC3P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `CC3E`
        pub type CC3E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3E`
        pub struct CC3E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CC2NP`
        pub type CC2NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2NP`
        pub struct CC2NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CC2P`
        pub type CC2P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2P`
        pub struct CC2P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `CC2E`
        pub type CC2E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2E`
        pub struct CC2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CC1NP`
        pub type CC1NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1NP`
        pub struct CC1NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC1P`
        pub type CC1P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1P`
        pub struct CC1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CC1E`
        pub type CC1E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1E`
        pub struct CC1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Capture/Compare 4 output Polarity
            #[inline(always)]
            pub fn cc4np(&self) -> CC4NP_R {
                CC4NP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 13 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc4p(&self) -> CC4P_R {
                CC4P_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Capture/Compare 4 output enable
            #[inline(always)]
            pub fn cc4e(&self) -> CC4E_R {
                CC4E_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3np(&self) -> CC3NP_R {
                CC3NP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 9 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3p(&self) -> CC3P_R {
                CC3P_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Capture/Compare 3 output enable
            #[inline(always)]
            pub fn cc3e(&self) -> CC3E_R {
                CC3E_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2np(&self) -> CC2NP_R {
                CC2NP_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 5 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2p(&self) -> CC2P_R {
                CC2P_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Capture/Compare 2 output enable
            #[inline(always)]
            pub fn cc2e(&self) -> CC2E_R {
                CC2E_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&self) -> CC1NP_R {
                CC1NP_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&self) -> CC1P_R {
                CC1P_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&self) -> CC1E_R {
                CC1E_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Capture/Compare 4 output Polarity
            #[inline(always)]
            pub fn cc4np(&mut self) -> CC4NP_W {
                CC4NP_W { w: self }
            }
            ///Bit 13 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc4p(&mut self) -> CC4P_W {
                CC4P_W { w: self }
            }
            ///Bit 12 - Capture/Compare 4 output enable
            #[inline(always)]
            pub fn cc4e(&mut self) -> CC4E_W {
                CC4E_W { w: self }
            }
            ///Bit 11 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3np(&mut self) -> CC3NP_W {
                CC3NP_W { w: self }
            }
            ///Bit 9 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3p(&mut self) -> CC3P_W {
                CC3P_W { w: self }
            }
            ///Bit 8 - Capture/Compare 3 output enable
            #[inline(always)]
            pub fn cc3e(&mut self) -> CC3E_W {
                CC3E_W { w: self }
            }
            ///Bit 7 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2np(&mut self) -> CC2NP_W {
                CC2NP_W { w: self }
            }
            ///Bit 5 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2p(&mut self) -> CC2P_W {
                CC2P_W { w: self }
            }
            ///Bit 4 - Capture/Compare 2 output enable
            #[inline(always)]
            pub fn cc2e(&mut self) -> CC2E_W {
                CC2E_W { w: self }
            }
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&mut self) -> CC1NP_W {
                CC1NP_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&mut self) -> CC1P_W {
                CC1P_W { w: self }
            }
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&mut self) -> CC1E_W {
                CC1E_W { w: self }
            }
        }
    }
    ///counter
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cnt](cnt) module
    pub type CNT = crate::Reg<u32, _CNT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNT;
    ///`read()` method returns [cnt::R](cnt::R) reader structure
    impl crate::Readable for CNT {}
    ///`write(|w| ..)` method takes [cnt::W](cnt::W) writer structure
    impl crate::Writable for CNT {}
    ///counter
    pub mod cnt {
        ///Reader of register CNT
        pub type R = crate::R<u32, super::CNT>;
        ///Writer for register CNT
        pub type W = crate::W<u32, super::CNT>;
        ///Register CNT `reset()`'s with value 0
        impl crate::ResetValue for super::CNT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CNT_H`
        pub type CNT_H_R = crate::R<u16, u16>;
        ///Write proxy for field `CNT_H`
        pub struct CNT_H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CNT_H_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 16)) | (((value as u32) & 0x7fff) << 16);
                self.w
            }
        }
        ///Reader of field `CNT_L`
        pub type CNT_L_R = crate::R<u16, u16>;
        ///Write proxy for field `CNT_L`
        pub struct CNT_L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CNT_L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `UIFCPY`
        pub type UIFCPY_R = crate::R<bool, bool>;
        impl R {
            ///Bits 16:30 - High counter value (TIM2 only)
            #[inline(always)]
            pub fn cnt_h(&self) -> CNT_H_R {
                CNT_H_R::new(((self.bits >> 16) & 0x7fff) as u16)
            }
            ///Bits 0:15 - Low counter value
            #[inline(always)]
            pub fn cnt_l(&self) -> CNT_L_R {
                CNT_L_R::new((self.bits & 0xffff) as u16)
            }
            ///Bit 31 - Value depends on IUFREMAP in TIM2_CR1.
            #[inline(always)]
            pub fn uifcpy(&self) -> UIFCPY_R {
                UIFCPY_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 16:30 - High counter value (TIM2 only)
            #[inline(always)]
            pub fn cnt_h(&mut self) -> CNT_H_W {
                CNT_H_W { w: self }
            }
            ///Bits 0:15 - Low counter value
            #[inline(always)]
            pub fn cnt_l(&mut self) -> CNT_L_W {
                CNT_L_W { w: self }
            }
        }
    }
    ///prescaler
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [psc](psc) module
    pub type PSC = crate::Reg<u32, _PSC>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PSC;
    ///`read()` method returns [psc::R](psc::R) reader structure
    impl crate::Readable for PSC {}
    ///`write(|w| ..)` method takes [psc::W](psc::W) writer structure
    impl crate::Writable for PSC {}
    ///prescaler
    pub mod psc {
        ///Reader of register PSC
        pub type R = crate::R<u32, super::PSC>;
        ///Writer for register PSC
        pub type W = crate::W<u32, super::PSC>;
        ///Register PSC `reset()`'s with value 0
        impl crate::ResetValue for super::PSC {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PSC`
        pub type PSC_R = crate::R<u16, u16>;
        ///Write proxy for field `PSC`
        pub struct PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&self) -> PSC_R {
                PSC_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&mut self) -> PSC_W {
                PSC_W { w: self }
            }
        }
    }
    ///auto-reload register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [arr](arr) module
    pub type ARR = crate::Reg<u32, _ARR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ARR;
    ///`read()` method returns [arr::R](arr::R) reader structure
    impl crate::Readable for ARR {}
    ///`write(|w| ..)` method takes [arr::W](arr::W) writer structure
    impl crate::Writable for ARR {}
    ///auto-reload register
    pub mod arr {
        ///Reader of register ARR
        pub type R = crate::R<u32, super::ARR>;
        ///Writer for register ARR
        pub type W = crate::W<u32, super::ARR>;
        ///Register ARR `reset()`'s with value 0
        impl crate::ResetValue for super::ARR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ARR_H`
        pub type ARR_H_R = crate::R<u16, u16>;
        ///Write proxy for field `ARR_H`
        pub struct ARR_H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARR_H_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                self.w
            }
        }
        ///Reader of field `ARR_L`
        pub type ARR_L_R = crate::R<u16, u16>;
        ///Write proxy for field `ARR_L`
        pub struct ARR_L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARR_L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 16:31 - High Auto-reload value (TIM2 only)
            #[inline(always)]
            pub fn arr_h(&self) -> ARR_H_R {
                ARR_H_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
            ///Bits 0:15 - Low Auto-reload value
            #[inline(always)]
            pub fn arr_l(&self) -> ARR_L_R {
                ARR_L_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 16:31 - High Auto-reload value (TIM2 only)
            #[inline(always)]
            pub fn arr_h(&mut self) -> ARR_H_W {
                ARR_H_W { w: self }
            }
            ///Bits 0:15 - Low Auto-reload value
            #[inline(always)]
            pub fn arr_l(&mut self) -> ARR_L_W {
                ARR_L_W { w: self }
            }
        }
    }
    ///capture/compare register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr1](ccr1) module
    pub type CCR1 = crate::Reg<u32, _CCR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR1;
    ///`read()` method returns [ccr1::R](ccr1::R) reader structure
    impl crate::Readable for CCR1 {}
    ///`write(|w| ..)` method takes [ccr1::W](ccr1::W) writer structure
    impl crate::Writable for CCR1 {}
    ///capture/compare register 1
    pub mod ccr1 {
        ///Reader of register CCR1
        pub type R = crate::R<u32, super::CCR1>;
        ///Writer for register CCR1
        pub type W = crate::W<u32, super::CCR1>;
        ///Register CCR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR1_H`
        pub type CCR1_H_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR1_H`
        pub struct CCR1_H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR1_H_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                self.w
            }
        }
        ///Reader of field `CCR1_L`
        pub type CCR1_L_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR1_L`
        pub struct CCR1_L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR1_L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
            #[inline(always)]
            pub fn ccr1_h(&self) -> CCR1_H_R {
                CCR1_H_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
            ///Bits 0:15 - Low Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1_l(&self) -> CCR1_L_R {
                CCR1_L_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
            #[inline(always)]
            pub fn ccr1_h(&mut self) -> CCR1_H_W {
                CCR1_H_W { w: self }
            }
            ///Bits 0:15 - Low Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1_l(&mut self) -> CCR1_L_W {
                CCR1_L_W { w: self }
            }
        }
    }
    ///capture/compare register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr2](ccr2) module
    pub type CCR2 = crate::Reg<u32, _CCR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR2;
    ///`read()` method returns [ccr2::R](ccr2::R) reader structure
    impl crate::Readable for CCR2 {}
    ///`write(|w| ..)` method takes [ccr2::W](ccr2::W) writer structure
    impl crate::Writable for CCR2 {}
    ///capture/compare register 2
    pub mod ccr2 {
        ///Reader of register CCR2
        pub type R = crate::R<u32, super::CCR2>;
        ///Writer for register CCR2
        pub type W = crate::W<u32, super::CCR2>;
        ///Register CCR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR2_H`
        pub type CCR2_H_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR2_H`
        pub struct CCR2_H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR2_H_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                self.w
            }
        }
        ///Reader of field `CCR2_L`
        pub type CCR2_L_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR2_L`
        pub struct CCR2_L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR2_L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 16:31 - High Capture/Compare 2 value (TIM2 only)
            #[inline(always)]
            pub fn ccr2_h(&self) -> CCR2_H_R {
                CCR2_H_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
            ///Bits 0:15 - Low Capture/Compare 2 value
            #[inline(always)]
            pub fn ccr2_l(&self) -> CCR2_L_R {
                CCR2_L_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 16:31 - High Capture/Compare 2 value (TIM2 only)
            #[inline(always)]
            pub fn ccr2_h(&mut self) -> CCR2_H_W {
                CCR2_H_W { w: self }
            }
            ///Bits 0:15 - Low Capture/Compare 2 value
            #[inline(always)]
            pub fn ccr2_l(&mut self) -> CCR2_L_W {
                CCR2_L_W { w: self }
            }
        }
    }
    ///capture/compare register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr3](ccr3) module
    pub type CCR3 = crate::Reg<u32, _CCR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR3;
    ///`read()` method returns [ccr3::R](ccr3::R) reader structure
    impl crate::Readable for CCR3 {}
    ///`write(|w| ..)` method takes [ccr3::W](ccr3::W) writer structure
    impl crate::Writable for CCR3 {}
    ///capture/compare register 3
    pub mod ccr3 {
        ///Reader of register CCR3
        pub type R = crate::R<u32, super::CCR3>;
        ///Writer for register CCR3
        pub type W = crate::W<u32, super::CCR3>;
        ///Register CCR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR3_H`
        pub type CCR3_H_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR3_H`
        pub struct CCR3_H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR3_H_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                self.w
            }
        }
        ///Reader of field `CCR3_L`
        pub type CCR3_L_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR3_L`
        pub struct CCR3_L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR3_L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 16:31 - High Capture/Compare value (TIM2 only)
            #[inline(always)]
            pub fn ccr3_h(&self) -> CCR3_H_R {
                CCR3_H_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
            ///Bits 0:15 - Low Capture/Compare value
            #[inline(always)]
            pub fn ccr3_l(&self) -> CCR3_L_R {
                CCR3_L_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 16:31 - High Capture/Compare value (TIM2 only)
            #[inline(always)]
            pub fn ccr3_h(&mut self) -> CCR3_H_W {
                CCR3_H_W { w: self }
            }
            ///Bits 0:15 - Low Capture/Compare value
            #[inline(always)]
            pub fn ccr3_l(&mut self) -> CCR3_L_W {
                CCR3_L_W { w: self }
            }
        }
    }
    ///capture/compare register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr4](ccr4) module
    pub type CCR4 = crate::Reg<u32, _CCR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR4;
    ///`read()` method returns [ccr4::R](ccr4::R) reader structure
    impl crate::Readable for CCR4 {}
    ///`write(|w| ..)` method takes [ccr4::W](ccr4::W) writer structure
    impl crate::Writable for CCR4 {}
    ///capture/compare register 4
    pub mod ccr4 {
        ///Reader of register CCR4
        pub type R = crate::R<u32, super::CCR4>;
        ///Writer for register CCR4
        pub type W = crate::W<u32, super::CCR4>;
        ///Register CCR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR4_H`
        pub type CCR4_H_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR4_H`
        pub struct CCR4_H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR4_H_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
                self.w
            }
        }
        ///Reader of field `CCR4_L`
        pub type CCR4_L_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR4_L`
        pub struct CCR4_L_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR4_L_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 16:31 - High Capture/Compare value (TIM2 only)
            #[inline(always)]
            pub fn ccr4_h(&self) -> CCR4_H_R {
                CCR4_H_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
            ///Bits 0:15 - Low Capture/Compare value
            #[inline(always)]
            pub fn ccr4_l(&self) -> CCR4_L_R {
                CCR4_L_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 16:31 - High Capture/Compare value (TIM2 only)
            #[inline(always)]
            pub fn ccr4_h(&mut self) -> CCR4_H_W {
                CCR4_H_W { w: self }
            }
            ///Bits 0:15 - Low Capture/Compare value
            #[inline(always)]
            pub fn ccr4_l(&mut self) -> CCR4_L_W {
                CCR4_L_W { w: self }
            }
        }
    }
    ///DMA control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dcr](dcr) module
    pub type DCR = crate::Reg<u32, _DCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DCR;
    ///`read()` method returns [dcr::R](dcr::R) reader structure
    impl crate::Readable for DCR {}
    ///`write(|w| ..)` method takes [dcr::W](dcr::W) writer structure
    impl crate::Writable for DCR {}
    ///DMA control register
    pub mod dcr {
        ///Reader of register DCR
        pub type R = crate::R<u32, super::DCR>;
        ///Writer for register DCR
        pub type W = crate::W<u32, super::DCR>;
        ///Register DCR `reset()`'s with value 0
        impl crate::ResetValue for super::DCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBL`
        pub type DBL_R = crate::R<u8, u8>;
        ///Write proxy for field `DBL`
        pub struct DBL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8);
                self.w
            }
        }
        ///Reader of field `DBA`
        pub type DBA_R = crate::R<u8, u8>;
        ///Write proxy for field `DBA`
        pub struct DBA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&self) -> DBL_R {
                DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&self) -> DBA_R {
                DBA_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&mut self) -> DBL_W {
                DBL_W { w: self }
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&mut self) -> DBA_W {
                DBA_W { w: self }
            }
        }
    }
    ///DMA address for full transfer
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dmar](dmar) module
    pub type DMAR = crate::Reg<u32, _DMAR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DMAR;
    ///`read()` method returns [dmar::R](dmar::R) reader structure
    impl crate::Readable for DMAR {}
    ///`write(|w| ..)` method takes [dmar::W](dmar::W) writer structure
    impl crate::Writable for DMAR {}
    ///DMA address for full transfer
    pub mod dmar {
        ///Reader of register DMAR
        pub type R = crate::R<u32, super::DMAR>;
        ///Writer for register DMAR
        pub type W = crate::W<u32, super::DMAR>;
        ///Register DMAR `reset()`'s with value 0
        impl crate::ResetValue for super::DMAR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DMAB`
        pub type DMAB_R = crate::R<u16, u16>;
        ///Write proxy for field `DMAB`
        pub struct DMAB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&self) -> DMAB_R {
                DMAB_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&mut self) -> DMAB_W {
                DMAB_W { w: self }
            }
        }
    }
    ///TIM2 option register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [or](or) module
    pub type OR = crate::Reg<u32, _OR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OR;
    ///`read()` method returns [or::R](or::R) reader structure
    impl crate::Readable for OR {}
    ///`write(|w| ..)` method takes [or::W](or::W) writer structure
    impl crate::Writable for OR {}
    ///TIM2 option register
    pub mod or {
        ///Reader of register OR
        pub type R = crate::R<u32, super::OR>;
        ///Writer for register OR
        pub type W = crate::W<u32, super::OR>;
        ///Register OR `reset()`'s with value 0
        impl crate::ResetValue for super::OR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TI4_RMP`
        pub type TI4_RMP_R = crate::R<u8, u8>;
        ///Write proxy for field `TI4_RMP`
        pub struct TI4_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TI4_RMP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `ETR_RMP`
        pub type ETR_RMP_R = crate::R<bool, bool>;
        ///Write proxy for field `ETR_RMP`
        pub struct ETR_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETR_RMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ITR_RMP`
        pub type ITR_RMP_R = crate::R<bool, bool>;
        ///Write proxy for field `ITR_RMP`
        pub struct ITR_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ITR_RMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 2:3 - Input capture 4 remap
            #[inline(always)]
            pub fn ti4_rmp(&self) -> TI4_RMP_R {
                TI4_RMP_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bit 1 - External trigger remap
            #[inline(always)]
            pub fn etr_rmp(&self) -> ETR_RMP_R {
                ETR_RMP_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Internal trigger remap
            #[inline(always)]
            pub fn itr_rmp(&self) -> ITR_RMP_R {
                ITR_RMP_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 2:3 - Input capture 4 remap
            #[inline(always)]
            pub fn ti4_rmp(&mut self) -> TI4_RMP_W {
                TI4_RMP_W { w: self }
            }
            ///Bit 1 - External trigger remap
            #[inline(always)]
            pub fn etr_rmp(&mut self) -> ETR_RMP_W {
                ETR_RMP_W { w: self }
            }
            ///Bit 0 - Internal trigger remap
            #[inline(always)]
            pub fn itr_rmp(&mut self) -> ITR_RMP_W {
                ITR_RMP_W { w: self }
            }
        }
    }
    ///TIM2 alternate function option register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [af](af) module
    pub type AF = crate::Reg<u32, _AF>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AF;
    ///`read()` method returns [af::R](af::R) reader structure
    impl crate::Readable for AF {}
    ///`write(|w| ..)` method takes [af::W](af::W) writer structure
    impl crate::Writable for AF {}
    ///TIM2 alternate function option register 1
    pub mod af {
        ///Reader of register AF
        pub type R = crate::R<u32, super::AF>;
        ///Writer for register AF
        pub type W = crate::W<u32, super::AF>;
        ///Register AF `reset()`'s with value 0
        impl crate::ResetValue for super::AF {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ETRSEL`
        pub type ETRSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `ETRSEL`
        pub struct ETRSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETRSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 14)) | (((value as u32) & 0x07) << 14);
                self.w
            }
        }
        impl R {
            ///Bits 14:16 - External trigger source selection
            #[inline(always)]
            pub fn etrsel(&self) -> ETRSEL_R {
                ETRSEL_R::new(((self.bits >> 14) & 0x07) as u8)
            }
        }
        impl W {
            ///Bits 14:16 - External trigger source selection
            #[inline(always)]
            pub fn etrsel(&mut self) -> ETRSEL_W {
                ETRSEL_W { w: self }
            }
        }
    }
}
///General purpose timers
pub struct TIM16 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM16 {}
impl TIM16 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const tim16::RegisterBlock {
        0x4001_4400 as *const _
    }
}
impl Deref for TIM16 {
    type Target = tim16::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*TIM16::ptr() }
    }
}
///General purpose timers
pub mod tim16 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register 1
        pub cr1: CR1,
        ///0x04 - control register 2
        pub cr2: CR2,
        _reserved2: [u8; 4usize],
        ///0x0c - DMA/Interrupt enable register
        pub dier: DIER,
        ///0x10 - status register
        pub sr: SR,
        ///0x14 - event generation register
        pub egr: EGR,
        _reserved_5_ccmr1: [u8; 4usize],
        _reserved6: [u8; 4usize],
        ///0x20 - capture/compare enable register
        pub ccer: CCER,
        ///0x24 - counter
        pub cnt: CNT,
        ///0x28 - prescaler
        pub psc: PSC,
        ///0x2c - auto-reload register
        pub arr: ARR,
        ///0x30 - repetition counter register
        pub rcr: RCR,
        ///0x34 - capture/compare register 1
        pub ccr1: CCR1,
        _reserved12: [u8; 12usize],
        ///0x44 - break and dead-time register
        pub bdtr: BDTR,
        ///0x48 - DMA control register
        pub dcr: DCR,
        ///0x4c - DMA address for full transfer
        pub dmar: DMAR,
        ///0x50 - TIM16 option register 1
        pub or: OR,
        _reserved16: [u8; 12usize],
        ///0x60 - TIM17 option register 1
        pub af1: AF1,
    }
    impl RegisterBlock {
        ///0x18 - capture/compare mode register 1 (input mode)
        #[inline(always)]
        pub fn ccmr1_input(&self) -> &CCMR1_INPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_INPUT) }
        }
        ///0x18 - capture/compare mode register 1 (input mode)
        #[inline(always)]
        pub fn ccmr1_input_mut(&self) -> &mut CCMR1_INPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CCMR1_INPUT) }
        }
        ///0x18 - capture/compare mode register (output mode)
        #[inline(always)]
        pub fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_OUTPUT) }
        }
        ///0x18 - capture/compare mode register (output mode)
        #[inline(always)]
        pub fn ccmr1_output_mut(&self) -> &mut CCMR1_OUTPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CCMR1_OUTPUT) }
        }
    }
    ///control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CEN`
        pub type CEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CEN`
        pub struct CEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `UDIS`
        pub type UDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `UDIS`
        pub struct UDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `URS`
        pub type URS_R = crate::R<bool, bool>;
        ///Write proxy for field `URS`
        pub struct URS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> URS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OPM`
        pub type OPM_R = crate::R<bool, bool>;
        ///Write proxy for field `OPM`
        pub struct OPM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ARPE`
        pub type ARPE_R = crate::R<bool, bool>;
        ///Write proxy for field `ARPE`
        pub struct ARPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARPE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CKD`
        pub type CKD_R = crate::R<u8, u8>;
        ///Write proxy for field `CKD`
        pub struct CKD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `UIFREMAP`
        pub type UIFREMAP_R = crate::R<bool, bool>;
        ///Write proxy for field `UIFREMAP`
        pub struct UIFREMAP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIFREMAP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Counter enable.
            #[inline(always)]
            pub fn cen(&self) -> CEN_R {
                CEN_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Update disable.
            #[inline(always)]
            pub fn udis(&self) -> UDIS_R {
                UDIS_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Update request source.
            #[inline(always)]
            pub fn urs(&self) -> URS_R {
                URS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - One pulse mode.
            #[inline(always)]
            pub fn opm(&self) -> OPM_R {
                OPM_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 7 - Auto-reload preload enable.
            #[inline(always)]
            pub fn arpe(&self) -> ARPE_R {
                ARPE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:9 - Clock division.
            #[inline(always)]
            pub fn ckd(&self) -> CKD_R {
                CKD_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 11 - UIF status bit remapping.
            #[inline(always)]
            pub fn uifremap(&self) -> UIFREMAP_R {
                UIFREMAP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Counter enable.
            #[inline(always)]
            pub fn cen(&mut self) -> CEN_W {
                CEN_W { w: self }
            }
            ///Bit 1 - Update disable.
            #[inline(always)]
            pub fn udis(&mut self) -> UDIS_W {
                UDIS_W { w: self }
            }
            ///Bit 2 - Update request source.
            #[inline(always)]
            pub fn urs(&mut self) -> URS_W {
                URS_W { w: self }
            }
            ///Bit 3 - One pulse mode.
            #[inline(always)]
            pub fn opm(&mut self) -> OPM_W {
                OPM_W { w: self }
            }
            ///Bit 7 - Auto-reload preload enable.
            #[inline(always)]
            pub fn arpe(&mut self) -> ARPE_W {
                ARPE_W { w: self }
            }
            ///Bits 8:9 - Clock division.
            #[inline(always)]
            pub fn ckd(&mut self) -> CKD_W {
                CKD_W { w: self }
            }
            ///Bit 11 - UIF status bit remapping.
            #[inline(always)]
            pub fn uifremap(&mut self) -> UIFREMAP_W {
                UIFREMAP_W { w: self }
            }
        }
    }
    ///control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OIS1N`
        pub type OIS1N_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS1N`
        pub struct OIS1N_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS1N_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OIS1`
        pub type OIS1_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS1`
        pub struct OIS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CCDS`
        pub type CCDS_R = crate::R<bool, bool>;
        ///Write proxy for field `CCDS`
        pub struct CCDS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCDS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CCUS`
        pub type CCUS_R = crate::R<bool, bool>;
        ///Write proxy for field `CCUS`
        pub struct CCUS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCUS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CCPC`
        pub type CCPC_R = crate::R<bool, bool>;
        ///Write proxy for field `CCPC`
        pub struct CCPC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCPC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 9 - Output Idle state 1
            #[inline(always)]
            pub fn ois1n(&self) -> OIS1N_R {
                OIS1N_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Output Idle state 1
            #[inline(always)]
            pub fn ois1(&self) -> OIS1_R {
                OIS1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&self) -> CCDS_R {
                CCDS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Capture/compare control update selection
            #[inline(always)]
            pub fn ccus(&self) -> CCUS_R {
                CCUS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 0 - Capture/compare preloaded control
            #[inline(always)]
            pub fn ccpc(&self) -> CCPC_R {
                CCPC_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 9 - Output Idle state 1
            #[inline(always)]
            pub fn ois1n(&mut self) -> OIS1N_W {
                OIS1N_W { w: self }
            }
            ///Bit 8 - Output Idle state 1
            #[inline(always)]
            pub fn ois1(&mut self) -> OIS1_W {
                OIS1_W { w: self }
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&mut self) -> CCDS_W {
                CCDS_W { w: self }
            }
            ///Bit 2 - Capture/compare control update selection
            #[inline(always)]
            pub fn ccus(&mut self) -> CCUS_W {
                CCUS_W { w: self }
            }
            ///Bit 0 - Capture/compare preloaded control
            #[inline(always)]
            pub fn ccpc(&mut self) -> CCPC_W {
                CCPC_W { w: self }
            }
        }
    }
    ///DMA/Interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dier](dier) module
    pub type DIER = crate::Reg<u32, _DIER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DIER;
    ///`read()` method returns [dier::R](dier::R) reader structure
    impl crate::Readable for DIER {}
    ///`write(|w| ..)` method takes [dier::W](dier::W) writer structure
    impl crate::Writable for DIER {}
    ///DMA/Interrupt enable register
    pub mod dier {
        ///Reader of register DIER
        pub type R = crate::R<u32, super::DIER>;
        ///Writer for register DIER
        pub type W = crate::W<u32, super::DIER>;
        ///Register DIER `reset()`'s with value 0
        impl crate::ResetValue for super::DIER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `UIE`
        pub type UIE_R = crate::R<bool, bool>;
        ///Write proxy for field `UIE`
        pub struct UIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `CC1IE`
        pub type CC1IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IE`
        pub struct CC1IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `COMIE`
        pub type COMIE_R = crate::R<bool, bool>;
        ///Write proxy for field `COMIE`
        pub struct COMIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `BIE`
        pub type BIE_R = crate::R<bool, bool>;
        ///Write proxy for field `BIE`
        pub struct BIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `UDE`
        pub type UDE_R = crate::R<bool, bool>;
        ///Write proxy for field `UDE`
        pub struct UDE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CC1DE`
        pub type CC1DE_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1DE`
        pub struct CC1DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1DE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u32) & 0x03) << 9);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Update interrupt enable.
            #[inline(always)]
            pub fn uie(&self) -> UIE_R {
                UIE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable.
            #[inline(always)]
            pub fn cc1ie(&self) -> CC1IE_R {
                CC1IE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 5 - COM interrupt enable.
            #[inline(always)]
            pub fn comie(&self) -> COMIE_R {
                COMIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 8 - Break interrupt enable.
            #[inline(always)]
            pub fn bie(&self) -> BIE_R {
                BIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 8 - Update DMA request enable.
            #[inline(always)]
            pub fn ude(&self) -> UDE_R {
                UDE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Capture/Compare 1 DMA request enable.
            #[inline(always)]
            pub fn cc1de(&self) -> CC1DE_R {
                CC1DE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 0 - Update interrupt enable.
            #[inline(always)]
            pub fn uie(&mut self) -> UIE_W {
                UIE_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable.
            #[inline(always)]
            pub fn cc1ie(&mut self) -> CC1IE_W {
                CC1IE_W { w: self }
            }
            ///Bit 5 - COM interrupt enable.
            #[inline(always)]
            pub fn comie(&mut self) -> COMIE_W {
                COMIE_W { w: self }
            }
            ///Bit 8 - Break interrupt enable.
            #[inline(always)]
            pub fn bie(&mut self) -> BIE_W {
                BIE_W { w: self }
            }
            ///Bit 8 - Update DMA request enable.
            #[inline(always)]
            pub fn ude(&mut self) -> UDE_W {
                UDE_W { w: self }
            }
            ///Bits 9:10 - Capture/Compare 1 DMA request enable.
            #[inline(always)]
            pub fn cc1de(&mut self) -> CC1DE_W {
                CC1DE_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC1OF`
        pub type CC1OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1OF`
        pub struct CC1OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `BIF`
        pub type BIF_R = crate::R<bool, bool>;
        ///Write proxy for field `BIF`
        pub struct BIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `TIF`
        pub type TIF_R = crate::R<bool, bool>;
        ///Write proxy for field `TIF`
        pub struct TIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `COMIF`
        pub type COMIF_R = crate::R<bool, bool>;
        ///Write proxy for field `COMIF`
        pub struct COMIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `CC1IF`
        pub type CC1IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IF`
        pub struct CC1IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `UIF`
        pub type UIF_R = crate::R<bool, bool>;
        ///Write proxy for field `UIF`
        pub struct UIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&self) -> CC1OF_R {
                CC1OF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 7 - Break interrupt flag
            #[inline(always)]
            pub fn bif(&self) -> BIF_R {
                BIF_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&self) -> TIF_R {
                TIF_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - COM interrupt flag
            #[inline(always)]
            pub fn comif(&self) -> COMIF_R {
                COMIF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&self) -> CC1IF_R {
                CC1IF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&self) -> UIF_R {
                UIF_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&mut self) -> CC1OF_W {
                CC1OF_W { w: self }
            }
            ///Bit 7 - Break interrupt flag
            #[inline(always)]
            pub fn bif(&mut self) -> BIF_W {
                BIF_W { w: self }
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&mut self) -> TIF_W {
                TIF_W { w: self }
            }
            ///Bit 5 - COM interrupt flag
            #[inline(always)]
            pub fn comif(&mut self) -> COMIF_W {
                COMIF_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&mut self) -> CC1IF_W {
                CC1IF_W { w: self }
            }
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&mut self) -> UIF_W {
                UIF_W { w: self }
            }
        }
    }
    ///event generation register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [egr](egr) module
    pub type EGR = crate::Reg<u32, _EGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EGR;
    ///`write(|w| ..)` method takes [egr::W](egr::W) writer structure
    impl crate::Writable for EGR {}
    ///event generation register
    pub mod egr {
        ///Writer for register EGR
        pub type W = crate::W<u32, super::EGR>;
        ///Register EGR `reset()`'s with value 0
        impl crate::ResetValue for super::EGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BG`
        pub struct BG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `TG`
        pub struct TG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `COMG`
        pub struct COMG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `CC1G`
        pub struct CC1G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `UG`
        pub struct UG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 7 - Break generation
            #[inline(always)]
            pub fn bg(&mut self) -> BG_W {
                BG_W { w: self }
            }
            ///Bit 6 - Trigger generation
            #[inline(always)]
            pub fn tg(&mut self) -> TG_W {
                TG_W { w: self }
            }
            ///Bit 5 - Capture/Compare control update generation
            #[inline(always)]
            pub fn comg(&mut self) -> COMG_W {
                COMG_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 generation
            #[inline(always)]
            pub fn cc1g(&mut self) -> CC1G_W {
                CC1G_W { w: self }
            }
            ///Bit 0 - Update generation
            #[inline(always)]
            pub fn ug(&mut self) -> UG_W {
                UG_W { w: self }
            }
        }
    }
    ///capture/compare mode register (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_output](ccmr1_output) module
    pub type CCMR1_OUTPUT = crate::Reg<u32, _CCMR1_OUTPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_OUTPUT;
    ///`read()` method returns [ccmr1_output::R](ccmr1_output::R) reader structure
    impl crate::Readable for CCMR1_OUTPUT {}
    ///`write(|w| ..)` method takes [ccmr1_output::W](ccmr1_output::W) writer structure
    impl crate::Writable for CCMR1_OUTPUT {}
    ///capture/compare mode register (output mode)
    pub mod ccmr1_output {
        ///Reader of register CCMR1_Output
        pub type R = crate::R<u32, super::CCMR1_OUTPUT>;
        ///Writer for register CCMR1_Output
        pub type W = crate::W<u32, super::CCMR1_OUTPUT>;
        ///Register CCMR1_Output `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_OUTPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OC1M_2`
        pub type OC1M_2_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1M_2`
        pub struct OC1M_2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OC1M`
        pub type OC1M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC1M`
        pub struct OC1M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OC1PE`
        pub type OC1PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1PE`
        pub struct OC1PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OC1FE`
        pub type OC1FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1FE`
        pub struct OC1FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m_2(&self) -> OC1M_2_R {
                OC1M_2_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 4:6 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m(&self) -> OC1M_R {
                OC1M_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Output Compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&self) -> OC1PE_R {
                OC1PE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Output Compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&self) -> OC1FE_R {
                OC1FE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 16 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m_2(&mut self) -> OC1M_2_W {
                OC1M_2_W { w: self }
            }
            ///Bits 4:6 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m(&mut self) -> OC1M_W {
                OC1M_W { w: self }
            }
            ///Bit 3 - Output Compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&mut self) -> OC1PE_W {
                OC1PE_W { w: self }
            }
            ///Bit 2 - Output Compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&mut self) -> OC1FE_W {
                OC1FE_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
        }
    }
    ///capture/compare mode register 1 (input mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_input](ccmr1_input) module
    pub type CCMR1_INPUT = crate::Reg<u32, _CCMR1_INPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_INPUT;
    ///`read()` method returns [ccmr1_input::R](ccmr1_input::R) reader structure
    impl crate::Readable for CCMR1_INPUT {}
    ///`write(|w| ..)` method takes [ccmr1_input::W](ccmr1_input::W) writer structure
    impl crate::Writable for CCMR1_INPUT {}
    ///capture/compare mode register 1 (input mode)
    pub mod ccmr1_input {
        ///Reader of register CCMR1_Input
        pub type R = crate::R<u32, super::CCMR1_INPUT>;
        ///Writer for register CCMR1_Input
        pub type W = crate::W<u32, super::CCMR1_INPUT>;
        ///Register CCMR1_Input `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_INPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `IC1F`
        pub type IC1F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC1F`
        pub struct IC1F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC1F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `IC1PSC`
        pub type IC1PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC1PSC`
        pub struct IC1PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC1PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn ic1f(&self) -> IC1F_R {
                IC1F_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&self) -> IC1PSC_R {
                IC1PSC_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn ic1f(&mut self) -> IC1F_W {
                IC1F_W { w: self }
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&mut self) -> IC1PSC_W {
                IC1PSC_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
        }
    }
    ///capture/compare enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccer](ccer) module
    pub type CCER = crate::Reg<u32, _CCER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCER;
    ///`read()` method returns [ccer::R](ccer::R) reader structure
    impl crate::Readable for CCER {}
    ///`write(|w| ..)` method takes [ccer::W](ccer::W) writer structure
    impl crate::Writable for CCER {}
    ///capture/compare enable register
    pub mod ccer {
        ///Reader of register CCER
        pub type R = crate::R<u32, super::CCER>;
        ///Writer for register CCER
        pub type W = crate::W<u32, super::CCER>;
        ///Register CCER `reset()`'s with value 0
        impl crate::ResetValue for super::CCER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC1NP`
        pub type CC1NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1NP`
        pub struct CC1NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC1NE`
        pub type CC1NE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1NE`
        pub struct CC1NE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1NE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1P`
        pub type CC1P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1P`
        pub struct CC1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CC1E`
        pub type CC1E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1E`
        pub struct CC1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&self) -> CC1NP_R {
                CC1NP_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Capture/Compare 1 complementary output enable
            #[inline(always)]
            pub fn cc1ne(&self) -> CC1NE_R {
                CC1NE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&self) -> CC1P_R {
                CC1P_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&self) -> CC1E_R {
                CC1E_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&mut self) -> CC1NP_W {
                CC1NP_W { w: self }
            }
            ///Bit 2 - Capture/Compare 1 complementary output enable
            #[inline(always)]
            pub fn cc1ne(&mut self) -> CC1NE_W {
                CC1NE_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&mut self) -> CC1P_W {
                CC1P_W { w: self }
            }
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&mut self) -> CC1E_W {
                CC1E_W { w: self }
            }
        }
    }
    ///counter
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cnt](cnt) module
    pub type CNT = crate::Reg<u32, _CNT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNT;
    ///`read()` method returns [cnt::R](cnt::R) reader structure
    impl crate::Readable for CNT {}
    ///`write(|w| ..)` method takes [cnt::W](cnt::W) writer structure
    impl crate::Writable for CNT {}
    ///counter
    pub mod cnt {
        ///Reader of register CNT
        pub type R = crate::R<u32, super::CNT>;
        ///Writer for register CNT
        pub type W = crate::W<u32, super::CNT>;
        ///Register CNT `reset()`'s with value 0
        impl crate::ResetValue for super::CNT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        ///Write proxy for field `CNT`
        pub struct CNT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CNT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `UIFCPY`
        pub type UIFCPY_R = crate::R<bool, bool>;
        impl R {
            ///Bits 0:15 - counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0xffff) as u16)
            }
            ///Bit 31 - UIF Copy
            #[inline(always)]
            pub fn uifcpy(&self) -> UIFCPY_R {
                UIFCPY_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:15 - counter value
            #[inline(always)]
            pub fn cnt(&mut self) -> CNT_W {
                CNT_W { w: self }
            }
        }
    }
    ///prescaler
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [psc](psc) module
    pub type PSC = crate::Reg<u32, _PSC>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PSC;
    ///`read()` method returns [psc::R](psc::R) reader structure
    impl crate::Readable for PSC {}
    ///`write(|w| ..)` method takes [psc::W](psc::W) writer structure
    impl crate::Writable for PSC {}
    ///prescaler
    pub mod psc {
        ///Reader of register PSC
        pub type R = crate::R<u32, super::PSC>;
        ///Writer for register PSC
        pub type W = crate::W<u32, super::PSC>;
        ///Register PSC `reset()`'s with value 0
        impl crate::ResetValue for super::PSC {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PSC`
        pub type PSC_R = crate::R<u16, u16>;
        ///Write proxy for field `PSC`
        pub struct PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&self) -> PSC_R {
                PSC_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&mut self) -> PSC_W {
                PSC_W { w: self }
            }
        }
    }
    ///auto-reload register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [arr](arr) module
    pub type ARR = crate::Reg<u32, _ARR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ARR;
    ///`read()` method returns [arr::R](arr::R) reader structure
    impl crate::Readable for ARR {}
    ///`write(|w| ..)` method takes [arr::W](arr::W) writer structure
    impl crate::Writable for ARR {}
    ///auto-reload register
    pub mod arr {
        ///Reader of register ARR
        pub type R = crate::R<u32, super::ARR>;
        ///Writer for register ARR
        pub type W = crate::W<u32, super::ARR>;
        ///Register ARR `reset()`'s with value 0
        impl crate::ResetValue for super::ARR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ARR`
        pub type ARR_R = crate::R<u16, u16>;
        ///Write proxy for field `ARR`
        pub struct ARR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Auto-reload value
            #[inline(always)]
            pub fn arr(&self) -> ARR_R {
                ARR_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Auto-reload value
            #[inline(always)]
            pub fn arr(&mut self) -> ARR_W {
                ARR_W { w: self }
            }
        }
    }
    ///repetition counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rcr](rcr) module
    pub type RCR = crate::Reg<u32, _RCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RCR;
    ///`read()` method returns [rcr::R](rcr::R) reader structure
    impl crate::Readable for RCR {}
    ///`write(|w| ..)` method takes [rcr::W](rcr::W) writer structure
    impl crate::Writable for RCR {}
    ///repetition counter register
    pub mod rcr {
        ///Reader of register RCR
        pub type R = crate::R<u32, super::RCR>;
        ///Writer for register RCR
        pub type W = crate::W<u32, super::RCR>;
        ///Register RCR `reset()`'s with value 0
        impl crate::ResetValue for super::RCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `REP`
        pub type REP_R = crate::R<u8, u8>;
        ///Write proxy for field `REP`
        pub struct REP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> REP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Repetition counter value
            #[inline(always)]
            pub fn rep(&self) -> REP_R {
                REP_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - Repetition counter value
            #[inline(always)]
            pub fn rep(&mut self) -> REP_W {
                REP_W { w: self }
            }
        }
    }
    ///capture/compare register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr1](ccr1) module
    pub type CCR1 = crate::Reg<u32, _CCR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR1;
    ///`read()` method returns [ccr1::R](ccr1::R) reader structure
    impl crate::Readable for CCR1 {}
    ///`write(|w| ..)` method takes [ccr1::W](ccr1::W) writer structure
    impl crate::Writable for CCR1 {}
    ///capture/compare register 1
    pub mod ccr1 {
        ///Reader of register CCR1
        pub type R = crate::R<u32, super::CCR1>;
        ///Writer for register CCR1
        pub type W = crate::W<u32, super::CCR1>;
        ///Register CCR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR1`
        pub type CCR1_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR1`
        pub struct CCR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1(&self) -> CCR1_R {
                CCR1_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1(&mut self) -> CCR1_W {
                CCR1_W { w: self }
            }
        }
    }
    ///break and dead-time register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bdtr](bdtr) module
    pub type BDTR = crate::Reg<u32, _BDTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BDTR;
    ///`read()` method returns [bdtr::R](bdtr::R) reader structure
    impl crate::Readable for BDTR {}
    ///`write(|w| ..)` method takes [bdtr::W](bdtr::W) writer structure
    impl crate::Writable for BDTR {}
    ///break and dead-time register
    pub mod bdtr {
        ///Reader of register BDTR
        pub type R = crate::R<u32, super::BDTR>;
        ///Writer for register BDTR
        pub type W = crate::W<u32, super::BDTR>;
        ///Register BDTR `reset()`'s with value 0
        impl crate::ResetValue for super::BDTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DTG`
        pub type DTG_R = crate::R<u8, u8>;
        ///Write proxy for field `DTG`
        pub struct DTG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTG_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OSSI`
        pub type OSSI_R = crate::R<bool, bool>;
        ///Write proxy for field `OSSI`
        pub struct OSSI_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSSI_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OSSR`
        pub type OSSR_R = crate::R<bool, bool>;
        ///Write proxy for field `OSSR`
        pub struct OSSR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSSR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `BKE`
        pub type BKE_R = crate::R<bool, bool>;
        ///Write proxy for field `BKE`
        pub struct BKE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<bool, bool>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `AOE`
        pub type AOE_R = crate::R<bool, bool>;
        ///Write proxy for field `AOE`
        pub struct AOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `MOE`
        pub type MOE_R = crate::R<bool, bool>;
        ///Write proxy for field `MOE`
        pub struct MOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `BKF`
        pub type BKF_R = crate::R<u8, u8>;
        ///Write proxy for field `BKF`
        pub struct BKF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Dead-time generator setup
            #[inline(always)]
            pub fn dtg(&self) -> DTG_R {
                DTG_R::new((self.bits & 0xff) as u8)
            }
            ///Bits 8:9 - Lock configuration
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 10 - Off-state selection for Idle mode
            #[inline(always)]
            pub fn ossi(&self) -> OSSI_R {
                OSSI_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Off-state selection for Run mode
            #[inline(always)]
            pub fn ossr(&self) -> OSSR_R {
                OSSR_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Break enable
            #[inline(always)]
            pub fn bke(&self) -> BKE_R {
                BKE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Break polarity
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Automatic output enable
            #[inline(always)]
            pub fn aoe(&self) -> AOE_R {
                AOE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Main output enable
            #[inline(always)]
            pub fn moe(&self) -> MOE_R {
                MOE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 16:19 - Break filter
            #[inline(always)]
            pub fn bkf(&self) -> BKF_R {
                BKF_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - Dead-time generator setup
            #[inline(always)]
            pub fn dtg(&mut self) -> DTG_W {
                DTG_W { w: self }
            }
            ///Bits 8:9 - Lock configuration
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bit 10 - Off-state selection for Idle mode
            #[inline(always)]
            pub fn ossi(&mut self) -> OSSI_W {
                OSSI_W { w: self }
            }
            ///Bit 11 - Off-state selection for Run mode
            #[inline(always)]
            pub fn ossr(&mut self) -> OSSR_W {
                OSSR_W { w: self }
            }
            ///Bit 12 - Break enable
            #[inline(always)]
            pub fn bke(&mut self) -> BKE_W {
                BKE_W { w: self }
            }
            ///Bit 13 - Break polarity
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
            ///Bit 14 - Automatic output enable
            #[inline(always)]
            pub fn aoe(&mut self) -> AOE_W {
                AOE_W { w: self }
            }
            ///Bit 15 - Main output enable
            #[inline(always)]
            pub fn moe(&mut self) -> MOE_W {
                MOE_W { w: self }
            }
            ///Bits 16:19 - Break filter
            #[inline(always)]
            pub fn bkf(&mut self) -> BKF_W {
                BKF_W { w: self }
            }
        }
    }
    ///DMA control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dcr](dcr) module
    pub type DCR = crate::Reg<u32, _DCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DCR;
    ///`read()` method returns [dcr::R](dcr::R) reader structure
    impl crate::Readable for DCR {}
    ///`write(|w| ..)` method takes [dcr::W](dcr::W) writer structure
    impl crate::Writable for DCR {}
    ///DMA control register
    pub mod dcr {
        ///Reader of register DCR
        pub type R = crate::R<u32, super::DCR>;
        ///Writer for register DCR
        pub type W = crate::W<u32, super::DCR>;
        ///Register DCR `reset()`'s with value 0
        impl crate::ResetValue for super::DCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBL`
        pub type DBL_R = crate::R<u8, u8>;
        ///Write proxy for field `DBL`
        pub struct DBL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8);
                self.w
            }
        }
        ///Reader of field `DBA`
        pub type DBA_R = crate::R<u8, u8>;
        ///Write proxy for field `DBA`
        pub struct DBA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&self) -> DBL_R {
                DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&self) -> DBA_R {
                DBA_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&mut self) -> DBL_W {
                DBL_W { w: self }
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&mut self) -> DBA_W {
                DBA_W { w: self }
            }
        }
    }
    ///DMA address for full transfer
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dmar](dmar) module
    pub type DMAR = crate::Reg<u32, _DMAR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DMAR;
    ///`read()` method returns [dmar::R](dmar::R) reader structure
    impl crate::Readable for DMAR {}
    ///`write(|w| ..)` method takes [dmar::W](dmar::W) writer structure
    impl crate::Writable for DMAR {}
    ///DMA address for full transfer
    pub mod dmar {
        ///Reader of register DMAR
        pub type R = crate::R<u32, super::DMAR>;
        ///Writer for register DMAR
        pub type W = crate::W<u32, super::DMAR>;
        ///Register DMAR `reset()`'s with value 0
        impl crate::ResetValue for super::DMAR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DMAB`
        pub type DMAB_R = crate::R<u16, u16>;
        ///Write proxy for field `DMAB`
        pub struct DMAB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&self) -> DMAB_R {
                DMAB_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&mut self) -> DMAB_W {
                DMAB_W { w: self }
            }
        }
    }
    ///TIM16 option register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [or](or) module
    pub type OR = crate::Reg<u32, _OR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OR;
    ///`read()` method returns [or::R](or::R) reader structure
    impl crate::Readable for OR {}
    ///`write(|w| ..)` method takes [or::W](or::W) writer structure
    impl crate::Writable for OR {}
    ///TIM16 option register 1
    pub mod or {
        ///Reader of register OR
        pub type R = crate::R<u32, super::OR>;
        ///Writer for register OR
        pub type W = crate::W<u32, super::OR>;
        ///Register OR `reset()`'s with value 0
        impl crate::ResetValue for super::OR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TI1_RMP`
        pub type TI1_RMP_R = crate::R<u8, u8>;
        ///Write proxy for field `TI1_RMP`
        pub struct TI1_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TI1_RMP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 0:1 - Input capture 1 remap
            #[inline(always)]
            pub fn ti1_rmp(&self) -> TI1_RMP_R {
                TI1_RMP_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 0:1 - Input capture 1 remap
            #[inline(always)]
            pub fn ti1_rmp(&mut self) -> TI1_RMP_W {
                TI1_RMP_W { w: self }
            }
        }
    }
    ///TIM17 option register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [af1](af1) module
    pub type AF1 = crate::Reg<u32, _AF1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AF1;
    ///`read()` method returns [af1::R](af1::R) reader structure
    impl crate::Readable for AF1 {}
    ///`write(|w| ..)` method takes [af1::W](af1::W) writer structure
    impl crate::Writable for AF1 {}
    ///TIM17 option register 1
    pub mod af1 {
        ///Reader of register AF1
        pub type R = crate::R<u32, super::AF1>;
        ///Writer for register AF1
        pub type W = crate::W<u32, super::AF1>;
        ///Register AF1 `reset()`'s with value 0
        impl crate::ResetValue for super::AF1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKINE`
        pub type BKINE_R = crate::R<bool, bool>;
        ///Write proxy for field `BKINE`
        pub struct BKINE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKINE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `BKCMP1E`
        pub type BKCMP1E_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP1E`
        pub struct BKCMP1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `BKCMP2E`
        pub type BKCMP2E_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP2E`
        pub struct BKCMP2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `BKINP`
        pub type BKINP_R = crate::R<bool, bool>;
        ///Write proxy for field `BKINP`
        pub struct BKINP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKINP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `BKCMP1P`
        pub type BKCMP1P_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP1P`
        pub struct BKCMP1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `BKCMP2P`
        pub type BKCMP2P_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP2P`
        pub struct BKCMP2P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP2P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 0 - BRK BKIN input enable
            #[inline(always)]
            pub fn bkine(&self) -> BKINE_R {
                BKINE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - BRK COMP1 enable
            #[inline(always)]
            pub fn bkcmp1e(&self) -> BKCMP1E_R {
                BKCMP1E_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - BRK COMP2 enable
            #[inline(always)]
            pub fn bkcmp2e(&self) -> BKCMP2E_R {
                BKCMP2E_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 9 - BRK BKIN input polarity
            #[inline(always)]
            pub fn bkinp(&self) -> BKINP_R {
                BKINP_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - BRK COMP1 input polarity
            #[inline(always)]
            pub fn bkcmp1p(&self) -> BKCMP1P_R {
                BKCMP1P_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - BRK COMP2 input polarit
            #[inline(always)]
            pub fn bkcmp2p(&self) -> BKCMP2P_R {
                BKCMP2P_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - BRK BKIN input enable
            #[inline(always)]
            pub fn bkine(&mut self) -> BKINE_W {
                BKINE_W { w: self }
            }
            ///Bit 1 - BRK COMP1 enable
            #[inline(always)]
            pub fn bkcmp1e(&mut self) -> BKCMP1E_W {
                BKCMP1E_W { w: self }
            }
            ///Bit 2 - BRK COMP2 enable
            #[inline(always)]
            pub fn bkcmp2e(&mut self) -> BKCMP2E_W {
                BKCMP2E_W { w: self }
            }
            ///Bit 9 - BRK BKIN input polarity
            #[inline(always)]
            pub fn bkinp(&mut self) -> BKINP_W {
                BKINP_W { w: self }
            }
            ///Bit 10 - BRK COMP1 input polarity
            #[inline(always)]
            pub fn bkcmp1p(&mut self) -> BKCMP1P_W {
                BKCMP1P_W { w: self }
            }
            ///Bit 11 - BRK COMP2 input polarit
            #[inline(always)]
            pub fn bkcmp2p(&mut self) -> BKCMP2P_W {
                BKCMP2P_W { w: self }
            }
        }
    }
}
///General purpose timers
pub struct TIM17 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM17 {}
impl TIM17 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const tim17::RegisterBlock {
        0x4001_4800 as *const _
    }
}
impl Deref for TIM17 {
    type Target = tim17::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*TIM17::ptr() }
    }
}
///General purpose timers
pub mod tim17 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register 1
        pub cr1: CR1,
        ///0x04 - control register 2
        pub cr2: CR2,
        ///0x08 - DMA/Interrupt enable register
        pub dier: DIER,
        ///0x0c - status register
        pub sr: SR,
        ///0x10 - event generation register
        pub egr: EGR,
        ///0x14 - capture/compare mode register (output mode)
        pub ccmr1_output: CCMR1_OUTPUT,
        ///0x18 - capture/compare mode register 1 (input mode)
        pub ccmr1_input: CCMR1_INPUT,
        ///0x1c - capture/compare enable register
        pub ccer: CCER,
        ///0x20 - counter
        pub cnt: CNT,
        ///0x24 - prescaler
        pub psc: PSC,
        ///0x28 - auto-reload register
        pub arr: ARR,
        ///0x2c - repetition counter register
        pub rcr: RCR,
        ///0x30 - capture/compare register 1
        pub ccr1: CCR1,
        ///0x34 - break and dead-time register
        pub bdtr: BDTR,
        ///0x38 - DMA control register
        pub dcr: DCR,
        ///0x3c - DMA address for full transfer
        pub dmar: DMAR,
        ///0x40 - TIM16 option register 1
        pub or: OR,
        ///0x44 - TIM17 option register 1
        pub af1: AF1,
    }
    ///control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CEN`
        pub type CEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CEN`
        pub struct CEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `UDIS`
        pub type UDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `UDIS`
        pub struct UDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `URS`
        pub type URS_R = crate::R<bool, bool>;
        ///Write proxy for field `URS`
        pub struct URS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> URS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OPM`
        pub type OPM_R = crate::R<bool, bool>;
        ///Write proxy for field `OPM`
        pub struct OPM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `ARPE`
        pub type ARPE_R = crate::R<bool, bool>;
        ///Write proxy for field `ARPE`
        pub struct ARPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARPE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CKD`
        pub type CKD_R = crate::R<u8, u8>;
        ///Write proxy for field `CKD`
        pub struct CKD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `UIFREMAP`
        pub type UIFREMAP_R = crate::R<bool, bool>;
        ///Write proxy for field `UIFREMAP`
        pub struct UIFREMAP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIFREMAP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn cen(&self) -> CEN_R {
                CEN_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Update disable
            #[inline(always)]
            pub fn udis(&self) -> UDIS_R {
                UDIS_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Update request source
            #[inline(always)]
            pub fn urs(&self) -> URS_R {
                URS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - One-pulse mode
            #[inline(always)]
            pub fn opm(&self) -> OPM_R {
                OPM_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 7 - Auto-reload preload enable
            #[inline(always)]
            pub fn arpe(&self) -> ARPE_R {
                ARPE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:9 - Clock division
            #[inline(always)]
            pub fn ckd(&self) -> CKD_R {
                CKD_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 11 - UIF status bit remapping
            #[inline(always)]
            pub fn uifremap(&self) -> UIFREMAP_R {
                UIFREMAP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn cen(&mut self) -> CEN_W {
                CEN_W { w: self }
            }
            ///Bit 1 - Update disable
            #[inline(always)]
            pub fn udis(&mut self) -> UDIS_W {
                UDIS_W { w: self }
            }
            ///Bit 2 - Update request source
            #[inline(always)]
            pub fn urs(&mut self) -> URS_W {
                URS_W { w: self }
            }
            ///Bit 3 - One-pulse mode
            #[inline(always)]
            pub fn opm(&mut self) -> OPM_W {
                OPM_W { w: self }
            }
            ///Bit 7 - Auto-reload preload enable
            #[inline(always)]
            pub fn arpe(&mut self) -> ARPE_W {
                ARPE_W { w: self }
            }
            ///Bits 8:9 - Clock division
            #[inline(always)]
            pub fn ckd(&mut self) -> CKD_W {
                CKD_W { w: self }
            }
            ///Bit 11 - UIF status bit remapping
            #[inline(always)]
            pub fn uifremap(&mut self) -> UIFREMAP_W {
                UIFREMAP_W { w: self }
            }
        }
    }
    ///control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OIS1N`
        pub type OIS1N_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS1N`
        pub struct OIS1N_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS1N_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OIS1`
        pub type OIS1_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS1`
        pub struct OIS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CCDS`
        pub type CCDS_R = crate::R<bool, bool>;
        ///Write proxy for field `CCDS`
        pub struct CCDS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCDS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CCUS`
        pub type CCUS_R = crate::R<bool, bool>;
        ///Write proxy for field `CCUS`
        pub struct CCUS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCUS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CCPC`
        pub type CCPC_R = crate::R<bool, bool>;
        ///Write proxy for field `CCPC`
        pub struct CCPC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCPC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 9 - Output Idle state 1
            #[inline(always)]
            pub fn ois1n(&self) -> OIS1N_R {
                OIS1N_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Output Idle state 1
            #[inline(always)]
            pub fn ois1(&self) -> OIS1_R {
                OIS1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&self) -> CCDS_R {
                CCDS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Capture/compare control update selection
            #[inline(always)]
            pub fn ccus(&self) -> CCUS_R {
                CCUS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 0 - Capture/compare preloaded control
            #[inline(always)]
            pub fn ccpc(&self) -> CCPC_R {
                CCPC_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 9 - Output Idle state 1
            #[inline(always)]
            pub fn ois1n(&mut self) -> OIS1N_W {
                OIS1N_W { w: self }
            }
            ///Bit 8 - Output Idle state 1
            #[inline(always)]
            pub fn ois1(&mut self) -> OIS1_W {
                OIS1_W { w: self }
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&mut self) -> CCDS_W {
                CCDS_W { w: self }
            }
            ///Bit 2 - Capture/compare control update selection
            #[inline(always)]
            pub fn ccus(&mut self) -> CCUS_W {
                CCUS_W { w: self }
            }
            ///Bit 0 - Capture/compare preloaded control
            #[inline(always)]
            pub fn ccpc(&mut self) -> CCPC_W {
                CCPC_W { w: self }
            }
        }
    }
    ///DMA/Interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dier](dier) module
    pub type DIER = crate::Reg<u32, _DIER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DIER;
    ///`read()` method returns [dier::R](dier::R) reader structure
    impl crate::Readable for DIER {}
    ///`write(|w| ..)` method takes [dier::W](dier::W) writer structure
    impl crate::Writable for DIER {}
    ///DMA/Interrupt enable register
    pub mod dier {
        ///Reader of register DIER
        pub type R = crate::R<u32, super::DIER>;
        ///Writer for register DIER
        pub type W = crate::W<u32, super::DIER>;
        ///Register DIER `reset()`'s with value 0
        impl crate::ResetValue for super::DIER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `UIE`
        pub type UIE_R = crate::R<bool, bool>;
        ///Write proxy for field `UIE`
        pub struct UIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `CC1IE`
        pub type CC1IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IE`
        pub struct CC1IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `COMIE`
        pub type COMIE_R = crate::R<bool, bool>;
        ///Write proxy for field `COMIE`
        pub struct COMIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `BIE`
        pub type BIE_R = crate::R<bool, bool>;
        ///Write proxy for field `BIE`
        pub struct BIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `UDE`
        pub type UDE_R = crate::R<bool, bool>;
        ///Write proxy for field `UDE`
        pub struct UDE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CC1DE`
        pub type CC1DE_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1DE`
        pub struct CC1DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1DE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u32) & 0x03) << 9);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Update interrupt enable.
            #[inline(always)]
            pub fn uie(&self) -> UIE_R {
                UIE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable.
            #[inline(always)]
            pub fn cc1ie(&self) -> CC1IE_R {
                CC1IE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 5 - COM interrupt enable.
            #[inline(always)]
            pub fn comie(&self) -> COMIE_R {
                COMIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 8 - Break interrupt enable.
            #[inline(always)]
            pub fn bie(&self) -> BIE_R {
                BIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 8 - Update DMA request enable.
            #[inline(always)]
            pub fn ude(&self) -> UDE_R {
                UDE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Capture/Compare 1 DMA request enable.
            #[inline(always)]
            pub fn cc1de(&self) -> CC1DE_R {
                CC1DE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 0 - Update interrupt enable.
            #[inline(always)]
            pub fn uie(&mut self) -> UIE_W {
                UIE_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable.
            #[inline(always)]
            pub fn cc1ie(&mut self) -> CC1IE_W {
                CC1IE_W { w: self }
            }
            ///Bit 5 - COM interrupt enable.
            #[inline(always)]
            pub fn comie(&mut self) -> COMIE_W {
                COMIE_W { w: self }
            }
            ///Bit 8 - Break interrupt enable.
            #[inline(always)]
            pub fn bie(&mut self) -> BIE_W {
                BIE_W { w: self }
            }
            ///Bit 8 - Update DMA request enable.
            #[inline(always)]
            pub fn ude(&mut self) -> UDE_W {
                UDE_W { w: self }
            }
            ///Bits 9:10 - Capture/Compare 1 DMA request enable.
            #[inline(always)]
            pub fn cc1de(&mut self) -> CC1DE_W {
                CC1DE_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC1OF`
        pub type CC1OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1OF`
        pub struct CC1OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `BIF`
        pub type BIF_R = crate::R<bool, bool>;
        ///Write proxy for field `BIF`
        pub struct BIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `TIF`
        pub type TIF_R = crate::R<bool, bool>;
        ///Write proxy for field `TIF`
        pub struct TIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `COMIF`
        pub type COMIF_R = crate::R<bool, bool>;
        ///Write proxy for field `COMIF`
        pub struct COMIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `CC1IF`
        pub type CC1IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IF`
        pub struct CC1IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `UIF`
        pub type UIF_R = crate::R<bool, bool>;
        ///Write proxy for field `UIF`
        pub struct UIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&self) -> CC1OF_R {
                CC1OF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 7 - Break interrupt flag
            #[inline(always)]
            pub fn bif(&self) -> BIF_R {
                BIF_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&self) -> TIF_R {
                TIF_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - COM interrupt flag
            #[inline(always)]
            pub fn comif(&self) -> COMIF_R {
                COMIF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&self) -> CC1IF_R {
                CC1IF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&self) -> UIF_R {
                UIF_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&mut self) -> CC1OF_W {
                CC1OF_W { w: self }
            }
            ///Bit 7 - Break interrupt flag
            #[inline(always)]
            pub fn bif(&mut self) -> BIF_W {
                BIF_W { w: self }
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&mut self) -> TIF_W {
                TIF_W { w: self }
            }
            ///Bit 5 - COM interrupt flag
            #[inline(always)]
            pub fn comif(&mut self) -> COMIF_W {
                COMIF_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&mut self) -> CC1IF_W {
                CC1IF_W { w: self }
            }
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&mut self) -> UIF_W {
                UIF_W { w: self }
            }
        }
    }
    ///event generation register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [egr](egr) module
    pub type EGR = crate::Reg<u32, _EGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EGR;
    ///`write(|w| ..)` method takes [egr::W](egr::W) writer structure
    impl crate::Writable for EGR {}
    ///event generation register
    pub mod egr {
        ///Writer for register EGR
        pub type W = crate::W<u32, super::EGR>;
        ///Register EGR `reset()`'s with value 0
        impl crate::ResetValue for super::EGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `BG`
        pub struct BG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `TG`
        pub struct TG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `COMG`
        pub struct COMG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `CC1G`
        pub struct CC1G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `UG`
        pub struct UG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 7 - Break generation
            #[inline(always)]
            pub fn bg(&mut self) -> BG_W {
                BG_W { w: self }
            }
            ///Bit 6 - Trigger generation
            #[inline(always)]
            pub fn tg(&mut self) -> TG_W {
                TG_W { w: self }
            }
            ///Bit 5 - Capture/Compare control update generation
            #[inline(always)]
            pub fn comg(&mut self) -> COMG_W {
                COMG_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 generation
            #[inline(always)]
            pub fn cc1g(&mut self) -> CC1G_W {
                CC1G_W { w: self }
            }
            ///Bit 0 - Update generation
            #[inline(always)]
            pub fn ug(&mut self) -> UG_W {
                UG_W { w: self }
            }
        }
    }
    ///capture/compare mode register (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_output](ccmr1_output) module
    pub type CCMR1_OUTPUT = crate::Reg<u32, _CCMR1_OUTPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_OUTPUT;
    ///`read()` method returns [ccmr1_output::R](ccmr1_output::R) reader structure
    impl crate::Readable for CCMR1_OUTPUT {}
    ///`write(|w| ..)` method takes [ccmr1_output::W](ccmr1_output::W) writer structure
    impl crate::Writable for CCMR1_OUTPUT {}
    ///capture/compare mode register (output mode)
    pub mod ccmr1_output {
        ///Reader of register CCMR1_Output
        pub type R = crate::R<u32, super::CCMR1_OUTPUT>;
        ///Writer for register CCMR1_Output
        pub type W = crate::W<u32, super::CCMR1_OUTPUT>;
        ///Register CCMR1_Output `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_OUTPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OC1M_2`
        pub type OC1M_2_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1M_2`
        pub struct OC1M_2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OC1M`
        pub type OC1M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC1M`
        pub struct OC1M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OC1PE`
        pub type OC1PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1PE`
        pub struct OC1PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OC1FE`
        pub type OC1FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1FE`
        pub struct OC1FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bit 16 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m_2(&self) -> OC1M_2_R {
                OC1M_2_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bits 4:6 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m(&self) -> OC1M_R {
                OC1M_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Output Compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&self) -> OC1PE_R {
                OC1PE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Output Compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&self) -> OC1FE_R {
                OC1FE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 16 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m_2(&mut self) -> OC1M_2_W {
                OC1M_2_W { w: self }
            }
            ///Bits 4:6 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m(&mut self) -> OC1M_W {
                OC1M_W { w: self }
            }
            ///Bit 3 - Output Compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&mut self) -> OC1PE_W {
                OC1PE_W { w: self }
            }
            ///Bit 2 - Output Compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&mut self) -> OC1FE_W {
                OC1FE_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
        }
    }
    ///capture/compare mode register 1 (input mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_input](ccmr1_input) module
    pub type CCMR1_INPUT = crate::Reg<u32, _CCMR1_INPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_INPUT;
    ///`read()` method returns [ccmr1_input::R](ccmr1_input::R) reader structure
    impl crate::Readable for CCMR1_INPUT {}
    ///`write(|w| ..)` method takes [ccmr1_input::W](ccmr1_input::W) writer structure
    impl crate::Writable for CCMR1_INPUT {}
    ///capture/compare mode register 1 (input mode)
    pub mod ccmr1_input {
        ///Reader of register CCMR1_Input
        pub type R = crate::R<u32, super::CCMR1_INPUT>;
        ///Writer for register CCMR1_Input
        pub type W = crate::W<u32, super::CCMR1_INPUT>;
        ///Register CCMR1_Input `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_INPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `IC1F`
        pub type IC1F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC1F`
        pub struct IC1F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC1F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `IC1PSC`
        pub type IC1PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC1PSC`
        pub struct IC1PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC1PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn ic1f(&self) -> IC1F_R {
                IC1F_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&self) -> IC1PSC_R {
                IC1PSC_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn ic1f(&mut self) -> IC1F_W {
                IC1F_W { w: self }
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&mut self) -> IC1PSC_W {
                IC1PSC_W { w: self }
            }
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
        }
    }
    ///capture/compare enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccer](ccer) module
    pub type CCER = crate::Reg<u32, _CCER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCER;
    ///`read()` method returns [ccer::R](ccer::R) reader structure
    impl crate::Readable for CCER {}
    ///`write(|w| ..)` method takes [ccer::W](ccer::W) writer structure
    impl crate::Writable for CCER {}
    ///capture/compare enable register
    pub mod ccer {
        ///Reader of register CCER
        pub type R = crate::R<u32, super::CCER>;
        ///Writer for register CCER
        pub type W = crate::W<u32, super::CCER>;
        ///Register CCER `reset()`'s with value 0
        impl crate::ResetValue for super::CCER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC1NP`
        pub type CC1NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1NP`
        pub struct CC1NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC1NE`
        pub type CC1NE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1NE`
        pub struct CC1NE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1NE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1P`
        pub type CC1P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1P`
        pub struct CC1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CC1E`
        pub type CC1E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1E`
        pub struct CC1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&self) -> CC1NP_R {
                CC1NP_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Capture/Compare 1 complementary output enable
            #[inline(always)]
            pub fn cc1ne(&self) -> CC1NE_R {
                CC1NE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&self) -> CC1P_R {
                CC1P_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&self) -> CC1E_R {
                CC1E_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&mut self) -> CC1NP_W {
                CC1NP_W { w: self }
            }
            ///Bit 2 - Capture/Compare 1 complementary output enable
            #[inline(always)]
            pub fn cc1ne(&mut self) -> CC1NE_W {
                CC1NE_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&mut self) -> CC1P_W {
                CC1P_W { w: self }
            }
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&mut self) -> CC1E_W {
                CC1E_W { w: self }
            }
        }
    }
    ///counter
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cnt](cnt) module
    pub type CNT = crate::Reg<u32, _CNT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNT;
    ///`read()` method returns [cnt::R](cnt::R) reader structure
    impl crate::Readable for CNT {}
    ///`write(|w| ..)` method takes [cnt::W](cnt::W) writer structure
    impl crate::Writable for CNT {}
    ///counter
    pub mod cnt {
        ///Reader of register CNT
        pub type R = crate::R<u32, super::CNT>;
        ///Writer for register CNT
        pub type W = crate::W<u32, super::CNT>;
        ///Register CNT `reset()`'s with value 0
        impl crate::ResetValue for super::CNT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        ///Write proxy for field `CNT`
        pub struct CNT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CNT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `UIFCPY`
        pub type UIFCPY_R = crate::R<bool, bool>;
        impl R {
            ///Bits 0:15 - counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0xffff) as u16)
            }
            ///Bit 31 - UIF Copy
            #[inline(always)]
            pub fn uifcpy(&self) -> UIFCPY_R {
                UIFCPY_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:15 - counter value
            #[inline(always)]
            pub fn cnt(&mut self) -> CNT_W {
                CNT_W { w: self }
            }
        }
    }
    ///prescaler
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [psc](psc) module
    pub type PSC = crate::Reg<u32, _PSC>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PSC;
    ///`read()` method returns [psc::R](psc::R) reader structure
    impl crate::Readable for PSC {}
    ///`write(|w| ..)` method takes [psc::W](psc::W) writer structure
    impl crate::Writable for PSC {}
    ///prescaler
    pub mod psc {
        ///Reader of register PSC
        pub type R = crate::R<u32, super::PSC>;
        ///Writer for register PSC
        pub type W = crate::W<u32, super::PSC>;
        ///Register PSC `reset()`'s with value 0
        impl crate::ResetValue for super::PSC {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PSC`
        pub type PSC_R = crate::R<u16, u16>;
        ///Write proxy for field `PSC`
        pub struct PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&self) -> PSC_R {
                PSC_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&mut self) -> PSC_W {
                PSC_W { w: self }
            }
        }
    }
    ///auto-reload register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [arr](arr) module
    pub type ARR = crate::Reg<u32, _ARR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ARR;
    ///`read()` method returns [arr::R](arr::R) reader structure
    impl crate::Readable for ARR {}
    ///`write(|w| ..)` method takes [arr::W](arr::W) writer structure
    impl crate::Writable for ARR {}
    ///auto-reload register
    pub mod arr {
        ///Reader of register ARR
        pub type R = crate::R<u32, super::ARR>;
        ///Writer for register ARR
        pub type W = crate::W<u32, super::ARR>;
        ///Register ARR `reset()`'s with value 0
        impl crate::ResetValue for super::ARR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ARR`
        pub type ARR_R = crate::R<u16, u16>;
        ///Write proxy for field `ARR`
        pub struct ARR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Auto-reload value
            #[inline(always)]
            pub fn arr(&self) -> ARR_R {
                ARR_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Auto-reload value
            #[inline(always)]
            pub fn arr(&mut self) -> ARR_W {
                ARR_W { w: self }
            }
        }
    }
    ///repetition counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rcr](rcr) module
    pub type RCR = crate::Reg<u32, _RCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RCR;
    ///`read()` method returns [rcr::R](rcr::R) reader structure
    impl crate::Readable for RCR {}
    ///`write(|w| ..)` method takes [rcr::W](rcr::W) writer structure
    impl crate::Writable for RCR {}
    ///repetition counter register
    pub mod rcr {
        ///Reader of register RCR
        pub type R = crate::R<u32, super::RCR>;
        ///Writer for register RCR
        pub type W = crate::W<u32, super::RCR>;
        ///Register RCR `reset()`'s with value 0
        impl crate::ResetValue for super::RCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `REP`
        pub type REP_R = crate::R<u8, u8>;
        ///Write proxy for field `REP`
        pub struct REP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> REP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Repetition counter value
            #[inline(always)]
            pub fn rep(&self) -> REP_R {
                REP_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - Repetition counter value
            #[inline(always)]
            pub fn rep(&mut self) -> REP_W {
                REP_W { w: self }
            }
        }
    }
    ///capture/compare register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr1](ccr1) module
    pub type CCR1 = crate::Reg<u32, _CCR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR1;
    ///`read()` method returns [ccr1::R](ccr1::R) reader structure
    impl crate::Readable for CCR1 {}
    ///`write(|w| ..)` method takes [ccr1::W](ccr1::W) writer structure
    impl crate::Writable for CCR1 {}
    ///capture/compare register 1
    pub mod ccr1 {
        ///Reader of register CCR1
        pub type R = crate::R<u32, super::CCR1>;
        ///Writer for register CCR1
        pub type W = crate::W<u32, super::CCR1>;
        ///Register CCR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR1`
        pub type CCR1_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR1`
        pub struct CCR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1(&self) -> CCR1_R {
                CCR1_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1(&mut self) -> CCR1_W {
                CCR1_W { w: self }
            }
        }
    }
    ///break and dead-time register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bdtr](bdtr) module
    pub type BDTR = crate::Reg<u32, _BDTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BDTR;
    ///`read()` method returns [bdtr::R](bdtr::R) reader structure
    impl crate::Readable for BDTR {}
    ///`write(|w| ..)` method takes [bdtr::W](bdtr::W) writer structure
    impl crate::Writable for BDTR {}
    ///break and dead-time register
    pub mod bdtr {
        ///Reader of register BDTR
        pub type R = crate::R<u32, super::BDTR>;
        ///Writer for register BDTR
        pub type W = crate::W<u32, super::BDTR>;
        ///Register BDTR `reset()`'s with value 0
        impl crate::ResetValue for super::BDTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DTG`
        pub type DTG_R = crate::R<u8, u8>;
        ///Write proxy for field `DTG`
        pub struct DTG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTG_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OSSI`
        pub type OSSI_R = crate::R<bool, bool>;
        ///Write proxy for field `OSSI`
        pub struct OSSI_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSSI_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OSSR`
        pub type OSSR_R = crate::R<bool, bool>;
        ///Write proxy for field `OSSR`
        pub struct OSSR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSSR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `BKE`
        pub type BKE_R = crate::R<bool, bool>;
        ///Write proxy for field `BKE`
        pub struct BKE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<bool, bool>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `AOE`
        pub type AOE_R = crate::R<bool, bool>;
        ///Write proxy for field `AOE`
        pub struct AOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `MOE`
        pub type MOE_R = crate::R<bool, bool>;
        ///Write proxy for field `MOE`
        pub struct MOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `BKF`
        pub type BKF_R = crate::R<u8, u8>;
        ///Write proxy for field `BKF`
        pub struct BKF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Dead-time generator setup
            #[inline(always)]
            pub fn dtg(&self) -> DTG_R {
                DTG_R::new((self.bits & 0xff) as u8)
            }
            ///Bits 8:9 - Lock configuration
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 10 - Off-state selection for Idle mode
            #[inline(always)]
            pub fn ossi(&self) -> OSSI_R {
                OSSI_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Off-state selection for Run mode
            #[inline(always)]
            pub fn ossr(&self) -> OSSR_R {
                OSSR_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Break enable
            #[inline(always)]
            pub fn bke(&self) -> BKE_R {
                BKE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Break polarity
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Automatic output enable
            #[inline(always)]
            pub fn aoe(&self) -> AOE_R {
                AOE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Main output enable
            #[inline(always)]
            pub fn moe(&self) -> MOE_R {
                MOE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 16:19 - Break filter
            #[inline(always)]
            pub fn bkf(&self) -> BKF_R {
                BKF_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 0:7 - Dead-time generator setup
            #[inline(always)]
            pub fn dtg(&mut self) -> DTG_W {
                DTG_W { w: self }
            }
            ///Bits 8:9 - Lock configuration
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bit 10 - Off-state selection for Idle mode
            #[inline(always)]
            pub fn ossi(&mut self) -> OSSI_W {
                OSSI_W { w: self }
            }
            ///Bit 11 - Off-state selection for Run mode
            #[inline(always)]
            pub fn ossr(&mut self) -> OSSR_W {
                OSSR_W { w: self }
            }
            ///Bit 12 - Break enable
            #[inline(always)]
            pub fn bke(&mut self) -> BKE_W {
                BKE_W { w: self }
            }
            ///Bit 13 - Break polarity
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
            ///Bit 14 - Automatic output enable
            #[inline(always)]
            pub fn aoe(&mut self) -> AOE_W {
                AOE_W { w: self }
            }
            ///Bit 15 - Main output enable
            #[inline(always)]
            pub fn moe(&mut self) -> MOE_W {
                MOE_W { w: self }
            }
            ///Bits 16:19 - Break filter
            #[inline(always)]
            pub fn bkf(&mut self) -> BKF_W {
                BKF_W { w: self }
            }
        }
    }
    ///DMA control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dcr](dcr) module
    pub type DCR = crate::Reg<u32, _DCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DCR;
    ///`read()` method returns [dcr::R](dcr::R) reader structure
    impl crate::Readable for DCR {}
    ///`write(|w| ..)` method takes [dcr::W](dcr::W) writer structure
    impl crate::Writable for DCR {}
    ///DMA control register
    pub mod dcr {
        ///Reader of register DCR
        pub type R = crate::R<u32, super::DCR>;
        ///Writer for register DCR
        pub type W = crate::W<u32, super::DCR>;
        ///Register DCR `reset()`'s with value 0
        impl crate::ResetValue for super::DCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBL`
        pub type DBL_R = crate::R<u8, u8>;
        ///Write proxy for field `DBL`
        pub struct DBL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8);
                self.w
            }
        }
        ///Reader of field `DBA`
        pub type DBA_R = crate::R<u8, u8>;
        ///Write proxy for field `DBA`
        pub struct DBA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&self) -> DBL_R {
                DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&self) -> DBA_R {
                DBA_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&mut self) -> DBL_W {
                DBL_W { w: self }
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&mut self) -> DBA_W {
                DBA_W { w: self }
            }
        }
    }
    ///DMA address for full transfer
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dmar](dmar) module
    pub type DMAR = crate::Reg<u32, _DMAR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DMAR;
    ///`read()` method returns [dmar::R](dmar::R) reader structure
    impl crate::Readable for DMAR {}
    ///`write(|w| ..)` method takes [dmar::W](dmar::W) writer structure
    impl crate::Writable for DMAR {}
    ///DMA address for full transfer
    pub mod dmar {
        ///Reader of register DMAR
        pub type R = crate::R<u32, super::DMAR>;
        ///Writer for register DMAR
        pub type W = crate::W<u32, super::DMAR>;
        ///Register DMAR `reset()`'s with value 0
        impl crate::ResetValue for super::DMAR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DMAB`
        pub type DMAB_R = crate::R<u16, u16>;
        ///Write proxy for field `DMAB`
        pub struct DMAB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&self) -> DMAB_R {
                DMAB_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&mut self) -> DMAB_W {
                DMAB_W { w: self }
            }
        }
    }
    ///TIM16 option register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [or](or) module
    pub type OR = crate::Reg<u32, _OR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OR;
    ///`read()` method returns [or::R](or::R) reader structure
    impl crate::Readable for OR {}
    ///`write(|w| ..)` method takes [or::W](or::W) writer structure
    impl crate::Writable for OR {}
    ///TIM16 option register 1
    pub mod or {
        ///Reader of register OR
        pub type R = crate::R<u32, super::OR>;
        ///Writer for register OR
        pub type W = crate::W<u32, super::OR>;
        ///Register OR `reset()`'s with value 0
        impl crate::ResetValue for super::OR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TI1_RMP`
        pub type TI1_RMP_R = crate::R<u8, u8>;
        ///Write proxy for field `TI1_RMP`
        pub struct TI1_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TI1_RMP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        impl R {
            ///Bits 0:1 - Input capture 1 remap
            #[inline(always)]
            pub fn ti1_rmp(&self) -> TI1_RMP_R {
                TI1_RMP_R::new((self.bits & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 0:1 - Input capture 1 remap
            #[inline(always)]
            pub fn ti1_rmp(&mut self) -> TI1_RMP_W {
                TI1_RMP_W { w: self }
            }
        }
    }
    ///TIM17 option register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [af1](af1) module
    pub type AF1 = crate::Reg<u32, _AF1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AF1;
    ///`read()` method returns [af1::R](af1::R) reader structure
    impl crate::Readable for AF1 {}
    ///`write(|w| ..)` method takes [af1::W](af1::W) writer structure
    impl crate::Writable for AF1 {}
    ///TIM17 option register 1
    pub mod af1 {
        ///Reader of register AF1
        pub type R = crate::R<u32, super::AF1>;
        ///Writer for register AF1
        pub type W = crate::W<u32, super::AF1>;
        ///Register AF1 `reset()`'s with value 0
        impl crate::ResetValue for super::AF1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKINE`
        pub type BKINE_R = crate::R<bool, bool>;
        ///Write proxy for field `BKINE`
        pub struct BKINE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKINE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `BKCMP1E`
        pub type BKCMP1E_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP1E`
        pub struct BKCMP1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `BKCMP2E`
        pub type BKCMP2E_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP2E`
        pub struct BKCMP2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `BKINP`
        pub type BKINP_R = crate::R<bool, bool>;
        ///Write proxy for field `BKINP`
        pub struct BKINP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKINP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `BKCMP1P`
        pub type BKCMP1P_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP1P`
        pub struct BKCMP1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `BKCMP2P`
        pub type BKCMP2P_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP2P`
        pub struct BKCMP2P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP2P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 0 - BRK BKIN input enable
            #[inline(always)]
            pub fn bkine(&self) -> BKINE_R {
                BKINE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - BRK COMP1 enable
            #[inline(always)]
            pub fn bkcmp1e(&self) -> BKCMP1E_R {
                BKCMP1E_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - BRK COMP2 enable
            #[inline(always)]
            pub fn bkcmp2e(&self) -> BKCMP2E_R {
                BKCMP2E_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 9 - BRK BKIN input polarity
            #[inline(always)]
            pub fn bkinp(&self) -> BKINP_R {
                BKINP_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - BRK COMP1 input polarity
            #[inline(always)]
            pub fn bkcmp1p(&self) -> BKCMP1P_R {
                BKCMP1P_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - BRK COMP2 input polarit
            #[inline(always)]
            pub fn bkcmp2p(&self) -> BKCMP2P_R {
                BKCMP2P_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - BRK BKIN input enable
            #[inline(always)]
            pub fn bkine(&mut self) -> BKINE_W {
                BKINE_W { w: self }
            }
            ///Bit 1 - BRK COMP1 enable
            #[inline(always)]
            pub fn bkcmp1e(&mut self) -> BKCMP1E_W {
                BKCMP1E_W { w: self }
            }
            ///Bit 2 - BRK COMP2 enable
            #[inline(always)]
            pub fn bkcmp2e(&mut self) -> BKCMP2E_W {
                BKCMP2E_W { w: self }
            }
            ///Bit 9 - BRK BKIN input polarity
            #[inline(always)]
            pub fn bkinp(&mut self) -> BKINP_W {
                BKINP_W { w: self }
            }
            ///Bit 10 - BRK COMP1 input polarity
            #[inline(always)]
            pub fn bkcmp1p(&mut self) -> BKCMP1P_W {
                BKCMP1P_W { w: self }
            }
            ///Bit 11 - BRK COMP2 input polarit
            #[inline(always)]
            pub fn bkcmp2p(&mut self) -> BKCMP2P_W {
                BKCMP2P_W { w: self }
            }
        }
    }
}
///Advanced-timers
pub struct TIM1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM1 {}
impl TIM1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const tim1::RegisterBlock {
        0x4001_2c00 as *const _
    }
}
impl Deref for TIM1 {
    type Target = tim1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*TIM1::ptr() }
    }
}
///Advanced-timers
pub mod tim1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register 1
        pub cr1: CR1,
        ///0x04 - control register 2
        pub cr2: CR2,
        ///0x08 - slave mode control register
        pub smcr: SMCR,
        ///0x0c - DMA/Interrupt enable register
        pub dier: DIER,
        ///0x10 - status register
        pub sr: SR,
        ///0x14 - event generation register
        pub egr: EGR,
        _reserved_6_ccmr1: [u8; 4usize],
        _reserved_7_ccmr2: [u8; 4usize],
        ///0x20 - capture/compare enable register
        pub ccer: CCER,
        ///0x24 - counter
        pub cnt: CNT,
        ///0x28 - prescaler
        pub psc: PSC,
        ///0x2c - auto-reload register
        pub arr: ARR,
        ///0x30 - repetition counter register
        pub rcr: RCR,
        ///0x34 - capture/compare register 1
        pub ccr1: CCR1,
        ///0x38 - capture/compare register 2
        pub ccr2: CCR2,
        ///0x3c - capture/compare register 3
        pub ccr3: CCR3,
        ///0x40 - capture/compare register 4
        pub ccr4: CCR4,
        ///0x44 - break and dead-time register
        pub bdtr: BDTR,
        ///0x48 - DMA control register
        pub dcr: DCR,
        ///0x4c - DMA address for full transfer
        pub dmar: DMAR,
        ///0x50 - DMA address for full transfer
        pub or: OR,
        ///0x54 - capture/compare mode register 2 (output mode)
        pub ccmr3_output: CCMR3_OUTPUT,
        ///0x58 - capture/compare register 4
        pub ccr5: CCR5,
        ///0x5c - capture/compare register 4
        pub ccr6: CCR6,
        ///0x60 - DMA address for full transfer
        pub af1: AF1,
        ///0x64 - DMA address for full transfer
        pub af2: AF2,
    }
    impl RegisterBlock {
        ///0x18 - capture/compare mode register 1 (output mode)
        #[inline(always)]
        pub fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_OUTPUT) }
        }
        ///0x18 - capture/compare mode register 1 (output mode)
        #[inline(always)]
        pub fn ccmr1_output_mut(&self) -> &mut CCMR1_OUTPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CCMR1_OUTPUT) }
        }
        ///0x18 - capture/compare mode register 1 (output mode)
        #[inline(always)]
        pub fn ccmr1_input(&self) -> &CCMR1_INPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_INPUT) }
        }
        ///0x18 - capture/compare mode register 1 (output mode)
        #[inline(always)]
        pub fn ccmr1_input_mut(&self) -> &mut CCMR1_INPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CCMR1_INPUT) }
        }
        ///0x1c - capture/compare mode register 2 (output mode)
        #[inline(always)]
        pub fn ccmr2_input(&self) -> &CCMR2_INPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(28usize) as *const CCMR2_INPUT) }
        }
        ///0x1c - capture/compare mode register 2 (output mode)
        #[inline(always)]
        pub fn ccmr2_input_mut(&self) -> &mut CCMR2_INPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(28usize) as *mut CCMR2_INPUT) }
        }
        ///0x1c - capture/compare mode register 2 (output mode)
        #[inline(always)]
        pub fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
            unsafe { &*(((self as *const Self) as *const u8).add(28usize) as *const CCMR2_OUTPUT) }
        }
        ///0x1c - capture/compare mode register 2 (output mode)
        #[inline(always)]
        pub fn ccmr2_output_mut(&self) -> &mut CCMR2_OUTPUT {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(28usize) as *mut CCMR2_OUTPUT) }
        }
    }
    ///control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CEN`
        pub type CEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CEN`
        pub struct CEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `OPM`
        pub type OPM_R = crate::R<bool, bool>;
        ///Write proxy for field `OPM`
        pub struct OPM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OPM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `UDIS`
        pub type UDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `UDIS`
        pub struct UDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `URS`
        pub type URS_R = crate::R<bool, bool>;
        ///Write proxy for field `URS`
        pub struct URS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> URS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Write proxy for field `DIR`
        pub struct DIR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CMS`
        pub type CMS_R = crate::R<u8, u8>;
        ///Write proxy for field `CMS`
        pub struct CMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
                self.w
            }
        }
        ///Reader of field `ARPE`
        pub type ARPE_R = crate::R<bool, bool>;
        ///Write proxy for field `ARPE`
        pub struct ARPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARPE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CKD`
        pub type CKD_R = crate::R<u8, u8>;
        ///Write proxy for field `CKD`
        pub struct CKD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `UIFREMAP`
        pub type UIFREMAP_R = crate::R<bool, bool>;
        ///Write proxy for field `UIFREMAP`
        pub struct UIFREMAP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIFREMAP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn cen(&self) -> CEN_R {
                CEN_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 3 - One-pulse mode
            #[inline(always)]
            pub fn opm(&self) -> OPM_R {
                OPM_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 1 - Update disable
            #[inline(always)]
            pub fn udis(&self) -> UDIS_R {
                UDIS_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Update request source
            #[inline(always)]
            pub fn urs(&self) -> URS_R {
                URS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 4 - Direction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bits 5:6 - Center-aligned mode selection
            #[inline(always)]
            pub fn cms(&self) -> CMS_R {
                CMS_R::new(((self.bits >> 5) & 0x03) as u8)
            }
            ///Bit 7 - Auto-reload preload enable
            #[inline(always)]
            pub fn arpe(&self) -> ARPE_R {
                ARPE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:9 - Clock division
            #[inline(always)]
            pub fn ckd(&self) -> CKD_R {
                CKD_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 11 - UIF status bit remapping
            #[inline(always)]
            pub fn uifremap(&self) -> UIFREMAP_R {
                UIFREMAP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn cen(&mut self) -> CEN_W {
                CEN_W { w: self }
            }
            ///Bit 3 - One-pulse mode
            #[inline(always)]
            pub fn opm(&mut self) -> OPM_W {
                OPM_W { w: self }
            }
            ///Bit 1 - Update disable
            #[inline(always)]
            pub fn udis(&mut self) -> UDIS_W {
                UDIS_W { w: self }
            }
            ///Bit 2 - Update request source
            #[inline(always)]
            pub fn urs(&mut self) -> URS_W {
                URS_W { w: self }
            }
            ///Bit 4 - Direction
            #[inline(always)]
            pub fn dir(&mut self) -> DIR_W {
                DIR_W { w: self }
            }
            ///Bits 5:6 - Center-aligned mode selection
            #[inline(always)]
            pub fn cms(&mut self) -> CMS_W {
                CMS_W { w: self }
            }
            ///Bit 7 - Auto-reload preload enable
            #[inline(always)]
            pub fn arpe(&mut self) -> ARPE_W {
                ARPE_W { w: self }
            }
            ///Bits 8:9 - Clock division
            #[inline(always)]
            pub fn ckd(&mut self) -> CKD_W {
                CKD_W { w: self }
            }
            ///Bit 11 - UIF status bit remapping
            #[inline(always)]
            pub fn uifremap(&mut self) -> UIFREMAP_W {
                UIFREMAP_W { w: self }
            }
        }
    }
    ///control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MMS2`
        pub type MMS2_R = crate::R<u8, u8>;
        ///Write proxy for field `MMS2`
        pub struct MMS2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MMS2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `OIS6`
        pub type OIS6_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS6`
        pub struct OIS6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `OIS5`
        pub type OIS5_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS5`
        pub struct OIS5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OIS4`
        pub type OIS4_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS4`
        pub struct OIS4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `OIS3N`
        pub type OIS3N_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS3N`
        pub struct OIS3N_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS3N_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `OIS3`
        pub type OIS3_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS3`
        pub struct OIS3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `OIS2N`
        pub type OIS2N_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS2N`
        pub struct OIS2N_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS2N_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OIS2`
        pub type OIS2_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS2`
        pub struct OIS2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OIS1N`
        pub type OIS1N_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS1N`
        pub struct OIS1N_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS1N_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `OIS1`
        pub type OIS1_R = crate::R<bool, bool>;
        ///Write proxy for field `OIS1`
        pub struct OIS1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OIS1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `TI1S`
        pub type TI1S_R = crate::R<bool, bool>;
        ///Write proxy for field `TI1S`
        pub struct TI1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TI1S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `MMS`
        pub type MMS_R = crate::R<u8, u8>;
        ///Write proxy for field `MMS`
        pub struct MMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `CCDS`
        pub type CCDS_R = crate::R<bool, bool>;
        ///Write proxy for field `CCDS`
        pub struct CCDS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCDS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CCUS`
        pub type CCUS_R = crate::R<bool, bool>;
        ///Write proxy for field `CCUS`
        pub struct CCUS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCUS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CCPC`
        pub type CCPC_R = crate::R<bool, bool>;
        ///Write proxy for field `CCPC`
        pub struct CCPC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCPC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 20:23 - Master mode selection 2
            #[inline(always)]
            pub fn mms2(&self) -> MMS2_R {
                MMS2_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bit 18 - Output Idle state 6 (OC6 output)
            #[inline(always)]
            pub fn ois6(&self) -> OIS6_R {
                OIS6_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 16 - Output Idle state 5 (OC5 output)
            #[inline(always)]
            pub fn ois5(&self) -> OIS5_R {
                OIS5_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 14 - Output Idle state 4
            #[inline(always)]
            pub fn ois4(&self) -> OIS4_R {
                OIS4_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Output Idle state 3
            #[inline(always)]
            pub fn ois3n(&self) -> OIS3N_R {
                OIS3N_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Output Idle state 3
            #[inline(always)]
            pub fn ois3(&self) -> OIS3_R {
                OIS3_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Output Idle state 2
            #[inline(always)]
            pub fn ois2n(&self) -> OIS2N_R {
                OIS2N_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Output Idle state 2
            #[inline(always)]
            pub fn ois2(&self) -> OIS2_R {
                OIS2_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Output Idle state 1
            #[inline(always)]
            pub fn ois1n(&self) -> OIS1N_R {
                OIS1N_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Output Idle state 1
            #[inline(always)]
            pub fn ois1(&self) -> OIS1_R {
                OIS1_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - TI1 selection
            #[inline(always)]
            pub fn ti1s(&self) -> TI1S_R {
                TI1S_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Master mode selection
            #[inline(always)]
            pub fn mms(&self) -> MMS_R {
                MMS_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&self) -> CCDS_R {
                CCDS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Capture/compare control update selection
            #[inline(always)]
            pub fn ccus(&self) -> CCUS_R {
                CCUS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 0 - Capture/compare preloaded control
            #[inline(always)]
            pub fn ccpc(&self) -> CCPC_R {
                CCPC_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 20:23 - Master mode selection 2
            #[inline(always)]
            pub fn mms2(&mut self) -> MMS2_W {
                MMS2_W { w: self }
            }
            ///Bit 18 - Output Idle state 6 (OC6 output)
            #[inline(always)]
            pub fn ois6(&mut self) -> OIS6_W {
                OIS6_W { w: self }
            }
            ///Bit 16 - Output Idle state 5 (OC5 output)
            #[inline(always)]
            pub fn ois5(&mut self) -> OIS5_W {
                OIS5_W { w: self }
            }
            ///Bit 14 - Output Idle state 4
            #[inline(always)]
            pub fn ois4(&mut self) -> OIS4_W {
                OIS4_W { w: self }
            }
            ///Bit 13 - Output Idle state 3
            #[inline(always)]
            pub fn ois3n(&mut self) -> OIS3N_W {
                OIS3N_W { w: self }
            }
            ///Bit 12 - Output Idle state 3
            #[inline(always)]
            pub fn ois3(&mut self) -> OIS3_W {
                OIS3_W { w: self }
            }
            ///Bit 11 - Output Idle state 2
            #[inline(always)]
            pub fn ois2n(&mut self) -> OIS2N_W {
                OIS2N_W { w: self }
            }
            ///Bit 10 - Output Idle state 2
            #[inline(always)]
            pub fn ois2(&mut self) -> OIS2_W {
                OIS2_W { w: self }
            }
            ///Bit 9 - Output Idle state 1
            #[inline(always)]
            pub fn ois1n(&mut self) -> OIS1N_W {
                OIS1N_W { w: self }
            }
            ///Bit 8 - Output Idle state 1
            #[inline(always)]
            pub fn ois1(&mut self) -> OIS1_W {
                OIS1_W { w: self }
            }
            ///Bit 7 - TI1 selection
            #[inline(always)]
            pub fn ti1s(&mut self) -> TI1S_W {
                TI1S_W { w: self }
            }
            ///Bits 4:6 - Master mode selection
            #[inline(always)]
            pub fn mms(&mut self) -> MMS_W {
                MMS_W { w: self }
            }
            ///Bit 3 - Capture/compare DMA selection
            #[inline(always)]
            pub fn ccds(&mut self) -> CCDS_W {
                CCDS_W { w: self }
            }
            ///Bit 2 - Capture/compare control update selection
            #[inline(always)]
            pub fn ccus(&mut self) -> CCUS_W {
                CCUS_W { w: self }
            }
            ///Bit 0 - Capture/compare preloaded control
            #[inline(always)]
            pub fn ccpc(&mut self) -> CCPC_W {
                CCPC_W { w: self }
            }
        }
    }
    ///slave mode control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [smcr](smcr) module
    pub type SMCR = crate::Reg<u32, _SMCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SMCR;
    ///`read()` method returns [smcr::R](smcr::R) reader structure
    impl crate::Readable for SMCR {}
    ///`write(|w| ..)` method takes [smcr::W](smcr::W) writer structure
    impl crate::Writable for SMCR {}
    ///slave mode control register
    pub mod smcr {
        ///Reader of register SMCR
        pub type R = crate::R<u32, super::SMCR>;
        ///Writer for register SMCR
        pub type W = crate::W<u32, super::SMCR>;
        ///Register SMCR `reset()`'s with value 0
        impl crate::ResetValue for super::SMCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SMS`
        pub type SMS_R = crate::R<u8, u8>;
        ///Write proxy for field `SMS`
        pub struct SMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        ///Reader of field `OCCS`
        pub type OCCS_R = crate::R<bool, bool>;
        ///Write proxy for field `OCCS`
        pub struct OCCS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OCCS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `TS`
        pub type TS_R = crate::R<u8, u8>;
        ///Write proxy for field `TS`
        pub struct TS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `MSM`
        pub type MSM_R = crate::R<bool, bool>;
        ///Write proxy for field `MSM`
        pub struct MSM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ETF`
        pub type ETF_R = crate::R<u8, u8>;
        ///Write proxy for field `ETF`
        pub struct ETF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `ETPS`
        pub type ETPS_R = crate::R<u8, u8>;
        ///Write proxy for field `ETPS`
        pub struct ETPS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETPS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `ECE`
        pub type ECE_R = crate::R<bool, bool>;
        ///Write proxy for field `ECE`
        pub struct ECE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ECE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `ETP`
        pub type ETP_R = crate::R<bool, bool>;
        ///Write proxy for field `ETP`
        pub struct ETP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `SMS_3`
        pub type SMS_3_R = crate::R<bool, bool>;
        ///Write proxy for field `SMS_3`
        pub struct SMS_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SMS_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        impl R {
            ///Bits 0:2 - Slave mode selection
            #[inline(always)]
            pub fn sms(&self) -> SMS_R {
                SMS_R::new((self.bits & 0x07) as u8)
            }
            ///Bit 3 - OCREF clear selection
            #[inline(always)]
            pub fn occs(&self) -> OCCS_R {
                OCCS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bits 4:6 - Trigger selection
            #[inline(always)]
            pub fn ts(&self) -> TS_R {
                TS_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 7 - Master/Slave mode
            #[inline(always)]
            pub fn msm(&self) -> MSM_R {
                MSM_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:11 - External trigger filter
            #[inline(always)]
            pub fn etf(&self) -> ETF_R {
                ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 12:13 - External trigger prescaler
            #[inline(always)]
            pub fn etps(&self) -> ETPS_R {
                ETPS_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - External clock enable
            #[inline(always)]
            pub fn ece(&self) -> ECE_R {
                ECE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - External trigger polarity
            #[inline(always)]
            pub fn etp(&self) -> ETP_R {
                ETP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Slave mode selection - bit 3
            #[inline(always)]
            pub fn sms_3(&self) -> SMS_3_R {
                SMS_3_R::new(((self.bits >> 16) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:2 - Slave mode selection
            #[inline(always)]
            pub fn sms(&mut self) -> SMS_W {
                SMS_W { w: self }
            }
            ///Bit 3 - OCREF clear selection
            #[inline(always)]
            pub fn occs(&mut self) -> OCCS_W {
                OCCS_W { w: self }
            }
            ///Bits 4:6 - Trigger selection
            #[inline(always)]
            pub fn ts(&mut self) -> TS_W {
                TS_W { w: self }
            }
            ///Bit 7 - Master/Slave mode
            #[inline(always)]
            pub fn msm(&mut self) -> MSM_W {
                MSM_W { w: self }
            }
            ///Bits 8:11 - External trigger filter
            #[inline(always)]
            pub fn etf(&mut self) -> ETF_W {
                ETF_W { w: self }
            }
            ///Bits 12:13 - External trigger prescaler
            #[inline(always)]
            pub fn etps(&mut self) -> ETPS_W {
                ETPS_W { w: self }
            }
            ///Bit 14 - External clock enable
            #[inline(always)]
            pub fn ece(&mut self) -> ECE_W {
                ECE_W { w: self }
            }
            ///Bit 15 - External trigger polarity
            #[inline(always)]
            pub fn etp(&mut self) -> ETP_W {
                ETP_W { w: self }
            }
            ///Bit 16 - Slave mode selection - bit 3
            #[inline(always)]
            pub fn sms_3(&mut self) -> SMS_3_W {
                SMS_3_W { w: self }
            }
        }
    }
    ///DMA/Interrupt enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dier](dier) module
    pub type DIER = crate::Reg<u32, _DIER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DIER;
    ///`read()` method returns [dier::R](dier::R) reader structure
    impl crate::Readable for DIER {}
    ///`write(|w| ..)` method takes [dier::W](dier::W) writer structure
    impl crate::Writable for DIER {}
    ///DMA/Interrupt enable register
    pub mod dier {
        ///Reader of register DIER
        pub type R = crate::R<u32, super::DIER>;
        ///Writer for register DIER
        pub type W = crate::W<u32, super::DIER>;
        ///Register DIER `reset()`'s with value 0
        impl crate::ResetValue for super::DIER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `UIE`
        pub type UIE_R = crate::R<bool, bool>;
        ///Write proxy for field `UIE`
        pub struct UIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `CC1IE`
        pub type CC1IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IE`
        pub struct CC1IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CC2IE`
        pub type CC2IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2IE`
        pub struct CC2IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC3IE`
        pub type CC3IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3IE`
        pub struct CC3IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC4IE`
        pub type CC4IE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4IE`
        pub struct CC4IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `COMIE`
        pub type COMIE_R = crate::R<bool, bool>;
        ///Write proxy for field `COMIE`
        pub struct COMIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `TIE`
        pub type TIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TIE`
        pub struct TIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `BIE`
        pub type BIE_R = crate::R<bool, bool>;
        ///Write proxy for field `BIE`
        pub struct BIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `UDE`
        pub type UDE_R = crate::R<bool, bool>;
        ///Write proxy for field `UDE`
        pub struct UDE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CC1DE`
        pub type CC1DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1DE`
        pub struct CC1DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `CC2DE`
        pub type CC2DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2DE`
        pub struct CC2DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CC3DE`
        pub type CC3DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3DE`
        pub struct CC3DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CC4DE`
        pub type CC4DE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4DE`
        pub struct CC4DE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4DE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `COMDE`
        pub type COMDE_R = crate::R<bool, bool>;
        ///Write proxy for field `COMDE`
        pub struct COMDE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMDE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `TDE`
        pub type TDE_R = crate::R<bool, bool>;
        ///Write proxy for field `TDE`
        pub struct TDE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TDE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Update interrupt enable
            #[inline(always)]
            pub fn uie(&self) -> UIE_R {
                UIE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable
            #[inline(always)]
            pub fn cc1ie(&self) -> CC1IE_R {
                CC1IE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Capture/Compare 2 interrupt enable
            #[inline(always)]
            pub fn cc2ie(&self) -> CC2IE_R {
                CC2IE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Capture/Compare 3 interrupt enable
            #[inline(always)]
            pub fn cc3ie(&self) -> CC3IE_R {
                CC3IE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Capture/Compare 4 interrupt enable
            #[inline(always)]
            pub fn cc4ie(&self) -> CC4IE_R {
                CC4IE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - COM interrupt enable
            #[inline(always)]
            pub fn comie(&self) -> COMIE_R {
                COMIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Trigger interrupt enable
            #[inline(always)]
            pub fn tie(&self) -> TIE_R {
                TIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Break interrupt enable
            #[inline(always)]
            pub fn bie(&self) -> BIE_R {
                BIE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Update DMA request enable
            #[inline(always)]
            pub fn ude(&self) -> UDE_R {
                UDE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Capture/Compare 1 DMA request enable
            #[inline(always)]
            pub fn cc1de(&self) -> CC1DE_R {
                CC1DE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Capture/Compare 2 DMA request enable
            #[inline(always)]
            pub fn cc2de(&self) -> CC2DE_R {
                CC2DE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Capture/Compare 3 DMA request enable
            #[inline(always)]
            pub fn cc3de(&self) -> CC3DE_R {
                CC3DE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Capture/Compare 4 DMA request enable
            #[inline(always)]
            pub fn cc4de(&self) -> CC4DE_R {
                CC4DE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - COM DMA request enable
            #[inline(always)]
            pub fn comde(&self) -> COMDE_R {
                COMDE_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Trigger DMA request enable
            #[inline(always)]
            pub fn tde(&self) -> TDE_R {
                TDE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Update interrupt enable
            #[inline(always)]
            pub fn uie(&mut self) -> UIE_W {
                UIE_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 interrupt enable
            #[inline(always)]
            pub fn cc1ie(&mut self) -> CC1IE_W {
                CC1IE_W { w: self }
            }
            ///Bit 2 - Capture/Compare 2 interrupt enable
            #[inline(always)]
            pub fn cc2ie(&mut self) -> CC2IE_W {
                CC2IE_W { w: self }
            }
            ///Bit 3 - Capture/Compare 3 interrupt enable
            #[inline(always)]
            pub fn cc3ie(&mut self) -> CC3IE_W {
                CC3IE_W { w: self }
            }
            ///Bit 4 - Capture/Compare 4 interrupt enable
            #[inline(always)]
            pub fn cc4ie(&mut self) -> CC4IE_W {
                CC4IE_W { w: self }
            }
            ///Bit 5 - COM interrupt enable
            #[inline(always)]
            pub fn comie(&mut self) -> COMIE_W {
                COMIE_W { w: self }
            }
            ///Bit 6 - Trigger interrupt enable
            #[inline(always)]
            pub fn tie(&mut self) -> TIE_W {
                TIE_W { w: self }
            }
            ///Bit 7 - Break interrupt enable
            #[inline(always)]
            pub fn bie(&mut self) -> BIE_W {
                BIE_W { w: self }
            }
            ///Bit 8 - Update DMA request enable
            #[inline(always)]
            pub fn ude(&mut self) -> UDE_W {
                UDE_W { w: self }
            }
            ///Bit 9 - Capture/Compare 1 DMA request enable
            #[inline(always)]
            pub fn cc1de(&mut self) -> CC1DE_W {
                CC1DE_W { w: self }
            }
            ///Bit 10 - Capture/Compare 2 DMA request enable
            #[inline(always)]
            pub fn cc2de(&mut self) -> CC2DE_W {
                CC2DE_W { w: self }
            }
            ///Bit 11 - Capture/Compare 3 DMA request enable
            #[inline(always)]
            pub fn cc3de(&mut self) -> CC3DE_W {
                CC3DE_W { w: self }
            }
            ///Bit 12 - Capture/Compare 4 DMA request enable
            #[inline(always)]
            pub fn cc4de(&mut self) -> CC4DE_W {
                CC4DE_W { w: self }
            }
            ///Bit 13 - COM DMA request enable
            #[inline(always)]
            pub fn comde(&mut self) -> COMDE_W {
                COMDE_W { w: self }
            }
            ///Bit 14 - Trigger DMA request enable
            #[inline(always)]
            pub fn tde(&mut self) -> TDE_W {
                TDE_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `UIF`
        pub type UIF_R = crate::R<bool, bool>;
        ///Write proxy for field `UIF`
        pub struct UIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `CC1IF`
        pub type CC1IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1IF`
        pub struct CC1IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CC2IF`
        pub type CC2IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2IF`
        pub struct CC2IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC3IF`
        pub type CC3IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3IF`
        pub struct CC3IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC4IF`
        pub type CC4IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4IF`
        pub struct CC4IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `COMIF`
        pub type COMIF_R = crate::R<bool, bool>;
        ///Write proxy for field `COMIF`
        pub struct COMIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `TIF`
        pub type TIF_R = crate::R<bool, bool>;
        ///Write proxy for field `TIF`
        pub struct TIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `BIF`
        pub type BIF_R = crate::R<bool, bool>;
        ///Write proxy for field `BIF`
        pub struct BIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `B2IF`
        pub type B2IF_R = crate::R<bool, bool>;
        ///Write proxy for field `B2IF`
        pub struct B2IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> B2IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CC1OF`
        pub type CC1OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1OF`
        pub struct CC1OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `CC2OF`
        pub type CC2OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2OF`
        pub struct CC2OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CC3OF`
        pub type CC3OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3OF`
        pub struct CC3OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CC4OF`
        pub type CC4OF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4OF`
        pub struct CC4OF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4OF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `SBIF`
        pub type SBIF_R = crate::R<bool, bool>;
        ///Write proxy for field `SBIF`
        pub struct SBIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SBIF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `CC5IF`
        pub type CC5IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC5IF`
        pub struct CC5IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC5IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CC6IF`
        pub type CC6IF_R = crate::R<bool, bool>;
        ///Write proxy for field `CC6IF`
        pub struct CC6IF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC6IF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&self) -> UIF_R {
                UIF_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&self) -> CC1IF_R {
                CC1IF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Capture/Compare 2 interrupt flag
            #[inline(always)]
            pub fn cc2if(&self) -> CC2IF_R {
                CC2IF_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Capture/Compare 3 interrupt flag
            #[inline(always)]
            pub fn cc3if(&self) -> CC3IF_R {
                CC3IF_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Capture/Compare 4 interrupt flag
            #[inline(always)]
            pub fn cc4if(&self) -> CC4IF_R {
                CC4IF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - COM interrupt flag
            #[inline(always)]
            pub fn comif(&self) -> COMIF_R {
                COMIF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&self) -> TIF_R {
                TIF_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Break interrupt flag
            #[inline(always)]
            pub fn bif(&self) -> BIF_R {
                BIF_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Break 2 interrupt flag
            #[inline(always)]
            pub fn b2if(&self) -> B2IF_R {
                B2IF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&self) -> CC1OF_R {
                CC1OF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Capture/compare 2 overcapture flag
            #[inline(always)]
            pub fn cc2of(&self) -> CC2OF_R {
                CC2OF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Capture/Compare 3 overcapture flag
            #[inline(always)]
            pub fn cc3of(&self) -> CC3OF_R {
                CC3OF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Capture/Compare 4 overcapture flag
            #[inline(always)]
            pub fn cc4of(&self) -> CC4OF_R {
                CC4OF_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - System Break interrupt flag
            #[inline(always)]
            pub fn sbif(&self) -> SBIF_R {
                SBIF_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 16 - Compare 5 interrupt flag
            #[inline(always)]
            pub fn cc5if(&self) -> CC5IF_R {
                CC5IF_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Compare 6 interrupt flag
            #[inline(always)]
            pub fn cc6if(&self) -> CC6IF_R {
                CC6IF_R::new(((self.bits >> 17) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Update interrupt flag
            #[inline(always)]
            pub fn uif(&mut self) -> UIF_W {
                UIF_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 interrupt flag
            #[inline(always)]
            pub fn cc1if(&mut self) -> CC1IF_W {
                CC1IF_W { w: self }
            }
            ///Bit 2 - Capture/Compare 2 interrupt flag
            #[inline(always)]
            pub fn cc2if(&mut self) -> CC2IF_W {
                CC2IF_W { w: self }
            }
            ///Bit 3 - Capture/Compare 3 interrupt flag
            #[inline(always)]
            pub fn cc3if(&mut self) -> CC3IF_W {
                CC3IF_W { w: self }
            }
            ///Bit 4 - Capture/Compare 4 interrupt flag
            #[inline(always)]
            pub fn cc4if(&mut self) -> CC4IF_W {
                CC4IF_W { w: self }
            }
            ///Bit 5 - COM interrupt flag
            #[inline(always)]
            pub fn comif(&mut self) -> COMIF_W {
                COMIF_W { w: self }
            }
            ///Bit 6 - Trigger interrupt flag
            #[inline(always)]
            pub fn tif(&mut self) -> TIF_W {
                TIF_W { w: self }
            }
            ///Bit 7 - Break interrupt flag
            #[inline(always)]
            pub fn bif(&mut self) -> BIF_W {
                BIF_W { w: self }
            }
            ///Bit 8 - Break 2 interrupt flag
            #[inline(always)]
            pub fn b2if(&mut self) -> B2IF_W {
                B2IF_W { w: self }
            }
            ///Bit 9 - Capture/Compare 1 overcapture flag
            #[inline(always)]
            pub fn cc1of(&mut self) -> CC1OF_W {
                CC1OF_W { w: self }
            }
            ///Bit 10 - Capture/compare 2 overcapture flag
            #[inline(always)]
            pub fn cc2of(&mut self) -> CC2OF_W {
                CC2OF_W { w: self }
            }
            ///Bit 11 - Capture/Compare 3 overcapture flag
            #[inline(always)]
            pub fn cc3of(&mut self) -> CC3OF_W {
                CC3OF_W { w: self }
            }
            ///Bit 12 - Capture/Compare 4 overcapture flag
            #[inline(always)]
            pub fn cc4of(&mut self) -> CC4OF_W {
                CC4OF_W { w: self }
            }
            ///Bit 13 - System Break interrupt flag
            #[inline(always)]
            pub fn sbif(&mut self) -> SBIF_W {
                SBIF_W { w: self }
            }
            ///Bit 16 - Compare 5 interrupt flag
            #[inline(always)]
            pub fn cc5if(&mut self) -> CC5IF_W {
                CC5IF_W { w: self }
            }
            ///Bit 17 - Compare 6 interrupt flag
            #[inline(always)]
            pub fn cc6if(&mut self) -> CC6IF_W {
                CC6IF_W { w: self }
            }
        }
    }
    ///event generation register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [egr](egr) module
    pub type EGR = crate::Reg<u32, _EGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EGR;
    ///`write(|w| ..)` method takes [egr::W](egr::W) writer structure
    impl crate::Writable for EGR {}
    ///event generation register
    pub mod egr {
        ///Writer for register EGR
        pub type W = crate::W<u32, super::EGR>;
        ///Register EGR `reset()`'s with value 0
        impl crate::ResetValue for super::EGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `UG`
        pub struct UG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Write proxy for field `CC1G`
        pub struct CC1G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CC2G`
        pub struct CC2G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CC3G`
        pub struct CC3G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CC4G`
        pub struct CC4G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `COMG`
        pub struct COMG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COMG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `TG`
        pub struct TG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `BG`
        pub struct BG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `B2G`
        pub struct B2G_W<'a> {
            w: &'a mut W,
        }
        impl<'a> B2G_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        impl W {
            ///Bit 0 - Update generation
            #[inline(always)]
            pub fn ug(&mut self) -> UG_W {
                UG_W { w: self }
            }
            ///Bit 1 - Capture/compare 1 generation
            #[inline(always)]
            pub fn cc1g(&mut self) -> CC1G_W {
                CC1G_W { w: self }
            }
            ///Bit 2 - Capture/compare 2 generation
            #[inline(always)]
            pub fn cc2g(&mut self) -> CC2G_W {
                CC2G_W { w: self }
            }
            ///Bit 3 - Capture/compare 3 generation
            #[inline(always)]
            pub fn cc3g(&mut self) -> CC3G_W {
                CC3G_W { w: self }
            }
            ///Bit 4 - Capture/compare 4 generation
            #[inline(always)]
            pub fn cc4g(&mut self) -> CC4G_W {
                CC4G_W { w: self }
            }
            ///Bit 5 - Capture/Compare control update generation
            #[inline(always)]
            pub fn comg(&mut self) -> COMG_W {
                COMG_W { w: self }
            }
            ///Bit 6 - Trigger generation
            #[inline(always)]
            pub fn tg(&mut self) -> TG_W {
                TG_W { w: self }
            }
            ///Bit 7 - Break generation
            #[inline(always)]
            pub fn bg(&mut self) -> BG_W {
                BG_W { w: self }
            }
            ///Bit 8 - Break 2 generation
            #[inline(always)]
            pub fn b2g(&mut self) -> B2G_W {
                B2G_W { w: self }
            }
        }
    }
    ///capture/compare mode register 1 (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_input](ccmr1_input) module
    pub type CCMR1_INPUT = crate::Reg<u32, _CCMR1_INPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_INPUT;
    ///`read()` method returns [ccmr1_input::R](ccmr1_input::R) reader structure
    impl crate::Readable for CCMR1_INPUT {}
    ///`write(|w| ..)` method takes [ccmr1_input::W](ccmr1_input::W) writer structure
    impl crate::Writable for CCMR1_INPUT {}
    ///capture/compare mode register 1 (output mode)
    pub mod ccmr1_input {
        ///Reader of register CCMR1_Input
        pub type R = crate::R<u32, super::CCMR1_INPUT>;
        ///Writer for register CCMR1_Input
        pub type W = crate::W<u32, super::CCMR1_INPUT>;
        ///Register CCMR1_Input `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_INPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        ///Reader of field `IC1PSC`
        pub type IC1PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC1PSC`
        pub struct IC1PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC1PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `C1F`
        pub type C1F_R = crate::R<u8, u8>;
        ///Write proxy for field `C1F`
        pub struct C1F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C1F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `CC2S`
        pub type CC2S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC2S`
        pub struct CC2S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `IC2PSC`
        pub type IC2PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC2PSC`
        pub struct IC2PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC2PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `IC2F`
        pub type IC2F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC2F`
        pub struct IC2F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC2F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        impl R {
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&self) -> IC1PSC_R {
                IC1PSC_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn c1f(&self) -> C1F_R {
                C1F_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 8:9 - capture/Compare 2 selection
            #[inline(always)]
            pub fn cc2s(&self) -> CC2S_R {
                CC2S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 10:11 - Input capture 2 prescaler
            #[inline(always)]
            pub fn ic2psc(&self) -> IC2PSC_R {
                IC2PSC_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 12:15 - Input capture 2 filter
            #[inline(always)]
            pub fn ic2f(&self) -> IC2F_R {
                IC2F_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
            ///Bits 2:3 - Input capture 1 prescaler
            #[inline(always)]
            pub fn ic1psc(&mut self) -> IC1PSC_W {
                IC1PSC_W { w: self }
            }
            ///Bits 4:7 - Input capture 1 filter
            #[inline(always)]
            pub fn c1f(&mut self) -> C1F_W {
                C1F_W { w: self }
            }
            ///Bits 8:9 - capture/Compare 2 selection
            #[inline(always)]
            pub fn cc2s(&mut self) -> CC2S_W {
                CC2S_W { w: self }
            }
            ///Bits 10:11 - Input capture 2 prescaler
            #[inline(always)]
            pub fn ic2psc(&mut self) -> IC2PSC_W {
                IC2PSC_W { w: self }
            }
            ///Bits 12:15 - Input capture 2 filter
            #[inline(always)]
            pub fn ic2f(&mut self) -> IC2F_W {
                IC2F_W { w: self }
            }
        }
    }
    ///capture/compare mode register 1 (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr1_output](ccmr1_output) module
    pub type CCMR1_OUTPUT = crate::Reg<u32, _CCMR1_OUTPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR1_OUTPUT;
    ///`read()` method returns [ccmr1_output::R](ccmr1_output::R) reader structure
    impl crate::Readable for CCMR1_OUTPUT {}
    ///`write(|w| ..)` method takes [ccmr1_output::W](ccmr1_output::W) writer structure
    impl crate::Writable for CCMR1_OUTPUT {}
    ///capture/compare mode register 1 (output mode)
    pub mod ccmr1_output {
        ///Reader of register CCMR1_Output
        pub type R = crate::R<u32, super::CCMR1_OUTPUT>;
        ///Writer for register CCMR1_Output
        pub type W = crate::W<u32, super::CCMR1_OUTPUT>;
        ///Register CCMR1_Output `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR1_OUTPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC1S`
        pub type CC1S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC1S`
        pub struct CC1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        ///Reader of field `OC1FE`
        pub type OC1FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1FE`
        pub struct OC1FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OC1PE`
        pub type OC1PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1PE`
        pub struct OC1PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OC1M`
        pub type OC1M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC1M`
        pub struct OC1M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OC1CE`
        pub type OC1CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1CE`
        pub struct OC1CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CC2S`
        pub type CC2S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC2S`
        pub struct CC2S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OC2FE`
        pub type OC2FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2FE`
        pub struct OC2FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OC2PE`
        pub type OC2PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2PE`
        pub struct OC2PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OC2M`
        pub type OC2M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC2M`
        pub struct OC2M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `OC2CE`
        pub type OC2CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2CE`
        pub struct OC2CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OC1M_3`
        pub type OC1M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC1M_3`
        pub struct OC1M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC1M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OC2M_3`
        pub type OC2M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC2M_3`
        pub struct OC2M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC2M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        impl R {
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&self) -> CC1S_R {
                CC1S_R::new((self.bits & 0x03) as u8)
            }
            ///Bit 2 - Output Compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&self) -> OC1FE_R {
                OC1FE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Output Compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&self) -> OC1PE_R {
                OC1PE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bits 4:6 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m(&self) -> OC1M_R {
                OC1M_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 7 - Output Compare 1 clear enable
            #[inline(always)]
            pub fn oc1ce(&self) -> OC1CE_R {
                OC1CE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:9 - Capture/Compare 2 selection
            #[inline(always)]
            pub fn cc2s(&self) -> CC2S_R {
                CC2S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 10 - Output Compare 2 fast enable
            #[inline(always)]
            pub fn oc2fe(&self) -> OC2FE_R {
                OC2FE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Output Compare 2 preload enable
            #[inline(always)]
            pub fn oc2pe(&self) -> OC2PE_R {
                OC2PE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:14 - Output Compare 2 mode
            #[inline(always)]
            pub fn oc2m(&self) -> OC2M_R {
                OC2M_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bit 15 - Output Compare 2 clear enable
            #[inline(always)]
            pub fn oc2ce(&self) -> OC2CE_R {
                OC2CE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Output Compare 1 mode - bit 3
            #[inline(always)]
            pub fn oc1m_3(&self) -> OC1M_3_R {
                OC1M_3_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 24 - Output Compare 2 mode - bit 3
            #[inline(always)]
            pub fn oc2m_3(&self) -> OC2M_3_R {
                OC2M_3_R::new(((self.bits >> 24) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:1 - Capture/Compare 1 selection
            #[inline(always)]
            pub fn cc1s(&mut self) -> CC1S_W {
                CC1S_W { w: self }
            }
            ///Bit 2 - Output Compare 1 fast enable
            #[inline(always)]
            pub fn oc1fe(&mut self) -> OC1FE_W {
                OC1FE_W { w: self }
            }
            ///Bit 3 - Output Compare 1 preload enable
            #[inline(always)]
            pub fn oc1pe(&mut self) -> OC1PE_W {
                OC1PE_W { w: self }
            }
            ///Bits 4:6 - Output Compare 1 mode
            #[inline(always)]
            pub fn oc1m(&mut self) -> OC1M_W {
                OC1M_W { w: self }
            }
            ///Bit 7 - Output Compare 1 clear enable
            #[inline(always)]
            pub fn oc1ce(&mut self) -> OC1CE_W {
                OC1CE_W { w: self }
            }
            ///Bits 8:9 - Capture/Compare 2 selection
            #[inline(always)]
            pub fn cc2s(&mut self) -> CC2S_W {
                CC2S_W { w: self }
            }
            ///Bit 10 - Output Compare 2 fast enable
            #[inline(always)]
            pub fn oc2fe(&mut self) -> OC2FE_W {
                OC2FE_W { w: self }
            }
            ///Bit 11 - Output Compare 2 preload enable
            #[inline(always)]
            pub fn oc2pe(&mut self) -> OC2PE_W {
                OC2PE_W { w: self }
            }
            ///Bits 12:14 - Output Compare 2 mode
            #[inline(always)]
            pub fn oc2m(&mut self) -> OC2M_W {
                OC2M_W { w: self }
            }
            ///Bit 15 - Output Compare 2 clear enable
            #[inline(always)]
            pub fn oc2ce(&mut self) -> OC2CE_W {
                OC2CE_W { w: self }
            }
            ///Bit 16 - Output Compare 1 mode - bit 3
            #[inline(always)]
            pub fn oc1m_3(&mut self) -> OC1M_3_W {
                OC1M_3_W { w: self }
            }
            ///Bit 24 - Output Compare 2 mode - bit 3
            #[inline(always)]
            pub fn oc2m_3(&mut self) -> OC2M_3_W {
                OC2M_3_W { w: self }
            }
        }
    }
    ///capture/compare mode register 2 (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr2_output](ccmr2_output) module
    pub type CCMR2_OUTPUT = crate::Reg<u32, _CCMR2_OUTPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR2_OUTPUT;
    ///`read()` method returns [ccmr2_output::R](ccmr2_output::R) reader structure
    impl crate::Readable for CCMR2_OUTPUT {}
    ///`write(|w| ..)` method takes [ccmr2_output::W](ccmr2_output::W) writer structure
    impl crate::Writable for CCMR2_OUTPUT {}
    ///capture/compare mode register 2 (output mode)
    pub mod ccmr2_output {
        ///Reader of register CCMR2_Output
        pub type R = crate::R<u32, super::CCMR2_OUTPUT>;
        ///Writer for register CCMR2_Output
        pub type W = crate::W<u32, super::CCMR2_OUTPUT>;
        ///Register CCMR2_Output `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR2_OUTPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC3S`
        pub type CC3S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC3S`
        pub struct CC3S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        ///Reader of field `OC3FE`
        pub type OC3FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3FE`
        pub struct OC3FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `OC3PE`
        pub type OC3PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3PE`
        pub struct OC3PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OC3M`
        pub type OC3M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC3M`
        pub struct OC3M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OC3CE`
        pub type OC3CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3CE`
        pub struct OC3CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CC4S`
        pub type CC4S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC4S`
        pub struct CC4S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OC4FE`
        pub type OC4FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4FE`
        pub struct OC4FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OC4PE`
        pub type OC4PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4PE`
        pub struct OC4PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OC4M`
        pub type OC4M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC4M`
        pub struct OC4M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `OC4CE`
        pub type OC4CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4CE`
        pub struct OC4CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OC3M_3`
        pub type OC3M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC3M_3`
        pub struct OC3M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC3M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OC4M_3`
        pub type OC4M_3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC4M_3`
        pub struct OC4M_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC4M_3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        impl R {
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&self) -> CC3S_R {
                CC3S_R::new((self.bits & 0x03) as u8)
            }
            ///Bit 2 - Output compare 3 fast enable
            #[inline(always)]
            pub fn oc3fe(&self) -> OC3FE_R {
                OC3FE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Output compare 3 preload enable
            #[inline(always)]
            pub fn oc3pe(&self) -> OC3PE_R {
                OC3PE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bits 4:6 - Output compare 3 mode
            #[inline(always)]
            pub fn oc3m(&self) -> OC3M_R {
                OC3M_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 7 - Output compare 3 clear enable
            #[inline(always)]
            pub fn oc3ce(&self) -> OC3CE_R {
                OC3CE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&self) -> CC4S_R {
                CC4S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 10 - Output compare 4 fast enable
            #[inline(always)]
            pub fn oc4fe(&self) -> OC4FE_R {
                OC4FE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Output compare 4 preload enable
            #[inline(always)]
            pub fn oc4pe(&self) -> OC4PE_R {
                OC4PE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:14 - Output compare 4 mode
            #[inline(always)]
            pub fn oc4m(&self) -> OC4M_R {
                OC4M_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bit 15 - Output compare 4 clear enable
            #[inline(always)]
            pub fn oc4ce(&self) -> OC4CE_R {
                OC4CE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Output Compare 3 mode - bit 3
            #[inline(always)]
            pub fn oc3m_3(&self) -> OC3M_3_R {
                OC3M_3_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 24 - Output Compare 4 mode - bit 3
            #[inline(always)]
            pub fn oc4m_3(&self) -> OC4M_3_R {
                OC4M_3_R::new(((self.bits >> 24) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&mut self) -> CC3S_W {
                CC3S_W { w: self }
            }
            ///Bit 2 - Output compare 3 fast enable
            #[inline(always)]
            pub fn oc3fe(&mut self) -> OC3FE_W {
                OC3FE_W { w: self }
            }
            ///Bit 3 - Output compare 3 preload enable
            #[inline(always)]
            pub fn oc3pe(&mut self) -> OC3PE_W {
                OC3PE_W { w: self }
            }
            ///Bits 4:6 - Output compare 3 mode
            #[inline(always)]
            pub fn oc3m(&mut self) -> OC3M_W {
                OC3M_W { w: self }
            }
            ///Bit 7 - Output compare 3 clear enable
            #[inline(always)]
            pub fn oc3ce(&mut self) -> OC3CE_W {
                OC3CE_W { w: self }
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&mut self) -> CC4S_W {
                CC4S_W { w: self }
            }
            ///Bit 10 - Output compare 4 fast enable
            #[inline(always)]
            pub fn oc4fe(&mut self) -> OC4FE_W {
                OC4FE_W { w: self }
            }
            ///Bit 11 - Output compare 4 preload enable
            #[inline(always)]
            pub fn oc4pe(&mut self) -> OC4PE_W {
                OC4PE_W { w: self }
            }
            ///Bits 12:14 - Output compare 4 mode
            #[inline(always)]
            pub fn oc4m(&mut self) -> OC4M_W {
                OC4M_W { w: self }
            }
            ///Bit 15 - Output compare 4 clear enable
            #[inline(always)]
            pub fn oc4ce(&mut self) -> OC4CE_W {
                OC4CE_W { w: self }
            }
            ///Bit 16 - Output Compare 3 mode - bit 3
            #[inline(always)]
            pub fn oc3m_3(&mut self) -> OC3M_3_W {
                OC3M_3_W { w: self }
            }
            ///Bit 24 - Output Compare 4 mode - bit 3
            #[inline(always)]
            pub fn oc4m_3(&mut self) -> OC4M_3_W {
                OC4M_3_W { w: self }
            }
        }
    }
    ///capture/compare mode register 2 (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr2_input](ccmr2_input) module
    pub type CCMR2_INPUT = crate::Reg<u32, _CCMR2_INPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR2_INPUT;
    ///`read()` method returns [ccmr2_input::R](ccmr2_input::R) reader structure
    impl crate::Readable for CCMR2_INPUT {}
    ///`write(|w| ..)` method takes [ccmr2_input::W](ccmr2_input::W) writer structure
    impl crate::Writable for CCMR2_INPUT {}
    ///capture/compare mode register 2 (output mode)
    pub mod ccmr2_input {
        ///Reader of register CCMR2_Input
        pub type R = crate::R<u32, super::CCMR2_INPUT>;
        ///Writer for register CCMR2_Input
        pub type W = crate::W<u32, super::CCMR2_INPUT>;
        ///Register CCMR2_Input `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR2_INPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC3S`
        pub type CC3S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC3S`
        pub struct CC3S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        ///Reader of field `C3PSC`
        pub type C3PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `C3PSC`
        pub struct C3PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> C3PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
                self.w
            }
        }
        ///Reader of field `IC3F`
        pub type IC3F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC3F`
        pub struct IC3F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC3F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
                self.w
            }
        }
        ///Reader of field `CC4S`
        pub type CC4S_R = crate::R<u8, u8>;
        ///Write proxy for field `CC4S`
        pub struct CC4S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `IC4PSC`
        pub type IC4PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `IC4PSC`
        pub struct IC4PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC4PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
                self.w
            }
        }
        ///Reader of field `IC4F`
        pub type IC4F_R = crate::R<u8, u8>;
        ///Write proxy for field `IC4F`
        pub struct IC4F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IC4F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
                self.w
            }
        }
        impl R {
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&self) -> CC3S_R {
                CC3S_R::new((self.bits & 0x03) as u8)
            }
            ///Bits 2:3 - Input capture 3 prescaler
            #[inline(always)]
            pub fn c3psc(&self) -> C3PSC_R {
                C3PSC_R::new(((self.bits >> 2) & 0x03) as u8)
            }
            ///Bits 4:7 - Input capture 3 filter
            #[inline(always)]
            pub fn ic3f(&self) -> IC3F_R {
                IC3F_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&self) -> CC4S_R {
                CC4S_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bits 10:11 - Input capture 4 prescaler
            #[inline(always)]
            pub fn ic4psc(&self) -> IC4PSC_R {
                IC4PSC_R::new(((self.bits >> 10) & 0x03) as u8)
            }
            ///Bits 12:15 - Input capture 4 filter
            #[inline(always)]
            pub fn ic4f(&self) -> IC4F_R {
                IC4F_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 0:1 - Capture/Compare 3 selection
            #[inline(always)]
            pub fn cc3s(&mut self) -> CC3S_W {
                CC3S_W { w: self }
            }
            ///Bits 2:3 - Input capture 3 prescaler
            #[inline(always)]
            pub fn c3psc(&mut self) -> C3PSC_W {
                C3PSC_W { w: self }
            }
            ///Bits 4:7 - Input capture 3 filter
            #[inline(always)]
            pub fn ic3f(&mut self) -> IC3F_W {
                IC3F_W { w: self }
            }
            ///Bits 8:9 - Capture/Compare 4 selection
            #[inline(always)]
            pub fn cc4s(&mut self) -> CC4S_W {
                CC4S_W { w: self }
            }
            ///Bits 10:11 - Input capture 4 prescaler
            #[inline(always)]
            pub fn ic4psc(&mut self) -> IC4PSC_W {
                IC4PSC_W { w: self }
            }
            ///Bits 12:15 - Input capture 4 filter
            #[inline(always)]
            pub fn ic4f(&mut self) -> IC4F_W {
                IC4F_W { w: self }
            }
        }
    }
    ///capture/compare enable register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccer](ccer) module
    pub type CCER = crate::Reg<u32, _CCER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCER;
    ///`read()` method returns [ccer::R](ccer::R) reader structure
    impl crate::Readable for CCER {}
    ///`write(|w| ..)` method takes [ccer::W](ccer::W) writer structure
    impl crate::Writable for CCER {}
    ///capture/compare enable register
    pub mod ccer {
        ///Reader of register CCER
        pub type R = crate::R<u32, super::CCER>;
        ///Writer for register CCER
        pub type W = crate::W<u32, super::CCER>;
        ///Register CCER `reset()`'s with value 0
        impl crate::ResetValue for super::CCER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CC1E`
        pub type CC1E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1E`
        pub struct CC1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `CC1P`
        pub type CC1P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1P`
        pub struct CC1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CC1NE`
        pub type CC1NE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1NE`
        pub struct CC1NE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1NE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CC1NP`
        pub type CC1NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC1NP`
        pub struct CC1NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC1NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CC2E`
        pub type CC2E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2E`
        pub struct CC2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CC2P`
        pub type CC2P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2P`
        pub struct CC2P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `CC2NE`
        pub type CC2NE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2NE`
        pub struct CC2NE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2NE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CC2NP`
        pub type CC2NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC2NP`
        pub struct CC2NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC2NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `CC3E`
        pub type CC3E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3E`
        pub struct CC3E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `CC3P`
        pub type CC3P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3P`
        pub struct CC3P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `CC3NE`
        pub type CC3NE_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3NE`
        pub struct CC3NE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3NE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CC3NP`
        pub type CC3NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC3NP`
        pub struct CC3NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC3NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CC4E`
        pub type CC4E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4E`
        pub struct CC4E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `CC4P`
        pub type CC4P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4P`
        pub struct CC4P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `CC4NP`
        pub type CC4NP_R = crate::R<bool, bool>;
        ///Write proxy for field `CC4NP`
        pub struct CC4NP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC4NP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `CC5E`
        pub type CC5E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC5E`
        pub struct CC5E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC5E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CC5P`
        pub type CC5P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC5P`
        pub struct CC5P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC5P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `CC6E`
        pub type CC6E_R = crate::R<bool, bool>;
        ///Write proxy for field `CC6E`
        pub struct CC6E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC6E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `CC6P`
        pub type CC6P_R = crate::R<bool, bool>;
        ///Write proxy for field `CC6P`
        pub struct CC6P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CC6P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&self) -> CC1E_R {
                CC1E_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&self) -> CC1P_R {
                CC1P_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Capture/Compare 1 complementary output enable
            #[inline(always)]
            pub fn cc1ne(&self) -> CC1NE_R {
                CC1NE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&self) -> CC1NP_R {
                CC1NP_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Capture/Compare 2 output enable
            #[inline(always)]
            pub fn cc2e(&self) -> CC2E_R {
                CC2E_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2p(&self) -> CC2P_R {
                CC2P_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Capture/Compare 2 complementary output enable
            #[inline(always)]
            pub fn cc2ne(&self) -> CC2NE_R {
                CC2NE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2np(&self) -> CC2NP_R {
                CC2NP_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Capture/Compare 3 output enable
            #[inline(always)]
            pub fn cc3e(&self) -> CC3E_R {
                CC3E_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3p(&self) -> CC3P_R {
                CC3P_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Capture/Compare 3 complementary output enable
            #[inline(always)]
            pub fn cc3ne(&self) -> CC3NE_R {
                CC3NE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3np(&self) -> CC3NP_R {
                CC3NP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Capture/Compare 4 output enable
            #[inline(always)]
            pub fn cc4e(&self) -> CC4E_R {
                CC4E_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc4p(&self) -> CC4P_R {
                CC4P_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 15 - Capture/Compare 4 complementary output polarity
            #[inline(always)]
            pub fn cc4np(&self) -> CC4NP_R {
                CC4NP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Capture/Compare 5 output enable
            #[inline(always)]
            pub fn cc5e(&self) -> CC5E_R {
                CC5E_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Capture/Compare 5 output polarity
            #[inline(always)]
            pub fn cc5p(&self) -> CC5P_R {
                CC5P_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 20 - Capture/Compare 6 output enable
            #[inline(always)]
            pub fn cc6e(&self) -> CC6E_R {
                CC6E_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 21 - Capture/Compare 6 output polarity
            #[inline(always)]
            pub fn cc6p(&self) -> CC6P_R {
                CC6P_R::new(((self.bits >> 21) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Capture/Compare 1 output enable
            #[inline(always)]
            pub fn cc1e(&mut self) -> CC1E_W {
                CC1E_W { w: self }
            }
            ///Bit 1 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1p(&mut self) -> CC1P_W {
                CC1P_W { w: self }
            }
            ///Bit 2 - Capture/Compare 1 complementary output enable
            #[inline(always)]
            pub fn cc1ne(&mut self) -> CC1NE_W {
                CC1NE_W { w: self }
            }
            ///Bit 3 - Capture/Compare 1 output Polarity
            #[inline(always)]
            pub fn cc1np(&mut self) -> CC1NP_W {
                CC1NP_W { w: self }
            }
            ///Bit 4 - Capture/Compare 2 output enable
            #[inline(always)]
            pub fn cc2e(&mut self) -> CC2E_W {
                CC2E_W { w: self }
            }
            ///Bit 5 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2p(&mut self) -> CC2P_W {
                CC2P_W { w: self }
            }
            ///Bit 6 - Capture/Compare 2 complementary output enable
            #[inline(always)]
            pub fn cc2ne(&mut self) -> CC2NE_W {
                CC2NE_W { w: self }
            }
            ///Bit 7 - Capture/Compare 2 output Polarity
            #[inline(always)]
            pub fn cc2np(&mut self) -> CC2NP_W {
                CC2NP_W { w: self }
            }
            ///Bit 8 - Capture/Compare 3 output enable
            #[inline(always)]
            pub fn cc3e(&mut self) -> CC3E_W {
                CC3E_W { w: self }
            }
            ///Bit 9 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3p(&mut self) -> CC3P_W {
                CC3P_W { w: self }
            }
            ///Bit 10 - Capture/Compare 3 complementary output enable
            #[inline(always)]
            pub fn cc3ne(&mut self) -> CC3NE_W {
                CC3NE_W { w: self }
            }
            ///Bit 11 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc3np(&mut self) -> CC3NP_W {
                CC3NP_W { w: self }
            }
            ///Bit 12 - Capture/Compare 4 output enable
            #[inline(always)]
            pub fn cc4e(&mut self) -> CC4E_W {
                CC4E_W { w: self }
            }
            ///Bit 13 - Capture/Compare 3 output Polarity
            #[inline(always)]
            pub fn cc4p(&mut self) -> CC4P_W {
                CC4P_W { w: self }
            }
            ///Bit 15 - Capture/Compare 4 complementary output polarity
            #[inline(always)]
            pub fn cc4np(&mut self) -> CC4NP_W {
                CC4NP_W { w: self }
            }
            ///Bit 16 - Capture/Compare 5 output enable
            #[inline(always)]
            pub fn cc5e(&mut self) -> CC5E_W {
                CC5E_W { w: self }
            }
            ///Bit 17 - Capture/Compare 5 output polarity
            #[inline(always)]
            pub fn cc5p(&mut self) -> CC5P_W {
                CC5P_W { w: self }
            }
            ///Bit 20 - Capture/Compare 6 output enable
            #[inline(always)]
            pub fn cc6e(&mut self) -> CC6E_W {
                CC6E_W { w: self }
            }
            ///Bit 21 - Capture/Compare 6 output polarity
            #[inline(always)]
            pub fn cc6p(&mut self) -> CC6P_W {
                CC6P_W { w: self }
            }
        }
    }
    ///counter
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cnt](cnt) module
    pub type CNT = crate::Reg<u32, _CNT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNT;
    ///`read()` method returns [cnt::R](cnt::R) reader structure
    impl crate::Readable for CNT {}
    ///`write(|w| ..)` method takes [cnt::W](cnt::W) writer structure
    impl crate::Writable for CNT {}
    ///counter
    pub mod cnt {
        ///Reader of register CNT
        pub type R = crate::R<u32, super::CNT>;
        ///Writer for register CNT
        pub type W = crate::W<u32, super::CNT>;
        ///Register CNT `reset()`'s with value 0
        impl crate::ResetValue for super::CNT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        ///Write proxy for field `CNT`
        pub struct CNT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CNT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `UIFCPY`
        pub type UIFCPY_R = crate::R<bool, bool>;
        impl R {
            ///Bits 0:15 - counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0xffff) as u16)
            }
            ///Bit 31 - UIF copy
            #[inline(always)]
            pub fn uifcpy(&self) -> UIFCPY_R {
                UIFCPY_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:15 - counter value
            #[inline(always)]
            pub fn cnt(&mut self) -> CNT_W {
                CNT_W { w: self }
            }
        }
    }
    ///prescaler
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [psc](psc) module
    pub type PSC = crate::Reg<u32, _PSC>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PSC;
    ///`read()` method returns [psc::R](psc::R) reader structure
    impl crate::Readable for PSC {}
    ///`write(|w| ..)` method takes [psc::W](psc::W) writer structure
    impl crate::Writable for PSC {}
    ///prescaler
    pub mod psc {
        ///Reader of register PSC
        pub type R = crate::R<u32, super::PSC>;
        ///Writer for register PSC
        pub type W = crate::W<u32, super::PSC>;
        ///Register PSC `reset()`'s with value 0
        impl crate::ResetValue for super::PSC {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PSC`
        pub type PSC_R = crate::R<u16, u16>;
        ///Write proxy for field `PSC`
        pub struct PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&self) -> PSC_R {
                PSC_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Prescaler value
            #[inline(always)]
            pub fn psc(&mut self) -> PSC_W {
                PSC_W { w: self }
            }
        }
    }
    ///auto-reload register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [arr](arr) module
    pub type ARR = crate::Reg<u32, _ARR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ARR;
    ///`read()` method returns [arr::R](arr::R) reader structure
    impl crate::Readable for ARR {}
    ///`write(|w| ..)` method takes [arr::W](arr::W) writer structure
    impl crate::Writable for ARR {}
    ///auto-reload register
    pub mod arr {
        ///Reader of register ARR
        pub type R = crate::R<u32, super::ARR>;
        ///Writer for register ARR
        pub type W = crate::W<u32, super::ARR>;
        ///Register ARR `reset()`'s with value 0xffff
        impl crate::ResetValue for super::ARR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff
            }
        }
        ///Reader of field `ARR`
        pub type ARR_R = crate::R<u16, u16>;
        ///Write proxy for field `ARR`
        pub struct ARR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Auto-reload value
            #[inline(always)]
            pub fn arr(&self) -> ARR_R {
                ARR_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Auto-reload value
            #[inline(always)]
            pub fn arr(&mut self) -> ARR_W {
                ARR_W { w: self }
            }
        }
    }
    ///repetition counter register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rcr](rcr) module
    pub type RCR = crate::Reg<u32, _RCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RCR;
    ///`read()` method returns [rcr::R](rcr::R) reader structure
    impl crate::Readable for RCR {}
    ///`write(|w| ..)` method takes [rcr::W](rcr::W) writer structure
    impl crate::Writable for RCR {}
    ///repetition counter register
    pub mod rcr {
        ///Reader of register RCR
        pub type R = crate::R<u32, super::RCR>;
        ///Writer for register RCR
        pub type W = crate::W<u32, super::RCR>;
        ///Register RCR `reset()`'s with value 0
        impl crate::ResetValue for super::RCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `REP`
        pub type REP_R = crate::R<u16, u16>;
        ///Write proxy for field `REP`
        pub struct REP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> REP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Repetition counter value
            #[inline(always)]
            pub fn rep(&self) -> REP_R {
                REP_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Repetition counter value
            #[inline(always)]
            pub fn rep(&mut self) -> REP_W {
                REP_W { w: self }
            }
        }
    }
    ///capture/compare register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr1](ccr1) module
    pub type CCR1 = crate::Reg<u32, _CCR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR1;
    ///`read()` method returns [ccr1::R](ccr1::R) reader structure
    impl crate::Readable for CCR1 {}
    ///`write(|w| ..)` method takes [ccr1::W](ccr1::W) writer structure
    impl crate::Writable for CCR1 {}
    ///capture/compare register 1
    pub mod ccr1 {
        ///Reader of register CCR1
        pub type R = crate::R<u32, super::CCR1>;
        ///Writer for register CCR1
        pub type W = crate::W<u32, super::CCR1>;
        ///Register CCR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR1`
        pub type CCR1_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR1`
        pub struct CCR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR1_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1(&self) -> CCR1_R {
                CCR1_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare 1 value
            #[inline(always)]
            pub fn ccr1(&mut self) -> CCR1_W {
                CCR1_W { w: self }
            }
        }
    }
    ///capture/compare register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr2](ccr2) module
    pub type CCR2 = crate::Reg<u32, _CCR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR2;
    ///`read()` method returns [ccr2::R](ccr2::R) reader structure
    impl crate::Readable for CCR2 {}
    ///`write(|w| ..)` method takes [ccr2::W](ccr2::W) writer structure
    impl crate::Writable for CCR2 {}
    ///capture/compare register 2
    pub mod ccr2 {
        ///Reader of register CCR2
        pub type R = crate::R<u32, super::CCR2>;
        ///Writer for register CCR2
        pub type W = crate::W<u32, super::CCR2>;
        ///Register CCR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR2`
        pub type CCR2_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR2`
        pub struct CCR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR2_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare 2 value
            #[inline(always)]
            pub fn ccr2(&self) -> CCR2_R {
                CCR2_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare 2 value
            #[inline(always)]
            pub fn ccr2(&mut self) -> CCR2_W {
                CCR2_W { w: self }
            }
        }
    }
    ///capture/compare register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr3](ccr3) module
    pub type CCR3 = crate::Reg<u32, _CCR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR3;
    ///`read()` method returns [ccr3::R](ccr3::R) reader structure
    impl crate::Readable for CCR3 {}
    ///`write(|w| ..)` method takes [ccr3::W](ccr3::W) writer structure
    impl crate::Writable for CCR3 {}
    ///capture/compare register 3
    pub mod ccr3 {
        ///Reader of register CCR3
        pub type R = crate::R<u32, super::CCR3>;
        ///Writer for register CCR3
        pub type W = crate::W<u32, super::CCR3>;
        ///Register CCR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR3`
        pub type CCR3_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR3`
        pub struct CCR3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr3(&self) -> CCR3_R {
                CCR3_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr3(&mut self) -> CCR3_W {
                CCR3_W { w: self }
            }
        }
    }
    ///capture/compare register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr4](ccr4) module
    pub type CCR4 = crate::Reg<u32, _CCR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR4;
    ///`read()` method returns [ccr4::R](ccr4::R) reader structure
    impl crate::Readable for CCR4 {}
    ///`write(|w| ..)` method takes [ccr4::W](ccr4::W) writer structure
    impl crate::Writable for CCR4 {}
    ///capture/compare register 4
    pub mod ccr4 {
        ///Reader of register CCR4
        pub type R = crate::R<u32, super::CCR4>;
        ///Writer for register CCR4
        pub type W = crate::W<u32, super::CCR4>;
        ///Register CCR4 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR4 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR4`
        pub type CCR4_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR4`
        pub struct CCR4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR4_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr4(&self) -> CCR4_R {
                CCR4_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr4(&mut self) -> CCR4_W {
                CCR4_W { w: self }
            }
        }
    }
    ///break and dead-time register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bdtr](bdtr) module
    pub type BDTR = crate::Reg<u32, _BDTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BDTR;
    ///`read()` method returns [bdtr::R](bdtr::R) reader structure
    impl crate::Readable for BDTR {}
    ///`write(|w| ..)` method takes [bdtr::W](bdtr::W) writer structure
    impl crate::Writable for BDTR {}
    ///break and dead-time register
    pub mod bdtr {
        ///Reader of register BDTR
        pub type R = crate::R<u32, super::BDTR>;
        ///Writer for register BDTR
        pub type W = crate::W<u32, super::BDTR>;
        ///Register BDTR `reset()`'s with value 0
        impl crate::ResetValue for super::BDTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DTG`
        pub type DTG_R = crate::R<u8, u8>;
        ///Write proxy for field `DTG`
        pub struct DTG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTG_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        ///Reader of field `LOCK`
        pub type LOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `LOCK`
        pub struct LOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        ///Reader of field `OSSI`
        pub type OSSI_R = crate::R<bool, bool>;
        ///Write proxy for field `OSSI`
        pub struct OSSI_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSSI_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OSSR`
        pub type OSSR_R = crate::R<bool, bool>;
        ///Write proxy for field `OSSR`
        pub struct OSSR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSSR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `BKE`
        pub type BKE_R = crate::R<bool, bool>;
        ///Write proxy for field `BKE`
        pub struct BKE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<bool, bool>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `AOE`
        pub type AOE_R = crate::R<bool, bool>;
        ///Write proxy for field `AOE`
        pub struct AOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `MOE`
        pub type MOE_R = crate::R<bool, bool>;
        ///Write proxy for field `MOE`
        pub struct MOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `BKF`
        pub type BKF_R = crate::R<u8, u8>;
        ///Write proxy for field `BKF`
        pub struct BKF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `BK2F`
        pub type BK2F_R = crate::R<u8, u8>;
        ///Write proxy for field `BK2F`
        pub struct BK2F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2F_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `BK2E`
        pub type BK2E_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2E`
        pub struct BK2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `BK2P`
        pub type BK2P_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2P`
        pub struct BK2P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        impl R {
            ///Bits 0:7 - Dead-time generator setup
            #[inline(always)]
            pub fn dtg(&self) -> DTG_R {
                DTG_R::new((self.bits & 0xff) as u8)
            }
            ///Bits 8:9 - Lock configuration
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 8) & 0x03) as u8)
            }
            ///Bit 10 - Off-state selection for Idle mode
            #[inline(always)]
            pub fn ossi(&self) -> OSSI_R {
                OSSI_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Off-state selection for Run mode
            #[inline(always)]
            pub fn ossr(&self) -> OSSR_R {
                OSSR_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Break enable
            #[inline(always)]
            pub fn bke(&self) -> BKE_R {
                BKE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Break polarity
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Automatic output enable
            #[inline(always)]
            pub fn aoe(&self) -> AOE_R {
                AOE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Main output enable
            #[inline(always)]
            pub fn moe(&self) -> MOE_R {
                MOE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 16:19 - Break filter
            #[inline(always)]
            pub fn bkf(&self) -> BKF_R {
                BKF_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 20:23 - Break 2 filter
            #[inline(always)]
            pub fn bk2f(&self) -> BK2F_R {
                BK2F_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bit 24 - Break 2 enable
            #[inline(always)]
            pub fn bk2e(&self) -> BK2E_R {
                BK2E_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 25 - Break 2 polarity
            #[inline(always)]
            pub fn bk2p(&self) -> BK2P_R {
                BK2P_R::new(((self.bits >> 25) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:7 - Dead-time generator setup
            #[inline(always)]
            pub fn dtg(&mut self) -> DTG_W {
                DTG_W { w: self }
            }
            ///Bits 8:9 - Lock configuration
            #[inline(always)]
            pub fn lock(&mut self) -> LOCK_W {
                LOCK_W { w: self }
            }
            ///Bit 10 - Off-state selection for Idle mode
            #[inline(always)]
            pub fn ossi(&mut self) -> OSSI_W {
                OSSI_W { w: self }
            }
            ///Bit 11 - Off-state selection for Run mode
            #[inline(always)]
            pub fn ossr(&mut self) -> OSSR_W {
                OSSR_W { w: self }
            }
            ///Bit 12 - Break enable
            #[inline(always)]
            pub fn bke(&mut self) -> BKE_W {
                BKE_W { w: self }
            }
            ///Bit 13 - Break polarity
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
            ///Bit 14 - Automatic output enable
            #[inline(always)]
            pub fn aoe(&mut self) -> AOE_W {
                AOE_W { w: self }
            }
            ///Bit 15 - Main output enable
            #[inline(always)]
            pub fn moe(&mut self) -> MOE_W {
                MOE_W { w: self }
            }
            ///Bits 16:19 - Break filter
            #[inline(always)]
            pub fn bkf(&mut self) -> BKF_W {
                BKF_W { w: self }
            }
            ///Bits 20:23 - Break 2 filter
            #[inline(always)]
            pub fn bk2f(&mut self) -> BK2F_W {
                BK2F_W { w: self }
            }
            ///Bit 24 - Break 2 enable
            #[inline(always)]
            pub fn bk2e(&mut self) -> BK2E_W {
                BK2E_W { w: self }
            }
            ///Bit 25 - Break 2 polarity
            #[inline(always)]
            pub fn bk2p(&mut self) -> BK2P_W {
                BK2P_W { w: self }
            }
        }
    }
    ///DMA control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dcr](dcr) module
    pub type DCR = crate::Reg<u32, _DCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DCR;
    ///`read()` method returns [dcr::R](dcr::R) reader structure
    impl crate::Readable for DCR {}
    ///`write(|w| ..)` method takes [dcr::W](dcr::W) writer structure
    impl crate::Writable for DCR {}
    ///DMA control register
    pub mod dcr {
        ///Reader of register DCR
        pub type R = crate::R<u32, super::DCR>;
        ///Writer for register DCR
        pub type W = crate::W<u32, super::DCR>;
        ///Register DCR `reset()`'s with value 0
        impl crate::ResetValue for super::DCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBL`
        pub type DBL_R = crate::R<u8, u8>;
        ///Write proxy for field `DBL`
        pub struct DBL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8);
                self.w
            }
        }
        ///Reader of field `DBA`
        pub type DBA_R = crate::R<u8, u8>;
        ///Write proxy for field `DBA`
        pub struct DBA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
                self.w
            }
        }
        impl R {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&self) -> DBL_R {
                DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&self) -> DBA_R {
                DBA_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 8:12 - DMA burst length
            #[inline(always)]
            pub fn dbl(&mut self) -> DBL_W {
                DBL_W { w: self }
            }
            ///Bits 0:4 - DMA base address
            #[inline(always)]
            pub fn dba(&mut self) -> DBA_W {
                DBA_W { w: self }
            }
        }
    }
    ///DMA address for full transfer
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dmar](dmar) module
    pub type DMAR = crate::Reg<u32, _DMAR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DMAR;
    ///`read()` method returns [dmar::R](dmar::R) reader structure
    impl crate::Readable for DMAR {}
    ///`write(|w| ..)` method takes [dmar::W](dmar::W) writer structure
    impl crate::Writable for DMAR {}
    ///DMA address for full transfer
    pub mod dmar {
        ///Reader of register DMAR
        pub type R = crate::R<u32, super::DMAR>;
        ///Writer for register DMAR
        pub type W = crate::W<u32, super::DMAR>;
        ///Register DMAR `reset()`'s with value 0
        impl crate::ResetValue for super::DMAR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DMAB`
        pub type DMAB_R = crate::R<u16, u16>;
        ///Write proxy for field `DMAB`
        pub struct DMAB_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAB_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&self) -> DMAB_R {
                DMAB_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - DMA register for burst accesses
            #[inline(always)]
            pub fn dmab(&mut self) -> DMAB_W {
                DMAB_W { w: self }
            }
        }
    }
    ///DMA address for full transfer
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [or](or) module
    pub type OR = crate::Reg<u32, _OR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OR;
    ///`read()` method returns [or::R](or::R) reader structure
    impl crate::Readable for OR {}
    ///`write(|w| ..)` method takes [or::W](or::W) writer structure
    impl crate::Writable for OR {}
    ///DMA address for full transfer
    pub mod or {
        ///Reader of register OR
        pub type R = crate::R<u32, super::OR>;
        ///Writer for register OR
        pub type W = crate::W<u32, super::OR>;
        ///Register OR `reset()`'s with value 0
        impl crate::ResetValue for super::OR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TIM1_ETR_ADC1_RMP`
        pub type TIM1_ETR_ADC1_RMP_R = crate::R<u8, u8>;
        ///Write proxy for field `TIM1_ETR_ADC1_RMP`
        pub struct TIM1_ETR_ADC1_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIM1_ETR_ADC1_RMP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
                self.w
            }
        }
        ///Reader of field `TI1_RMP`
        pub type TI1_RMP_R = crate::R<bool, bool>;
        ///Write proxy for field `TI1_RMP`
        pub struct TI1_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TI1_RMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        impl R {
            ///Bits 0:1 - TIM1_ETR_ADC1 remapping capability
            #[inline(always)]
            pub fn tim1_etr_adc1_rmp(&self) -> TIM1_ETR_ADC1_RMP_R {
                TIM1_ETR_ADC1_RMP_R::new((self.bits & 0x03) as u8)
            }
            ///Bit 4 - Input Capture 1 remap
            #[inline(always)]
            pub fn ti1_rmp(&self) -> TI1_RMP_R {
                TI1_RMP_R::new(((self.bits >> 4) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:1 - TIM1_ETR_ADC1 remapping capability
            #[inline(always)]
            pub fn tim1_etr_adc1_rmp(&mut self) -> TIM1_ETR_ADC1_RMP_W {
                TIM1_ETR_ADC1_RMP_W { w: self }
            }
            ///Bit 4 - Input Capture 1 remap
            #[inline(always)]
            pub fn ti1_rmp(&mut self) -> TI1_RMP_W {
                TI1_RMP_W { w: self }
            }
        }
    }
    ///capture/compare mode register 2 (output mode)
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccmr3_output](ccmr3_output) module
    pub type CCMR3_OUTPUT = crate::Reg<u32, _CCMR3_OUTPUT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCMR3_OUTPUT;
    ///`read()` method returns [ccmr3_output::R](ccmr3_output::R) reader structure
    impl crate::Readable for CCMR3_OUTPUT {}
    ///`write(|w| ..)` method takes [ccmr3_output::W](ccmr3_output::W) writer structure
    impl crate::Writable for CCMR3_OUTPUT {}
    ///capture/compare mode register 2 (output mode)
    pub mod ccmr3_output {
        ///Reader of register CCMR3_Output
        pub type R = crate::R<u32, super::CCMR3_OUTPUT>;
        ///Writer for register CCMR3_Output
        pub type W = crate::W<u32, super::CCMR3_OUTPUT>;
        ///Register CCMR3_Output `reset()`'s with value 0
        impl crate::ResetValue for super::CCMR3_OUTPUT {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OC6M_bit3`
        pub type OC6M_BIT3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC6M_bit3`
        pub struct OC6M_BIT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC6M_BIT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `OC5M_bit3`
        pub type OC5M_BIT3_R = crate::R<bool, bool>;
        ///Write proxy for field `OC5M_bit3`
        pub struct OC5M_BIT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC5M_BIT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OC6CE`
        pub type OC6CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC6CE`
        pub struct OC6CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC6CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `OC6M`
        pub type OC6M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC6M`
        pub struct OC6M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC6M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `OC6PE`
        pub type OC6PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC6PE`
        pub struct OC6PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC6PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `OC6FE`
        pub type OC6FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC6FE`
        pub struct OC6FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC6FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `OC5CE`
        pub type OC5CE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC5CE`
        pub struct OC5CE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC5CE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `OC5M`
        pub type OC5M_R = crate::R<u8, u8>;
        ///Write proxy for field `OC5M`
        pub struct OC5M_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC5M_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `OC5PE`
        pub type OC5PE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC5PE`
        pub struct OC5PE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC5PE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `OC5FE`
        pub type OC5FE_R = crate::R<bool, bool>;
        ///Write proxy for field `OC5FE`
        pub struct OC5FE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OC5FE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        impl R {
            ///Bit 24 - Output Compare 6 mode bit 3
            #[inline(always)]
            pub fn oc6m_bit3(&self) -> OC6M_BIT3_R {
                OC6M_BIT3_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 16 - Output Compare 5 mode bit 3
            #[inline(always)]
            pub fn oc5m_bit3(&self) -> OC5M_BIT3_R {
                OC5M_BIT3_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Output compare 6 clear enable
            #[inline(always)]
            pub fn oc6ce(&self) -> OC6CE_R {
                OC6CE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 12:14 - Output compare 6 mode
            #[inline(always)]
            pub fn oc6m(&self) -> OC6M_R {
                OC6M_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bit 11 - Output compare 6 preload enable
            #[inline(always)]
            pub fn oc6pe(&self) -> OC6PE_R {
                OC6PE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Output compare 6 fast enable
            #[inline(always)]
            pub fn oc6fe(&self) -> OC6FE_R {
                OC6FE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 7 - Output compare 5 clear enable
            #[inline(always)]
            pub fn oc5ce(&self) -> OC5CE_R {
                OC5CE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Output compare 5 mode
            #[inline(always)]
            pub fn oc5m(&self) -> OC5M_R {
                OC5M_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bit 3 - Output compare 5 preload enable
            #[inline(always)]
            pub fn oc5pe(&self) -> OC5PE_R {
                OC5PE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Output compare 5 fast enable
            #[inline(always)]
            pub fn oc5fe(&self) -> OC5FE_R {
                OC5FE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 24 - Output Compare 6 mode bit 3
            #[inline(always)]
            pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W {
                OC6M_BIT3_W { w: self }
            }
            ///Bit 16 - Output Compare 5 mode bit 3
            #[inline(always)]
            pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W {
                OC5M_BIT3_W { w: self }
            }
            ///Bit 15 - Output compare 6 clear enable
            #[inline(always)]
            pub fn oc6ce(&mut self) -> OC6CE_W {
                OC6CE_W { w: self }
            }
            ///Bits 12:14 - Output compare 6 mode
            #[inline(always)]
            pub fn oc6m(&mut self) -> OC6M_W {
                OC6M_W { w: self }
            }
            ///Bit 11 - Output compare 6 preload enable
            #[inline(always)]
            pub fn oc6pe(&mut self) -> OC6PE_W {
                OC6PE_W { w: self }
            }
            ///Bit 10 - Output compare 6 fast enable
            #[inline(always)]
            pub fn oc6fe(&mut self) -> OC6FE_W {
                OC6FE_W { w: self }
            }
            ///Bit 7 - Output compare 5 clear enable
            #[inline(always)]
            pub fn oc5ce(&mut self) -> OC5CE_W {
                OC5CE_W { w: self }
            }
            ///Bits 4:6 - Output compare 5 mode
            #[inline(always)]
            pub fn oc5m(&mut self) -> OC5M_W {
                OC5M_W { w: self }
            }
            ///Bit 3 - Output compare 5 preload enable
            #[inline(always)]
            pub fn oc5pe(&mut self) -> OC5PE_W {
                OC5PE_W { w: self }
            }
            ///Bit 2 - Output compare 5 fast enable
            #[inline(always)]
            pub fn oc5fe(&mut self) -> OC5FE_W {
                OC5FE_W { w: self }
            }
        }
    }
    ///capture/compare register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr5](ccr5) module
    pub type CCR5 = crate::Reg<u32, _CCR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR5;
    ///`read()` method returns [ccr5::R](ccr5::R) reader structure
    impl crate::Readable for CCR5 {}
    ///`write(|w| ..)` method takes [ccr5::W](ccr5::W) writer structure
    impl crate::Writable for CCR5 {}
    ///capture/compare register 4
    pub mod ccr5 {
        ///Reader of register CCR5
        pub type R = crate::R<u32, super::CCR5>;
        ///Writer for register CCR5
        pub type W = crate::W<u32, super::CCR5>;
        ///Register CCR5 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR5 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR5`
        pub type CCR5_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR5`
        pub struct CCR5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR5_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `GC5C1`
        pub type GC5C1_R = crate::R<bool, bool>;
        ///Write proxy for field `GC5C1`
        pub struct GC5C1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GC5C1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `GC5C2`
        pub type GC5C2_R = crate::R<bool, bool>;
        ///Write proxy for field `GC5C2`
        pub struct GC5C2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GC5C2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `GC5C3`
        pub type GC5C3_R = crate::R<bool, bool>;
        ///Write proxy for field `GC5C3`
        pub struct GC5C3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GC5C3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr5(&self) -> CCR5_R {
                CCR5_R::new((self.bits & 0xffff) as u16)
            }
            ///Bit 29 - Group Channel 5 and Channel 1
            #[inline(always)]
            pub fn gc5c1(&self) -> GC5C1_R {
                GC5C1_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 30 - Group Channel 5 and Channel 2
            #[inline(always)]
            pub fn gc5c2(&self) -> GC5C2_R {
                GC5C2_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - Group Channel 5 and Channel 3
            #[inline(always)]
            pub fn gc5c3(&self) -> GC5C3_R {
                GC5C3_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr5(&mut self) -> CCR5_W {
                CCR5_W { w: self }
            }
            ///Bit 29 - Group Channel 5 and Channel 1
            #[inline(always)]
            pub fn gc5c1(&mut self) -> GC5C1_W {
                GC5C1_W { w: self }
            }
            ///Bit 30 - Group Channel 5 and Channel 2
            #[inline(always)]
            pub fn gc5c2(&mut self) -> GC5C2_W {
                GC5C2_W { w: self }
            }
            ///Bit 31 - Group Channel 5 and Channel 3
            #[inline(always)]
            pub fn gc5c3(&mut self) -> GC5C3_W {
                GC5C3_W { w: self }
            }
        }
    }
    ///capture/compare register 4
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr6](ccr6) module
    pub type CCR6 = crate::Reg<u32, _CCR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR6;
    ///`read()` method returns [ccr6::R](ccr6::R) reader structure
    impl crate::Readable for CCR6 {}
    ///`write(|w| ..)` method takes [ccr6::W](ccr6::W) writer structure
    impl crate::Writable for CCR6 {}
    ///capture/compare register 4
    pub mod ccr6 {
        ///Reader of register CCR6
        pub type R = crate::R<u32, super::CCR6>;
        ///Writer for register CCR6
        pub type W = crate::W<u32, super::CCR6>;
        ///Register CCR6 `reset()`'s with value 0
        impl crate::ResetValue for super::CCR6 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CCR6`
        pub type CCR6_R = crate::R<u16, u16>;
        ///Write proxy for field `CCR6`
        pub struct CCR6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CCR6_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr6(&self) -> CCR6_R {
                CCR6_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Capture/Compare value
            #[inline(always)]
            pub fn ccr6(&mut self) -> CCR6_W {
                CCR6_W { w: self }
            }
        }
    }
    ///DMA address for full transfer
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [af1](af1) module
    pub type AF1 = crate::Reg<u32, _AF1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AF1;
    ///`read()` method returns [af1::R](af1::R) reader structure
    impl crate::Readable for AF1 {}
    ///`write(|w| ..)` method takes [af1::W](af1::W) writer structure
    impl crate::Writable for AF1 {}
    ///DMA address for full transfer
    pub mod af1 {
        ///Reader of register AF1
        pub type R = crate::R<u32, super::AF1>;
        ///Writer for register AF1
        pub type W = crate::W<u32, super::AF1>;
        ///Register AF1 `reset()`'s with value 0x01
        impl crate::ResetValue for super::AF1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x01
            }
        }
        ///Reader of field `BKINE`
        pub type BKINE_R = crate::R<bool, bool>;
        ///Write proxy for field `BKINE`
        pub struct BKINE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKINE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `BKCMP1E`
        pub type BKCMP1E_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP1E`
        pub struct BKCMP1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `BKCMP2E`
        pub type BKCMP2E_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP2E`
        pub struct BKCMP2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `BKINP`
        pub type BKINP_R = crate::R<bool, bool>;
        ///Write proxy for field `BKINP`
        pub struct BKINP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKINP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `BKCMP1P`
        pub type BKCMP1P_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP1P`
        pub struct BKCMP1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `BKCMP2P`
        pub type BKCMP2P_R = crate::R<bool, bool>;
        ///Write proxy for field `BKCMP2P`
        pub struct BKCMP2P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKCMP2P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ETRSEL`
        pub type ETRSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `ETRSEL`
        pub struct ETRSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ETRSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 14)) | (((value as u32) & 0x07) << 14);
                self.w
            }
        }
        impl R {
            ///Bit 0 - BRK BKIN input enable
            #[inline(always)]
            pub fn bkine(&self) -> BKINE_R {
                BKINE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - BRK COMP1 enable
            #[inline(always)]
            pub fn bkcmp1e(&self) -> BKCMP1E_R {
                BKCMP1E_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - BRK COMP2 enable
            #[inline(always)]
            pub fn bkcmp2e(&self) -> BKCMP2E_R {
                BKCMP2E_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 9 - BRK BKIN input polarity
            #[inline(always)]
            pub fn bkinp(&self) -> BKINP_R {
                BKINP_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - BRK COMP1 input polarity
            #[inline(always)]
            pub fn bkcmp1p(&self) -> BKCMP1P_R {
                BKCMP1P_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - BRK COMP2 input polarity
            #[inline(always)]
            pub fn bkcmp2p(&self) -> BKCMP2P_R {
                BKCMP2P_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 14:16 - ETR source selection
            #[inline(always)]
            pub fn etrsel(&self) -> ETRSEL_R {
                ETRSEL_R::new(((self.bits >> 14) & 0x07) as u8)
            }
        }
        impl W {
            ///Bit 0 - BRK BKIN input enable
            #[inline(always)]
            pub fn bkine(&mut self) -> BKINE_W {
                BKINE_W { w: self }
            }
            ///Bit 1 - BRK COMP1 enable
            #[inline(always)]
            pub fn bkcmp1e(&mut self) -> BKCMP1E_W {
                BKCMP1E_W { w: self }
            }
            ///Bit 2 - BRK COMP2 enable
            #[inline(always)]
            pub fn bkcmp2e(&mut self) -> BKCMP2E_W {
                BKCMP2E_W { w: self }
            }
            ///Bit 9 - BRK BKIN input polarity
            #[inline(always)]
            pub fn bkinp(&mut self) -> BKINP_W {
                BKINP_W { w: self }
            }
            ///Bit 10 - BRK COMP1 input polarity
            #[inline(always)]
            pub fn bkcmp1p(&mut self) -> BKCMP1P_W {
                BKCMP1P_W { w: self }
            }
            ///Bit 11 - BRK COMP2 input polarity
            #[inline(always)]
            pub fn bkcmp2p(&mut self) -> BKCMP2P_W {
                BKCMP2P_W { w: self }
            }
            ///Bits 14:16 - ETR source selection
            #[inline(always)]
            pub fn etrsel(&mut self) -> ETRSEL_W {
                ETRSEL_W { w: self }
            }
        }
    }
    ///DMA address for full transfer
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [af2](af2) module
    pub type AF2 = crate::Reg<u32, _AF2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _AF2;
    ///`read()` method returns [af2::R](af2::R) reader structure
    impl crate::Readable for AF2 {}
    ///`write(|w| ..)` method takes [af2::W](af2::W) writer structure
    impl crate::Writable for AF2 {}
    ///DMA address for full transfer
    pub mod af2 {
        ///Reader of register AF2
        pub type R = crate::R<u32, super::AF2>;
        ///Writer for register AF2
        pub type W = crate::W<u32, super::AF2>;
        ///Register AF2 `reset()`'s with value 0x01
        impl crate::ResetValue for super::AF2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x01
            }
        }
        ///Reader of field `BK2INE`
        pub type BK2INE_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2INE`
        pub struct BK2INE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2INE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `BK2CMP1E`
        pub type BK2CMP1E_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2CMP1E`
        pub struct BK2CMP1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2CMP1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `BK2CMP2E`
        pub type BK2CMP2E_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2CMP2E`
        pub struct BK2CMP2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2CMP2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `BK2DFBK0E`
        pub type BK2DFBK0E_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2DFBK0E`
        pub struct BK2DFBK0E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2DFBK0E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `BK2INP`
        pub type BK2INP_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2INP`
        pub struct BK2INP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2INP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `BK2CMP1P`
        pub type BK2CMP1P_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2CMP1P`
        pub struct BK2CMP1P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2CMP1P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `BK2CMP2P`
        pub type BK2CMP2P_R = crate::R<bool, bool>;
        ///Write proxy for field `BK2CMP2P`
        pub struct BK2CMP2P_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BK2CMP2P_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        impl R {
            ///Bit 0 - BRK2 BKIN input enable
            #[inline(always)]
            pub fn bk2ine(&self) -> BK2INE_R {
                BK2INE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - BRK2 COMP1 enable
            #[inline(always)]
            pub fn bk2cmp1e(&self) -> BK2CMP1E_R {
                BK2CMP1E_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - BRK2 COMP2 enable
            #[inline(always)]
            pub fn bk2cmp2e(&self) -> BK2CMP2E_R {
                BK2CMP2E_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 8 - BRK2 DFSDM_BREAK0 enable
            #[inline(always)]
            pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R {
                BK2DFBK0E_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - BRK2 BKIN input polarity
            #[inline(always)]
            pub fn bk2inp(&self) -> BK2INP_R {
                BK2INP_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - BRK2 COMP1 input polarity
            #[inline(always)]
            pub fn bk2cmp1p(&self) -> BK2CMP1P_R {
                BK2CMP1P_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - BRK2 COMP2 input polarity
            #[inline(always)]
            pub fn bk2cmp2p(&self) -> BK2CMP2P_R {
                BK2CMP2P_R::new(((self.bits >> 11) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - BRK2 BKIN input enable
            #[inline(always)]
            pub fn bk2ine(&mut self) -> BK2INE_W {
                BK2INE_W { w: self }
            }
            ///Bit 1 - BRK2 COMP1 enable
            #[inline(always)]
            pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W {
                BK2CMP1E_W { w: self }
            }
            ///Bit 2 - BRK2 COMP2 enable
            #[inline(always)]
            pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W {
                BK2CMP2E_W { w: self }
            }
            ///Bit 8 - BRK2 DFSDM_BREAK0 enable
            #[inline(always)]
            pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W {
                BK2DFBK0E_W { w: self }
            }
            ///Bit 9 - BRK2 BKIN input polarity
            #[inline(always)]
            pub fn bk2inp(&mut self) -> BK2INP_W {
                BK2INP_W { w: self }
            }
            ///Bit 10 - BRK2 COMP1 input polarity
            #[inline(always)]
            pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W {
                BK2CMP1P_W { w: self }
            }
            ///Bit 11 - BRK2 COMP2 input polarity
            #[inline(always)]
            pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W {
                BK2CMP2P_W { w: self }
            }
        }
    }
}
///Low power timer
pub struct LPTIM1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LPTIM1 {}
impl LPTIM1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const lptim1::RegisterBlock {
        0x4000_7c00 as *const _
    }
}
impl Deref for LPTIM1 {
    type Target = lptim1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*LPTIM1::ptr() }
    }
}
///Low power timer
pub mod lptim1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Interrupt and Status Register
        pub isr: ISR,
        ///0x04 - Interrupt Clear Register
        pub icr: ICR,
        ///0x08 - Interrupt Enable Register
        pub ier: IER,
        ///0x0c - Configuration Register
        pub cfgr: CFGR,
        ///0x10 - Control Register
        pub cr: CR,
        ///0x14 - Compare Register
        pub cmp: CMP,
        ///0x18 - Autoreload Register
        pub arr: ARR,
        ///0x1c - Counter Register
        pub cnt: CNT,
        ///0x20 - Option Register
        pub or: OR,
    }
    ///Interrupt and Status Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///Interrupt and Status Register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Reader of field `DOWN`
        pub type DOWN_R = crate::R<bool, bool>;
        ///Reader of field `UP`
        pub type UP_R = crate::R<bool, bool>;
        ///Reader of field `ARROK`
        pub type ARROK_R = crate::R<bool, bool>;
        ///Reader of field `CMPOK`
        pub type CMPOK_R = crate::R<bool, bool>;
        ///Reader of field `EXTTRIG`
        pub type EXTTRIG_R = crate::R<bool, bool>;
        ///Reader of field `ARRM`
        pub type ARRM_R = crate::R<bool, bool>;
        ///Reader of field `CMPM`
        pub type CMPM_R = crate::R<bool, bool>;
        impl R {
            ///Bit 6 - Counter direction change up to down
            #[inline(always)]
            pub fn down(&self) -> DOWN_R {
                DOWN_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Counter direction change down to up
            #[inline(always)]
            pub fn up(&self) -> UP_R {
                UP_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Autoreload register update OK
            #[inline(always)]
            pub fn arrok(&self) -> ARROK_R {
                ARROK_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Compare register update OK
            #[inline(always)]
            pub fn cmpok(&self) -> CMPOK_R {
                CMPOK_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - External trigger edge event
            #[inline(always)]
            pub fn exttrig(&self) -> EXTTRIG_R {
                EXTTRIG_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Autoreload match
            #[inline(always)]
            pub fn arrm(&self) -> ARRM_R {
                ARRM_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Compare match
            #[inline(always)]
            pub fn cmpm(&self) -> CMPM_R {
                CMPM_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///Interrupt Clear Register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [icr](icr) module
    pub type ICR = crate::Reg<u32, _ICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ICR;
    ///`write(|w| ..)` method takes [icr::W](icr::W) writer structure
    impl crate::Writable for ICR {}
    ///Interrupt Clear Register
    pub mod icr {
        ///Writer for register ICR
        pub type W = crate::W<u32, super::ICR>;
        ///Register ICR `reset()`'s with value 0
        impl crate::ResetValue for super::ICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `DOWNCF`
        pub struct DOWNCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DOWNCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `UPCF`
        pub struct UPCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UPCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `ARROKCF`
        pub struct ARROKCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARROKCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CMPOKCF`
        pub struct CMPOKCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMPOKCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `EXTTRIGCF`
        pub struct EXTTRIGCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTTRIGCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `ARRMCF`
        pub struct ARRMCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARRMCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CMPMCF`
        pub struct CMPMCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMPMCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 6 - Direction change to down Clear Flag
            #[inline(always)]
            pub fn downcf(&mut self) -> DOWNCF_W {
                DOWNCF_W { w: self }
            }
            ///Bit 5 - Direction change to UP Clear Flag
            #[inline(always)]
            pub fn upcf(&mut self) -> UPCF_W {
                UPCF_W { w: self }
            }
            ///Bit 4 - Autoreload register update OK Clear Flag
            #[inline(always)]
            pub fn arrokcf(&mut self) -> ARROKCF_W {
                ARROKCF_W { w: self }
            }
            ///Bit 3 - Compare register update OK Clear Flag
            #[inline(always)]
            pub fn cmpokcf(&mut self) -> CMPOKCF_W {
                CMPOKCF_W { w: self }
            }
            ///Bit 2 - External trigger valid edge Clear Flag
            #[inline(always)]
            pub fn exttrigcf(&mut self) -> EXTTRIGCF_W {
                EXTTRIGCF_W { w: self }
            }
            ///Bit 1 - Autoreload match Clear Flag
            #[inline(always)]
            pub fn arrmcf(&mut self) -> ARRMCF_W {
                ARRMCF_W { w: self }
            }
            ///Bit 0 - compare match Clear Flag
            #[inline(always)]
            pub fn cmpmcf(&mut self) -> CMPMCF_W {
                CMPMCF_W { w: self }
            }
        }
    }
    ///Interrupt Enable Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ier](ier) module
    pub type IER = crate::Reg<u32, _IER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IER;
    ///`read()` method returns [ier::R](ier::R) reader structure
    impl crate::Readable for IER {}
    ///`write(|w| ..)` method takes [ier::W](ier::W) writer structure
    impl crate::Writable for IER {}
    ///Interrupt Enable Register
    pub mod ier {
        ///Reader of register IER
        pub type R = crate::R<u32, super::IER>;
        ///Writer for register IER
        pub type W = crate::W<u32, super::IER>;
        ///Register IER `reset()`'s with value 0
        impl crate::ResetValue for super::IER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DOWNIE`
        pub type DOWNIE_R = crate::R<bool, bool>;
        ///Write proxy for field `DOWNIE`
        pub struct DOWNIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DOWNIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `UPIE`
        pub type UPIE_R = crate::R<bool, bool>;
        ///Write proxy for field `UPIE`
        pub struct UPIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UPIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `ARROKIE`
        pub type ARROKIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ARROKIE`
        pub struct ARROKIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARROKIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CMPOKIE`
        pub type CMPOKIE_R = crate::R<bool, bool>;
        ///Write proxy for field `CMPOKIE`
        pub struct CMPOKIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMPOKIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `EXTTRIGIE`
        pub type EXTTRIGIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EXTTRIGIE`
        pub struct EXTTRIGIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EXTTRIGIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ARRMIE`
        pub type ARRMIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ARRMIE`
        pub struct ARRMIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARRMIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CMPMIE`
        pub type CMPMIE_R = crate::R<bool, bool>;
        ///Write proxy for field `CMPMIE`
        pub struct CMPMIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMPMIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 6 - Direction change to down Interrupt Enable
            #[inline(always)]
            pub fn downie(&self) -> DOWNIE_R {
                DOWNIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Direction change to UP Interrupt Enable
            #[inline(always)]
            pub fn upie(&self) -> UPIE_R {
                UPIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Autoreload register update OK Interrupt Enable
            #[inline(always)]
            pub fn arrokie(&self) -> ARROKIE_R {
                ARROKIE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Compare register update OK Interrupt Enable
            #[inline(always)]
            pub fn cmpokie(&self) -> CMPOKIE_R {
                CMPOKIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - External trigger valid edge Interrupt Enable
            #[inline(always)]
            pub fn exttrigie(&self) -> EXTTRIGIE_R {
                EXTTRIGIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Autoreload match Interrupt Enable
            #[inline(always)]
            pub fn arrmie(&self) -> ARRMIE_R {
                ARRMIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Compare match Interrupt Enable
            #[inline(always)]
            pub fn cmpmie(&self) -> CMPMIE_R {
                CMPMIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 6 - Direction change to down Interrupt Enable
            #[inline(always)]
            pub fn downie(&mut self) -> DOWNIE_W {
                DOWNIE_W { w: self }
            }
            ///Bit 5 - Direction change to UP Interrupt Enable
            #[inline(always)]
            pub fn upie(&mut self) -> UPIE_W {
                UPIE_W { w: self }
            }
            ///Bit 4 - Autoreload register update OK Interrupt Enable
            #[inline(always)]
            pub fn arrokie(&mut self) -> ARROKIE_W {
                ARROKIE_W { w: self }
            }
            ///Bit 3 - Compare register update OK Interrupt Enable
            #[inline(always)]
            pub fn cmpokie(&mut self) -> CMPOKIE_W {
                CMPOKIE_W { w: self }
            }
            ///Bit 2 - External trigger valid edge Interrupt Enable
            #[inline(always)]
            pub fn exttrigie(&mut self) -> EXTTRIGIE_W {
                EXTTRIGIE_W { w: self }
            }
            ///Bit 1 - Autoreload match Interrupt Enable
            #[inline(always)]
            pub fn arrmie(&mut self) -> ARRMIE_W {
                ARRMIE_W { w: self }
            }
            ///Bit 0 - Compare match Interrupt Enable
            #[inline(always)]
            pub fn cmpmie(&mut self) -> CMPMIE_W {
                CMPMIE_W { w: self }
            }
        }
    }
    ///Configuration Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfgr](cfgr) module
    pub type CFGR = crate::Reg<u32, _CFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFGR;
    ///`read()` method returns [cfgr::R](cfgr::R) reader structure
    impl crate::Readable for CFGR {}
    ///`write(|w| ..)` method takes [cfgr::W](cfgr::W) writer structure
    impl crate::Writable for CFGR {}
    ///Configuration Register
    pub mod cfgr {
        ///Reader of register CFGR
        pub type R = crate::R<u32, super::CFGR>;
        ///Writer for register CFGR
        pub type W = crate::W<u32, super::CFGR>;
        ///Register CFGR `reset()`'s with value 0
        impl crate::ResetValue for super::CFGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ENC`
        pub type ENC_R = crate::R<bool, bool>;
        ///Write proxy for field `ENC`
        pub struct ENC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ENC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `COUNTMODE`
        pub type COUNTMODE_R = crate::R<bool, bool>;
        ///Write proxy for field `COUNTMODE`
        pub struct COUNTMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNTMODE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `PRELOAD`
        pub type PRELOAD_R = crate::R<bool, bool>;
        ///Write proxy for field `PRELOAD`
        pub struct PRELOAD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRELOAD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `WAVPOL`
        pub type WAVPOL_R = crate::R<bool, bool>;
        ///Write proxy for field `WAVPOL`
        pub struct WAVPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WAVPOL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `WAVE`
        pub type WAVE_R = crate::R<bool, bool>;
        ///Write proxy for field `WAVE`
        pub struct WAVE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WAVE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `TIMOUT`
        pub type TIMOUT_R = crate::R<bool, bool>;
        ///Write proxy for field `TIMOUT`
        pub struct TIMOUT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TIMOUT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `TRIGEN`
        pub type TRIGEN_R = crate::R<u8, u8>;
        ///Write proxy for field `TRIGEN`
        pub struct TRIGEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TRIGEN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
                self.w
            }
        }
        ///Reader of field `TRIGSEL`
        pub type TRIGSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `TRIGSEL`
        pub struct TRIGSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TRIGSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 13)) | (((value as u32) & 0x07) << 13);
                self.w
            }
        }
        ///Reader of field `PRESC`
        pub type PRESC_R = crate::R<u8, u8>;
        ///Write proxy for field `PRESC`
        pub struct PRESC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRESC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 9)) | (((value as u32) & 0x07) << 9);
                self.w
            }
        }
        ///Reader of field `TRGFLT`
        pub type TRGFLT_R = crate::R<u8, u8>;
        ///Write proxy for field `TRGFLT`
        pub struct TRGFLT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TRGFLT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
                self.w
            }
        }
        ///Reader of field `CKFLT`
        pub type CKFLT_R = crate::R<u8, u8>;
        ///Write proxy for field `CKFLT`
        pub struct CKFLT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKFLT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
                self.w
            }
        }
        ///Reader of field `CKPOL`
        pub type CKPOL_R = crate::R<u8, u8>;
        ///Write proxy for field `CKPOL`
        pub struct CKPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKPOL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1);
                self.w
            }
        }
        ///Reader of field `CKSEL`
        pub type CKSEL_R = crate::R<bool, bool>;
        ///Write proxy for field `CKSEL`
        pub struct CKSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CKSEL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 24 - Encoder mode enable
            #[inline(always)]
            pub fn enc(&self) -> ENC_R {
                ENC_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - counter mode enabled
            #[inline(always)]
            pub fn countmode(&self) -> COUNTMODE_R {
                COUNTMODE_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - Registers update mode
            #[inline(always)]
            pub fn preload(&self) -> PRELOAD_R {
                PRELOAD_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - Waveform shape polarity
            #[inline(always)]
            pub fn wavpol(&self) -> WAVPOL_R {
                WAVPOL_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - Waveform shape
            #[inline(always)]
            pub fn wave(&self) -> WAVE_R {
                WAVE_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Timeout enable
            #[inline(always)]
            pub fn timout(&self) -> TIMOUT_R {
                TIMOUT_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bits 17:18 - Trigger enable and polarity
            #[inline(always)]
            pub fn trigen(&self) -> TRIGEN_R {
                TRIGEN_R::new(((self.bits >> 17) & 0x03) as u8)
            }
            ///Bits 13:15 - Trigger selector
            #[inline(always)]
            pub fn trigsel(&self) -> TRIGSEL_R {
                TRIGSEL_R::new(((self.bits >> 13) & 0x07) as u8)
            }
            ///Bits 9:11 - Clock prescaler
            #[inline(always)]
            pub fn presc(&self) -> PRESC_R {
                PRESC_R::new(((self.bits >> 9) & 0x07) as u8)
            }
            ///Bits 6:7 - Configurable digital filter for trigger
            #[inline(always)]
            pub fn trgflt(&self) -> TRGFLT_R {
                TRGFLT_R::new(((self.bits >> 6) & 0x03) as u8)
            }
            ///Bits 3:4 - Configurable digital filter for external clock
            #[inline(always)]
            pub fn ckflt(&self) -> CKFLT_R {
                CKFLT_R::new(((self.bits >> 3) & 0x03) as u8)
            }
            ///Bits 1:2 - Clock Polarity
            #[inline(always)]
            pub fn ckpol(&self) -> CKPOL_R {
                CKPOL_R::new(((self.bits >> 1) & 0x03) as u8)
            }
            ///Bit 0 - Clock selector
            #[inline(always)]
            pub fn cksel(&self) -> CKSEL_R {
                CKSEL_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 24 - Encoder mode enable
            #[inline(always)]
            pub fn enc(&mut self) -> ENC_W {
                ENC_W { w: self }
            }
            ///Bit 23 - counter mode enabled
            #[inline(always)]
            pub fn countmode(&mut self) -> COUNTMODE_W {
                COUNTMODE_W { w: self }
            }
            ///Bit 22 - Registers update mode
            #[inline(always)]
            pub fn preload(&mut self) -> PRELOAD_W {
                PRELOAD_W { w: self }
            }
            ///Bit 21 - Waveform shape polarity
            #[inline(always)]
            pub fn wavpol(&mut self) -> WAVPOL_W {
                WAVPOL_W { w: self }
            }
            ///Bit 20 - Waveform shape
            #[inline(always)]
            pub fn wave(&mut self) -> WAVE_W {
                WAVE_W { w: self }
            }
            ///Bit 19 - Timeout enable
            #[inline(always)]
            pub fn timout(&mut self) -> TIMOUT_W {
                TIMOUT_W { w: self }
            }
            ///Bits 17:18 - Trigger enable and polarity
            #[inline(always)]
            pub fn trigen(&mut self) -> TRIGEN_W {
                TRIGEN_W { w: self }
            }
            ///Bits 13:15 - Trigger selector
            #[inline(always)]
            pub fn trigsel(&mut self) -> TRIGSEL_W {
                TRIGSEL_W { w: self }
            }
            ///Bits 9:11 - Clock prescaler
            #[inline(always)]
            pub fn presc(&mut self) -> PRESC_W {
                PRESC_W { w: self }
            }
            ///Bits 6:7 - Configurable digital filter for trigger
            #[inline(always)]
            pub fn trgflt(&mut self) -> TRGFLT_W {
                TRGFLT_W { w: self }
            }
            ///Bits 3:4 - Configurable digital filter for external clock
            #[inline(always)]
            pub fn ckflt(&mut self) -> CKFLT_W {
                CKFLT_W { w: self }
            }
            ///Bits 1:2 - Clock Polarity
            #[inline(always)]
            pub fn ckpol(&mut self) -> CKPOL_W {
                CKPOL_W { w: self }
            }
            ///Bit 0 - Clock selector
            #[inline(always)]
            pub fn cksel(&mut self) -> CKSEL_W {
                CKSEL_W { w: self }
            }
        }
    }
    ///Control Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Control Register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RSTARE`
        pub type RSTARE_R = crate::R<bool, bool>;
        ///Write proxy for field `RSTARE`
        pub struct RSTARE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RSTARE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `COUNTRST`
        pub type COUNTRST_R = crate::R<bool, bool>;
        ///Write proxy for field `COUNTRST`
        pub struct COUNTRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNTRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CNTSTRT`
        pub type CNTSTRT_R = crate::R<bool, bool>;
        ///Write proxy for field `CNTSTRT`
        pub struct CNTSTRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CNTSTRT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `SNGSTRT`
        pub type SNGSTRT_R = crate::R<bool, bool>;
        ///Write proxy for field `SNGSTRT`
        pub struct SNGSTRT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SNGSTRT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ENABLE`
        pub type ENABLE_R = crate::R<bool, bool>;
        ///Write proxy for field `ENABLE`
        pub struct ENABLE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ENABLE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 4 - Reset after read enable
            #[inline(always)]
            pub fn rstare(&self) -> RSTARE_R {
                RSTARE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Counter reset
            #[inline(always)]
            pub fn countrst(&self) -> COUNTRST_R {
                COUNTRST_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Timer start in continuous mode
            #[inline(always)]
            pub fn cntstrt(&self) -> CNTSTRT_R {
                CNTSTRT_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - LPTIM start in single mode
            #[inline(always)]
            pub fn sngstrt(&self) -> SNGSTRT_R {
                SNGSTRT_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - LPTIM Enable
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 4 - Reset after read enable
            #[inline(always)]
            pub fn rstare(&mut self) -> RSTARE_W {
                RSTARE_W { w: self }
            }
            ///Bit 3 - Counter reset
            #[inline(always)]
            pub fn countrst(&mut self) -> COUNTRST_W {
                COUNTRST_W { w: self }
            }
            ///Bit 2 - Timer start in continuous mode
            #[inline(always)]
            pub fn cntstrt(&mut self) -> CNTSTRT_W {
                CNTSTRT_W { w: self }
            }
            ///Bit 1 - LPTIM start in single mode
            #[inline(always)]
            pub fn sngstrt(&mut self) -> SNGSTRT_W {
                SNGSTRT_W { w: self }
            }
            ///Bit 0 - LPTIM Enable
            #[inline(always)]
            pub fn enable(&mut self) -> ENABLE_W {
                ENABLE_W { w: self }
            }
        }
    }
    ///Compare Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cmp](cmp) module
    pub type CMP = crate::Reg<u32, _CMP>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CMP;
    ///`read()` method returns [cmp::R](cmp::R) reader structure
    impl crate::Readable for CMP {}
    ///`write(|w| ..)` method takes [cmp::W](cmp::W) writer structure
    impl crate::Writable for CMP {}
    ///Compare Register
    pub mod cmp {
        ///Reader of register CMP
        pub type R = crate::R<u32, super::CMP>;
        ///Writer for register CMP
        pub type W = crate::W<u32, super::CMP>;
        ///Register CMP `reset()`'s with value 0
        impl crate::ResetValue for super::CMP {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CMP`
        pub type CMP_R = crate::R<u16, u16>;
        ///Write proxy for field `CMP`
        pub struct CMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Compare value
            #[inline(always)]
            pub fn cmp(&self) -> CMP_R {
                CMP_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Compare value
            #[inline(always)]
            pub fn cmp(&mut self) -> CMP_W {
                CMP_W { w: self }
            }
        }
    }
    ///Autoreload Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [arr](arr) module
    pub type ARR = crate::Reg<u32, _ARR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ARR;
    ///`read()` method returns [arr::R](arr::R) reader structure
    impl crate::Readable for ARR {}
    ///`write(|w| ..)` method takes [arr::W](arr::W) writer structure
    impl crate::Writable for ARR {}
    ///Autoreload Register
    pub mod arr {
        ///Reader of register ARR
        pub type R = crate::R<u32, super::ARR>;
        ///Writer for register ARR
        pub type W = crate::W<u32, super::ARR>;
        ///Register ARR `reset()`'s with value 0x01
        impl crate::ResetValue for super::ARR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x01
            }
        }
        ///Reader of field `ARR`
        pub type ARR_R = crate::R<u16, u16>;
        ///Write proxy for field `ARR`
        pub struct ARR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ARR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Auto reload value
            #[inline(always)]
            pub fn arr(&self) -> ARR_R {
                ARR_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Auto reload value
            #[inline(always)]
            pub fn arr(&mut self) -> ARR_W {
                ARR_W { w: self }
            }
        }
    }
    ///Counter Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cnt](cnt) module
    pub type CNT = crate::Reg<u32, _CNT>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNT;
    ///`read()` method returns [cnt::R](cnt::R) reader structure
    impl crate::Readable for CNT {}
    ///Counter Register
    pub mod cnt {
        ///Reader of register CNT
        pub type R = crate::R<u32, super::CNT>;
        ///Reader of field `CNT`
        pub type CNT_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - Counter value
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///Option Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [or](or) module
    pub type OR = crate::Reg<u32, _OR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OR;
    ///`read()` method returns [or::R](or::R) reader structure
    impl crate::Readable for OR {}
    ///`write(|w| ..)` method takes [or::W](or::W) writer structure
    impl crate::Writable for OR {}
    ///Option Register
    pub mod or {
        ///Reader of register OR
        pub type R = crate::R<u32, super::OR>;
        ///Writer for register OR
        pub type W = crate::W<u32, super::OR>;
        ///Register OR `reset()`'s with value 0
        impl crate::ResetValue for super::OR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `OR1`
        pub type OR1_R = crate::R<bool, bool>;
        ///Write proxy for field `OR1`
        pub struct OR1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OR1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `OR2`
        pub type OR2_R = crate::R<bool, bool>;
        ///Write proxy for field `OR2`
        pub struct OR2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OR2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Option register bit 1
            #[inline(always)]
            pub fn or1(&self) -> OR1_R {
                OR1_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Option register bit 2
            #[inline(always)]
            pub fn or2(&self) -> OR2_R {
                OR2_R::new(((self.bits >> 1) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Option register bit 1
            #[inline(always)]
            pub fn or1(&mut self) -> OR1_W {
                OR1_W { w: self }
            }
            ///Bit 1 - Option register bit 2
            #[inline(always)]
            pub fn or2(&mut self) -> OR2_W {
                OR2_W { w: self }
            }
        }
    }
}
///Low power timer
pub struct LPTIM2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LPTIM2 {}
impl LPTIM2 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const lptim1::RegisterBlock {
        0x4000_9400 as *const _
    }
}
impl Deref for LPTIM2 {
    type Target = lptim1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*LPTIM2::ptr() }
    }
}
///Universal synchronous asynchronous receiver transmitter
pub struct USART1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for USART1 {}
impl USART1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const usart1::RegisterBlock {
        0x4001_3800 as *const _
    }
}
impl Deref for USART1 {
    type Target = usart1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*USART1::ptr() }
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod usart1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Control register 1
        pub cr1: CR1,
        ///0x04 - Control register 2
        pub cr2: CR2,
        ///0x08 - Control register 3
        pub cr3: CR3,
        ///0x0c - Baud rate register
        pub brr: BRR,
        ///0x10 - Guard time and prescaler register
        pub gtpr: GTPR,
        ///0x14 - Receiver timeout register
        pub rtor: RTOR,
        ///0x18 - Request register
        pub rqr: RQR,
        ///0x1c - Interrupt & status register
        pub isr: ISR,
        ///0x20 - Interrupt flag clear register
        pub icr: ICR,
        ///0x24 - Receive data register
        pub rdr: RDR,
        ///0x28 - Transmit data register
        pub tdr: TDR,
        ///0x2c - Prescaler register
        pub presc: PRESC,
    }
    ///Control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///Control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RXFFIE`
        pub type RXFFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RXFFIE`
        pub struct RXFFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXFFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `TXFEIE`
        pub type TXFEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXFEIE`
        pub struct TXFEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXFEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `FIFOEN`
        pub type FIFOEN_R = crate::R<bool, bool>;
        ///Write proxy for field `FIFOEN`
        pub struct FIFOEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FIFOEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `M1`
        pub type M1_R = crate::R<bool, bool>;
        ///Write proxy for field `M1`
        pub struct M1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> M1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `EOBIE`
        pub type EOBIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EOBIE`
        pub struct EOBIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOBIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `RTOIE`
        pub type RTOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RTOIE`
        pub struct RTOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `DEAT4`
        pub type DEAT4_R = crate::R<bool, bool>;
        ///Write proxy for field `DEAT4`
        pub struct DEAT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEAT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `DEAT3`
        pub type DEAT3_R = crate::R<bool, bool>;
        ///Write proxy for field `DEAT3`
        pub struct DEAT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEAT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `DEAT2`
        pub type DEAT2_R = crate::R<bool, bool>;
        ///Write proxy for field `DEAT2`
        pub struct DEAT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEAT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `DEAT1`
        pub type DEAT1_R = crate::R<bool, bool>;
        ///Write proxy for field `DEAT1`
        pub struct DEAT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEAT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `DEAT0`
        pub type DEAT0_R = crate::R<bool, bool>;
        ///Write proxy for field `DEAT0`
        pub struct DEAT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEAT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `DEDT4`
        pub type DEDT4_R = crate::R<bool, bool>;
        ///Write proxy for field `DEDT4`
        pub struct DEDT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEDT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `DEDT3`
        pub type DEDT3_R = crate::R<bool, bool>;
        ///Write proxy for field `DEDT3`
        pub struct DEDT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEDT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `DEDT2`
        pub type DEDT2_R = crate::R<bool, bool>;
        ///Write proxy for field `DEDT2`
        pub struct DEDT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEDT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `DEDT1`
        pub type DEDT1_R = crate::R<bool, bool>;
        ///Write proxy for field `DEDT1`
        pub struct DEDT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEDT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `DEDT0`
        pub type DEDT0_R = crate::R<bool, bool>;
        ///Write proxy for field `DEDT0`
        pub struct DEDT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEDT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `OVER8`
        pub type OVER8_R = crate::R<bool, bool>;
        ///Write proxy for field `OVER8`
        pub struct OVER8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVER8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `CMIE`
        pub type CMIE_R = crate::R<bool, bool>;
        ///Write proxy for field `CMIE`
        pub struct CMIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `MME`
        pub type MME_R = crate::R<bool, bool>;
        ///Write proxy for field `MME`
        pub struct MME_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MME_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `M0`
        pub type M0_R = crate::R<bool, bool>;
        ///Write proxy for field `M0`
        pub struct M0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> M0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `WAKE`
        pub type WAKE_R = crate::R<bool, bool>;
        ///Write proxy for field `WAKE`
        pub struct WAKE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WAKE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `PCE`
        pub type PCE_R = crate::R<bool, bool>;
        ///Write proxy for field `PCE`
        pub struct PCE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PCE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `PS`
        pub type PS_R = crate::R<bool, bool>;
        ///Write proxy for field `PS`
        pub struct PS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `PEIE`
        pub type PEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `PEIE`
        pub struct PEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `TXEIE`
        pub type TXEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXEIE`
        pub struct TXEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `TCIE`
        pub type TCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCIE`
        pub struct TCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `RXNEIE`
        pub type RXNEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RXNEIE`
        pub struct RXNEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXNEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `IDLEIE`
        pub type IDLEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `IDLEIE`
        pub struct IDLEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IDLEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TE`
        pub type TE_R = crate::R<bool, bool>;
        ///Write proxy for field `TE`
        pub struct TE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `RE`
        pub type RE_R = crate::R<bool, bool>;
        ///Write proxy for field `RE`
        pub struct RE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `UESM`
        pub type UESM_R = crate::R<bool, bool>;
        ///Write proxy for field `UESM`
        pub struct UESM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UESM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `UE`
        pub type UE_R = crate::R<bool, bool>;
        ///Write proxy for field `UE`
        pub struct UE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 31 - RXFIFO Full interrupt enable
            #[inline(always)]
            pub fn rxffie(&self) -> RXFFIE_R {
                RXFFIE_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - TXFIFO empty interrupt enable
            #[inline(always)]
            pub fn txfeie(&self) -> TXFEIE_R {
                TXFEIE_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 29 - FIFO mode enable
            #[inline(always)]
            pub fn fifoen(&self) -> FIFOEN_R {
                FIFOEN_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 28 - Word length
            #[inline(always)]
            pub fn m1(&self) -> M1_R {
                M1_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 27 - End of Block interrupt enable
            #[inline(always)]
            pub fn eobie(&self) -> EOBIE_R {
                EOBIE_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - Receiver timeout interrupt enable
            #[inline(always)]
            pub fn rtoie(&self) -> RTOIE_R {
                RTOIE_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - Driver Enable assertion time
            #[inline(always)]
            pub fn deat4(&self) -> DEAT4_R {
                DEAT4_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - DEAT3
            #[inline(always)]
            pub fn deat3(&self) -> DEAT3_R {
                DEAT3_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - DEAT2
            #[inline(always)]
            pub fn deat2(&self) -> DEAT2_R {
                DEAT2_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - DEAT1
            #[inline(always)]
            pub fn deat1(&self) -> DEAT1_R {
                DEAT1_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - DEAT0
            #[inline(always)]
            pub fn deat0(&self) -> DEAT0_R {
                DEAT0_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - Driver Enable de-assertion time
            #[inline(always)]
            pub fn dedt4(&self) -> DEDT4_R {
                DEDT4_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - DEDT3
            #[inline(always)]
            pub fn dedt3(&self) -> DEDT3_R {
                DEDT3_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - DEDT2
            #[inline(always)]
            pub fn dedt2(&self) -> DEDT2_R {
                DEDT2_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - DEDT1
            #[inline(always)]
            pub fn dedt1(&self) -> DEDT1_R {
                DEDT1_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - DEDT0
            #[inline(always)]
            pub fn dedt0(&self) -> DEDT0_R {
                DEDT0_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Oversampling mode
            #[inline(always)]
            pub fn over8(&self) -> OVER8_R {
                OVER8_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Character match interrupt enable
            #[inline(always)]
            pub fn cmie(&self) -> CMIE_R {
                CMIE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Mute mode enable
            #[inline(always)]
            pub fn mme(&self) -> MME_R {
                MME_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Word length
            #[inline(always)]
            pub fn m0(&self) -> M0_R {
                M0_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Receiver wakeup method
            #[inline(always)]
            pub fn wake(&self) -> WAKE_R {
                WAKE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Parity control enable
            #[inline(always)]
            pub fn pce(&self) -> PCE_R {
                PCE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Parity selection
            #[inline(always)]
            pub fn ps(&self) -> PS_R {
                PS_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - PE interrupt enable
            #[inline(always)]
            pub fn peie(&self) -> PEIE_R {
                PEIE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - interrupt enable
            #[inline(always)]
            pub fn txeie(&self) -> TXEIE_R {
                TXEIE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - Transmission complete interrupt enable
            #[inline(always)]
            pub fn tcie(&self) -> TCIE_R {
                TCIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - RXNE interrupt enable
            #[inline(always)]
            pub fn rxneie(&self) -> RXNEIE_R {
                RXNEIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - IDLE interrupt enable
            #[inline(always)]
            pub fn idleie(&self) -> IDLEIE_R {
                IDLEIE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Transmitter enable
            #[inline(always)]
            pub fn te(&self) -> TE_R {
                TE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Receiver enable
            #[inline(always)]
            pub fn re(&self) -> RE_R {
                RE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - USART enable in Stop mode
            #[inline(always)]
            pub fn uesm(&self) -> UESM_R {
                UESM_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - USART enable
            #[inline(always)]
            pub fn ue(&self) -> UE_R {
                UE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 31 - RXFIFO Full interrupt enable
            #[inline(always)]
            pub fn rxffie(&mut self) -> RXFFIE_W {
                RXFFIE_W { w: self }
            }
            ///Bit 30 - TXFIFO empty interrupt enable
            #[inline(always)]
            pub fn txfeie(&mut self) -> TXFEIE_W {
                TXFEIE_W { w: self }
            }
            ///Bit 29 - FIFO mode enable
            #[inline(always)]
            pub fn fifoen(&mut self) -> FIFOEN_W {
                FIFOEN_W { w: self }
            }
            ///Bit 28 - Word length
            #[inline(always)]
            pub fn m1(&mut self) -> M1_W {
                M1_W { w: self }
            }
            ///Bit 27 - End of Block interrupt enable
            #[inline(always)]
            pub fn eobie(&mut self) -> EOBIE_W {
                EOBIE_W { w: self }
            }
            ///Bit 26 - Receiver timeout interrupt enable
            #[inline(always)]
            pub fn rtoie(&mut self) -> RTOIE_W {
                RTOIE_W { w: self }
            }
            ///Bit 25 - Driver Enable assertion time
            #[inline(always)]
            pub fn deat4(&mut self) -> DEAT4_W {
                DEAT4_W { w: self }
            }
            ///Bit 24 - DEAT3
            #[inline(always)]
            pub fn deat3(&mut self) -> DEAT3_W {
                DEAT3_W { w: self }
            }
            ///Bit 23 - DEAT2
            #[inline(always)]
            pub fn deat2(&mut self) -> DEAT2_W {
                DEAT2_W { w: self }
            }
            ///Bit 22 - DEAT1
            #[inline(always)]
            pub fn deat1(&mut self) -> DEAT1_W {
                DEAT1_W { w: self }
            }
            ///Bit 21 - DEAT0
            #[inline(always)]
            pub fn deat0(&mut self) -> DEAT0_W {
                DEAT0_W { w: self }
            }
            ///Bit 20 - Driver Enable de-assertion time
            #[inline(always)]
            pub fn dedt4(&mut self) -> DEDT4_W {
                DEDT4_W { w: self }
            }
            ///Bit 19 - DEDT3
            #[inline(always)]
            pub fn dedt3(&mut self) -> DEDT3_W {
                DEDT3_W { w: self }
            }
            ///Bit 18 - DEDT2
            #[inline(always)]
            pub fn dedt2(&mut self) -> DEDT2_W {
                DEDT2_W { w: self }
            }
            ///Bit 17 - DEDT1
            #[inline(always)]
            pub fn dedt1(&mut self) -> DEDT1_W {
                DEDT1_W { w: self }
            }
            ///Bit 16 - DEDT0
            #[inline(always)]
            pub fn dedt0(&mut self) -> DEDT0_W {
                DEDT0_W { w: self }
            }
            ///Bit 15 - Oversampling mode
            #[inline(always)]
            pub fn over8(&mut self) -> OVER8_W {
                OVER8_W { w: self }
            }
            ///Bit 14 - Character match interrupt enable
            #[inline(always)]
            pub fn cmie(&mut self) -> CMIE_W {
                CMIE_W { w: self }
            }
            ///Bit 13 - Mute mode enable
            #[inline(always)]
            pub fn mme(&mut self) -> MME_W {
                MME_W { w: self }
            }
            ///Bit 12 - Word length
            #[inline(always)]
            pub fn m0(&mut self) -> M0_W {
                M0_W { w: self }
            }
            ///Bit 11 - Receiver wakeup method
            #[inline(always)]
            pub fn wake(&mut self) -> WAKE_W {
                WAKE_W { w: self }
            }
            ///Bit 10 - Parity control enable
            #[inline(always)]
            pub fn pce(&mut self) -> PCE_W {
                PCE_W { w: self }
            }
            ///Bit 9 - Parity selection
            #[inline(always)]
            pub fn ps(&mut self) -> PS_W {
                PS_W { w: self }
            }
            ///Bit 8 - PE interrupt enable
            #[inline(always)]
            pub fn peie(&mut self) -> PEIE_W {
                PEIE_W { w: self }
            }
            ///Bit 7 - interrupt enable
            #[inline(always)]
            pub fn txeie(&mut self) -> TXEIE_W {
                TXEIE_W { w: self }
            }
            ///Bit 6 - Transmission complete interrupt enable
            #[inline(always)]
            pub fn tcie(&mut self) -> TCIE_W {
                TCIE_W { w: self }
            }
            ///Bit 5 - RXNE interrupt enable
            #[inline(always)]
            pub fn rxneie(&mut self) -> RXNEIE_W {
                RXNEIE_W { w: self }
            }
            ///Bit 4 - IDLE interrupt enable
            #[inline(always)]
            pub fn idleie(&mut self) -> IDLEIE_W {
                IDLEIE_W { w: self }
            }
            ///Bit 3 - Transmitter enable
            #[inline(always)]
            pub fn te(&mut self) -> TE_W {
                TE_W { w: self }
            }
            ///Bit 2 - Receiver enable
            #[inline(always)]
            pub fn re(&mut self) -> RE_W {
                RE_W { w: self }
            }
            ///Bit 1 - USART enable in Stop mode
            #[inline(always)]
            pub fn uesm(&mut self) -> UESM_W {
                UESM_W { w: self }
            }
            ///Bit 0 - USART enable
            #[inline(always)]
            pub fn ue(&mut self) -> UE_W {
                UE_W { w: self }
            }
        }
    }
    ///Control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///Control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADD4_7`
        pub type ADD4_7_R = crate::R<u8, u8>;
        ///Write proxy for field `ADD4_7`
        pub struct ADD4_7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADD4_7_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
                self.w
            }
        }
        ///Reader of field `ADD0_3`
        pub type ADD0_3_R = crate::R<u8, u8>;
        ///Write proxy for field `ADD0_3`
        pub struct ADD0_3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADD0_3_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `RTOEN`
        pub type RTOEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RTOEN`
        pub struct RTOEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTOEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `ABRMOD1`
        pub type ABRMOD1_R = crate::R<bool, bool>;
        ///Write proxy for field `ABRMOD1`
        pub struct ABRMOD1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ABRMOD1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `ABRMOD0`
        pub type ABRMOD0_R = crate::R<bool, bool>;
        ///Write proxy for field `ABRMOD0`
        pub struct ABRMOD0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ABRMOD0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `ABREN`
        pub type ABREN_R = crate::R<bool, bool>;
        ///Write proxy for field `ABREN`
        pub struct ABREN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ABREN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `MSBFIRST`
        pub type MSBFIRST_R = crate::R<bool, bool>;
        ///Write proxy for field `MSBFIRST`
        pub struct MSBFIRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSBFIRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `TAINV`
        pub type TAINV_R = crate::R<bool, bool>;
        ///Write proxy for field `TAINV`
        pub struct TAINV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAINV_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TXINV`
        pub type TXINV_R = crate::R<bool, bool>;
        ///Write proxy for field `TXINV`
        pub struct TXINV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXINV_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `RXINV`
        pub type RXINV_R = crate::R<bool, bool>;
        ///Write proxy for field `RXINV`
        pub struct RXINV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXINV_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `SWAP`
        pub type SWAP_R = crate::R<bool, bool>;
        ///Write proxy for field `SWAP`
        pub struct SWAP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SWAP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `LINEN`
        pub type LINEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LINEN`
        pub struct LINEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LINEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `STOP`
        pub type STOP_R = crate::R<u8, u8>;
        ///Write proxy for field `STOP`
        pub struct STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STOP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `CLKEN`
        pub type CLKEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CLKEN`
        pub struct CLKEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CLKEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CPOL`
        pub type CPOL_R = crate::R<bool, bool>;
        ///Write proxy for field `CPOL`
        pub struct CPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CPOL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CPHA`
        pub type CPHA_R = crate::R<bool, bool>;
        ///Write proxy for field `CPHA`
        pub struct CPHA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CPHA_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `LBCL`
        pub type LBCL_R = crate::R<bool, bool>;
        ///Write proxy for field `LBCL`
        pub struct LBCL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LBCL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `LBDIE`
        pub type LBDIE_R = crate::R<bool, bool>;
        ///Write proxy for field `LBDIE`
        pub struct LBDIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LBDIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `LBDL`
        pub type LBDL_R = crate::R<bool, bool>;
        ///Write proxy for field `LBDL`
        pub struct LBDL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LBDL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `ADDM7`
        pub type ADDM7_R = crate::R<bool, bool>;
        ///Write proxy for field `ADDM7`
        pub struct ADDM7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDM7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `DIS_NSS`
        pub type DIS_NSS_R = crate::R<bool, bool>;
        ///Write proxy for field `DIS_NSS`
        pub struct DIS_NSS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DIS_NSS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `SLVEN`
        pub type SLVEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SLVEN`
        pub struct SLVEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SLVEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 28:31 - Address of the USART node
            #[inline(always)]
            pub fn add4_7(&self) -> ADD4_7_R {
                ADD4_7_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
            ///Bits 24:27 - Address of the USART node
            #[inline(always)]
            pub fn add0_3(&self) -> ADD0_3_R {
                ADD0_3_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bit 23 - Receiver timeout enable
            #[inline(always)]
            pub fn rtoen(&self) -> RTOEN_R {
                RTOEN_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - Auto baud rate mode
            #[inline(always)]
            pub fn abrmod1(&self) -> ABRMOD1_R {
                ABRMOD1_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - ABRMOD0
            #[inline(always)]
            pub fn abrmod0(&self) -> ABRMOD0_R {
                ABRMOD0_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - Auto baud rate enable
            #[inline(always)]
            pub fn abren(&self) -> ABREN_R {
                ABREN_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Most significant bit first
            #[inline(always)]
            pub fn msbfirst(&self) -> MSBFIRST_R {
                MSBFIRST_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - Binary data inversion
            #[inline(always)]
            pub fn tainv(&self) -> TAINV_R {
                TAINV_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - TX pin active level inversion
            #[inline(always)]
            pub fn txinv(&self) -> TXINV_R {
                TXINV_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - RX pin active level inversion
            #[inline(always)]
            pub fn rxinv(&self) -> RXINV_R {
                RXINV_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - Swap TX/RX pins
            #[inline(always)]
            pub fn swap(&self) -> SWAP_R {
                SWAP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - LIN mode enable
            #[inline(always)]
            pub fn linen(&self) -> LINEN_R {
                LINEN_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bits 12:13 - STOP bits
            #[inline(always)]
            pub fn stop(&self) -> STOP_R {
                STOP_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 11 - Clock enable
            #[inline(always)]
            pub fn clken(&self) -> CLKEN_R {
                CLKEN_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Clock polarity
            #[inline(always)]
            pub fn cpol(&self) -> CPOL_R {
                CPOL_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Clock phase
            #[inline(always)]
            pub fn cpha(&self) -> CPHA_R {
                CPHA_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Last bit clock pulse
            #[inline(always)]
            pub fn lbcl(&self) -> LBCL_R {
                LBCL_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 6 - LIN break detection interrupt enable
            #[inline(always)]
            pub fn lbdie(&self) -> LBDIE_R {
                LBDIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - LIN break detection length
            #[inline(always)]
            pub fn lbdl(&self) -> LBDL_R {
                LBDL_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - 7-bit Address Detection/4-bit Address Detection
            #[inline(always)]
            pub fn addm7(&self) -> ADDM7_R {
                ADDM7_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored
            #[inline(always)]
            pub fn dis_nss(&self) -> DIS_NSS_R {
                DIS_NSS_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 0 - Synchronous Slave mode enable
            #[inline(always)]
            pub fn slven(&self) -> SLVEN_R {
                SLVEN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 28:31 - Address of the USART node
            #[inline(always)]
            pub fn add4_7(&mut self) -> ADD4_7_W {
                ADD4_7_W { w: self }
            }
            ///Bits 24:27 - Address of the USART node
            #[inline(always)]
            pub fn add0_3(&mut self) -> ADD0_3_W {
                ADD0_3_W { w: self }
            }
            ///Bit 23 - Receiver timeout enable
            #[inline(always)]
            pub fn rtoen(&mut self) -> RTOEN_W {
                RTOEN_W { w: self }
            }
            ///Bit 22 - Auto baud rate mode
            #[inline(always)]
            pub fn abrmod1(&mut self) -> ABRMOD1_W {
                ABRMOD1_W { w: self }
            }
            ///Bit 21 - ABRMOD0
            #[inline(always)]
            pub fn abrmod0(&mut self) -> ABRMOD0_W {
                ABRMOD0_W { w: self }
            }
            ///Bit 20 - Auto baud rate enable
            #[inline(always)]
            pub fn abren(&mut self) -> ABREN_W {
                ABREN_W { w: self }
            }
            ///Bit 19 - Most significant bit first
            #[inline(always)]
            pub fn msbfirst(&mut self) -> MSBFIRST_W {
                MSBFIRST_W { w: self }
            }
            ///Bit 18 - Binary data inversion
            #[inline(always)]
            pub fn tainv(&mut self) -> TAINV_W {
                TAINV_W { w: self }
            }
            ///Bit 17 - TX pin active level inversion
            #[inline(always)]
            pub fn txinv(&mut self) -> TXINV_W {
                TXINV_W { w: self }
            }
            ///Bit 16 - RX pin active level inversion
            #[inline(always)]
            pub fn rxinv(&mut self) -> RXINV_W {
                RXINV_W { w: self }
            }
            ///Bit 15 - Swap TX/RX pins
            #[inline(always)]
            pub fn swap(&mut self) -> SWAP_W {
                SWAP_W { w: self }
            }
            ///Bit 14 - LIN mode enable
            #[inline(always)]
            pub fn linen(&mut self) -> LINEN_W {
                LINEN_W { w: self }
            }
            ///Bits 12:13 - STOP bits
            #[inline(always)]
            pub fn stop(&mut self) -> STOP_W {
                STOP_W { w: self }
            }
            ///Bit 11 - Clock enable
            #[inline(always)]
            pub fn clken(&mut self) -> CLKEN_W {
                CLKEN_W { w: self }
            }
            ///Bit 10 - Clock polarity
            #[inline(always)]
            pub fn cpol(&mut self) -> CPOL_W {
                CPOL_W { w: self }
            }
            ///Bit 9 - Clock phase
            #[inline(always)]
            pub fn cpha(&mut self) -> CPHA_W {
                CPHA_W { w: self }
            }
            ///Bit 8 - Last bit clock pulse
            #[inline(always)]
            pub fn lbcl(&mut self) -> LBCL_W {
                LBCL_W { w: self }
            }
            ///Bit 6 - LIN break detection interrupt enable
            #[inline(always)]
            pub fn lbdie(&mut self) -> LBDIE_W {
                LBDIE_W { w: self }
            }
            ///Bit 5 - LIN break detection length
            #[inline(always)]
            pub fn lbdl(&mut self) -> LBDL_W {
                LBDL_W { w: self }
            }
            ///Bit 4 - 7-bit Address Detection/4-bit Address Detection
            #[inline(always)]
            pub fn addm7(&mut self) -> ADDM7_W {
                ADDM7_W { w: self }
            }
            ///Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored
            #[inline(always)]
            pub fn dis_nss(&mut self) -> DIS_NSS_W {
                DIS_NSS_W { w: self }
            }
            ///Bit 0 - Synchronous Slave mode enable
            #[inline(always)]
            pub fn slven(&mut self) -> SLVEN_W {
                SLVEN_W { w: self }
            }
        }
    }
    ///Control register 3
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr3](cr3) module
    pub type CR3 = crate::Reg<u32, _CR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR3;
    ///`read()` method returns [cr3::R](cr3::R) reader structure
    impl crate::Readable for CR3 {}
    ///`write(|w| ..)` method takes [cr3::W](cr3::W) writer structure
    impl crate::Writable for CR3 {}
    ///Control register 3
    pub mod cr3 {
        ///Reader of register CR3
        pub type R = crate::R<u32, super::CR3>;
        ///Writer for register CR3
        pub type W = crate::W<u32, super::CR3>;
        ///Register CR3 `reset()`'s with value 0
        impl crate::ResetValue for super::CR3 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TXFTCFG`
        pub type TXFTCFG_R = crate::R<u8, u8>;
        ///Write proxy for field `TXFTCFG`
        pub struct TXFTCFG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXFTCFG_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
                self.w
            }
        }
        ///Reader of field `RXFTIE`
        pub type RXFTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RXFTIE`
        pub struct RXFTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXFTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `RXFTCFG`
        pub type RXFTCFG_R = crate::R<u8, u8>;
        ///Write proxy for field `RXFTCFG`
        pub struct RXFTCFG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXFTCFG_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 25)) | (((value as u32) & 0x07) << 25);
                self.w
            }
        }
        ///Reader of field `TCBGTIE`
        pub type TCBGTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TCBGTIE`
        pub struct TCBGTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCBGTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `TXFTIE`
        pub type TXFTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXFTIE`
        pub struct TXFTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXFTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `WUFIE`
        pub type WUFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `WUFIE`
        pub struct WUFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `WUS`
        pub type WUS_R = crate::R<u8, u8>;
        ///Write proxy for field `WUS`
        pub struct WUS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `SCARCNT`
        pub type SCARCNT_R = crate::R<u8, u8>;
        ///Write proxy for field `SCARCNT`
        pub struct SCARCNT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SCARCNT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 17)) | (((value as u32) & 0x07) << 17);
                self.w
            }
        }
        ///Reader of field `DEP`
        pub type DEP_R = crate::R<bool, bool>;
        ///Write proxy for field `DEP`
        pub struct DEP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `DEM`
        pub type DEM_R = crate::R<bool, bool>;
        ///Write proxy for field `DEM`
        pub struct DEM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DEM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `DDRE`
        pub type DDRE_R = crate::R<bool, bool>;
        ///Write proxy for field `DDRE`
        pub struct DDRE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DDRE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `OVRDIS`
        pub type OVRDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `OVRDIS`
        pub struct OVRDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OVRDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ONEBIT`
        pub type ONEBIT_R = crate::R<bool, bool>;
        ///Write proxy for field `ONEBIT`
        pub struct ONEBIT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ONEBIT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `CTSIE`
        pub type CTSIE_R = crate::R<bool, bool>;
        ///Write proxy for field `CTSIE`
        pub struct CTSIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTSIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `CTSE`
        pub type CTSE_R = crate::R<bool, bool>;
        ///Write proxy for field `CTSE`
        pub struct CTSE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTSE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `RTSE`
        pub type RTSE_R = crate::R<bool, bool>;
        ///Write proxy for field `RTSE`
        pub struct RTSE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTSE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DMAT`
        pub type DMAT_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAT`
        pub struct DMAT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `DMAR`
        pub type DMAR_R = crate::R<bool, bool>;
        ///Write proxy for field `DMAR`
        pub struct DMAR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DMAR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `SCEN`
        pub type SCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SCEN`
        pub struct SCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `NACK`
        pub type NACK_R = crate::R<bool, bool>;
        ///Write proxy for field `NACK`
        pub struct NACK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NACK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `HDSEL`
        pub type HDSEL_R = crate::R<bool, bool>;
        ///Write proxy for field `HDSEL`
        pub struct HDSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HDSEL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `IRLP`
        pub type IRLP_R = crate::R<bool, bool>;
        ///Write proxy for field `IRLP`
        pub struct IRLP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IRLP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `IREN`
        pub type IREN_R = crate::R<bool, bool>;
        ///Write proxy for field `IREN`
        pub struct IREN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IREN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EIE`
        pub type EIE_R = crate::R<bool, bool>;
        ///Write proxy for field `EIE`
        pub struct EIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bits 29:31 - TXFIFO threshold configuration
            #[inline(always)]
            pub fn txftcfg(&self) -> TXFTCFG_R {
                TXFTCFG_R::new(((self.bits >> 29) & 0x07) as u8)
            }
            ///Bit 28 - RXFIFO threshold interrupt enable
            #[inline(always)]
            pub fn rxftie(&self) -> RXFTIE_R {
                RXFTIE_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bits 25:27 - Receive FIFO threshold configuration
            #[inline(always)]
            pub fn rxftcfg(&self) -> RXFTCFG_R {
                RXFTCFG_R::new(((self.bits >> 25) & 0x07) as u8)
            }
            ///Bit 24 - Tr Complete before guard time, interrupt enable
            #[inline(always)]
            pub fn tcbgtie(&self) -> TCBGTIE_R {
                TCBGTIE_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - threshold interrupt enable
            #[inline(always)]
            pub fn txftie(&self) -> TXFTIE_R {
                TXFTIE_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - Wakeup from Stop mode interrupt enable
            #[inline(always)]
            pub fn wufie(&self) -> WUFIE_R {
                WUFIE_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bits 20:21 - Wakeup from Stop mode interrupt flag selection
            #[inline(always)]
            pub fn wus(&self) -> WUS_R {
                WUS_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 17:19 - Smartcard auto-retry count
            #[inline(always)]
            pub fn scarcnt(&self) -> SCARCNT_R {
                SCARCNT_R::new(((self.bits >> 17) & 0x07) as u8)
            }
            ///Bit 15 - Driver enable polarity selection
            #[inline(always)]
            pub fn dep(&self) -> DEP_R {
                DEP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Driver enable mode
            #[inline(always)]
            pub fn dem(&self) -> DEM_R {
                DEM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - DMA Disable on Reception Error
            #[inline(always)]
            pub fn ddre(&self) -> DDRE_R {
                DDRE_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - Overrun Disable
            #[inline(always)]
            pub fn ovrdis(&self) -> OVRDIS_R {
                OVRDIS_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - One sample bit method enable
            #[inline(always)]
            pub fn onebit(&self) -> ONEBIT_R {
                ONEBIT_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - CTS interrupt enable
            #[inline(always)]
            pub fn ctsie(&self) -> CTSIE_R {
                CTSIE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - CTS enable
            #[inline(always)]
            pub fn ctse(&self) -> CTSE_R {
                CTSE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - RTS enable
            #[inline(always)]
            pub fn rtse(&self) -> RTSE_R {
                RTSE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - DMA enable transmitter
            #[inline(always)]
            pub fn dmat(&self) -> DMAT_R {
                DMAT_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - DMA enable receiver
            #[inline(always)]
            pub fn dmar(&self) -> DMAR_R {
                DMAR_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - Smartcard mode enable
            #[inline(always)]
            pub fn scen(&self) -> SCEN_R {
                SCEN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - Smartcard NACK enable
            #[inline(always)]
            pub fn nack(&self) -> NACK_R {
                NACK_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - Half-duplex selection
            #[inline(always)]
            pub fn hdsel(&self) -> HDSEL_R {
                HDSEL_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - Ir low-power
            #[inline(always)]
            pub fn irlp(&self) -> IRLP_R {
                IRLP_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Ir mode enable
            #[inline(always)]
            pub fn iren(&self) -> IREN_R {
                IREN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Error interrupt enable
            #[inline(always)]
            pub fn eie(&self) -> EIE_R {
                EIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 29:31 - TXFIFO threshold configuration
            #[inline(always)]
            pub fn txftcfg(&mut self) -> TXFTCFG_W {
                TXFTCFG_W { w: self }
            }
            ///Bit 28 - RXFIFO threshold interrupt enable
            #[inline(always)]
            pub fn rxftie(&mut self) -> RXFTIE_W {
                RXFTIE_W { w: self }
            }
            ///Bits 25:27 - Receive FIFO threshold configuration
            #[inline(always)]
            pub fn rxftcfg(&mut self) -> RXFTCFG_W {
                RXFTCFG_W { w: self }
            }
            ///Bit 24 - Tr Complete before guard time, interrupt enable
            #[inline(always)]
            pub fn tcbgtie(&mut self) -> TCBGTIE_W {
                TCBGTIE_W { w: self }
            }
            ///Bit 23 - threshold interrupt enable
            #[inline(always)]
            pub fn txftie(&mut self) -> TXFTIE_W {
                TXFTIE_W { w: self }
            }
            ///Bit 22 - Wakeup from Stop mode interrupt enable
            #[inline(always)]
            pub fn wufie(&mut self) -> WUFIE_W {
                WUFIE_W { w: self }
            }
            ///Bits 20:21 - Wakeup from Stop mode interrupt flag selection
            #[inline(always)]
            pub fn wus(&mut self) -> WUS_W {
                WUS_W { w: self }
            }
            ///Bits 17:19 - Smartcard auto-retry count
            #[inline(always)]
            pub fn scarcnt(&mut self) -> SCARCNT_W {
                SCARCNT_W { w: self }
            }
            ///Bit 15 - Driver enable polarity selection
            #[inline(always)]
            pub fn dep(&mut self) -> DEP_W {
                DEP_W { w: self }
            }
            ///Bit 14 - Driver enable mode
            #[inline(always)]
            pub fn dem(&mut self) -> DEM_W {
                DEM_W { w: self }
            }
            ///Bit 13 - DMA Disable on Reception Error
            #[inline(always)]
            pub fn ddre(&mut self) -> DDRE_W {
                DDRE_W { w: self }
            }
            ///Bit 12 - Overrun Disable
            #[inline(always)]
            pub fn ovrdis(&mut self) -> OVRDIS_W {
                OVRDIS_W { w: self }
            }
            ///Bit 11 - One sample bit method enable
            #[inline(always)]
            pub fn onebit(&mut self) -> ONEBIT_W {
                ONEBIT_W { w: self }
            }
            ///Bit 10 - CTS interrupt enable
            #[inline(always)]
            pub fn ctsie(&mut self) -> CTSIE_W {
                CTSIE_W { w: self }
            }
            ///Bit 9 - CTS enable
            #[inline(always)]
            pub fn ctse(&mut self) -> CTSE_W {
                CTSE_W { w: self }
            }
            ///Bit 8 - RTS enable
            #[inline(always)]
            pub fn rtse(&mut self) -> RTSE_W {
                RTSE_W { w: self }
            }
            ///Bit 7 - DMA enable transmitter
            #[inline(always)]
            pub fn dmat(&mut self) -> DMAT_W {
                DMAT_W { w: self }
            }
            ///Bit 6 - DMA enable receiver
            #[inline(always)]
            pub fn dmar(&mut self) -> DMAR_W {
                DMAR_W { w: self }
            }
            ///Bit 5 - Smartcard mode enable
            #[inline(always)]
            pub fn scen(&mut self) -> SCEN_W {
                SCEN_W { w: self }
            }
            ///Bit 4 - Smartcard NACK enable
            #[inline(always)]
            pub fn nack(&mut self) -> NACK_W {
                NACK_W { w: self }
            }
            ///Bit 3 - Half-duplex selection
            #[inline(always)]
            pub fn hdsel(&mut self) -> HDSEL_W {
                HDSEL_W { w: self }
            }
            ///Bit 2 - Ir low-power
            #[inline(always)]
            pub fn irlp(&mut self) -> IRLP_W {
                IRLP_W { w: self }
            }
            ///Bit 1 - Ir mode enable
            #[inline(always)]
            pub fn iren(&mut self) -> IREN_W {
                IREN_W { w: self }
            }
            ///Bit 0 - Error interrupt enable
            #[inline(always)]
            pub fn eie(&mut self) -> EIE_W {
                EIE_W { w: self }
            }
        }
    }
    ///Baud rate register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [brr](brr) module
    pub type BRR = crate::Reg<u32, _BRR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BRR;
    ///`read()` method returns [brr::R](brr::R) reader structure
    impl crate::Readable for BRR {}
    ///`write(|w| ..)` method takes [brr::W](brr::W) writer structure
    impl crate::Writable for BRR {}
    ///Baud rate register
    pub mod brr {
        ///Reader of register BRR
        pub type R = crate::R<u32, super::BRR>;
        ///Writer for register BRR
        pub type W = crate::W<u32, super::BRR>;
        ///Register BRR `reset()`'s with value 0
        impl crate::ResetValue for super::BRR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BRR`
        pub type BRR_R = crate::R<u16, u16>;
        ///Write proxy for field `BRR`
        pub struct BRR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BRR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - BRR_4_15
            #[inline(always)]
            pub fn brr(&self) -> BRR_R {
                BRR_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - BRR_4_15
            #[inline(always)]
            pub fn brr(&mut self) -> BRR_W {
                BRR_W { w: self }
            }
        }
    }
    ///Guard time and prescaler register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [gtpr](gtpr) module
    pub type GTPR = crate::Reg<u32, _GTPR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _GTPR;
    ///`read()` method returns [gtpr::R](gtpr::R) reader structure
    impl crate::Readable for GTPR {}
    ///`write(|w| ..)` method takes [gtpr::W](gtpr::W) writer structure
    impl crate::Writable for GTPR {}
    ///Guard time and prescaler register
    pub mod gtpr {
        ///Reader of register GTPR
        pub type R = crate::R<u32, super::GTPR>;
        ///Writer for register GTPR
        pub type W = crate::W<u32, super::GTPR>;
        ///Register GTPR `reset()`'s with value 0
        impl crate::ResetValue for super::GTPR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `GT`
        pub type GT_R = crate::R<u8, u8>;
        ///Write proxy for field `GT`
        pub struct GT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> GT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
                self.w
            }
        }
        ///Reader of field `PSC`
        pub type PSC_R = crate::R<u8, u8>;
        ///Write proxy for field `PSC`
        pub struct PSC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PSC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl R {
            ///Bits 8:15 - Guard time value
            #[inline(always)]
            pub fn gt(&self) -> GT_R {
                GT_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            ///Bits 0:7 - Prescaler value
            #[inline(always)]
            pub fn psc(&self) -> PSC_R {
                PSC_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            ///Bits 8:15 - Guard time value
            #[inline(always)]
            pub fn gt(&mut self) -> GT_W {
                GT_W { w: self }
            }
            ///Bits 0:7 - Prescaler value
            #[inline(always)]
            pub fn psc(&mut self) -> PSC_W {
                PSC_W { w: self }
            }
        }
    }
    ///Receiver timeout register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rtor](rtor) module
    pub type RTOR = crate::Reg<u32, _RTOR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RTOR;
    ///`read()` method returns [rtor::R](rtor::R) reader structure
    impl crate::Readable for RTOR {}
    ///`write(|w| ..)` method takes [rtor::W](rtor::W) writer structure
    impl crate::Writable for RTOR {}
    ///Receiver timeout register
    pub mod rtor {
        ///Reader of register RTOR
        pub type R = crate::R<u32, super::RTOR>;
        ///Writer for register RTOR
        pub type W = crate::W<u32, super::RTOR>;
        ///Register RTOR `reset()`'s with value 0
        impl crate::ResetValue for super::RTOR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BLEN`
        pub type BLEN_R = crate::R<u8, u8>;
        ///Write proxy for field `BLEN`
        pub struct BLEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BLEN_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
                self.w
            }
        }
        ///Reader of field `RTO`
        pub type RTO_R = crate::R<u32, u32>;
        ///Write proxy for field `RTO`
        pub struct RTO_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTO_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x00ff_ffff) | ((value as u32) & 0x00ff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 24:31 - Block Length
            #[inline(always)]
            pub fn blen(&self) -> BLEN_R {
                BLEN_R::new(((self.bits >> 24) & 0xff) as u8)
            }
            ///Bits 0:23 - Receiver timeout value
            #[inline(always)]
            pub fn rto(&self) -> RTO_R {
                RTO_R::new((self.bits & 0x00ff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 24:31 - Block Length
            #[inline(always)]
            pub fn blen(&mut self) -> BLEN_W {
                BLEN_W { w: self }
            }
            ///Bits 0:23 - Receiver timeout value
            #[inline(always)]
            pub fn rto(&mut self) -> RTO_W {
                RTO_W { w: self }
            }
        }
    }
    ///Request register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rqr](rqr) module
    pub type RQR = crate::Reg<u32, _RQR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RQR;
    ///`write(|w| ..)` method takes [rqr::W](rqr::W) writer structure
    impl crate::Writable for RQR {}
    ///Request register
    pub mod rqr {
        ///Writer for register RQR
        pub type W = crate::W<u32, super::RQR>;
        ///Register RQR `reset()`'s with value 0
        impl crate::ResetValue for super::RQR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `TXFRQ`
        pub struct TXFRQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXFRQ_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `RXFRQ`
        pub struct RXFRQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXFRQ_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `MMRQ`
        pub struct MMRQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MMRQ_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `SBKRQ`
        pub struct SBKRQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SBKRQ_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `ABRRQ`
        pub struct ABRRQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ABRRQ_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 4 - Transmit data flush request
            #[inline(always)]
            pub fn txfrq(&mut self) -> TXFRQ_W {
                TXFRQ_W { w: self }
            }
            ///Bit 3 - Receive data flush request
            #[inline(always)]
            pub fn rxfrq(&mut self) -> RXFRQ_W {
                RXFRQ_W { w: self }
            }
            ///Bit 2 - Mute mode request
            #[inline(always)]
            pub fn mmrq(&mut self) -> MMRQ_W {
                MMRQ_W { w: self }
            }
            ///Bit 1 - Send break request
            #[inline(always)]
            pub fn sbkrq(&mut self) -> SBKRQ_W {
                SBKRQ_W { w: self }
            }
            ///Bit 0 - Auto baud rate request
            #[inline(always)]
            pub fn abrrq(&mut self) -> ABRRQ_W {
                ABRRQ_W { w: self }
            }
        }
    }
    ///Interrupt & status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///Interrupt & status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Reader of field `TXFT`
        pub type TXFT_R = crate::R<bool, bool>;
        ///Reader of field `RXFT`
        pub type RXFT_R = crate::R<bool, bool>;
        ///Reader of field `TCBGT`
        pub type TCBGT_R = crate::R<bool, bool>;
        ///Reader of field `RXFF`
        pub type RXFF_R = crate::R<bool, bool>;
        ///Reader of field `TXFE`
        pub type TXFE_R = crate::R<bool, bool>;
        ///Reader of field `REACK`
        pub type REACK_R = crate::R<bool, bool>;
        ///Reader of field `TEACK`
        pub type TEACK_R = crate::R<bool, bool>;
        ///Reader of field `WUF`
        pub type WUF_R = crate::R<bool, bool>;
        ///Reader of field `RWU`
        pub type RWU_R = crate::R<bool, bool>;
        ///Reader of field `SBKF`
        pub type SBKF_R = crate::R<bool, bool>;
        ///Reader of field `CMF`
        pub type CMF_R = crate::R<bool, bool>;
        ///Reader of field `BUSY`
        pub type BUSY_R = crate::R<bool, bool>;
        ///Reader of field `ABRF`
        pub type ABRF_R = crate::R<bool, bool>;
        ///Reader of field `ABRE`
        pub type ABRE_R = crate::R<bool, bool>;
        ///Reader of field `UDR`
        pub type UDR_R = crate::R<bool, bool>;
        ///Reader of field `EOBF`
        pub type EOBF_R = crate::R<bool, bool>;
        ///Reader of field `RTOF`
        pub type RTOF_R = crate::R<bool, bool>;
        ///Reader of field `CTS`
        pub type CTS_R = crate::R<bool, bool>;
        ///Reader of field `CTSIF`
        pub type CTSIF_R = crate::R<bool, bool>;
        ///Reader of field `LBDF`
        pub type LBDF_R = crate::R<bool, bool>;
        ///Reader of field `TXE`
        pub type TXE_R = crate::R<bool, bool>;
        ///Reader of field `TC`
        pub type TC_R = crate::R<bool, bool>;
        ///Reader of field `RXNE`
        pub type RXNE_R = crate::R<bool, bool>;
        ///Reader of field `IDLE`
        pub type IDLE_R = crate::R<bool, bool>;
        ///Reader of field `ORE`
        pub type ORE_R = crate::R<bool, bool>;
        ///Reader of field `NF`
        pub type NF_R = crate::R<bool, bool>;
        ///Reader of field `FE`
        pub type FE_R = crate::R<bool, bool>;
        ///Reader of field `PE`
        pub type PE_R = crate::R<bool, bool>;
        impl R {
            ///Bit 27 - TXFIFO threshold flag
            #[inline(always)]
            pub fn txft(&self) -> TXFT_R {
                TXFT_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 26 - RXFIFO threshold flag
            #[inline(always)]
            pub fn rxft(&self) -> RXFT_R {
                RXFT_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 25 - Transmission complete before guard time flag
            #[inline(always)]
            pub fn tcbgt(&self) -> TCBGT_R {
                TCBGT_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 24 - RXFIFO Full
            #[inline(always)]
            pub fn rxff(&self) -> RXFF_R {
                RXFF_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 23 - TXFIFO Empty
            #[inline(always)]
            pub fn txfe(&self) -> TXFE_R {
                TXFE_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - REACK
            #[inline(always)]
            pub fn reack(&self) -> REACK_R {
                REACK_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 21 - TEACK
            #[inline(always)]
            pub fn teack(&self) -> TEACK_R {
                TEACK_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - WUF
            #[inline(always)]
            pub fn wuf(&self) -> WUF_R {
                WUF_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - RWU
            #[inline(always)]
            pub fn rwu(&self) -> RWU_R {
                RWU_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - SBKF
            #[inline(always)]
            pub fn sbkf(&self) -> SBKF_R {
                SBKF_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - CMF
            #[inline(always)]
            pub fn cmf(&self) -> CMF_R {
                CMF_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - BUSY
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 15 - ABRF
            #[inline(always)]
            pub fn abrf(&self) -> ABRF_R {
                ABRF_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - ABRE
            #[inline(always)]
            pub fn abre(&self) -> ABRE_R {
                ABRE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - SPI slave underrun error flag
            #[inline(always)]
            pub fn udr(&self) -> UDR_R {
                UDR_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - EOBF
            #[inline(always)]
            pub fn eobf(&self) -> EOBF_R {
                EOBF_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - RTOF
            #[inline(always)]
            pub fn rtof(&self) -> RTOF_R {
                RTOF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - CTS
            #[inline(always)]
            pub fn cts(&self) -> CTS_R {
                CTS_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - CTSIF
            #[inline(always)]
            pub fn ctsif(&self) -> CTSIF_R {
                CTSIF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - LBDF
            #[inline(always)]
            pub fn lbdf(&self) -> LBDF_R {
                LBDF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - TXE
            #[inline(always)]
            pub fn txe(&self) -> TXE_R {
                TXE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - TC
            #[inline(always)]
            pub fn tc(&self) -> TC_R {
                TC_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 5 - RXNE
            #[inline(always)]
            pub fn rxne(&self) -> RXNE_R {
                RXNE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - IDLE
            #[inline(always)]
            pub fn idle(&self) -> IDLE_R {
                IDLE_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - ORE
            #[inline(always)]
            pub fn ore(&self) -> ORE_R {
                ORE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - NF
            #[inline(always)]
            pub fn nf(&self) -> NF_R {
                NF_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - FE
            #[inline(always)]
            pub fn fe(&self) -> FE_R {
                FE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - PE
            #[inline(always)]
            pub fn pe(&self) -> PE_R {
                PE_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///Interrupt flag clear register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [icr](icr) module
    pub type ICR = crate::Reg<u32, _ICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ICR;
    ///`write(|w| ..)` method takes [icr::W](icr::W) writer structure
    impl crate::Writable for ICR {}
    ///Interrupt flag clear register
    pub mod icr {
        ///Writer for register ICR
        pub type W = crate::W<u32, super::ICR>;
        ///Register ICR `reset()`'s with value 0
        impl crate::ResetValue for super::ICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `WUCF`
        pub struct WUCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `CMCF`
        pub struct CMCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CMCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `UDRCF`
        pub struct UDRCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> UDRCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Write proxy for field `EOBCF`
        pub struct EOBCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EOBCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Write proxy for field `RTOCF`
        pub struct RTOCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTOCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Write proxy for field `CTSCF`
        pub struct CTSCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTSCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Write proxy for field `LBDCF`
        pub struct LBDCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LBDCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Write proxy for field `TCBGTCF`
        pub struct TCBGTCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCBGTCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Write proxy for field `TCCF`
        pub struct TCCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TCCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Write proxy for field `TXFECF`
        pub struct TXFECF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXFECF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `IDLECF`
        pub struct IDLECF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IDLECF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `ORECF`
        pub struct ORECF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ORECF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `NCF`
        pub struct NCF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NCF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `FECF`
        pub struct FECF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FECF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `PECF`
        pub struct PECF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PECF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 20 - Wakeup from Stop mode clear flag
            #[inline(always)]
            pub fn wucf(&mut self) -> WUCF_W {
                WUCF_W { w: self }
            }
            ///Bit 17 - Character match clear flag
            #[inline(always)]
            pub fn cmcf(&mut self) -> CMCF_W {
                CMCF_W { w: self }
            }
            ///Bit 13 - SPI slave underrun clear flag
            #[inline(always)]
            pub fn udrcf(&mut self) -> UDRCF_W {
                UDRCF_W { w: self }
            }
            ///Bit 12 - End of block clear flag
            #[inline(always)]
            pub fn eobcf(&mut self) -> EOBCF_W {
                EOBCF_W { w: self }
            }
            ///Bit 11 - Receiver timeout clear flag
            #[inline(always)]
            pub fn rtocf(&mut self) -> RTOCF_W {
                RTOCF_W { w: self }
            }
            ///Bit 9 - CTS clear flag
            #[inline(always)]
            pub fn ctscf(&mut self) -> CTSCF_W {
                CTSCF_W { w: self }
            }
            ///Bit 8 - LIN break detection clear flag
            #[inline(always)]
            pub fn lbdcf(&mut self) -> LBDCF_W {
                LBDCF_W { w: self }
            }
            ///Bit 7 - Transmission complete before Guard time clear flag
            #[inline(always)]
            pub fn tcbgtcf(&mut self) -> TCBGTCF_W {
                TCBGTCF_W { w: self }
            }
            ///Bit 6 - Transmission complete clear flag
            #[inline(always)]
            pub fn tccf(&mut self) -> TCCF_W {
                TCCF_W { w: self }
            }
            ///Bit 5 - TXFIFO empty clear flag
            #[inline(always)]
            pub fn txfecf(&mut self) -> TXFECF_W {
                TXFECF_W { w: self }
            }
            ///Bit 4 - Idle line detected clear flag
            #[inline(always)]
            pub fn idlecf(&mut self) -> IDLECF_W {
                IDLECF_W { w: self }
            }
            ///Bit 3 - Overrun error clear flag
            #[inline(always)]
            pub fn orecf(&mut self) -> ORECF_W {
                ORECF_W { w: self }
            }
            ///Bit 2 - Noise detected clear flag
            #[inline(always)]
            pub fn ncf(&mut self) -> NCF_W {
                NCF_W { w: self }
            }
            ///Bit 1 - Framing error clear flag
            #[inline(always)]
            pub fn fecf(&mut self) -> FECF_W {
                FECF_W { w: self }
            }
            ///Bit 0 - Parity error clear flag
            #[inline(always)]
            pub fn pecf(&mut self) -> PECF_W {
                PECF_W { w: self }
            }
        }
    }
    ///Receive data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rdr](rdr) module
    pub type RDR = crate::Reg<u32, _RDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RDR;
    ///`read()` method returns [rdr::R](rdr::R) reader structure
    impl crate::Readable for RDR {}
    ///Receive data register
    pub mod rdr {
        ///Reader of register RDR
        pub type R = crate::R<u32, super::RDR>;
        ///Reader of field `RDR`
        pub type RDR_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:8 - Receive data value
            #[inline(always)]
            pub fn rdr(&self) -> RDR_R {
                RDR_R::new((self.bits & 0x01ff) as u16)
            }
        }
    }
    ///Transmit data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tdr](tdr) module
    pub type TDR = crate::Reg<u32, _TDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TDR;
    ///`read()` method returns [tdr::R](tdr::R) reader structure
    impl crate::Readable for TDR {}
    ///`write(|w| ..)` method takes [tdr::W](tdr::W) writer structure
    impl crate::Writable for TDR {}
    ///Transmit data register
    pub mod tdr {
        ///Reader of register TDR
        pub type R = crate::R<u32, super::TDR>;
        ///Writer for register TDR
        pub type W = crate::W<u32, super::TDR>;
        ///Register TDR `reset()`'s with value 0
        impl crate::ResetValue for super::TDR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TDR`
        pub type TDR_R = crate::R<u16, u16>;
        ///Write proxy for field `TDR`
        pub struct TDR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TDR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:8 - Transmit data value
            #[inline(always)]
            pub fn tdr(&self) -> TDR_R {
                TDR_R::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            ///Bits 0:8 - Transmit data value
            #[inline(always)]
            pub fn tdr(&mut self) -> TDR_W {
                TDR_W { w: self }
            }
        }
    }
    ///Prescaler register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [presc](presc) module
    pub type PRESC = crate::Reg<u32, _PRESC>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PRESC;
    ///`read()` method returns [presc::R](presc::R) reader structure
    impl crate::Readable for PRESC {}
    ///`write(|w| ..)` method takes [presc::W](presc::W) writer structure
    impl crate::Writable for PRESC {}
    ///Prescaler register
    pub mod presc {
        ///Reader of register PRESC
        pub type R = crate::R<u32, super::PRESC>;
        ///Writer for register PRESC
        pub type W = crate::W<u32, super::PRESC>;
        ///Register PRESC `reset()`'s with value 0
        impl crate::ResetValue for super::PRESC {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PRESCALER`
        pub type PRESCALER_R = crate::R<u8, u8>;
        ///Write proxy for field `PRESCALER`
        pub struct PRESCALER_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PRESCALER_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Clock prescaler
            #[inline(always)]
            pub fn prescaler(&self) -> PRESCALER_R {
                PRESCALER_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 0:3 - Clock prescaler
            #[inline(always)]
            pub fn prescaler(&mut self) -> PRESCALER_W {
                PRESCALER_W { w: self }
            }
        }
    }
}
///Universal synchronous asynchronous receiver transmitter
pub struct LPUART1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LPUART1 {}
impl LPUART1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const usart1::RegisterBlock {
        0x4000_8000 as *const _
    }
}
impl Deref for LPUART1 {
    type Target = usart1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*LPUART1::ptr() }
    }
}
///Serial peripheral interface/Inter-IC sound
pub struct SPI1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI1 {}
impl SPI1 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const spi1::RegisterBlock {
        0x4001_3000 as *const _
    }
}
impl Deref for SPI1 {
    type Target = spi1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*SPI1::ptr() }
    }
}
///Serial peripheral interface/Inter-IC sound
pub mod spi1 {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - control register 1
        pub cr1: CR1,
        ///0x04 - control register 2
        pub cr2: CR2,
        ///0x08 - status register
        pub sr: SR,
        ///0x0c - data register
        pub dr: DR,
        ///0x10 - CRC polynomial register
        pub crcpr: CRCPR,
        ///0x14 - RX CRC register
        pub rxcrcr: RXCRCR,
        ///0x18 - TX CRC register
        pub txcrcr: TXCRCR,
    }
    ///control register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr1](cr1) module
    pub type CR1 = crate::Reg<u32, _CR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR1;
    ///`read()` method returns [cr1::R](cr1::R) reader structure
    impl crate::Readable for CR1 {}
    ///`write(|w| ..)` method takes [cr1::W](cr1::W) writer structure
    impl crate::Writable for CR1 {}
    ///control register 1
    pub mod cr1 {
        ///Reader of register CR1
        pub type R = crate::R<u32, super::CR1>;
        ///Writer for register CR1
        pub type W = crate::W<u32, super::CR1>;
        ///Register CR1 `reset()`'s with value 0
        impl crate::ResetValue for super::CR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BIDIMODE`
        pub type BIDIMODE_R = crate::R<bool, bool>;
        ///Write proxy for field `BIDIMODE`
        pub struct BIDIMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIDIMODE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `BIDIOE`
        pub type BIDIOE_R = crate::R<bool, bool>;
        ///Write proxy for field `BIDIOE`
        pub struct BIDIOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BIDIOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CRCEN`
        pub type CRCEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCEN`
        pub struct CRCEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `CRCNEXT`
        pub type CRCNEXT_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCNEXT`
        pub struct CRCNEXT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCNEXT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DFF`
        pub type DFF_R = crate::R<bool, bool>;
        ///Write proxy for field `DFF`
        pub struct DFF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DFF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `RXONLY`
        pub type RXONLY_R = crate::R<bool, bool>;
        ///Write proxy for field `RXONLY`
        pub struct RXONLY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXONLY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `SSM`
        pub type SSM_R = crate::R<bool, bool>;
        ///Write proxy for field `SSM`
        pub struct SSM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SSM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `SSI`
        pub type SSI_R = crate::R<bool, bool>;
        ///Write proxy for field `SSI`
        pub struct SSI_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SSI_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `LSBFIRST`
        pub type LSBFIRST_R = crate::R<bool, bool>;
        ///Write proxy for field `LSBFIRST`
        pub struct LSBFIRST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LSBFIRST_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `SPE`
        pub type SPE_R = crate::R<bool, bool>;
        ///Write proxy for field `SPE`
        pub struct SPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SPE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `BR`
        pub type BR_R = crate::R<u8, u8>;
        ///Write proxy for field `BR`
        pub struct BR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 3)) | (((value as u32) & 0x07) << 3);
                self.w
            }
        }
        ///Reader of field `MSTR`
        pub type MSTR_R = crate::R<bool, bool>;
        ///Write proxy for field `MSTR`
        pub struct MSTR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSTR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CPOL`
        pub type CPOL_R = crate::R<bool, bool>;
        ///Write proxy for field `CPOL`
        pub struct CPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CPOL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CPHA`
        pub type CPHA_R = crate::R<bool, bool>;
        ///Write proxy for field `CPHA`
        pub struct CPHA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CPHA_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Bidirectional data mode enable
            #[inline(always)]
            pub fn bidimode(&self) -> BIDIMODE_R {
                BIDIMODE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Output enable in bidirectional mode
            #[inline(always)]
            pub fn bidioe(&self) -> BIDIOE_R {
                BIDIOE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Hardware CRC calculation enable
            #[inline(always)]
            pub fn crcen(&self) -> CRCEN_R {
                CRCEN_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 12 - CRC transfer next
            #[inline(always)]
            pub fn crcnext(&self) -> CRCNEXT_R {
                CRCNEXT_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 11 - Data frame format
            #[inline(always)]
            pub fn dff(&self) -> DFF_R {
                DFF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 10 - Receive only
            #[inline(always)]
            pub fn rxonly(&self) -> RXONLY_R {
                RXONLY_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 9 - Software slave management
            #[inline(always)]
            pub fn ssm(&self) -> SSM_R {
                SSM_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 8 - Internal slave select
            #[inline(always)]
            pub fn ssi(&self) -> SSI_R {
                SSI_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 7 - Frame format
            #[inline(always)]
            pub fn lsbfirst(&self) -> LSBFIRST_R {
                LSBFIRST_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 6 - SPI enable
            #[inline(always)]
            pub fn spe(&self) -> SPE_R {
                SPE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bits 3:5 - Baud rate control
            #[inline(always)]
            pub fn br(&self) -> BR_R {
                BR_R::new(((self.bits >> 3) & 0x07) as u8)
            }
            ///Bit 2 - Master selection
            #[inline(always)]
            pub fn mstr(&self) -> MSTR_R {
                MSTR_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Clock polarity
            #[inline(always)]
            pub fn cpol(&self) -> CPOL_R {
                CPOL_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Clock phase
            #[inline(always)]
            pub fn cpha(&self) -> CPHA_R {
                CPHA_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 15 - Bidirectional data mode enable
            #[inline(always)]
            pub fn bidimode(&mut self) -> BIDIMODE_W {
                BIDIMODE_W { w: self }
            }
            ///Bit 14 - Output enable in bidirectional mode
            #[inline(always)]
            pub fn bidioe(&mut self) -> BIDIOE_W {
                BIDIOE_W { w: self }
            }
            ///Bit 13 - Hardware CRC calculation enable
            #[inline(always)]
            pub fn crcen(&mut self) -> CRCEN_W {
                CRCEN_W { w: self }
            }
            ///Bit 12 - CRC transfer next
            #[inline(always)]
            pub fn crcnext(&mut self) -> CRCNEXT_W {
                CRCNEXT_W { w: self }
            }
            ///Bit 11 - Data frame format
            #[inline(always)]
            pub fn dff(&mut self) -> DFF_W {
                DFF_W { w: self }
            }
            ///Bit 10 - Receive only
            #[inline(always)]
            pub fn rxonly(&mut self) -> RXONLY_W {
                RXONLY_W { w: self }
            }
            ///Bit 9 - Software slave management
            #[inline(always)]
            pub fn ssm(&mut self) -> SSM_W {
                SSM_W { w: self }
            }
            ///Bit 8 - Internal slave select
            #[inline(always)]
            pub fn ssi(&mut self) -> SSI_W {
                SSI_W { w: self }
            }
            ///Bit 7 - Frame format
            #[inline(always)]
            pub fn lsbfirst(&mut self) -> LSBFIRST_W {
                LSBFIRST_W { w: self }
            }
            ///Bit 6 - SPI enable
            #[inline(always)]
            pub fn spe(&mut self) -> SPE_W {
                SPE_W { w: self }
            }
            ///Bits 3:5 - Baud rate control
            #[inline(always)]
            pub fn br(&mut self) -> BR_W {
                BR_W { w: self }
            }
            ///Bit 2 - Master selection
            #[inline(always)]
            pub fn mstr(&mut self) -> MSTR_W {
                MSTR_W { w: self }
            }
            ///Bit 1 - Clock polarity
            #[inline(always)]
            pub fn cpol(&mut self) -> CPOL_W {
                CPOL_W { w: self }
            }
            ///Bit 0 - Clock phase
            #[inline(always)]
            pub fn cpha(&mut self) -> CPHA_W {
                CPHA_W { w: self }
            }
        }
    }
    ///control register 2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr2](cr2) module
    pub type CR2 = crate::Reg<u32, _CR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR2;
    ///`read()` method returns [cr2::R](cr2::R) reader structure
    impl crate::Readable for CR2 {}
    ///`write(|w| ..)` method takes [cr2::W](cr2::W) writer structure
    impl crate::Writable for CR2 {}
    ///control register 2
    pub mod cr2 {
        ///Reader of register CR2
        pub type R = crate::R<u32, super::CR2>;
        ///Writer for register CR2
        pub type W = crate::W<u32, super::CR2>;
        ///Register CR2 `reset()`'s with value 0x0700
        impl crate::ResetValue for super::CR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0700
            }
        }
        ///Reader of field `RXDMAEN`
        pub type RXDMAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `RXDMAEN`
        pub struct RXDMAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXDMAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `TXDMAEN`
        pub type TXDMAEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TXDMAEN`
        pub struct TXDMAEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXDMAEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `SSOE`
        pub type SSOE_R = crate::R<bool, bool>;
        ///Write proxy for field `SSOE`
        pub struct SSOE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SSOE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `NSSP`
        pub type NSSP_R = crate::R<bool, bool>;
        ///Write proxy for field `NSSP`
        pub struct NSSP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NSSP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `FRF`
        pub type FRF_R = crate::R<bool, bool>;
        ///Write proxy for field `FRF`
        pub struct FRF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FRF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `ERRIE`
        pub type ERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRIE`
        pub struct ERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `RXNEIE`
        pub type RXNEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RXNEIE`
        pub struct RXNEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXNEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `TXEIE`
        pub type TXEIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXEIE`
        pub struct TXEIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXEIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `DS`
        pub type DS_R = crate::R<u8, u8>;
        ///Write proxy for field `DS`
        pub struct DS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `FRXTH`
        pub type FRXTH_R = crate::R<bool, bool>;
        ///Write proxy for field `FRXTH`
        pub struct FRXTH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FRXTH_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `LDMA_RX`
        pub type LDMA_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `LDMA_RX`
        pub struct LDMA_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LDMA_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `LDMA_TX`
        pub type LDMA_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `LDMA_TX`
        pub struct LDMA_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LDMA_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Rx buffer DMA enable
            #[inline(always)]
            pub fn rxdmaen(&self) -> RXDMAEN_R {
                RXDMAEN_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Tx buffer DMA enable
            #[inline(always)]
            pub fn txdmaen(&self) -> TXDMAEN_R {
                TXDMAEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - SS output enable
            #[inline(always)]
            pub fn ssoe(&self) -> SSOE_R {
                SSOE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - NSS pulse management
            #[inline(always)]
            pub fn nssp(&self) -> NSSP_R {
                NSSP_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Frame format
            #[inline(always)]
            pub fn frf(&self) -> FRF_R {
                FRF_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&self) -> ERRIE_R {
                ERRIE_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - RX buffer not empty interrupt enable
            #[inline(always)]
            pub fn rxneie(&self) -> RXNEIE_R {
                RXNEIE_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Tx buffer empty interrupt enable
            #[inline(always)]
            pub fn txeie(&self) -> TXEIE_R {
                TXEIE_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:11 - Data size
            #[inline(always)]
            pub fn ds(&self) -> DS_R {
                DS_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bit 12 - FIFO reception threshold
            #[inline(always)]
            pub fn frxth(&self) -> FRXTH_R {
                FRXTH_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Last DMA transfer for reception
            #[inline(always)]
            pub fn ldma_rx(&self) -> LDMA_RX_R {
                LDMA_RX_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Last DMA transfer for transmission
            #[inline(always)]
            pub fn ldma_tx(&self) -> LDMA_TX_R {
                LDMA_TX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Rx buffer DMA enable
            #[inline(always)]
            pub fn rxdmaen(&mut self) -> RXDMAEN_W {
                RXDMAEN_W { w: self }
            }
            ///Bit 1 - Tx buffer DMA enable
            #[inline(always)]
            pub fn txdmaen(&mut self) -> TXDMAEN_W {
                TXDMAEN_W { w: self }
            }
            ///Bit 2 - SS output enable
            #[inline(always)]
            pub fn ssoe(&mut self) -> SSOE_W {
                SSOE_W { w: self }
            }
            ///Bit 3 - NSS pulse management
            #[inline(always)]
            pub fn nssp(&mut self) -> NSSP_W {
                NSSP_W { w: self }
            }
            ///Bit 4 - Frame format
            #[inline(always)]
            pub fn frf(&mut self) -> FRF_W {
                FRF_W { w: self }
            }
            ///Bit 5 - Error interrupt enable
            #[inline(always)]
            pub fn errie(&mut self) -> ERRIE_W {
                ERRIE_W { w: self }
            }
            ///Bit 6 - RX buffer not empty interrupt enable
            #[inline(always)]
            pub fn rxneie(&mut self) -> RXNEIE_W {
                RXNEIE_W { w: self }
            }
            ///Bit 7 - Tx buffer empty interrupt enable
            #[inline(always)]
            pub fn txeie(&mut self) -> TXEIE_W {
                TXEIE_W { w: self }
            }
            ///Bits 8:11 - Data size
            #[inline(always)]
            pub fn ds(&mut self) -> DS_W {
                DS_W { w: self }
            }
            ///Bit 12 - FIFO reception threshold
            #[inline(always)]
            pub fn frxth(&mut self) -> FRXTH_W {
                FRXTH_W { w: self }
            }
            ///Bit 13 - Last DMA transfer for reception
            #[inline(always)]
            pub fn ldma_rx(&mut self) -> LDMA_RX_W {
                LDMA_RX_W { w: self }
            }
            ///Bit 14 - Last DMA transfer for transmission
            #[inline(always)]
            pub fn ldma_tx(&mut self) -> LDMA_TX_W {
                LDMA_TX_W { w: self }
            }
        }
    }
    ///status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///`write(|w| ..)` method takes [sr::W](sr::W) writer structure
    impl crate::Writable for SR {}
    ///status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Writer for register SR
        pub type W = crate::W<u32, super::SR>;
        ///Register SR `reset()`'s with value 0x02
        impl crate::ResetValue for super::SR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x02
            }
        }
        ///Reader of field `RXNE`
        pub type RXNE_R = crate::R<bool, bool>;
        ///Reader of field `TXE`
        pub type TXE_R = crate::R<bool, bool>;
        ///Reader of field `CRCERR`
        pub type CRCERR_R = crate::R<bool, bool>;
        ///Write proxy for field `CRCERR`
        pub struct CRCERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `MODF`
        pub type MODF_R = crate::R<bool, bool>;
        ///Reader of field `OVR`
        pub type OVR_R = crate::R<bool, bool>;
        ///Reader of field `BSY`
        pub type BSY_R = crate::R<bool, bool>;
        ///Reader of field `TIFRFE`
        pub type TIFRFE_R = crate::R<bool, bool>;
        ///Reader of field `FRLVL`
        pub type FRLVL_R = crate::R<u8, u8>;
        ///Reader of field `FTLVL`
        pub type FTLVL_R = crate::R<u8, u8>;
        impl R {
            ///Bit 0 - Receive buffer not empty
            #[inline(always)]
            pub fn rxne(&self) -> RXNE_R {
                RXNE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Transmit buffer empty
            #[inline(always)]
            pub fn txe(&self) -> TXE_R {
                TXE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 4 - CRC error flag
            #[inline(always)]
            pub fn crcerr(&self) -> CRCERR_R {
                CRCERR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Mode fault
            #[inline(always)]
            pub fn modf(&self) -> MODF_R {
                MODF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Overrun flag
            #[inline(always)]
            pub fn ovr(&self) -> OVR_R {
                OVR_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Busy flag
            #[inline(always)]
            pub fn bsy(&self) -> BSY_R {
                BSY_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - TI frame format error
            #[inline(always)]
            pub fn tifrfe(&self) -> TIFRFE_R {
                TIFRFE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - FIFO reception level
            #[inline(always)]
            pub fn frlvl(&self) -> FRLVL_R {
                FRLVL_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bits 11:12 - FIFO transmission level
            #[inline(always)]
            pub fn ftlvl(&self) -> FTLVL_R {
                FTLVL_R::new(((self.bits >> 11) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 4 - CRC error flag
            #[inline(always)]
            pub fn crcerr(&mut self) -> CRCERR_W {
                CRCERR_W { w: self }
            }
        }
    }
    ///data register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dr](dr) module
    pub type DR = crate::Reg<u32, _DR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DR;
    ///`read()` method returns [dr::R](dr::R) reader structure
    impl crate::Readable for DR {}
    ///`write(|w| ..)` method takes [dr::W](dr::W) writer structure
    impl crate::Writable for DR {}
    ///data register
    pub mod dr {
        ///Reader of register DR
        pub type R = crate::R<u32, super::DR>;
        ///Writer for register DR
        pub type W = crate::W<u32, super::DR>;
        ///Register DR `reset()`'s with value 0
        impl crate::ResetValue for super::DR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DR`
        pub type DR_R = crate::R<u16, u16>;
        ///Write proxy for field `DR`
        pub struct DR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DR_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Data register
            #[inline(always)]
            pub fn dr(&self) -> DR_R {
                DR_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Data register
            #[inline(always)]
            pub fn dr(&mut self) -> DR_W {
                DR_W { w: self }
            }
        }
    }
    ///CRC polynomial register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [crcpr](crcpr) module
    pub type CRCPR = crate::Reg<u32, _CRCPR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CRCPR;
    ///`read()` method returns [crcpr::R](crcpr::R) reader structure
    impl crate::Readable for CRCPR {}
    ///`write(|w| ..)` method takes [crcpr::W](crcpr::W) writer structure
    impl crate::Writable for CRCPR {}
    ///CRC polynomial register
    pub mod crcpr {
        ///Reader of register CRCPR
        pub type R = crate::R<u32, super::CRCPR>;
        ///Writer for register CRCPR
        pub type W = crate::W<u32, super::CRCPR>;
        ///Register CRCPR `reset()`'s with value 0x07
        impl crate::ResetValue for super::CRCPR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x07
            }
        }
        ///Reader of field `CRCPOLY`
        pub type CRCPOLY_R = crate::R<u16, u16>;
        ///Write proxy for field `CRCPOLY`
        pub struct CRCPOLY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CRCPOLY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - CRC polynomial register
            #[inline(always)]
            pub fn crcpoly(&self) -> CRCPOLY_R {
                CRCPOLY_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - CRC polynomial register
            #[inline(always)]
            pub fn crcpoly(&mut self) -> CRCPOLY_W {
                CRCPOLY_W { w: self }
            }
        }
    }
    ///RX CRC register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rxcrcr](rxcrcr) module
    pub type RXCRCR = crate::Reg<u32, _RXCRCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RXCRCR;
    ///`read()` method returns [rxcrcr::R](rxcrcr::R) reader structure
    impl crate::Readable for RXCRCR {}
    ///RX CRC register
    pub mod rxcrcr {
        ///Reader of register RXCRCR
        pub type R = crate::R<u32, super::RXCRCR>;
        ///Reader of field `RxCRC`
        pub type RXCRC_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - Rx CRC register
            #[inline(always)]
            pub fn rx_crc(&self) -> RXCRC_R {
                RXCRC_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///TX CRC register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [txcrcr](txcrcr) module
    pub type TXCRCR = crate::Reg<u32, _TXCRCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TXCRCR;
    ///`read()` method returns [txcrcr::R](txcrcr::R) reader structure
    impl crate::Readable for TXCRCR {}
    ///TX CRC register
    pub mod txcrcr {
        ///Reader of register TXCRCR
        pub type R = crate::R<u32, super::TXCRCR>;
        ///Reader of field `TxCRC`
        pub type TXCRC_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - Tx CRC register
            #[inline(always)]
            pub fn tx_crc(&self) -> TXCRC_R {
                TXCRC_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
}
///Serial peripheral interface/Inter-IC sound
pub struct SPI2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI2 {}
impl SPI2 {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const spi1::RegisterBlock {
        0x4000_3800 as *const _
    }
}
impl Deref for SPI2 {
    type Target = spi1::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*SPI2::ptr() }
    }
}
///Voltage reference buffer
pub struct VREFBUF {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for VREFBUF {}
impl VREFBUF {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const vrefbuf::RegisterBlock {
        0x4001_0030 as *const _
    }
}
impl Deref for VREFBUF {
    type Target = vrefbuf::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*VREFBUF::ptr() }
    }
}
///Voltage reference buffer
pub mod vrefbuf {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - VREF control and status register
        pub csr: CSR,
        ///0x04 - calibration control register
        pub ccr: CCR,
    }
    ///VREF control and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [csr](csr) module
    pub type CSR = crate::Reg<u32, _CSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CSR;
    ///`read()` method returns [csr::R](csr::R) reader structure
    impl crate::Readable for CSR {}
    ///`write(|w| ..)` method takes [csr::W](csr::W) writer structure
    impl crate::Writable for CSR {}
    ///VREF control and status register
    pub mod csr {
        ///Reader of register CSR
        pub type R = crate::R<u32, super::CSR>;
        ///Writer for register CSR
        pub type W = crate::W<u32, super::CSR>;
        ///Register CSR `reset()`'s with value 0x02
        impl crate::ResetValue for super::CSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x02
            }
        }
        ///Reader of field `ENVR`
        pub type ENVR_R = crate::R<bool, bool>;
        ///Write proxy for field `ENVR`
        pub struct ENVR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ENVR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `HIZ`
        pub type HIZ_R = crate::R<bool, bool>;
        ///Write proxy for field `HIZ`
        pub struct HIZ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HIZ_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `VRS`
        pub type VRS_R = crate::R<bool, bool>;
        ///Write proxy for field `VRS`
        pub struct VRS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> VRS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `VRR`
        pub type VRR_R = crate::R<bool, bool>;
        impl R {
            ///Bit 0 - Voltage reference buffer enable
            #[inline(always)]
            pub fn envr(&self) -> ENVR_R {
                ENVR_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - High impedance mode
            #[inline(always)]
            pub fn hiz(&self) -> HIZ_R {
                HIZ_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Voltage reference scale
            #[inline(always)]
            pub fn vrs(&self) -> VRS_R {
                VRS_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Voltage reference buffer ready
            #[inline(always)]
            pub fn vrr(&self) -> VRR_R {
                VRR_R::new(((self.bits >> 3) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Voltage reference buffer enable
            #[inline(always)]
            pub fn envr(&mut self) -> ENVR_W {
                ENVR_W { w: self }
            }
            ///Bit 1 - High impedance mode
            #[inline(always)]
            pub fn hiz(&mut self) -> HIZ_W {
                HIZ_W { w: self }
            }
            ///Bit 2 - Voltage reference scale
            #[inline(always)]
            pub fn vrs(&mut self) -> VRS_W {
                VRS_W { w: self }
            }
        }
    }
    ///calibration control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ccr](ccr) module
    pub type CCR = crate::Reg<u32, _CCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CCR;
    ///`read()` method returns [ccr::R](ccr::R) reader structure
    impl crate::Readable for CCR {}
    ///`write(|w| ..)` method takes [ccr::W](ccr::W) writer structure
    impl crate::Writable for CCR {}
    ///calibration control register
    pub mod ccr {
        ///Reader of register CCR
        pub type R = crate::R<u32, super::CCR>;
        ///Writer for register CCR
        pub type W = crate::W<u32, super::CCR>;
        ///Register CCR `reset()`'s with value 0
        impl crate::ResetValue for super::CCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TRIM`
        pub type TRIM_R = crate::R<u8, u8>;
        ///Write proxy for field `TRIM`
        pub struct TRIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TRIM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f);
                self.w
            }
        }
        impl R {
            ///Bits 0:5 - Trimming code
            #[inline(always)]
            pub fn trim(&self) -> TRIM_R {
                TRIM_R::new((self.bits & 0x3f) as u8)
            }
        }
        impl W {
            ///Bits 0:5 - Trimming code
            #[inline(always)]
            pub fn trim(&mut self) -> TRIM_W {
                TRIM_W { w: self }
            }
        }
    }
}
///Real-time clock
pub struct RTC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for RTC {}
impl RTC {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const rtc::RegisterBlock {
        0x4000_2800 as *const _
    }
}
impl Deref for RTC {
    type Target = rtc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*RTC::ptr() }
    }
}
///Real-time clock
pub mod rtc {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - time register
        pub tr: TR,
        ///0x04 - date register
        pub dr: DR,
        ///0x08 - control register
        pub cr: CR,
        ///0x0c - initialization and status register
        pub isr: ISR,
        ///0x10 - prescaler register
        pub prer: PRER,
        ///0x14 - wakeup timer register
        pub wutr: WUTR,
        _reserved6: [u8; 4usize],
        ///0x1c - alarm A register
        pub alrmar: ALRMAR,
        ///0x20 - alarm B register
        pub alrmbr: ALRMBR,
        ///0x24 - write protection register
        pub wpr: WPR,
        ///0x28 - sub second register
        pub ssr: SSR,
        ///0x2c - shift control register
        pub shiftr: SHIFTR,
        ///0x30 - time stamp time register
        pub tstr: TSTR,
        ///0x34 - time stamp date register
        pub tsdr: TSDR,
        ///0x38 - timestamp sub second register
        pub tsssr: TSSSR,
        ///0x3c - calibration register
        pub calr: CALR,
        ///0x40 - tamper configuration register
        pub tampcr: TAMPCR,
        ///0x44 - alarm A sub second register
        pub alrmassr: ALRMASSR,
        ///0x48 - alarm B sub second register
        pub alrmbssr: ALRMBSSR,
        ///0x4c - option register
        pub or: OR,
        ///0x50 - backup register
        pub bkp0r: BKP0R,
        ///0x54 - backup register
        pub bkp1r: BKP1R,
        ///0x58 - backup register
        pub bkp2r: BKP2R,
        ///0x5c - backup register
        pub bkp3r: BKP3R,
        ///0x60 - backup register
        pub bkp4r: BKP4R,
        ///0x64 - backup register
        pub bkp5r: BKP5R,
        ///0x68 - backup register
        pub bkp6r: BKP6R,
        ///0x6c - backup register
        pub bkp7r: BKP7R,
        ///0x70 - backup register
        pub bkp8r: BKP8R,
        ///0x74 - backup register
        pub bkp9r: BKP9R,
        ///0x78 - backup register
        pub bkp10r: BKP10R,
        ///0x7c - backup register
        pub bkp11r: BKP11R,
        ///0x80 - backup register
        pub bkp12r: BKP12R,
        ///0x84 - backup register
        pub bkp13r: BKP13R,
        ///0x88 - backup register
        pub bkp14r: BKP14R,
        ///0x8c - backup register
        pub bkp15r: BKP15R,
        ///0x90 - backup register
        pub bkp16r: BKP16R,
        ///0x94 - backup register
        pub bkp17r: BKP17R,
        ///0x98 - backup register
        pub bkp18r: BKP18R,
        ///0x9c - backup register
        pub bkp19r: BKP19R,
    }
    ///time register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tr](tr) module
    pub type TR = crate::Reg<u32, _TR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TR;
    ///`read()` method returns [tr::R](tr::R) reader structure
    impl crate::Readable for TR {}
    ///`write(|w| ..)` method takes [tr::W](tr::W) writer structure
    impl crate::Writable for TR {}
    ///time register
    pub mod tr {
        ///Reader of register TR
        pub type R = crate::R<u32, super::TR>;
        ///Writer for register TR
        pub type W = crate::W<u32, super::TR>;
        ///Register TR `reset()`'s with value 0
        impl crate::ResetValue for super::TR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PM`
        pub type PM_R = crate::R<bool, bool>;
        ///Write proxy for field `PM`
        pub struct PM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `HT`
        pub type HT_R = crate::R<u8, u8>;
        ///Write proxy for field `HT`
        pub struct HT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `HU`
        pub type HU_R = crate::R<u8, u8>;
        ///Write proxy for field `HU`
        pub struct HU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `MNT`
        pub type MNT_R = crate::R<u8, u8>;
        ///Write proxy for field `MNT`
        pub struct MNT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MNT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `MNU`
        pub type MNU_R = crate::R<u8, u8>;
        ///Write proxy for field `MNU`
        pub struct MNU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MNU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `ST`
        pub type ST_R = crate::R<u8, u8>;
        ///Write proxy for field `ST`
        pub struct ST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ST_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `SU`
        pub type SU_R = crate::R<u8, u8>;
        ///Write proxy for field `SU`
        pub struct SU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bit 22 - AM/PM notation
            #[inline(always)]
            pub fn pm(&self) -> PM_R {
                PM_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bits 20:21 - Hour tens in BCD format
            #[inline(always)]
            pub fn ht(&self) -> HT_R {
                HT_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 16:19 - Hour units in BCD format
            #[inline(always)]
            pub fn hu(&self) -> HU_R {
                HU_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 12:14 - Minute tens in BCD format
            #[inline(always)]
            pub fn mnt(&self) -> MNT_R {
                MNT_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:11 - Minute units in BCD format
            #[inline(always)]
            pub fn mnu(&self) -> MNU_R {
                MNU_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:6 - Second tens in BCD format
            #[inline(always)]
            pub fn st(&self) -> ST_R {
                ST_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:3 - Second units in BCD format
            #[inline(always)]
            pub fn su(&self) -> SU_R {
                SU_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bit 22 - AM/PM notation
            #[inline(always)]
            pub fn pm(&mut self) -> PM_W {
                PM_W { w: self }
            }
            ///Bits 20:21 - Hour tens in BCD format
            #[inline(always)]
            pub fn ht(&mut self) -> HT_W {
                HT_W { w: self }
            }
            ///Bits 16:19 - Hour units in BCD format
            #[inline(always)]
            pub fn hu(&mut self) -> HU_W {
                HU_W { w: self }
            }
            ///Bits 12:14 - Minute tens in BCD format
            #[inline(always)]
            pub fn mnt(&mut self) -> MNT_W {
                MNT_W { w: self }
            }
            ///Bits 8:11 - Minute units in BCD format
            #[inline(always)]
            pub fn mnu(&mut self) -> MNU_W {
                MNU_W { w: self }
            }
            ///Bits 4:6 - Second tens in BCD format
            #[inline(always)]
            pub fn st(&mut self) -> ST_W {
                ST_W { w: self }
            }
            ///Bits 0:3 - Second units in BCD format
            #[inline(always)]
            pub fn su(&mut self) -> SU_W {
                SU_W { w: self }
            }
        }
    }
    ///date register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [dr](dr) module
    pub type DR = crate::Reg<u32, _DR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DR;
    ///`read()` method returns [dr::R](dr::R) reader structure
    impl crate::Readable for DR {}
    ///`write(|w| ..)` method takes [dr::W](dr::W) writer structure
    impl crate::Writable for DR {}
    ///date register
    pub mod dr {
        ///Reader of register DR
        pub type R = crate::R<u32, super::DR>;
        ///Writer for register DR
        pub type W = crate::W<u32, super::DR>;
        ///Register DR `reset()`'s with value 0x2101
        impl crate::ResetValue for super::DR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x2101
            }
        }
        ///Reader of field `YT`
        pub type YT_R = crate::R<u8, u8>;
        ///Write proxy for field `YT`
        pub struct YT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> YT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        ///Reader of field `YU`
        pub type YU_R = crate::R<u8, u8>;
        ///Write proxy for field `YU`
        pub struct YU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> YU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `WDU`
        pub type WDU_R = crate::R<u8, u8>;
        ///Write proxy for field `WDU`
        pub struct WDU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WDU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 13)) | (((value as u32) & 0x07) << 13);
                self.w
            }
        }
        ///Reader of field `MT`
        pub type MT_R = crate::R<bool, bool>;
        ///Write proxy for field `MT`
        pub struct MT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `MU`
        pub type MU_R = crate::R<u8, u8>;
        ///Write proxy for field `MU`
        pub struct MU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `DT`
        pub type DT_R = crate::R<u8, u8>;
        ///Write proxy for field `DT`
        pub struct DT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DU`
        pub type DU_R = crate::R<u8, u8>;
        ///Write proxy for field `DU`
        pub struct DU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bits 20:23 - Year tens in BCD format
            #[inline(always)]
            pub fn yt(&self) -> YT_R {
                YT_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            ///Bits 16:19 - Year units in BCD format
            #[inline(always)]
            pub fn yu(&self) -> YU_R {
                YU_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 13:15 - Week day units
            #[inline(always)]
            pub fn wdu(&self) -> WDU_R {
                WDU_R::new(((self.bits >> 13) & 0x07) as u8)
            }
            ///Bit 12 - Month tens in BCD format
            #[inline(always)]
            pub fn mt(&self) -> MT_R {
                MT_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bits 8:11 - Month units in BCD format
            #[inline(always)]
            pub fn mu(&self) -> MU_R {
                MU_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:5 - Date tens in BCD format
            #[inline(always)]
            pub fn dt(&self) -> DT_R {
                DT_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 0:3 - Date units in BCD format
            #[inline(always)]
            pub fn du(&self) -> DU_R {
                DU_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 20:23 - Year tens in BCD format
            #[inline(always)]
            pub fn yt(&mut self) -> YT_W {
                YT_W { w: self }
            }
            ///Bits 16:19 - Year units in BCD format
            #[inline(always)]
            pub fn yu(&mut self) -> YU_W {
                YU_W { w: self }
            }
            ///Bits 13:15 - Week day units
            #[inline(always)]
            pub fn wdu(&mut self) -> WDU_W {
                WDU_W { w: self }
            }
            ///Bit 12 - Month tens in BCD format
            #[inline(always)]
            pub fn mt(&mut self) -> MT_W {
                MT_W { w: self }
            }
            ///Bits 8:11 - Month units in BCD format
            #[inline(always)]
            pub fn mu(&mut self) -> MU_W {
                MU_W { w: self }
            }
            ///Bits 4:5 - Date tens in BCD format
            #[inline(always)]
            pub fn dt(&mut self) -> DT_W {
                DT_W { w: self }
            }
            ///Bits 0:3 - Date units in BCD format
            #[inline(always)]
            pub fn du(&mut self) -> DU_W {
                DU_W { w: self }
            }
        }
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `WUCKSEL`
        pub type WUCKSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `WUCKSEL`
        pub struct WUCKSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUCKSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
                self.w
            }
        }
        ///Reader of field `TSEDGE`
        pub type TSEDGE_R = crate::R<bool, bool>;
        ///Write proxy for field `TSEDGE`
        pub struct TSEDGE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSEDGE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `REFCKON`
        pub type REFCKON_R = crate::R<bool, bool>;
        ///Write proxy for field `REFCKON`
        pub struct REFCKON_W<'a> {
            w: &'a mut W,
        }
        impl<'a> REFCKON_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `BYPSHAD`
        pub type BYPSHAD_R = crate::R<bool, bool>;
        ///Write proxy for field `BYPSHAD`
        pub struct BYPSHAD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BYPSHAD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `FMT`
        pub type FMT_R = crate::R<bool, bool>;
        ///Write proxy for field `FMT`
        pub struct FMT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FMT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `ALRAE`
        pub type ALRAE_R = crate::R<bool, bool>;
        ///Write proxy for field `ALRAE`
        pub struct ALRAE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALRAE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `ALRBE`
        pub type ALRBE_R = crate::R<bool, bool>;
        ///Write proxy for field `ALRBE`
        pub struct ALRBE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALRBE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `WUTE`
        pub type WUTE_R = crate::R<bool, bool>;
        ///Write proxy for field `WUTE`
        pub struct WUTE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUTE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `TSE`
        pub type TSE_R = crate::R<bool, bool>;
        ///Write proxy for field `TSE`
        pub struct TSE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `ALRAIE`
        pub type ALRAIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ALRAIE`
        pub struct ALRAIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALRAIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ALRBIE`
        pub type ALRBIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ALRBIE`
        pub struct ALRBIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALRBIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `WUTIE`
        pub type WUTIE_R = crate::R<bool, bool>;
        ///Write proxy for field `WUTIE`
        pub struct WUTIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUTIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `TSIE`
        pub type TSIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TSIE`
        pub struct TSIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `ADD1H`
        pub type ADD1H_R = crate::R<bool, bool>;
        ///Write proxy for field `ADD1H`
        pub struct ADD1H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADD1H_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `SUB1H`
        pub type SUB1H_R = crate::R<bool, bool>;
        ///Write proxy for field `SUB1H`
        pub struct SUB1H_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SUB1H_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<bool, bool>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `COSEL`
        pub type COSEL_R = crate::R<bool, bool>;
        ///Write proxy for field `COSEL`
        pub struct COSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COSEL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `POL`
        pub type POL_R = crate::R<bool, bool>;
        ///Write proxy for field `POL`
        pub struct POL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> POL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `OSEL`
        pub type OSEL_R = crate::R<u8, u8>;
        ///Write proxy for field `OSEL`
        pub struct OSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> OSEL_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 21)) | (((value as u32) & 0x03) << 21);
                self.w
            }
        }
        ///Reader of field `COE`
        pub type COE_R = crate::R<bool, bool>;
        ///Write proxy for field `COE`
        pub struct COE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `ITSE`
        pub type ITSE_R = crate::R<bool, bool>;
        ///Write proxy for field `ITSE`
        pub struct ITSE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ITSE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        impl R {
            ///Bits 0:2 - Wakeup clock selection
            #[inline(always)]
            pub fn wucksel(&self) -> WUCKSEL_R {
                WUCKSEL_R::new((self.bits & 0x07) as u8)
            }
            ///Bit 3 - Time-stamp event active edge
            #[inline(always)]
            pub fn tsedge(&self) -> TSEDGE_R {
                TSEDGE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Reference clock detection enable (50 or 60 Hz)
            #[inline(always)]
            pub fn refckon(&self) -> REFCKON_R {
                REFCKON_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Bypass the shadow registers
            #[inline(always)]
            pub fn bypshad(&self) -> BYPSHAD_R {
                BYPSHAD_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Hour format
            #[inline(always)]
            pub fn fmt(&self) -> FMT_R {
                FMT_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 8 - Alarm A enable
            #[inline(always)]
            pub fn alrae(&self) -> ALRAE_R {
                ALRAE_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Alarm B enable
            #[inline(always)]
            pub fn alrbe(&self) -> ALRBE_R {
                ALRBE_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Wakeup timer enable
            #[inline(always)]
            pub fn wute(&self) -> WUTE_R {
                WUTE_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Time stamp enable
            #[inline(always)]
            pub fn tse(&self) -> TSE_R {
                TSE_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Alarm A interrupt enable
            #[inline(always)]
            pub fn alraie(&self) -> ALRAIE_R {
                ALRAIE_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Alarm B interrupt enable
            #[inline(always)]
            pub fn alrbie(&self) -> ALRBIE_R {
                ALRBIE_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Wakeup timer interrupt enable
            #[inline(always)]
            pub fn wutie(&self) -> WUTIE_R {
                WUTIE_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Time-stamp interrupt enable
            #[inline(always)]
            pub fn tsie(&self) -> TSIE_R {
                TSIE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Add 1 hour (summer time change)
            #[inline(always)]
            pub fn add1h(&self) -> ADD1H_R {
                ADD1H_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Subtract 1 hour (winter time change)
            #[inline(always)]
            pub fn sub1h(&self) -> SUB1H_R {
                SUB1H_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - Backup
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - Calibration output selection
            #[inline(always)]
            pub fn cosel(&self) -> COSEL_R {
                COSEL_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 20 - Output polarity
            #[inline(always)]
            pub fn pol(&self) -> POL_R {
                POL_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bits 21:22 - Output selection
            #[inline(always)]
            pub fn osel(&self) -> OSEL_R {
                OSEL_R::new(((self.bits >> 21) & 0x03) as u8)
            }
            ///Bit 23 - Calibration output enable
            #[inline(always)]
            pub fn coe(&self) -> COE_R {
                COE_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 24 - timestamp on internal event enable
            #[inline(always)]
            pub fn itse(&self) -> ITSE_R {
                ITSE_R::new(((self.bits >> 24) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:2 - Wakeup clock selection
            #[inline(always)]
            pub fn wucksel(&mut self) -> WUCKSEL_W {
                WUCKSEL_W { w: self }
            }
            ///Bit 3 - Time-stamp event active edge
            #[inline(always)]
            pub fn tsedge(&mut self) -> TSEDGE_W {
                TSEDGE_W { w: self }
            }
            ///Bit 4 - Reference clock detection enable (50 or 60 Hz)
            #[inline(always)]
            pub fn refckon(&mut self) -> REFCKON_W {
                REFCKON_W { w: self }
            }
            ///Bit 5 - Bypass the shadow registers
            #[inline(always)]
            pub fn bypshad(&mut self) -> BYPSHAD_W {
                BYPSHAD_W { w: self }
            }
            ///Bit 6 - Hour format
            #[inline(always)]
            pub fn fmt(&mut self) -> FMT_W {
                FMT_W { w: self }
            }
            ///Bit 8 - Alarm A enable
            #[inline(always)]
            pub fn alrae(&mut self) -> ALRAE_W {
                ALRAE_W { w: self }
            }
            ///Bit 9 - Alarm B enable
            #[inline(always)]
            pub fn alrbe(&mut self) -> ALRBE_W {
                ALRBE_W { w: self }
            }
            ///Bit 10 - Wakeup timer enable
            #[inline(always)]
            pub fn wute(&mut self) -> WUTE_W {
                WUTE_W { w: self }
            }
            ///Bit 11 - Time stamp enable
            #[inline(always)]
            pub fn tse(&mut self) -> TSE_W {
                TSE_W { w: self }
            }
            ///Bit 12 - Alarm A interrupt enable
            #[inline(always)]
            pub fn alraie(&mut self) -> ALRAIE_W {
                ALRAIE_W { w: self }
            }
            ///Bit 13 - Alarm B interrupt enable
            #[inline(always)]
            pub fn alrbie(&mut self) -> ALRBIE_W {
                ALRBIE_W { w: self }
            }
            ///Bit 14 - Wakeup timer interrupt enable
            #[inline(always)]
            pub fn wutie(&mut self) -> WUTIE_W {
                WUTIE_W { w: self }
            }
            ///Bit 15 - Time-stamp interrupt enable
            #[inline(always)]
            pub fn tsie(&mut self) -> TSIE_W {
                TSIE_W { w: self }
            }
            ///Bit 16 - Add 1 hour (summer time change)
            #[inline(always)]
            pub fn add1h(&mut self) -> ADD1H_W {
                ADD1H_W { w: self }
            }
            ///Bit 17 - Subtract 1 hour (winter time change)
            #[inline(always)]
            pub fn sub1h(&mut self) -> SUB1H_W {
                SUB1H_W { w: self }
            }
            ///Bit 18 - Backup
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
            ///Bit 19 - Calibration output selection
            #[inline(always)]
            pub fn cosel(&mut self) -> COSEL_W {
                COSEL_W { w: self }
            }
            ///Bit 20 - Output polarity
            #[inline(always)]
            pub fn pol(&mut self) -> POL_W {
                POL_W { w: self }
            }
            ///Bits 21:22 - Output selection
            #[inline(always)]
            pub fn osel(&mut self) -> OSEL_W {
                OSEL_W { w: self }
            }
            ///Bit 23 - Calibration output enable
            #[inline(always)]
            pub fn coe(&mut self) -> COE_W {
                COE_W { w: self }
            }
            ///Bit 24 - timestamp on internal event enable
            #[inline(always)]
            pub fn itse(&mut self) -> ITSE_W {
                ITSE_W { w: self }
            }
        }
    }
    ///initialization and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///`write(|w| ..)` method takes [isr::W](isr::W) writer structure
    impl crate::Writable for ISR {}
    ///initialization and status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Writer for register ISR
        pub type W = crate::W<u32, super::ISR>;
        ///Register ISR `reset()`'s with value 0x07
        impl crate::ResetValue for super::ISR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x07
            }
        }
        ///Reader of field `ALRAWF`
        pub type ALRAWF_R = crate::R<bool, bool>;
        ///Reader of field `ALRBWF`
        pub type ALRBWF_R = crate::R<bool, bool>;
        ///Reader of field `WUTWF`
        pub type WUTWF_R = crate::R<bool, bool>;
        ///Reader of field `SHPF`
        pub type SHPF_R = crate::R<bool, bool>;
        ///Write proxy for field `SHPF`
        pub struct SHPF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SHPF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `INITS`
        pub type INITS_R = crate::R<bool, bool>;
        ///Reader of field `RSF`
        pub type RSF_R = crate::R<bool, bool>;
        ///Write proxy for field `RSF`
        pub struct RSF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RSF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `INITF`
        pub type INITF_R = crate::R<bool, bool>;
        ///Reader of field `INIT`
        pub type INIT_R = crate::R<bool, bool>;
        ///Write proxy for field `INIT`
        pub struct INIT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> INIT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ALRAF`
        pub type ALRAF_R = crate::R<bool, bool>;
        ///Write proxy for field `ALRAF`
        pub struct ALRAF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALRAF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `ALRBF`
        pub type ALRBF_R = crate::R<bool, bool>;
        ///Write proxy for field `ALRBF`
        pub struct ALRBF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ALRBF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `WUTF`
        pub type WUTF_R = crate::R<bool, bool>;
        ///Write proxy for field `WUTF`
        pub struct WUTF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUTF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `TSF`
        pub type TSF_R = crate::R<bool, bool>;
        ///Write proxy for field `TSF`
        pub struct TSF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `TSOVF`
        pub type TSOVF_R = crate::R<bool, bool>;
        ///Write proxy for field `TSOVF`
        pub struct TSOVF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TSOVF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `TAMP1F`
        pub type TAMP1F_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP1F`
        pub struct TAMP1F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP1F_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `TAMP2F`
        pub type TAMP2F_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP2F`
        pub struct TAMP2F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP2F_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `TAMP3F`
        pub type TAMP3F_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP3F`
        pub struct TAMP3F_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP3F_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `RECALPF`
        pub type RECALPF_R = crate::R<bool, bool>;
        ///Reader of field `ITSF`
        pub type ITSF_R = crate::R<bool, bool>;
        ///Write proxy for field `ITSF`
        pub struct ITSF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ITSF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Alarm A write flag
            #[inline(always)]
            pub fn alrawf(&self) -> ALRAWF_R {
                ALRAWF_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Alarm B write flag
            #[inline(always)]
            pub fn alrbwf(&self) -> ALRBWF_R {
                ALRBWF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Wakeup timer write flag
            #[inline(always)]
            pub fn wutwf(&self) -> WUTWF_R {
                WUTWF_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Shift operation pending
            #[inline(always)]
            pub fn shpf(&self) -> SHPF_R {
                SHPF_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Initialization status flag
            #[inline(always)]
            pub fn inits(&self) -> INITS_R {
                INITS_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Registers synchronization flag
            #[inline(always)]
            pub fn rsf(&self) -> RSF_R {
                RSF_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Initialization flag
            #[inline(always)]
            pub fn initf(&self) -> INITF_R {
                INITF_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Initialization mode
            #[inline(always)]
            pub fn init(&self) -> INIT_R {
                INIT_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Alarm A flag
            #[inline(always)]
            pub fn alraf(&self) -> ALRAF_R {
                ALRAF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Alarm B flag
            #[inline(always)]
            pub fn alrbf(&self) -> ALRBF_R {
                ALRBF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Wakeup timer flag
            #[inline(always)]
            pub fn wutf(&self) -> WUTF_R {
                WUTF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Time-stamp flag
            #[inline(always)]
            pub fn tsf(&self) -> TSF_R {
                TSF_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Time-stamp overflow flag
            #[inline(always)]
            pub fn tsovf(&self) -> TSOVF_R {
                TSOVF_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Tamper detection flag
            #[inline(always)]
            pub fn tamp1f(&self) -> TAMP1F_R {
                TAMP1F_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - RTC_TAMP2 detection flag
            #[inline(always)]
            pub fn tamp2f(&self) -> TAMP2F_R {
                TAMP2F_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - RTC_TAMP3 detection flag
            #[inline(always)]
            pub fn tamp3f(&self) -> TAMP3F_R {
                TAMP3F_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Recalibration pending Flag
            #[inline(always)]
            pub fn recalpf(&self) -> RECALPF_R {
                RECALPF_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - INTERNAL TIME-STAMP FLAG
            #[inline(always)]
            pub fn itsf(&self) -> ITSF_R {
                ITSF_R::new(((self.bits >> 17) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 3 - Shift operation pending
            #[inline(always)]
            pub fn shpf(&mut self) -> SHPF_W {
                SHPF_W { w: self }
            }
            ///Bit 5 - Registers synchronization flag
            #[inline(always)]
            pub fn rsf(&mut self) -> RSF_W {
                RSF_W { w: self }
            }
            ///Bit 7 - Initialization mode
            #[inline(always)]
            pub fn init(&mut self) -> INIT_W {
                INIT_W { w: self }
            }
            ///Bit 8 - Alarm A flag
            #[inline(always)]
            pub fn alraf(&mut self) -> ALRAF_W {
                ALRAF_W { w: self }
            }
            ///Bit 9 - Alarm B flag
            #[inline(always)]
            pub fn alrbf(&mut self) -> ALRBF_W {
                ALRBF_W { w: self }
            }
            ///Bit 10 - Wakeup timer flag
            #[inline(always)]
            pub fn wutf(&mut self) -> WUTF_W {
                WUTF_W { w: self }
            }
            ///Bit 11 - Time-stamp flag
            #[inline(always)]
            pub fn tsf(&mut self) -> TSF_W {
                TSF_W { w: self }
            }
            ///Bit 12 - Time-stamp overflow flag
            #[inline(always)]
            pub fn tsovf(&mut self) -> TSOVF_W {
                TSOVF_W { w: self }
            }
            ///Bit 13 - Tamper detection flag
            #[inline(always)]
            pub fn tamp1f(&mut self) -> TAMP1F_W {
                TAMP1F_W { w: self }
            }
            ///Bit 14 - RTC_TAMP2 detection flag
            #[inline(always)]
            pub fn tamp2f(&mut self) -> TAMP2F_W {
                TAMP2F_W { w: self }
            }
            ///Bit 15 - RTC_TAMP3 detection flag
            #[inline(always)]
            pub fn tamp3f(&mut self) -> TAMP3F_W {
                TAMP3F_W { w: self }
            }
            ///Bit 17 - INTERNAL TIME-STAMP FLAG
            #[inline(always)]
            pub fn itsf(&mut self) -> ITSF_W {
                ITSF_W { w: self }
            }
        }
    }
    ///prescaler register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [prer](prer) module
    pub type PRER = crate::Reg<u32, _PRER>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PRER;
    ///`read()` method returns [prer::R](prer::R) reader structure
    impl crate::Readable for PRER {}
    ///`write(|w| ..)` method takes [prer::W](prer::W) writer structure
    impl crate::Writable for PRER {}
    ///prescaler register
    pub mod prer {
        ///Reader of register PRER
        pub type R = crate::R<u32, super::PRER>;
        ///Writer for register PRER
        pub type W = crate::W<u32, super::PRER>;
        ///Register PRER `reset()`'s with value 0x007f_00ff
        impl crate::ResetValue for super::PRER {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x007f_00ff
            }
        }
        ///Reader of field `PREDIV_A`
        pub type PREDIV_A_R = crate::R<u8, u8>;
        ///Write proxy for field `PREDIV_A`
        pub struct PREDIV_A_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PREDIV_A_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7f << 16)) | (((value as u32) & 0x7f) << 16);
                self.w
            }
        }
        ///Reader of field `PREDIV_S`
        pub type PREDIV_S_R = crate::R<u16, u16>;
        ///Write proxy for field `PREDIV_S`
        pub struct PREDIV_S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PREDIV_S_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7fff) | ((value as u32) & 0x7fff);
                self.w
            }
        }
        impl R {
            ///Bits 16:22 - Asynchronous prescaler factor
            #[inline(always)]
            pub fn prediv_a(&self) -> PREDIV_A_R {
                PREDIV_A_R::new(((self.bits >> 16) & 0x7f) as u8)
            }
            ///Bits 0:14 - Synchronous prescaler factor
            #[inline(always)]
            pub fn prediv_s(&self) -> PREDIV_S_R {
                PREDIV_S_R::new((self.bits & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 16:22 - Asynchronous prescaler factor
            #[inline(always)]
            pub fn prediv_a(&mut self) -> PREDIV_A_W {
                PREDIV_A_W { w: self }
            }
            ///Bits 0:14 - Synchronous prescaler factor
            #[inline(always)]
            pub fn prediv_s(&mut self) -> PREDIV_S_W {
                PREDIV_S_W { w: self }
            }
        }
    }
    ///wakeup timer register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [wutr](wutr) module
    pub type WUTR = crate::Reg<u32, _WUTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _WUTR;
    ///`read()` method returns [wutr::R](wutr::R) reader structure
    impl crate::Readable for WUTR {}
    ///`write(|w| ..)` method takes [wutr::W](wutr::W) writer structure
    impl crate::Writable for WUTR {}
    ///wakeup timer register
    pub mod wutr {
        ///Reader of register WUTR
        pub type R = crate::R<u32, super::WUTR>;
        ///Writer for register WUTR
        pub type W = crate::W<u32, super::WUTR>;
        ///Register WUTR `reset()`'s with value 0xffff
        impl crate::ResetValue for super::WUTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff
            }
        }
        ///Reader of field `WUT`
        pub type WUT_R = crate::R<u16, u16>;
        ///Write proxy for field `WUT`
        pub struct WUT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WUT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Wakeup auto-reload value bits
            #[inline(always)]
            pub fn wut(&self) -> WUT_R {
                WUT_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            ///Bits 0:15 - Wakeup auto-reload value bits
            #[inline(always)]
            pub fn wut(&mut self) -> WUT_W {
                WUT_W { w: self }
            }
        }
    }
    ///alarm A register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [alrmar](alrmar) module
    pub type ALRMAR = crate::Reg<u32, _ALRMAR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ALRMAR;
    ///`read()` method returns [alrmar::R](alrmar::R) reader structure
    impl crate::Readable for ALRMAR {}
    ///`write(|w| ..)` method takes [alrmar::W](alrmar::W) writer structure
    impl crate::Writable for ALRMAR {}
    ///alarm A register
    pub mod alrmar {
        ///Reader of register ALRMAR
        pub type R = crate::R<u32, super::ALRMAR>;
        ///Writer for register ALRMAR
        pub type W = crate::W<u32, super::ALRMAR>;
        ///Register ALRMAR `reset()`'s with value 0
        impl crate::ResetValue for super::ALRMAR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MSK4`
        pub type MSK4_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK4`
        pub struct MSK4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `WDSEL`
        pub type WDSEL_R = crate::R<bool, bool>;
        ///Write proxy for field `WDSEL`
        pub struct WDSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WDSEL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `DT`
        pub type DT_R = crate::R<u8, u8>;
        ///Write proxy for field `DT`
        pub struct DT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `DU`
        pub type DU_R = crate::R<u8, u8>;
        ///Write proxy for field `DU`
        pub struct DU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `MSK3`
        pub type MSK3_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK3`
        pub struct MSK3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `PM`
        pub type PM_R = crate::R<bool, bool>;
        ///Write proxy for field `PM`
        pub struct PM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `HT`
        pub type HT_R = crate::R<u8, u8>;
        ///Write proxy for field `HT`
        pub struct HT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `HU`
        pub type HU_R = crate::R<u8, u8>;
        ///Write proxy for field `HU`
        pub struct HU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `MSK2`
        pub type MSK2_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK2`
        pub struct MSK2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `MNT`
        pub type MNT_R = crate::R<u8, u8>;
        ///Write proxy for field `MNT`
        pub struct MNT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MNT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `MNU`
        pub type MNU_R = crate::R<u8, u8>;
        ///Write proxy for field `MNU`
        pub struct MNU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MNU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `MSK1`
        pub type MSK1_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK1`
        pub struct MSK1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ST`
        pub type ST_R = crate::R<u8, u8>;
        ///Write proxy for field `ST`
        pub struct ST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ST_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `SU`
        pub type SU_R = crate::R<u8, u8>;
        ///Write proxy for field `SU`
        pub struct SU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bit 31 - Alarm A date mask
            #[inline(always)]
            pub fn msk4(&self) -> MSK4_R {
                MSK4_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - Week day selection
            #[inline(always)]
            pub fn wdsel(&self) -> WDSEL_R {
                WDSEL_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bits 28:29 - Date tens in BCD format
            #[inline(always)]
            pub fn dt(&self) -> DT_R {
                DT_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 24:27 - Date units or day in BCD format
            #[inline(always)]
            pub fn du(&self) -> DU_R {
                DU_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bit 23 - Alarm A hours mask
            #[inline(always)]
            pub fn msk3(&self) -> MSK3_R {
                MSK3_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - AM/PM notation
            #[inline(always)]
            pub fn pm(&self) -> PM_R {
                PM_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bits 20:21 - Hour tens in BCD format
            #[inline(always)]
            pub fn ht(&self) -> HT_R {
                HT_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 16:19 - Hour units in BCD format
            #[inline(always)]
            pub fn hu(&self) -> HU_R {
                HU_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bit 15 - Alarm A minutes mask
            #[inline(always)]
            pub fn msk2(&self) -> MSK2_R {
                MSK2_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 12:14 - Minute tens in BCD format
            #[inline(always)]
            pub fn mnt(&self) -> MNT_R {
                MNT_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:11 - Minute units in BCD format
            #[inline(always)]
            pub fn mnu(&self) -> MNU_R {
                MNU_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bit 7 - Alarm A seconds mask
            #[inline(always)]
            pub fn msk1(&self) -> MSK1_R {
                MSK1_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Second tens in BCD format
            #[inline(always)]
            pub fn st(&self) -> ST_R {
                ST_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:3 - Second units in BCD format
            #[inline(always)]
            pub fn su(&self) -> SU_R {
                SU_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bit 31 - Alarm A date mask
            #[inline(always)]
            pub fn msk4(&mut self) -> MSK4_W {
                MSK4_W { w: self }
            }
            ///Bit 30 - Week day selection
            #[inline(always)]
            pub fn wdsel(&mut self) -> WDSEL_W {
                WDSEL_W { w: self }
            }
            ///Bits 28:29 - Date tens in BCD format
            #[inline(always)]
            pub fn dt(&mut self) -> DT_W {
                DT_W { w: self }
            }
            ///Bits 24:27 - Date units or day in BCD format
            #[inline(always)]
            pub fn du(&mut self) -> DU_W {
                DU_W { w: self }
            }
            ///Bit 23 - Alarm A hours mask
            #[inline(always)]
            pub fn msk3(&mut self) -> MSK3_W {
                MSK3_W { w: self }
            }
            ///Bit 22 - AM/PM notation
            #[inline(always)]
            pub fn pm(&mut self) -> PM_W {
                PM_W { w: self }
            }
            ///Bits 20:21 - Hour tens in BCD format
            #[inline(always)]
            pub fn ht(&mut self) -> HT_W {
                HT_W { w: self }
            }
            ///Bits 16:19 - Hour units in BCD format
            #[inline(always)]
            pub fn hu(&mut self) -> HU_W {
                HU_W { w: self }
            }
            ///Bit 15 - Alarm A minutes mask
            #[inline(always)]
            pub fn msk2(&mut self) -> MSK2_W {
                MSK2_W { w: self }
            }
            ///Bits 12:14 - Minute tens in BCD format
            #[inline(always)]
            pub fn mnt(&mut self) -> MNT_W {
                MNT_W { w: self }
            }
            ///Bits 8:11 - Minute units in BCD format
            #[inline(always)]
            pub fn mnu(&mut self) -> MNU_W {
                MNU_W { w: self }
            }
            ///Bit 7 - Alarm A seconds mask
            #[inline(always)]
            pub fn msk1(&mut self) -> MSK1_W {
                MSK1_W { w: self }
            }
            ///Bits 4:6 - Second tens in BCD format
            #[inline(always)]
            pub fn st(&mut self) -> ST_W {
                ST_W { w: self }
            }
            ///Bits 0:3 - Second units in BCD format
            #[inline(always)]
            pub fn su(&mut self) -> SU_W {
                SU_W { w: self }
            }
        }
    }
    ///alarm B register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [alrmbr](alrmbr) module
    pub type ALRMBR = crate::Reg<u32, _ALRMBR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ALRMBR;
    ///`read()` method returns [alrmbr::R](alrmbr::R) reader structure
    impl crate::Readable for ALRMBR {}
    ///`write(|w| ..)` method takes [alrmbr::W](alrmbr::W) writer structure
    impl crate::Writable for ALRMBR {}
    ///alarm B register
    pub mod alrmbr {
        ///Reader of register ALRMBR
        pub type R = crate::R<u32, super::ALRMBR>;
        ///Writer for register ALRMBR
        pub type W = crate::W<u32, super::ALRMBR>;
        ///Register ALRMBR `reset()`'s with value 0
        impl crate::ResetValue for super::ALRMBR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MSK4`
        pub type MSK4_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK4`
        pub struct MSK4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `WDSEL`
        pub type WDSEL_R = crate::R<bool, bool>;
        ///Write proxy for field `WDSEL`
        pub struct WDSEL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WDSEL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `DT`
        pub type DT_R = crate::R<u8, u8>;
        ///Write proxy for field `DT`
        pub struct DT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `DU`
        pub type DU_R = crate::R<u8, u8>;
        ///Write proxy for field `DU`
        pub struct DU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `MSK3`
        pub type MSK3_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK3`
        pub struct MSK3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `PM`
        pub type PM_R = crate::R<bool, bool>;
        ///Write proxy for field `PM`
        pub struct PM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `HT`
        pub type HT_R = crate::R<u8, u8>;
        ///Write proxy for field `HT`
        pub struct HT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
                self.w
            }
        }
        ///Reader of field `HU`
        pub type HU_R = crate::R<u8, u8>;
        ///Write proxy for field `HU`
        pub struct HU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> HU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
                self.w
            }
        }
        ///Reader of field `MSK2`
        pub type MSK2_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK2`
        pub struct MSK2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `MNT`
        pub type MNT_R = crate::R<u8, u8>;
        ///Write proxy for field `MNT`
        pub struct MNT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MNT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
                self.w
            }
        }
        ///Reader of field `MNU`
        pub type MNU_R = crate::R<u8, u8>;
        ///Write proxy for field `MNU`
        pub struct MNU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MNU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
                self.w
            }
        }
        ///Reader of field `MSK1`
        pub type MSK1_R = crate::R<bool, bool>;
        ///Write proxy for field `MSK1`
        pub struct MSK1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MSK1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ST`
        pub type ST_R = crate::R<u8, u8>;
        ///Write proxy for field `ST`
        pub struct ST_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ST_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
                self.w
            }
        }
        ///Reader of field `SU`
        pub type SU_R = crate::R<u8, u8>;
        ///Write proxy for field `SU`
        pub struct SU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SU_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
                self.w
            }
        }
        impl R {
            ///Bit 31 - Alarm B date mask
            #[inline(always)]
            pub fn msk4(&self) -> MSK4_R {
                MSK4_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 30 - Week day selection
            #[inline(always)]
            pub fn wdsel(&self) -> WDSEL_R {
                WDSEL_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bits 28:29 - Date tens in BCD format
            #[inline(always)]
            pub fn dt(&self) -> DT_R {
                DT_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bits 24:27 - Date units or day in BCD format
            #[inline(always)]
            pub fn du(&self) -> DU_R {
                DU_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bit 23 - Alarm B hours mask
            #[inline(always)]
            pub fn msk3(&self) -> MSK3_R {
                MSK3_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 22 - AM/PM notation
            #[inline(always)]
            pub fn pm(&self) -> PM_R {
                PM_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bits 20:21 - Hour tens in BCD format
            #[inline(always)]
            pub fn ht(&self) -> HT_R {
                HT_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bits 16:19 - Hour units in BCD format
            #[inline(always)]
            pub fn hu(&self) -> HU_R {
                HU_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bit 15 - Alarm B minutes mask
            #[inline(always)]
            pub fn msk2(&self) -> MSK2_R {
                MSK2_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 12:14 - Minute tens in BCD format
            #[inline(always)]
            pub fn mnt(&self) -> MNT_R {
                MNT_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 8:11 - Minute units in BCD format
            #[inline(always)]
            pub fn mnu(&self) -> MNU_R {
                MNU_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bit 7 - Alarm B seconds mask
            #[inline(always)]
            pub fn msk1(&self) -> MSK1_R {
                MSK1_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 4:6 - Second tens in BCD format
            #[inline(always)]
            pub fn st(&self) -> ST_R {
                ST_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 0:3 - Second units in BCD format
            #[inline(always)]
            pub fn su(&self) -> SU_R {
                SU_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            ///Bit 31 - Alarm B date mask
            #[inline(always)]
            pub fn msk4(&mut self) -> MSK4_W {
                MSK4_W { w: self }
            }
            ///Bit 30 - Week day selection
            #[inline(always)]
            pub fn wdsel(&mut self) -> WDSEL_W {
                WDSEL_W { w: self }
            }
            ///Bits 28:29 - Date tens in BCD format
            #[inline(always)]
            pub fn dt(&mut self) -> DT_W {
                DT_W { w: self }
            }
            ///Bits 24:27 - Date units or day in BCD format
            #[inline(always)]
            pub fn du(&mut self) -> DU_W {
                DU_W { w: self }
            }
            ///Bit 23 - Alarm B hours mask
            #[inline(always)]
            pub fn msk3(&mut self) -> MSK3_W {
                MSK3_W { w: self }
            }
            ///Bit 22 - AM/PM notation
            #[inline(always)]
            pub fn pm(&mut self) -> PM_W {
                PM_W { w: self }
            }
            ///Bits 20:21 - Hour tens in BCD format
            #[inline(always)]
            pub fn ht(&mut self) -> HT_W {
                HT_W { w: self }
            }
            ///Bits 16:19 - Hour units in BCD format
            #[inline(always)]
            pub fn hu(&mut self) -> HU_W {
                HU_W { w: self }
            }
            ///Bit 15 - Alarm B minutes mask
            #[inline(always)]
            pub fn msk2(&mut self) -> MSK2_W {
                MSK2_W { w: self }
            }
            ///Bits 12:14 - Minute tens in BCD format
            #[inline(always)]
            pub fn mnt(&mut self) -> MNT_W {
                MNT_W { w: self }
            }
            ///Bits 8:11 - Minute units in BCD format
            #[inline(always)]
            pub fn mnu(&mut self) -> MNU_W {
                MNU_W { w: self }
            }
            ///Bit 7 - Alarm B seconds mask
            #[inline(always)]
            pub fn msk1(&mut self) -> MSK1_W {
                MSK1_W { w: self }
            }
            ///Bits 4:6 - Second tens in BCD format
            #[inline(always)]
            pub fn st(&mut self) -> ST_W {
                ST_W { w: self }
            }
            ///Bits 0:3 - Second units in BCD format
            #[inline(always)]
            pub fn su(&mut self) -> SU_W {
                SU_W { w: self }
            }
        }
    }
    ///write protection register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [wpr](wpr) module
    pub type WPR = crate::Reg<u32, _WPR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _WPR;
    ///`write(|w| ..)` method takes [wpr::W](wpr::W) writer structure
    impl crate::Writable for WPR {}
    ///write protection register
    pub mod wpr {
        ///Writer for register WPR
        pub type W = crate::W<u32, super::WPR>;
        ///Register WPR `reset()`'s with value 0
        impl crate::ResetValue for super::WPR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `KEY`
        pub struct KEY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> KEY_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
                self.w
            }
        }
        impl W {
            ///Bits 0:7 - Write protection key
            #[inline(always)]
            pub fn key(&mut self) -> KEY_W {
                KEY_W { w: self }
            }
        }
    }
    ///sub second register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ssr](ssr) module
    pub type SSR = crate::Reg<u32, _SSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SSR;
    ///`read()` method returns [ssr::R](ssr::R) reader structure
    impl crate::Readable for SSR {}
    ///sub second register
    pub mod ssr {
        ///Reader of register SSR
        pub type R = crate::R<u32, super::SSR>;
        ///Reader of field `SS`
        pub type SS_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - Sub second value
            #[inline(always)]
            pub fn ss(&self) -> SS_R {
                SS_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///shift control register
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [shiftr](shiftr) module
    pub type SHIFTR = crate::Reg<u32, _SHIFTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SHIFTR;
    ///`write(|w| ..)` method takes [shiftr::W](shiftr::W) writer structure
    impl crate::Writable for SHIFTR {}
    ///shift control register
    pub mod shiftr {
        ///Writer for register SHIFTR
        pub type W = crate::W<u32, super::SHIFTR>;
        ///Register SHIFTR `reset()`'s with value 0
        impl crate::ResetValue for super::SHIFTR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `ADD1S`
        pub struct ADD1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADD1S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Write proxy for field `SUBFS`
        pub struct SUBFS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SUBFS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7fff) | ((value as u32) & 0x7fff);
                self.w
            }
        }
        impl W {
            ///Bit 31 - Add one second
            #[inline(always)]
            pub fn add1s(&mut self) -> ADD1S_W {
                ADD1S_W { w: self }
            }
            ///Bits 0:14 - Subtract a fraction of a second
            #[inline(always)]
            pub fn subfs(&mut self) -> SUBFS_W {
                SUBFS_W { w: self }
            }
        }
    }
    ///time stamp time register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tstr](tstr) module
    pub type TSTR = crate::Reg<u32, _TSTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TSTR;
    ///`read()` method returns [tstr::R](tstr::R) reader structure
    impl crate::Readable for TSTR {}
    ///time stamp time register
    pub mod tstr {
        ///Reader of register TSTR
        pub type R = crate::R<u32, super::TSTR>;
        ///Reader of field `SU`
        pub type SU_R = crate::R<u8, u8>;
        ///Reader of field `ST`
        pub type ST_R = crate::R<u8, u8>;
        ///Reader of field `MNU`
        pub type MNU_R = crate::R<u8, u8>;
        ///Reader of field `MNT`
        pub type MNT_R = crate::R<u8, u8>;
        ///Reader of field `HU`
        pub type HU_R = crate::R<u8, u8>;
        ///Reader of field `HT`
        pub type HT_R = crate::R<u8, u8>;
        ///Reader of field `PM`
        pub type PM_R = crate::R<bool, bool>;
        impl R {
            ///Bits 0:3 - Second units in BCD format
            #[inline(always)]
            pub fn su(&self) -> SU_R {
                SU_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:6 - Second tens in BCD format
            #[inline(always)]
            pub fn st(&self) -> ST_R {
                ST_R::new(((self.bits >> 4) & 0x07) as u8)
            }
            ///Bits 8:11 - Minute units in BCD format
            #[inline(always)]
            pub fn mnu(&self) -> MNU_R {
                MNU_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 12:14 - Minute tens in BCD format
            #[inline(always)]
            pub fn mnt(&self) -> MNT_R {
                MNT_R::new(((self.bits >> 12) & 0x07) as u8)
            }
            ///Bits 16:19 - Hour units in BCD format
            #[inline(always)]
            pub fn hu(&self) -> HU_R {
                HU_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            ///Bits 20:21 - Hour tens in BCD format
            #[inline(always)]
            pub fn ht(&self) -> HT_R {
                HT_R::new(((self.bits >> 20) & 0x03) as u8)
            }
            ///Bit 22 - AM/PM notation
            #[inline(always)]
            pub fn pm(&self) -> PM_R {
                PM_R::new(((self.bits >> 22) & 0x01) != 0)
            }
        }
    }
    ///time stamp date register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tsdr](tsdr) module
    pub type TSDR = crate::Reg<u32, _TSDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TSDR;
    ///`read()` method returns [tsdr::R](tsdr::R) reader structure
    impl crate::Readable for TSDR {}
    ///time stamp date register
    pub mod tsdr {
        ///Reader of register TSDR
        pub type R = crate::R<u32, super::TSDR>;
        ///Reader of field `WDU`
        pub type WDU_R = crate::R<u8, u8>;
        ///Reader of field `MT`
        pub type MT_R = crate::R<bool, bool>;
        ///Reader of field `MU`
        pub type MU_R = crate::R<u8, u8>;
        ///Reader of field `DT`
        pub type DT_R = crate::R<u8, u8>;
        ///Reader of field `DU`
        pub type DU_R = crate::R<u8, u8>;
        impl R {
            ///Bits 13:15 - Week day units
            #[inline(always)]
            pub fn wdu(&self) -> WDU_R {
                WDU_R::new(((self.bits >> 13) & 0x07) as u8)
            }
            ///Bit 12 - Month tens in BCD format
            #[inline(always)]
            pub fn mt(&self) -> MT_R {
                MT_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bits 8:11 - Month units in BCD format
            #[inline(always)]
            pub fn mu(&self) -> MU_R {
                MU_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 4:5 - Date tens in BCD format
            #[inline(always)]
            pub fn dt(&self) -> DT_R {
                DT_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bits 0:3 - Date units in BCD format
            #[inline(always)]
            pub fn du(&self) -> DU_R {
                DU_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///timestamp sub second register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tsssr](tsssr) module
    pub type TSSSR = crate::Reg<u32, _TSSSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TSSSR;
    ///`read()` method returns [tsssr::R](tsssr::R) reader structure
    impl crate::Readable for TSSSR {}
    ///timestamp sub second register
    pub mod tsssr {
        ///Reader of register TSSSR
        pub type R = crate::R<u32, super::TSSSR>;
        ///Reader of field `SS`
        pub type SS_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:15 - Sub second value
            #[inline(always)]
            pub fn ss(&self) -> SS_R {
                SS_R::new((self.bits & 0xffff) as u16)
            }
        }
    }
    ///calibration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [calr](calr) module
    pub type CALR = crate::Reg<u32, _CALR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CALR;
    ///`read()` method returns [calr::R](calr::R) reader structure
    impl crate::Readable for CALR {}
    ///`write(|w| ..)` method takes [calr::W](calr::W) writer structure
    impl crate::Writable for CALR {}
    ///calibration register
    pub mod calr {
        ///Reader of register CALR
        pub type R = crate::R<u32, super::CALR>;
        ///Writer for register CALR
        pub type W = crate::W<u32, super::CALR>;
        ///Register CALR `reset()`'s with value 0
        impl crate::ResetValue for super::CALR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CALP`
        pub type CALP_R = crate::R<bool, bool>;
        ///Write proxy for field `CALP`
        pub struct CALP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CALP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `CALW8`
        pub type CALW8_R = crate::R<bool, bool>;
        ///Write proxy for field `CALW8`
        pub struct CALW8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CALW8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CALW16`
        pub type CALW16_R = crate::R<bool, bool>;
        ///Write proxy for field `CALW16`
        pub struct CALW16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CALW16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `CALM`
        pub type CALM_R = crate::R<u16, u16>;
        ///Write proxy for field `CALM`
        pub struct CALM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CALM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
                self.w
            }
        }
        impl R {
            ///Bit 15 - Increase frequency of RTC by 488.5 ppm
            #[inline(always)]
            pub fn calp(&self) -> CALP_R {
                CALP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 14 - Use an 8-second calibration cycle period
            #[inline(always)]
            pub fn calw8(&self) -> CALW8_R {
                CALW8_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 13 - Use a 16-second calibration cycle period
            #[inline(always)]
            pub fn calw16(&self) -> CALW16_R {
                CALW16_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bits 0:8 - Calibration minus
            #[inline(always)]
            pub fn calm(&self) -> CALM_R {
                CALM_R::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            ///Bit 15 - Increase frequency of RTC by 488.5 ppm
            #[inline(always)]
            pub fn calp(&mut self) -> CALP_W {
                CALP_W { w: self }
            }
            ///Bit 14 - Use an 8-second calibration cycle period
            #[inline(always)]
            pub fn calw8(&mut self) -> CALW8_W {
                CALW8_W { w: self }
            }
            ///Bit 13 - Use a 16-second calibration cycle period
            #[inline(always)]
            pub fn calw16(&mut self) -> CALW16_W {
                CALW16_W { w: self }
            }
            ///Bits 0:8 - Calibration minus
            #[inline(always)]
            pub fn calm(&mut self) -> CALM_W {
                CALM_W { w: self }
            }
        }
    }
    ///tamper configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [tampcr](tampcr) module
    pub type TAMPCR = crate::Reg<u32, _TAMPCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _TAMPCR;
    ///`read()` method returns [tampcr::R](tampcr::R) reader structure
    impl crate::Readable for TAMPCR {}
    ///`write(|w| ..)` method takes [tampcr::W](tampcr::W) writer structure
    impl crate::Writable for TAMPCR {}
    ///tamper configuration register
    pub mod tampcr {
        ///Reader of register TAMPCR
        pub type R = crate::R<u32, super::TAMPCR>;
        ///Writer for register TAMPCR
        pub type W = crate::W<u32, super::TAMPCR>;
        ///Register TAMPCR `reset()`'s with value 0
        impl crate::ResetValue for super::TAMPCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TAMP1E`
        pub type TAMP1E_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP1E`
        pub struct TAMP1E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP1E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `TAMP1TRG`
        pub type TAMP1TRG_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP1TRG`
        pub struct TAMP1TRG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP1TRG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `TAMPIE`
        pub type TAMPIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMPIE`
        pub struct TAMPIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMPIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TAMP2E`
        pub type TAMP2E_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP2E`
        pub struct TAMP2E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP2E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `TAMP2TRG`
        pub type TAMP2TRG_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP2TRG`
        pub struct TAMP2TRG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP2TRG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `TAMP3E`
        pub type TAMP3E_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP3E`
        pub struct TAMP3E_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP3E_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `TAMP3TRG`
        pub type TAMP3TRG_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP3TRG`
        pub struct TAMP3TRG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP3TRG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `TAMPTS`
        pub type TAMPTS_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMPTS`
        pub struct TAMPTS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMPTS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `TAMPFREQ`
        pub type TAMPFREQ_R = crate::R<u8, u8>;
        ///Write proxy for field `TAMPFREQ`
        pub struct TAMPFREQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMPFREQ_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
                self.w
            }
        }
        ///Reader of field `TAMPFLT`
        pub type TAMPFLT_R = crate::R<u8, u8>;
        ///Write proxy for field `TAMPFLT`
        pub struct TAMPFLT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMPFLT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 11)) | (((value as u32) & 0x03) << 11);
                self.w
            }
        }
        ///Reader of field `TAMPPRCH`
        pub type TAMPPRCH_R = crate::R<u8, u8>;
        ///Write proxy for field `TAMPPRCH`
        pub struct TAMPPRCH_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMPPRCH_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 13)) | (((value as u32) & 0x03) << 13);
                self.w
            }
        }
        ///Reader of field `TAMPPUDIS`
        pub type TAMPPUDIS_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMPPUDIS`
        pub struct TAMPPUDIS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMPPUDIS_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `TAMP1IE`
        pub type TAMP1IE_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP1IE`
        pub struct TAMP1IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP1IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `TAMP1NOERASE`
        pub type TAMP1NOERASE_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP1NOERASE`
        pub struct TAMP1NOERASE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP1NOERASE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `TAMP1MF`
        pub type TAMP1MF_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP1MF`
        pub struct TAMP1MF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP1MF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `TAMP2IE`
        pub type TAMP2IE_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP2IE`
        pub struct TAMP2IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP2IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `TAMP2NOERASE`
        pub type TAMP2NOERASE_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP2NOERASE`
        pub struct TAMP2NOERASE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP2NOERASE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `TAMP2MF`
        pub type TAMP2MF_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP2MF`
        pub struct TAMP2MF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP2MF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `TAMP3IE`
        pub type TAMP3IE_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP3IE`
        pub struct TAMP3IE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP3IE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `TAMP3NOERASE`
        pub type TAMP3NOERASE_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP3NOERASE`
        pub struct TAMP3NOERASE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP3NOERASE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `TAMP3MF`
        pub type TAMP3MF_R = crate::R<bool, bool>;
        ///Write proxy for field `TAMP3MF`
        pub struct TAMP3MF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TAMP3MF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Tamper 1 detection enable
            #[inline(always)]
            pub fn tamp1e(&self) -> TAMP1E_R {
                TAMP1E_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Active level for tamper 1
            #[inline(always)]
            pub fn tamp1trg(&self) -> TAMP1TRG_R {
                TAMP1TRG_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Tamper interrupt enable
            #[inline(always)]
            pub fn tampie(&self) -> TAMPIE_R {
                TAMPIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Tamper 2 detection enable
            #[inline(always)]
            pub fn tamp2e(&self) -> TAMP2E_R {
                TAMP2E_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Active level for tamper 2
            #[inline(always)]
            pub fn tamp2trg(&self) -> TAMP2TRG_R {
                TAMP2TRG_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Tamper 3 detection enable
            #[inline(always)]
            pub fn tamp3e(&self) -> TAMP3E_R {
                TAMP3E_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Active level for tamper 3
            #[inline(always)]
            pub fn tamp3trg(&self) -> TAMP3TRG_R {
                TAMP3TRG_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Activate timestamp on tamper detection event
            #[inline(always)]
            pub fn tampts(&self) -> TAMPTS_R {
                TAMPTS_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:10 - Tamper sampling frequency
            #[inline(always)]
            pub fn tampfreq(&self) -> TAMPFREQ_R {
                TAMPFREQ_R::new(((self.bits >> 8) & 0x07) as u8)
            }
            ///Bits 11:12 - Tamper filter count
            #[inline(always)]
            pub fn tampflt(&self) -> TAMPFLT_R {
                TAMPFLT_R::new(((self.bits >> 11) & 0x03) as u8)
            }
            ///Bits 13:14 - Tamper precharge duration
            #[inline(always)]
            pub fn tampprch(&self) -> TAMPPRCH_R {
                TAMPPRCH_R::new(((self.bits >> 13) & 0x03) as u8)
            }
            ///Bit 15 - TAMPER pull-up disable
            #[inline(always)]
            pub fn tamppudis(&self) -> TAMPPUDIS_R {
                TAMPPUDIS_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Tamper 1 interrupt enable
            #[inline(always)]
            pub fn tamp1ie(&self) -> TAMP1IE_R {
                TAMP1IE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Tamper 1 no erase
            #[inline(always)]
            pub fn tamp1noerase(&self) -> TAMP1NOERASE_R {
                TAMP1NOERASE_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - Tamper 1 mask flag
            #[inline(always)]
            pub fn tamp1mf(&self) -> TAMP1MF_R {
                TAMP1MF_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - Tamper 2 interrupt enable
            #[inline(always)]
            pub fn tamp2ie(&self) -> TAMP2IE_R {
                TAMP2IE_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 20 - Tamper 2 no erase
            #[inline(always)]
            pub fn tamp2noerase(&self) -> TAMP2NOERASE_R {
                TAMP2NOERASE_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 21 - Tamper 2 mask flag
            #[inline(always)]
            pub fn tamp2mf(&self) -> TAMP2MF_R {
                TAMP2MF_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 22 - Tamper 3 interrupt enable
            #[inline(always)]
            pub fn tamp3ie(&self) -> TAMP3IE_R {
                TAMP3IE_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 23 - Tamper 3 no erase
            #[inline(always)]
            pub fn tamp3noerase(&self) -> TAMP3NOERASE_R {
                TAMP3NOERASE_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 24 - Tamper 3 mask flag
            #[inline(always)]
            pub fn tamp3mf(&self) -> TAMP3MF_R {
                TAMP3MF_R::new(((self.bits >> 24) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Tamper 1 detection enable
            #[inline(always)]
            pub fn tamp1e(&mut self) -> TAMP1E_W {
                TAMP1E_W { w: self }
            }
            ///Bit 1 - Active level for tamper 1
            #[inline(always)]
            pub fn tamp1trg(&mut self) -> TAMP1TRG_W {
                TAMP1TRG_W { w: self }
            }
            ///Bit 2 - Tamper interrupt enable
            #[inline(always)]
            pub fn tampie(&mut self) -> TAMPIE_W {
                TAMPIE_W { w: self }
            }
            ///Bit 3 - Tamper 2 detection enable
            #[inline(always)]
            pub fn tamp2e(&mut self) -> TAMP2E_W {
                TAMP2E_W { w: self }
            }
            ///Bit 4 - Active level for tamper 2
            #[inline(always)]
            pub fn tamp2trg(&mut self) -> TAMP2TRG_W {
                TAMP2TRG_W { w: self }
            }
            ///Bit 5 - Tamper 3 detection enable
            #[inline(always)]
            pub fn tamp3e(&mut self) -> TAMP3E_W {
                TAMP3E_W { w: self }
            }
            ///Bit 6 - Active level for tamper 3
            #[inline(always)]
            pub fn tamp3trg(&mut self) -> TAMP3TRG_W {
                TAMP3TRG_W { w: self }
            }
            ///Bit 7 - Activate timestamp on tamper detection event
            #[inline(always)]
            pub fn tampts(&mut self) -> TAMPTS_W {
                TAMPTS_W { w: self }
            }
            ///Bits 8:10 - Tamper sampling frequency
            #[inline(always)]
            pub fn tampfreq(&mut self) -> TAMPFREQ_W {
                TAMPFREQ_W { w: self }
            }
            ///Bits 11:12 - Tamper filter count
            #[inline(always)]
            pub fn tampflt(&mut self) -> TAMPFLT_W {
                TAMPFLT_W { w: self }
            }
            ///Bits 13:14 - Tamper precharge duration
            #[inline(always)]
            pub fn tampprch(&mut self) -> TAMPPRCH_W {
                TAMPPRCH_W { w: self }
            }
            ///Bit 15 - TAMPER pull-up disable
            #[inline(always)]
            pub fn tamppudis(&mut self) -> TAMPPUDIS_W {
                TAMPPUDIS_W { w: self }
            }
            ///Bit 16 - Tamper 1 interrupt enable
            #[inline(always)]
            pub fn tamp1ie(&mut self) -> TAMP1IE_W {
                TAMP1IE_W { w: self }
            }
            ///Bit 17 - Tamper 1 no erase
            #[inline(always)]
            pub fn tamp1noerase(&mut self) -> TAMP1NOERASE_W {
                TAMP1NOERASE_W { w: self }
            }
            ///Bit 18 - Tamper 1 mask flag
            #[inline(always)]
            pub fn tamp1mf(&mut self) -> TAMP1MF_W {
                TAMP1MF_W { w: self }
            }
            ///Bit 19 - Tamper 2 interrupt enable
            #[inline(always)]
            pub fn tamp2ie(&mut self) -> TAMP2IE_W {
                TAMP2IE_W { w: self }
            }
            ///Bit 20 - Tamper 2 no erase
            #[inline(always)]
            pub fn tamp2noerase(&mut self) -> TAMP2NOERASE_W {
                TAMP2NOERASE_W { w: self }
            }
            ///Bit 21 - Tamper 2 mask flag
            #[inline(always)]
            pub fn tamp2mf(&mut self) -> TAMP2MF_W {
                TAMP2MF_W { w: self }
            }
            ///Bit 22 - Tamper 3 interrupt enable
            #[inline(always)]
            pub fn tamp3ie(&mut self) -> TAMP3IE_W {
                TAMP3IE_W { w: self }
            }
            ///Bit 23 - Tamper 3 no erase
            #[inline(always)]
            pub fn tamp3noerase(&mut self) -> TAMP3NOERASE_W {
                TAMP3NOERASE_W { w: self }
            }
            ///Bit 24 - Tamper 3 mask flag
            #[inline(always)]
            pub fn tamp3mf(&mut self) -> TAMP3MF_W {
                TAMP3MF_W { w: self }
            }
        }
    }
    ///alarm A sub second register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [alrmassr](alrmassr) module
    pub type ALRMASSR = crate::Reg<u32, _ALRMASSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ALRMASSR;
    ///`read()` method returns [alrmassr::R](alrmassr::R) reader structure
    impl crate::Readable for ALRMASSR {}
    ///`write(|w| ..)` method takes [alrmassr::W](alrmassr::W) writer structure
    impl crate::Writable for ALRMASSR {}
    ///alarm A sub second register
    pub mod alrmassr {
        ///Reader of register ALRMASSR
        pub type R = crate::R<u32, super::ALRMASSR>;
        ///Writer for register ALRMASSR
        pub type W = crate::W<u32, super::ALRMASSR>;
        ///Register ALRMASSR `reset()`'s with value 0
        impl crate::ResetValue for super::ALRMASSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MASKSS`
        pub type MASKSS_R = crate::R<u8, u8>;
        ///Write proxy for field `MASKSS`
        pub struct MASKSS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MASKSS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `SS`
        pub type SS_R = crate::R<u16, u16>;
        ///Write proxy for field `SS`
        pub struct SS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7fff) | ((value as u32) & 0x7fff);
                self.w
            }
        }
        impl R {
            ///Bits 24:27 - Mask the most-significant bits starting at this bit
            #[inline(always)]
            pub fn maskss(&self) -> MASKSS_R {
                MASKSS_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 0:14 - Sub seconds value
            #[inline(always)]
            pub fn ss(&self) -> SS_R {
                SS_R::new((self.bits & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 24:27 - Mask the most-significant bits starting at this bit
            #[inline(always)]
            pub fn maskss(&mut self) -> MASKSS_W {
                MASKSS_W { w: self }
            }
            ///Bits 0:14 - Sub seconds value
            #[inline(always)]
            pub fn ss(&mut self) -> SS_W {
                SS_W { w: self }
            }
        }
    }
    ///alarm B sub second register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [alrmbssr](alrmbssr) module
    pub type ALRMBSSR = crate::Reg<u32, _ALRMBSSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ALRMBSSR;
    ///`read()` method returns [alrmbssr::R](alrmbssr::R) reader structure
    impl crate::Readable for ALRMBSSR {}
    ///`write(|w| ..)` method takes [alrmbssr::W](alrmbssr::W) writer structure
    impl crate::Writable for ALRMBSSR {}
    ///alarm B sub second register
    pub mod alrmbssr {
        ///Reader of register ALRMBSSR
        pub type R = crate::R<u32, super::ALRMBSSR>;
        ///Writer for register ALRMBSSR
        pub type W = crate::W<u32, super::ALRMBSSR>;
        ///Register ALRMBSSR `reset()`'s with value 0
        impl crate::ResetValue for super::ALRMBSSR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `MASKSS`
        pub type MASKSS_R = crate::R<u8, u8>;
        ///Write proxy for field `MASKSS`
        pub struct MASKSS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MASKSS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
                self.w
            }
        }
        ///Reader of field `SS`
        pub type SS_R = crate::R<u16, u16>;
        ///Write proxy for field `SS`
        pub struct SS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7fff) | ((value as u32) & 0x7fff);
                self.w
            }
        }
        impl R {
            ///Bits 24:27 - Mask the most-significant bits starting at this bit
            #[inline(always)]
            pub fn maskss(&self) -> MASKSS_R {
                MASKSS_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            ///Bits 0:14 - Sub seconds value
            #[inline(always)]
            pub fn ss(&self) -> SS_R {
                SS_R::new((self.bits & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 24:27 - Mask the most-significant bits starting at this bit
            #[inline(always)]
            pub fn maskss(&mut self) -> MASKSS_W {
                MASKSS_W { w: self }
            }
            ///Bits 0:14 - Sub seconds value
            #[inline(always)]
            pub fn ss(&mut self) -> SS_W {
                SS_W { w: self }
            }
        }
    }
    ///option register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [or](or) module
    pub type OR = crate::Reg<u32, _OR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _OR;
    ///`read()` method returns [or::R](or::R) reader structure
    impl crate::Readable for OR {}
    ///`write(|w| ..)` method takes [or::W](or::W) writer structure
    impl crate::Writable for OR {}
    ///option register
    pub mod or {
        ///Reader of register OR
        pub type R = crate::R<u32, super::OR>;
        ///Writer for register OR
        pub type W = crate::W<u32, super::OR>;
        ///Register OR `reset()`'s with value 0
        impl crate::ResetValue for super::OR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RTC_ALARM_TYPE`
        pub type RTC_ALARM_TYPE_R = crate::R<bool, bool>;
        ///Write proxy for field `RTC_ALARM_TYPE`
        pub struct RTC_ALARM_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTC_ALARM_TYPE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `RTC_OUT_RMP`
        pub type RTC_OUT_RMP_R = crate::R<bool, bool>;
        ///Write proxy for field `RTC_OUT_RMP`
        pub struct RTC_OUT_RMP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RTC_OUT_RMP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        impl R {
            ///Bit 0 - RTC_ALARM on PC13 output type
            #[inline(always)]
            pub fn rtc_alarm_type(&self) -> RTC_ALARM_TYPE_R {
                RTC_ALARM_TYPE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - RTC_OUT remap
            #[inline(always)]
            pub fn rtc_out_rmp(&self) -> RTC_OUT_RMP_R {
                RTC_OUT_RMP_R::new(((self.bits >> 1) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - RTC_ALARM on PC13 output type
            #[inline(always)]
            pub fn rtc_alarm_type(&mut self) -> RTC_ALARM_TYPE_W {
                RTC_ALARM_TYPE_W { w: self }
            }
            ///Bit 1 - RTC_OUT remap
            #[inline(always)]
            pub fn rtc_out_rmp(&mut self) -> RTC_OUT_RMP_W {
                RTC_OUT_RMP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp0r](bkp0r) module
    pub type BKP0R = crate::Reg<u32, _BKP0R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP0R;
    ///`read()` method returns [bkp0r::R](bkp0r::R) reader structure
    impl crate::Readable for BKP0R {}
    ///`write(|w| ..)` method takes [bkp0r::W](bkp0r::W) writer structure
    impl crate::Writable for BKP0R {}
    ///backup register
    pub mod bkp0r {
        ///Reader of register BKP0R
        pub type R = crate::R<u32, super::BKP0R>;
        ///Writer for register BKP0R
        pub type W = crate::W<u32, super::BKP0R>;
        ///Register BKP0R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP0R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp1r](bkp1r) module
    pub type BKP1R = crate::Reg<u32, _BKP1R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP1R;
    ///`read()` method returns [bkp1r::R](bkp1r::R) reader structure
    impl crate::Readable for BKP1R {}
    ///`write(|w| ..)` method takes [bkp1r::W](bkp1r::W) writer structure
    impl crate::Writable for BKP1R {}
    ///backup register
    pub mod bkp1r {
        ///Reader of register BKP1R
        pub type R = crate::R<u32, super::BKP1R>;
        ///Writer for register BKP1R
        pub type W = crate::W<u32, super::BKP1R>;
        ///Register BKP1R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP1R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp2r](bkp2r) module
    pub type BKP2R = crate::Reg<u32, _BKP2R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP2R;
    ///`read()` method returns [bkp2r::R](bkp2r::R) reader structure
    impl crate::Readable for BKP2R {}
    ///`write(|w| ..)` method takes [bkp2r::W](bkp2r::W) writer structure
    impl crate::Writable for BKP2R {}
    ///backup register
    pub mod bkp2r {
        ///Reader of register BKP2R
        pub type R = crate::R<u32, super::BKP2R>;
        ///Writer for register BKP2R
        pub type W = crate::W<u32, super::BKP2R>;
        ///Register BKP2R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP2R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp3r](bkp3r) module
    pub type BKP3R = crate::Reg<u32, _BKP3R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP3R;
    ///`read()` method returns [bkp3r::R](bkp3r::R) reader structure
    impl crate::Readable for BKP3R {}
    ///`write(|w| ..)` method takes [bkp3r::W](bkp3r::W) writer structure
    impl crate::Writable for BKP3R {}
    ///backup register
    pub mod bkp3r {
        ///Reader of register BKP3R
        pub type R = crate::R<u32, super::BKP3R>;
        ///Writer for register BKP3R
        pub type W = crate::W<u32, super::BKP3R>;
        ///Register BKP3R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP3R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp4r](bkp4r) module
    pub type BKP4R = crate::Reg<u32, _BKP4R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP4R;
    ///`read()` method returns [bkp4r::R](bkp4r::R) reader structure
    impl crate::Readable for BKP4R {}
    ///`write(|w| ..)` method takes [bkp4r::W](bkp4r::W) writer structure
    impl crate::Writable for BKP4R {}
    ///backup register
    pub mod bkp4r {
        ///Reader of register BKP4R
        pub type R = crate::R<u32, super::BKP4R>;
        ///Writer for register BKP4R
        pub type W = crate::W<u32, super::BKP4R>;
        ///Register BKP4R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP4R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp5r](bkp5r) module
    pub type BKP5R = crate::Reg<u32, _BKP5R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP5R;
    ///`read()` method returns [bkp5r::R](bkp5r::R) reader structure
    impl crate::Readable for BKP5R {}
    ///`write(|w| ..)` method takes [bkp5r::W](bkp5r::W) writer structure
    impl crate::Writable for BKP5R {}
    ///backup register
    pub mod bkp5r {
        ///Reader of register BKP5R
        pub type R = crate::R<u32, super::BKP5R>;
        ///Writer for register BKP5R
        pub type W = crate::W<u32, super::BKP5R>;
        ///Register BKP5R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP5R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp6r](bkp6r) module
    pub type BKP6R = crate::Reg<u32, _BKP6R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP6R;
    ///`read()` method returns [bkp6r::R](bkp6r::R) reader structure
    impl crate::Readable for BKP6R {}
    ///`write(|w| ..)` method takes [bkp6r::W](bkp6r::W) writer structure
    impl crate::Writable for BKP6R {}
    ///backup register
    pub mod bkp6r {
        ///Reader of register BKP6R
        pub type R = crate::R<u32, super::BKP6R>;
        ///Writer for register BKP6R
        pub type W = crate::W<u32, super::BKP6R>;
        ///Register BKP6R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP6R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp7r](bkp7r) module
    pub type BKP7R = crate::Reg<u32, _BKP7R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP7R;
    ///`read()` method returns [bkp7r::R](bkp7r::R) reader structure
    impl crate::Readable for BKP7R {}
    ///`write(|w| ..)` method takes [bkp7r::W](bkp7r::W) writer structure
    impl crate::Writable for BKP7R {}
    ///backup register
    pub mod bkp7r {
        ///Reader of register BKP7R
        pub type R = crate::R<u32, super::BKP7R>;
        ///Writer for register BKP7R
        pub type W = crate::W<u32, super::BKP7R>;
        ///Register BKP7R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP7R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp8r](bkp8r) module
    pub type BKP8R = crate::Reg<u32, _BKP8R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP8R;
    ///`read()` method returns [bkp8r::R](bkp8r::R) reader structure
    impl crate::Readable for BKP8R {}
    ///`write(|w| ..)` method takes [bkp8r::W](bkp8r::W) writer structure
    impl crate::Writable for BKP8R {}
    ///backup register
    pub mod bkp8r {
        ///Reader of register BKP8R
        pub type R = crate::R<u32, super::BKP8R>;
        ///Writer for register BKP8R
        pub type W = crate::W<u32, super::BKP8R>;
        ///Register BKP8R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP8R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp9r](bkp9r) module
    pub type BKP9R = crate::Reg<u32, _BKP9R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP9R;
    ///`read()` method returns [bkp9r::R](bkp9r::R) reader structure
    impl crate::Readable for BKP9R {}
    ///`write(|w| ..)` method takes [bkp9r::W](bkp9r::W) writer structure
    impl crate::Writable for BKP9R {}
    ///backup register
    pub mod bkp9r {
        ///Reader of register BKP9R
        pub type R = crate::R<u32, super::BKP9R>;
        ///Writer for register BKP9R
        pub type W = crate::W<u32, super::BKP9R>;
        ///Register BKP9R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP9R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp10r](bkp10r) module
    pub type BKP10R = crate::Reg<u32, _BKP10R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP10R;
    ///`read()` method returns [bkp10r::R](bkp10r::R) reader structure
    impl crate::Readable for BKP10R {}
    ///`write(|w| ..)` method takes [bkp10r::W](bkp10r::W) writer structure
    impl crate::Writable for BKP10R {}
    ///backup register
    pub mod bkp10r {
        ///Reader of register BKP10R
        pub type R = crate::R<u32, super::BKP10R>;
        ///Writer for register BKP10R
        pub type W = crate::W<u32, super::BKP10R>;
        ///Register BKP10R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP10R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp11r](bkp11r) module
    pub type BKP11R = crate::Reg<u32, _BKP11R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP11R;
    ///`read()` method returns [bkp11r::R](bkp11r::R) reader structure
    impl crate::Readable for BKP11R {}
    ///`write(|w| ..)` method takes [bkp11r::W](bkp11r::W) writer structure
    impl crate::Writable for BKP11R {}
    ///backup register
    pub mod bkp11r {
        ///Reader of register BKP11R
        pub type R = crate::R<u32, super::BKP11R>;
        ///Writer for register BKP11R
        pub type W = crate::W<u32, super::BKP11R>;
        ///Register BKP11R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP11R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp12r](bkp12r) module
    pub type BKP12R = crate::Reg<u32, _BKP12R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP12R;
    ///`read()` method returns [bkp12r::R](bkp12r::R) reader structure
    impl crate::Readable for BKP12R {}
    ///`write(|w| ..)` method takes [bkp12r::W](bkp12r::W) writer structure
    impl crate::Writable for BKP12R {}
    ///backup register
    pub mod bkp12r {
        ///Reader of register BKP12R
        pub type R = crate::R<u32, super::BKP12R>;
        ///Writer for register BKP12R
        pub type W = crate::W<u32, super::BKP12R>;
        ///Register BKP12R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP12R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp13r](bkp13r) module
    pub type BKP13R = crate::Reg<u32, _BKP13R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP13R;
    ///`read()` method returns [bkp13r::R](bkp13r::R) reader structure
    impl crate::Readable for BKP13R {}
    ///`write(|w| ..)` method takes [bkp13r::W](bkp13r::W) writer structure
    impl crate::Writable for BKP13R {}
    ///backup register
    pub mod bkp13r {
        ///Reader of register BKP13R
        pub type R = crate::R<u32, super::BKP13R>;
        ///Writer for register BKP13R
        pub type W = crate::W<u32, super::BKP13R>;
        ///Register BKP13R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP13R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp14r](bkp14r) module
    pub type BKP14R = crate::Reg<u32, _BKP14R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP14R;
    ///`read()` method returns [bkp14r::R](bkp14r::R) reader structure
    impl crate::Readable for BKP14R {}
    ///`write(|w| ..)` method takes [bkp14r::W](bkp14r::W) writer structure
    impl crate::Writable for BKP14R {}
    ///backup register
    pub mod bkp14r {
        ///Reader of register BKP14R
        pub type R = crate::R<u32, super::BKP14R>;
        ///Writer for register BKP14R
        pub type W = crate::W<u32, super::BKP14R>;
        ///Register BKP14R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP14R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp15r](bkp15r) module
    pub type BKP15R = crate::Reg<u32, _BKP15R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP15R;
    ///`read()` method returns [bkp15r::R](bkp15r::R) reader structure
    impl crate::Readable for BKP15R {}
    ///`write(|w| ..)` method takes [bkp15r::W](bkp15r::W) writer structure
    impl crate::Writable for BKP15R {}
    ///backup register
    pub mod bkp15r {
        ///Reader of register BKP15R
        pub type R = crate::R<u32, super::BKP15R>;
        ///Writer for register BKP15R
        pub type W = crate::W<u32, super::BKP15R>;
        ///Register BKP15R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP15R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp16r](bkp16r) module
    pub type BKP16R = crate::Reg<u32, _BKP16R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP16R;
    ///`read()` method returns [bkp16r::R](bkp16r::R) reader structure
    impl crate::Readable for BKP16R {}
    ///`write(|w| ..)` method takes [bkp16r::W](bkp16r::W) writer structure
    impl crate::Writable for BKP16R {}
    ///backup register
    pub mod bkp16r {
        ///Reader of register BKP16R
        pub type R = crate::R<u32, super::BKP16R>;
        ///Writer for register BKP16R
        pub type W = crate::W<u32, super::BKP16R>;
        ///Register BKP16R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP16R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp17r](bkp17r) module
    pub type BKP17R = crate::Reg<u32, _BKP17R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP17R;
    ///`read()` method returns [bkp17r::R](bkp17r::R) reader structure
    impl crate::Readable for BKP17R {}
    ///`write(|w| ..)` method takes [bkp17r::W](bkp17r::W) writer structure
    impl crate::Writable for BKP17R {}
    ///backup register
    pub mod bkp17r {
        ///Reader of register BKP17R
        pub type R = crate::R<u32, super::BKP17R>;
        ///Writer for register BKP17R
        pub type W = crate::W<u32, super::BKP17R>;
        ///Register BKP17R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP17R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp18r](bkp18r) module
    pub type BKP18R = crate::Reg<u32, _BKP18R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP18R;
    ///`read()` method returns [bkp18r::R](bkp18r::R) reader structure
    impl crate::Readable for BKP18R {}
    ///`write(|w| ..)` method takes [bkp18r::W](bkp18r::W) writer structure
    impl crate::Writable for BKP18R {}
    ///backup register
    pub mod bkp18r {
        ///Reader of register BKP18R
        pub type R = crate::R<u32, super::BKP18R>;
        ///Writer for register BKP18R
        pub type W = crate::W<u32, super::BKP18R>;
        ///Register BKP18R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP18R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
    ///backup register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bkp19r](bkp19r) module
    pub type BKP19R = crate::Reg<u32, _BKP19R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BKP19R;
    ///`read()` method returns [bkp19r::R](bkp19r::R) reader structure
    impl crate::Readable for BKP19R {}
    ///`write(|w| ..)` method takes [bkp19r::W](bkp19r::W) writer structure
    impl crate::Writable for BKP19R {}
    ///backup register
    pub mod bkp19r {
        ///Reader of register BKP19R
        pub type R = crate::R<u32, super::BKP19R>;
        ///Writer for register BKP19R
        pub type W = crate::W<u32, super::BKP19R>;
        ///Register BKP19R `reset()`'s with value 0
        impl crate::ResetValue for super::BKP19R {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BKP`
        pub type BKP_R = crate::R<u32, u32>;
        ///Write proxy for field `BKP`
        pub struct BKP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BKP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&self) -> BKP_R {
                BKP_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - BKP
            #[inline(always)]
            pub fn bkp(&mut self) -> BKP_W {
                BKP_W { w: self }
            }
        }
    }
}
///Debug support
pub struct DBGMCU {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for DBGMCU {}
impl DBGMCU {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const dbgmcu::RegisterBlock {
        0xe004_2000 as *const _
    }
}
impl Deref for DBGMCU {
    type Target = dbgmcu::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*DBGMCU::ptr() }
    }
}
///Debug support
pub mod dbgmcu {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - MCU Device ID Code Register
        pub idcode: IDCODE,
        ///0x04 - Debug MCU Configuration Register
        pub cr: CR,
        _reserved2: [u8; 52usize],
        ///0x3c - APB1 Low Freeze Register CPU1
        pub apb1fzr1: APB1FZR1,
        ///0x40 - APB1 Low Freeze Register CPU2
        pub c2ap_b1fzr1: C2AP_B1FZR1,
        ///0x44 - APB1 High Freeze Register CPU1
        pub apb1fzr2: APB1FZR2,
        _reserved_5_c2apb: [u8; 4usize],
        ///0x4c - APB2 Freeze Register CPU1
        pub apb2fzr: APB2FZR,
    }
    impl RegisterBlock {
        ///0x48 - APB2 Freeze Register CPU2
        #[inline(always)]
        pub fn c2apb2fzr(&self) -> &C2APB2FZR {
            unsafe { &*(((self as *const Self) as *const u8).add(72usize) as *const C2APB2FZR) }
        }
        ///0x48 - APB2 Freeze Register CPU2
        #[inline(always)]
        pub fn c2apb2fzr_mut(&self) -> &mut C2APB2FZR {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(72usize) as *mut C2APB2FZR) }
        }
        ///0x48 - APB1 High Freeze Register CPU2
        #[inline(always)]
        pub fn c2apb1fzr2(&self) -> &C2APB1FZR2 {
            unsafe { &*(((self as *const Self) as *const u8).add(72usize) as *const C2APB1FZR2) }
        }
        ///0x48 - APB1 High Freeze Register CPU2
        #[inline(always)]
        pub fn c2apb1fzr2_mut(&self) -> &mut C2APB1FZR2 {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(72usize) as *mut C2APB1FZR2) }
        }
    }
    ///MCU Device ID Code Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [idcode](idcode) module
    pub type IDCODE = crate::Reg<u32, _IDCODE>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IDCODE;
    ///`read()` method returns [idcode::R](idcode::R) reader structure
    impl crate::Readable for IDCODE {}
    ///MCU Device ID Code Register
    pub mod idcode {
        ///Reader of register IDCODE
        pub type R = crate::R<u32, super::IDCODE>;
        ///Reader of field `DEV_ID`
        pub type DEV_ID_R = crate::R<u16, u16>;
        ///Reader of field `REV_ID`
        pub type REV_ID_R = crate::R<u16, u16>;
        impl R {
            ///Bits 0:11 - Device Identifier
            #[inline(always)]
            pub fn dev_id(&self) -> DEV_ID_R {
                DEV_ID_R::new((self.bits & 0x0fff) as u16)
            }
            ///Bits 16:31 - Revision Identifier
            #[inline(always)]
            pub fn rev_id(&self) -> REV_ID_R {
                REV_ID_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
    }
    ///Debug MCU Configuration Register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Debug MCU Configuration Register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBG_SLEEP`
        pub type DBG_SLEEP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_SLEEP`
        pub struct DBG_SLEEP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_SLEEP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `DBG_STOP`
        pub type DBG_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_STOP`
        pub struct DBG_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DBG_STANDBY`
        pub type DBG_STANDBY_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_STANDBY`
        pub struct DBG_STANDBY_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_STANDBY_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `TRACE_IOEN`
        pub type TRACE_IOEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TRACE_IOEN`
        pub struct TRACE_IOEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TRACE_IOEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `TRGOEN`
        pub type TRGOEN_R = crate::R<bool, bool>;
        ///Write proxy for field `TRGOEN`
        pub struct TRGOEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TRGOEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Debug Sleep Mode
            #[inline(always)]
            pub fn dbg_sleep(&self) -> DBG_SLEEP_R {
                DBG_SLEEP_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Debug Stop Mode
            #[inline(always)]
            pub fn dbg_stop(&self) -> DBG_STOP_R {
                DBG_STOP_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Debug Standby Mode
            #[inline(always)]
            pub fn dbg_standby(&self) -> DBG_STANDBY_R {
                DBG_STANDBY_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 5 - Trace port and clock enable
            #[inline(always)]
            pub fn trace_ioen(&self) -> TRACE_IOEN_R {
                TRACE_IOEN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 28 - External trigger output enable
            #[inline(always)]
            pub fn trgoen(&self) -> TRGOEN_R {
                TRGOEN_R::new(((self.bits >> 28) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Debug Sleep Mode
            #[inline(always)]
            pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W {
                DBG_SLEEP_W { w: self }
            }
            ///Bit 1 - Debug Stop Mode
            #[inline(always)]
            pub fn dbg_stop(&mut self) -> DBG_STOP_W {
                DBG_STOP_W { w: self }
            }
            ///Bit 2 - Debug Standby Mode
            #[inline(always)]
            pub fn dbg_standby(&mut self) -> DBG_STANDBY_W {
                DBG_STANDBY_W { w: self }
            }
            ///Bit 5 - Trace port and clock enable
            #[inline(always)]
            pub fn trace_ioen(&mut self) -> TRACE_IOEN_W {
                TRACE_IOEN_W { w: self }
            }
            ///Bit 28 - External trigger output enable
            #[inline(always)]
            pub fn trgoen(&mut self) -> TRGOEN_W {
                TRGOEN_W { w: self }
            }
        }
    }
    ///APB1 Low Freeze Register CPU1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1fzr1](apb1fzr1) module
    pub type APB1FZR1 = crate::Reg<u32, _APB1FZR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1FZR1;
    ///`read()` method returns [apb1fzr1::R](apb1fzr1::R) reader structure
    impl crate::Readable for APB1FZR1 {}
    ///`write(|w| ..)` method takes [apb1fzr1::W](apb1fzr1::W) writer structure
    impl crate::Writable for APB1FZR1 {}
    ///APB1 Low Freeze Register CPU1
    pub mod apb1fzr1 {
        ///Reader of register APB1FZR1
        pub type R = crate::R<u32, super::APB1FZR1>;
        ///Writer for register APB1FZR1
        pub type W = crate::W<u32, super::APB1FZR1>;
        ///Register APB1FZR1 `reset()`'s with value 0
        impl crate::ResetValue for super::APB1FZR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBG_TIMER2_STOP`
        pub type DBG_TIMER2_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_TIMER2_STOP`
        pub struct DBG_TIMER2_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_TIMER2_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `DBG_RTC_STOP`
        pub type DBG_RTC_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_RTC_STOP`
        pub struct DBG_RTC_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_RTC_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `DBG_WWDG_STOP`
        pub type DBG_WWDG_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_WWDG_STOP`
        pub struct DBG_WWDG_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_WWDG_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `DBG_IWDG_STOP`
        pub type DBG_IWDG_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_IWDG_STOP`
        pub struct DBG_IWDG_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_IWDG_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DBG_I2C1_STOP`
        pub type DBG_I2C1_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_I2C1_STOP`
        pub struct DBG_I2C1_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_I2C1_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `DBG_I2C3_STOP`
        pub type DBG_I2C3_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_I2C3_STOP`
        pub struct DBG_I2C3_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_I2C3_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `DBG_LPTIM1_STOP`
        pub type DBG_LPTIM1_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_LPTIM1_STOP`
        pub struct DBG_LPTIM1_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_LPTIM1_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Debug Timer 2 stopped when Core is halted
            #[inline(always)]
            pub fn dbg_timer2_stop(&self) -> DBG_TIMER2_STOP_R {
                DBG_TIMER2_STOP_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 10 - RTC counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R {
                DBG_RTC_STOP_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - WWDG counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
                DBG_WWDG_STOP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - IWDG counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
                DBG_IWDG_STOP_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 21 - Debug I2C1 SMBUS timeout stopped when Core is halted
            #[inline(always)]
            pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R {
                DBG_I2C1_STOP_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 23 - Debug I2C3 SMBUS timeout stopped when core is halted
            #[inline(always)]
            pub fn dbg_i2c3_stop(&self) -> DBG_I2C3_STOP_R {
                DBG_I2C3_STOP_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 31 - Debug LPTIM1 stopped when Core is halted
            #[inline(always)]
            pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R {
                DBG_LPTIM1_STOP_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Debug Timer 2 stopped when Core is halted
            #[inline(always)]
            pub fn dbg_timer2_stop(&mut self) -> DBG_TIMER2_STOP_W {
                DBG_TIMER2_STOP_W { w: self }
            }
            ///Bit 10 - RTC counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W {
                DBG_RTC_STOP_W { w: self }
            }
            ///Bit 11 - WWDG counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W {
                DBG_WWDG_STOP_W { w: self }
            }
            ///Bit 12 - IWDG counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W {
                DBG_IWDG_STOP_W { w: self }
            }
            ///Bit 21 - Debug I2C1 SMBUS timeout stopped when Core is halted
            #[inline(always)]
            pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W {
                DBG_I2C1_STOP_W { w: self }
            }
            ///Bit 23 - Debug I2C3 SMBUS timeout stopped when core is halted
            #[inline(always)]
            pub fn dbg_i2c3_stop(&mut self) -> DBG_I2C3_STOP_W {
                DBG_I2C3_STOP_W { w: self }
            }
            ///Bit 31 - Debug LPTIM1 stopped when Core is halted
            #[inline(always)]
            pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W {
                DBG_LPTIM1_STOP_W { w: self }
            }
        }
    }
    ///APB1 Low Freeze Register CPU2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2ap_b1fzr1](c2ap_b1fzr1) module
    pub type C2AP_B1FZR1 = crate::Reg<u32, _C2AP_B1FZR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2AP_B1FZR1;
    ///`read()` method returns [c2ap_b1fzr1::R](c2ap_b1fzr1::R) reader structure
    impl crate::Readable for C2AP_B1FZR1 {}
    ///`write(|w| ..)` method takes [c2ap_b1fzr1::W](c2ap_b1fzr1::W) writer structure
    impl crate::Writable for C2AP_B1FZR1 {}
    ///APB1 Low Freeze Register CPU2
    pub mod c2ap_b1fzr1 {
        ///Reader of register C2AP_B1FZR1
        pub type R = crate::R<u32, super::C2AP_B1FZR1>;
        ///Writer for register C2AP_B1FZR1
        pub type W = crate::W<u32, super::C2AP_B1FZR1>;
        ///Register C2AP_B1FZR1 `reset()`'s with value 0
        impl crate::ResetValue for super::C2AP_B1FZR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBG_LPTIM2_STOP`
        pub type DBG_LPTIM2_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_LPTIM2_STOP`
        pub struct DBG_LPTIM2_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_LPTIM2_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `DBG_RTC_STOP`
        pub type DBG_RTC_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_RTC_STOP`
        pub struct DBG_RTC_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_RTC_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `DBG_IWDG_STOP`
        pub type DBG_IWDG_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_IWDG_STOP`
        pub struct DBG_IWDG_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_IWDG_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `DBG_I2C1_STOP`
        pub type DBG_I2C1_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_I2C1_STOP`
        pub struct DBG_I2C1_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_I2C1_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `DBG_I2C3_STOP`
        pub type DBG_I2C3_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_I2C3_STOP`
        pub struct DBG_I2C3_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_I2C3_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `DBG_LPTIM1_STOP`
        pub type DBG_LPTIM1_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_LPTIM1_STOP`
        pub struct DBG_LPTIM1_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_LPTIM1_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bit 0 - LPTIM2 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R {
                DBG_LPTIM2_STOP_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 10 - RTC counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R {
                DBG_RTC_STOP_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 12 - IWDG stopped when core is halted
            #[inline(always)]
            pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
                DBG_IWDG_STOP_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 21 - I2C1 SMBUS timeout stopped when core is halted
            #[inline(always)]
            pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R {
                DBG_I2C1_STOP_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 23 - I2C3 SMBUS timeout stopped when core is halted
            #[inline(always)]
            pub fn dbg_i2c3_stop(&self) -> DBG_I2C3_STOP_R {
                DBG_I2C3_STOP_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 31 - LPTIM1 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R {
                DBG_LPTIM1_STOP_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - LPTIM2 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W {
                DBG_LPTIM2_STOP_W { w: self }
            }
            ///Bit 10 - RTC counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W {
                DBG_RTC_STOP_W { w: self }
            }
            ///Bit 12 - IWDG stopped when core is halted
            #[inline(always)]
            pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W {
                DBG_IWDG_STOP_W { w: self }
            }
            ///Bit 21 - I2C1 SMBUS timeout stopped when core is halted
            #[inline(always)]
            pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W {
                DBG_I2C1_STOP_W { w: self }
            }
            ///Bit 23 - I2C3 SMBUS timeout stopped when core is halted
            #[inline(always)]
            pub fn dbg_i2c3_stop(&mut self) -> DBG_I2C3_STOP_W {
                DBG_I2C3_STOP_W { w: self }
            }
            ///Bit 31 - LPTIM1 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W {
                DBG_LPTIM1_STOP_W { w: self }
            }
        }
    }
    ///APB1 High Freeze Register CPU1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb1fzr2](apb1fzr2) module
    pub type APB1FZR2 = crate::Reg<u32, _APB1FZR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB1FZR2;
    ///`read()` method returns [apb1fzr2::R](apb1fzr2::R) reader structure
    impl crate::Readable for APB1FZR2 {}
    ///`write(|w| ..)` method takes [apb1fzr2::W](apb1fzr2::W) writer structure
    impl crate::Writable for APB1FZR2 {}
    ///APB1 High Freeze Register CPU1
    pub mod apb1fzr2 {
        ///Reader of register APB1FZR2
        pub type R = crate::R<u32, super::APB1FZR2>;
        ///Writer for register APB1FZR2
        pub type W = crate::W<u32, super::APB1FZR2>;
        ///Register APB1FZR2 `reset()`'s with value 0
        impl crate::ResetValue for super::APB1FZR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBG_LPTIM2_STOP`
        pub type DBG_LPTIM2_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_LPTIM2_STOP`
        pub struct DBG_LPTIM2_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_LPTIM2_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        impl R {
            ///Bit 5 - LPTIM2 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R {
                DBG_LPTIM2_STOP_R::new(((self.bits >> 5) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 5 - LPTIM2 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W {
                DBG_LPTIM2_STOP_W { w: self }
            }
        }
    }
    ///APB1 High Freeze Register CPU2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb1fzr2](c2apb1fzr2) module
    pub type C2APB1FZR2 = crate::Reg<u32, _C2APB1FZR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB1FZR2;
    ///`read()` method returns [c2apb1fzr2::R](c2apb1fzr2::R) reader structure
    impl crate::Readable for C2APB1FZR2 {}
    ///`write(|w| ..)` method takes [c2apb1fzr2::W](c2apb1fzr2::W) writer structure
    impl crate::Writable for C2APB1FZR2 {}
    ///APB1 High Freeze Register CPU2
    pub mod c2apb1fzr2 {
        ///Reader of register C2APB1FZR2
        pub type R = crate::R<u32, super::C2APB1FZR2>;
        ///Writer for register C2APB1FZR2
        pub type W = crate::W<u32, super::C2APB1FZR2>;
        ///Register C2APB1FZR2 `reset()`'s with value 0
        impl crate::ResetValue for super::C2APB1FZR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBG_LPTIM2_STOP`
        pub type DBG_LPTIM2_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_LPTIM2_STOP`
        pub struct DBG_LPTIM2_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_LPTIM2_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        impl R {
            ///Bit 5 - LPTIM2 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R {
                DBG_LPTIM2_STOP_R::new(((self.bits >> 5) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 5 - LPTIM2 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W {
                DBG_LPTIM2_STOP_W { w: self }
            }
        }
    }
    ///APB2 Freeze Register CPU1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [apb2fzr](apb2fzr) module
    pub type APB2FZR = crate::Reg<u32, _APB2FZR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _APB2FZR;
    ///`read()` method returns [apb2fzr::R](apb2fzr::R) reader structure
    impl crate::Readable for APB2FZR {}
    ///`write(|w| ..)` method takes [apb2fzr::W](apb2fzr::W) writer structure
    impl crate::Writable for APB2FZR {}
    ///APB2 Freeze Register CPU1
    pub mod apb2fzr {
        ///Reader of register APB2FZR
        pub type R = crate::R<u32, super::APB2FZR>;
        ///Writer for register APB2FZR
        pub type W = crate::W<u32, super::APB2FZR>;
        ///Register APB2FZR `reset()`'s with value 0
        impl crate::ResetValue for super::APB2FZR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBG_TIM1_STOP`
        pub type DBG_TIM1_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_TIM1_STOP`
        pub struct DBG_TIM1_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_TIM1_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `DBG_TIM16_STOP`
        pub type DBG_TIM16_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_TIM16_STOP`
        pub struct DBG_TIM16_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_TIM16_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `DBG_TIM17_STOP`
        pub type DBG_TIM17_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_TIM17_STOP`
        pub struct DBG_TIM17_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_TIM17_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        impl R {
            ///Bit 11 - TIM1 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R {
                DBG_TIM1_STOP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 17 - TIM16 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R {
                DBG_TIM16_STOP_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - TIM17 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R {
                DBG_TIM17_STOP_R::new(((self.bits >> 18) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 11 - TIM1 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W {
                DBG_TIM1_STOP_W { w: self }
            }
            ///Bit 17 - TIM16 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W {
                DBG_TIM16_STOP_W { w: self }
            }
            ///Bit 18 - TIM17 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W {
                DBG_TIM17_STOP_W { w: self }
            }
        }
    }
    ///APB2 Freeze Register CPU2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2apb2fzr](c2apb2fzr) module
    pub type C2APB2FZR = crate::Reg<u32, _C2APB2FZR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2APB2FZR;
    ///`read()` method returns [c2apb2fzr::R](c2apb2fzr::R) reader structure
    impl crate::Readable for C2APB2FZR {}
    ///`write(|w| ..)` method takes [c2apb2fzr::W](c2apb2fzr::W) writer structure
    impl crate::Writable for C2APB2FZR {}
    ///APB2 Freeze Register CPU2
    pub mod c2apb2fzr {
        ///Reader of register C2APB2FZR
        pub type R = crate::R<u32, super::C2APB2FZR>;
        ///Writer for register C2APB2FZR
        pub type W = crate::W<u32, super::C2APB2FZR>;
        ///Register C2APB2FZR `reset()`'s with value 0
        impl crate::ResetValue for super::C2APB2FZR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DBG_TIM1_STOP`
        pub type DBG_TIM1_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_TIM1_STOP`
        pub struct DBG_TIM1_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_TIM1_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `DBG_TIM16_STOP`
        pub type DBG_TIM16_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_TIM16_STOP`
        pub struct DBG_TIM16_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_TIM16_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `DBG_TIM17_STOP`
        pub type DBG_TIM17_STOP_R = crate::R<bool, bool>;
        ///Write proxy for field `DBG_TIM17_STOP`
        pub struct DBG_TIM17_STOP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DBG_TIM17_STOP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        impl R {
            ///Bit 11 - TIM1 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R {
                DBG_TIM1_STOP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 17 - TIM16 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R {
                DBG_TIM16_STOP_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - TIM17 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R {
                DBG_TIM17_STOP_R::new(((self.bits >> 18) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 11 - TIM1 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W {
                DBG_TIM1_STOP_W { w: self }
            }
            ///Bit 17 - TIM16 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W {
                DBG_TIM16_STOP_W { w: self }
            }
            ///Bit 18 - TIM17 counter stopped when core is halted
            #[inline(always)]
            pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W {
                DBG_TIM17_STOP_W { w: self }
            }
        }
    }
}
///PKA
pub struct PKA {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PKA {}
impl PKA {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const pka::RegisterBlock {
        0x5800_2000 as *const _
    }
}
impl Deref for PKA {
    type Target = pka::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*PKA::ptr() }
    }
}
///PKA
pub mod pka {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Control register
        pub cr: CR,
        ///0x04 - PKA status register
        pub sr: SR,
        ///0x08 - PKA clear flag register
        pub clrfr: CLRFR,
        _reserved3: [u8; 8168usize],
        ///0x1ff4 - PKA version register
        pub verr: VERR,
        ///0x1ff8 - PKA identification register
        pub ipidr: IPIDR,
        ///0x1ffc - PKA size ID register
        pub sidr: SIDR,
    }
    ///Control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///Control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDRERRIE`
        pub type ADDRERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ADDRERRIE`
        pub struct ADDRERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDRERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `RAMERRIE`
        pub type RAMERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RAMERRIE`
        pub struct RAMERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RAMERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `PROCENDIE`
        pub type PROCENDIE_R = crate::R<bool, bool>;
        ///Write proxy for field `PROCENDIE`
        pub struct PROCENDIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCENDIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `MODE`
        pub type MODE_R = crate::R<u8, u8>;
        ///Write proxy for field `MODE`
        pub struct MODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> MODE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x3f << 8)) | (((value as u32) & 0x3f) << 8);
                self.w
            }
        }
        ///Reader of field `SECLVL`
        pub type SECLVL_R = crate::R<bool, bool>;
        ///Write proxy for field `SECLVL`
        pub struct SECLVL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SECLVL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `START`
        pub type START_R = crate::R<bool, bool>;
        ///Write proxy for field `START`
        pub struct START_W<'a> {
            w: &'a mut W,
        }
        impl<'a> START_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `EN`
        pub type EN_R = crate::R<bool, bool>;
        ///Write proxy for field `EN`
        pub struct EN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 20 - Address error interrupt enable
            #[inline(always)]
            pub fn addrerrie(&self) -> ADDRERRIE_R {
                ADDRERRIE_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - RAM error interrupt enable
            #[inline(always)]
            pub fn ramerrie(&self) -> RAMERRIE_R {
                RAMERRIE_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 17 - End of operation interrupt enable
            #[inline(always)]
            pub fn procendie(&self) -> PROCENDIE_R {
                PROCENDIE_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bits 8:13 - PKA Operation Mode
            #[inline(always)]
            pub fn mode(&self) -> MODE_R {
                MODE_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
            ///Bit 2 - Security Enable
            #[inline(always)]
            pub fn seclvl(&self) -> SECLVL_R {
                SECLVL_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - Start the operation
            #[inline(always)]
            pub fn start(&self) -> START_R {
                START_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - Peripheral Enable
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 20 - Address error interrupt enable
            #[inline(always)]
            pub fn addrerrie(&mut self) -> ADDRERRIE_W {
                ADDRERRIE_W { w: self }
            }
            ///Bit 19 - RAM error interrupt enable
            #[inline(always)]
            pub fn ramerrie(&mut self) -> RAMERRIE_W {
                RAMERRIE_W { w: self }
            }
            ///Bit 17 - End of operation interrupt enable
            #[inline(always)]
            pub fn procendie(&mut self) -> PROCENDIE_W {
                PROCENDIE_W { w: self }
            }
            ///Bits 8:13 - PKA Operation Mode
            #[inline(always)]
            pub fn mode(&mut self) -> MODE_W {
                MODE_W { w: self }
            }
            ///Bit 2 - Security Enable
            #[inline(always)]
            pub fn seclvl(&mut self) -> SECLVL_W {
                SECLVL_W { w: self }
            }
            ///Bit 1 - Start the operation
            #[inline(always)]
            pub fn start(&mut self) -> START_W {
                START_W { w: self }
            }
            ///Bit 0 - Peripheral Enable
            #[inline(always)]
            pub fn en(&mut self) -> EN_W {
                EN_W { w: self }
            }
        }
    }
    ///PKA status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sr](sr) module
    pub type SR = crate::Reg<u32, _SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SR;
    ///`read()` method returns [sr::R](sr::R) reader structure
    impl crate::Readable for SR {}
    ///PKA status register
    pub mod sr {
        ///Reader of register SR
        pub type R = crate::R<u32, super::SR>;
        ///Reader of field `ADDRERRF`
        pub type ADDRERRF_R = crate::R<bool, bool>;
        ///Reader of field `RAMERRF`
        pub type RAMERRF_R = crate::R<bool, bool>;
        ///Reader of field `PROCENDF`
        pub type PROCENDF_R = crate::R<bool, bool>;
        ///Reader of field `BUSY`
        pub type BUSY_R = crate::R<bool, bool>;
        impl R {
            ///Bit 20 - Address error flag
            #[inline(always)]
            pub fn addrerrf(&self) -> ADDRERRF_R {
                ADDRERRF_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - RAM error flag
            #[inline(always)]
            pub fn ramerrf(&self) -> RAMERRF_R {
                RAMERRF_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 17 - PKA End of Operation flag
            #[inline(always)]
            pub fn procendf(&self) -> PROCENDF_R {
                PROCENDF_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - PKA Operation in progress
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 16) & 0x01) != 0)
            }
        }
    }
    ///PKA clear flag register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [clrfr](clrfr) module
    pub type CLRFR = crate::Reg<u32, _CLRFR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CLRFR;
    ///`read()` method returns [clrfr::R](clrfr::R) reader structure
    impl crate::Readable for CLRFR {}
    ///`write(|w| ..)` method takes [clrfr::W](clrfr::W) writer structure
    impl crate::Writable for CLRFR {}
    ///PKA clear flag register
    pub mod clrfr {
        ///Reader of register CLRFR
        pub type R = crate::R<u32, super::CLRFR>;
        ///Writer for register CLRFR
        pub type W = crate::W<u32, super::CLRFR>;
        ///Register CLRFR `reset()`'s with value 0
        impl crate::ResetValue for super::CLRFR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDRERRFC`
        pub type ADDRERRFC_R = crate::R<bool, bool>;
        ///Write proxy for field `ADDRERRFC`
        pub struct ADDRERRFC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDRERRFC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `RAMERRFC`
        pub type RAMERRFC_R = crate::R<bool, bool>;
        ///Write proxy for field `RAMERRFC`
        pub struct RAMERRFC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RAMERRFC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `PROCENDFC`
        pub type PROCENDFC_R = crate::R<bool, bool>;
        ///Write proxy for field `PROCENDFC`
        pub struct PROCENDFC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PROCENDFC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        impl R {
            ///Bit 20 - Clear Address error flag
            #[inline(always)]
            pub fn addrerrfc(&self) -> ADDRERRFC_R {
                ADDRERRFC_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - Clear RAM error flag
            #[inline(always)]
            pub fn ramerrfc(&self) -> RAMERRFC_R {
                RAMERRFC_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 17 - Clear PKA End of Operation flag
            #[inline(always)]
            pub fn procendfc(&self) -> PROCENDFC_R {
                PROCENDFC_R::new(((self.bits >> 17) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 20 - Clear Address error flag
            #[inline(always)]
            pub fn addrerrfc(&mut self) -> ADDRERRFC_W {
                ADDRERRFC_W { w: self }
            }
            ///Bit 19 - Clear RAM error flag
            #[inline(always)]
            pub fn ramerrfc(&mut self) -> RAMERRFC_W {
                RAMERRFC_W { w: self }
            }
            ///Bit 17 - Clear PKA End of Operation flag
            #[inline(always)]
            pub fn procendfc(&mut self) -> PROCENDFC_W {
                PROCENDFC_W { w: self }
            }
        }
    }
    ///PKA version register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [verr](verr) module
    pub type VERR = crate::Reg<u32, _VERR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _VERR;
    ///`read()` method returns [verr::R](verr::R) reader structure
    impl crate::Readable for VERR {}
    ///PKA version register
    pub mod verr {
        ///Reader of register VERR
        pub type R = crate::R<u32, super::VERR>;
        ///Reader of field `MINREV`
        pub type MINREV_R = crate::R<u8, u8>;
        ///Reader of field `MAJREV`
        pub type MAJREV_R = crate::R<u8, u8>;
        impl R {
            ///Bits 0:3 - Minor revision
            #[inline(always)]
            pub fn minrev(&self) -> MINREV_R {
                MINREV_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:7 - Major revision
            #[inline(always)]
            pub fn majrev(&self) -> MAJREV_R {
                MAJREV_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
        }
    }
    ///PKA identification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ipidr](ipidr) module
    pub type IPIDR = crate::Reg<u32, _IPIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IPIDR;
    ///`read()` method returns [ipidr::R](ipidr::R) reader structure
    impl crate::Readable for IPIDR {}
    ///PKA identification register
    pub mod ipidr {
        ///Reader of register IPIDR
        pub type R = crate::R<u32, super::IPIDR>;
        ///Reader of field `ID`
        pub type ID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Identification Code
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///PKA size ID register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sidr](sidr) module
    pub type SIDR = crate::Reg<u32, _SIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SIDR;
    ///`read()` method returns [sidr::R](sidr::R) reader structure
    impl crate::Readable for SIDR {}
    ///PKA size ID register
    pub mod sidr {
        ///Reader of register SIDR
        pub type R = crate::R<u32, super::SIDR>;
        ///Reader of field `SID`
        pub type SID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Side Identification Code
            #[inline(always)]
            pub fn sid(&self) -> SID_R {
                SID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
}
///IPCC
pub struct IPCC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for IPCC {}
impl IPCC {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const ipcc::RegisterBlock {
        0x5800_0c00 as *const _
    }
}
impl Deref for IPCC {
    type Target = ipcc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*IPCC::ptr() }
    }
}
///IPCC
pub mod ipcc {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Control register CPU1
        pub c1cr: C1CR,
        ///0x04 - Mask register CPU1
        pub c1mr: C1MR,
        ///0x08 - Status Set or Clear register CPU1
        pub c1scr: C1SCR,
        ///0x0c - CPU1 to CPU2 status register
        pub c1toc2sr: C1TOC2SR,
        ///0x10 - Control register CPU2
        pub c2cr: C2CR,
        ///0x14 - Mask register CPU2
        pub c2mr: C2MR,
        ///0x18 - Status Set or Clear register CPU2
        pub c2scr: C2SCR,
        ///0x1c - CPU2 to CPU1 status register
        pub c2toc1sr: C2TOC1SR,
        _reserved8: [u8; 976usize],
        ///0x3f0 - IPCC Hardware configuration register
        pub hwcfgr: HWCFGR,
        ///0x3f4 - IPCC version register
        pub verr: VERR,
        ///0x3f8 - IPCC indentification register
        pub ipidr: IPIDR,
        ///0x3fc - IPCC size indentification register
        pub sidr: SIDR,
    }
    ///Control register CPU1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1cr](c1cr) module
    pub type C1CR = crate::Reg<u32, _C1CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1CR;
    ///`read()` method returns [c1cr::R](c1cr::R) reader structure
    impl crate::Readable for C1CR {}
    ///`write(|w| ..)` method takes [c1cr::W](c1cr::W) writer structure
    impl crate::Writable for C1CR {}
    ///Control register CPU1
    pub mod c1cr {
        ///Reader of register C1CR
        pub type R = crate::R<u32, super::C1CR>;
        ///Writer for register C1CR
        pub type W = crate::W<u32, super::C1CR>;
        ///Register C1CR `reset()`'s with value 0
        impl crate::ResetValue for super::C1CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TXFIE`
        pub type TXFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXFIE`
        pub struct TXFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `RXOIE`
        pub type RXOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RXOIE`
        pub struct RXOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - processor 1 Transmit channel free interrupt enable
            #[inline(always)]
            pub fn txfie(&self) -> TXFIE_R {
                TXFIE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 0 - processor 1 Receive channel occupied interrupt enable
            #[inline(always)]
            pub fn rxoie(&self) -> RXOIE_R {
                RXOIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - processor 1 Transmit channel free interrupt enable
            #[inline(always)]
            pub fn txfie(&mut self) -> TXFIE_W {
                TXFIE_W { w: self }
            }
            ///Bit 0 - processor 1 Receive channel occupied interrupt enable
            #[inline(always)]
            pub fn rxoie(&mut self) -> RXOIE_W {
                RXOIE_W { w: self }
            }
        }
    }
    ///Mask register CPU1
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1mr](c1mr) module
    pub type C1MR = crate::Reg<u32, _C1MR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1MR;
    ///`read()` method returns [c1mr::R](c1mr::R) reader structure
    impl crate::Readable for C1MR {}
    ///`write(|w| ..)` method takes [c1mr::W](c1mr::W) writer structure
    impl crate::Writable for C1MR {}
    ///Mask register CPU1
    pub mod c1mr {
        ///Reader of register C1MR
        pub type R = crate::R<u32, super::C1MR>;
        ///Writer for register C1MR
        pub type W = crate::W<u32, super::C1MR>;
        ///Register C1MR `reset()`'s with value 0xffff_ffff
        impl crate::ResetValue for super::C1MR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_ffff
            }
        }
        ///Reader of field `CH6FM`
        pub type CH6FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH6FM`
        pub struct CH6FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `CH5FM`
        pub type CH5FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH5FM`
        pub struct CH5FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `CH4FM`
        pub type CH4FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH4FM`
        pub struct CH4FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `CH3FM`
        pub type CH3FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH3FM`
        pub struct CH3FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `CH2FM`
        pub type CH2FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH2FM`
        pub struct CH2FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `CH1FM`
        pub type CH1FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH1FM`
        pub struct CH1FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CH6OM`
        pub type CH6OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH6OM`
        pub struct CH6OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `CH5OM`
        pub type CH5OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH5OM`
        pub struct CH5OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CH4OM`
        pub type CH4OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH4OM`
        pub struct CH4OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CH3OM`
        pub type CH3OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH3OM`
        pub struct CH3OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CH2OM`
        pub type CH2OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH2OM`
        pub struct CH2OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CH1OM`
        pub type CH1OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH1OM`
        pub struct CH1OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 21 - processor 1 Transmit channel 6 free interrupt mask
            #[inline(always)]
            pub fn ch6fm(&self) -> CH6FM_R {
                CH6FM_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - processor 1 Transmit channel 5 free interrupt mask
            #[inline(always)]
            pub fn ch5fm(&self) -> CH5FM_R {
                CH5FM_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - processor 1 Transmit channel 4 free interrupt mask
            #[inline(always)]
            pub fn ch4fm(&self) -> CH4FM_R {
                CH4FM_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - processor 1 Transmit channel 3 free interrupt mask
            #[inline(always)]
            pub fn ch3fm(&self) -> CH3FM_R {
                CH3FM_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - processor 1 Transmit channel 2 free interrupt mask
            #[inline(always)]
            pub fn ch2fm(&self) -> CH2FM_R {
                CH2FM_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - processor 1 Transmit channel 1 free interrupt mask
            #[inline(always)]
            pub fn ch1fm(&self) -> CH1FM_R {
                CH1FM_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 5 - processor 1 Receive channel 6 occupied interrupt enable
            #[inline(always)]
            pub fn ch6om(&self) -> CH6OM_R {
                CH6OM_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - processor 1 Receive channel 5 occupied interrupt enable
            #[inline(always)]
            pub fn ch5om(&self) -> CH5OM_R {
                CH5OM_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - processor 1 Receive channel 4 occupied interrupt enable
            #[inline(always)]
            pub fn ch4om(&self) -> CH4OM_R {
                CH4OM_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - processor 1 Receive channel 3 occupied interrupt enable
            #[inline(always)]
            pub fn ch3om(&self) -> CH3OM_R {
                CH3OM_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - processor 1 Receive channel 2 occupied interrupt enable
            #[inline(always)]
            pub fn ch2om(&self) -> CH2OM_R {
                CH2OM_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - processor 1 Receive channel 1 occupied interrupt enable
            #[inline(always)]
            pub fn ch1om(&self) -> CH1OM_R {
                CH1OM_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 21 - processor 1 Transmit channel 6 free interrupt mask
            #[inline(always)]
            pub fn ch6fm(&mut self) -> CH6FM_W {
                CH6FM_W { w: self }
            }
            ///Bit 20 - processor 1 Transmit channel 5 free interrupt mask
            #[inline(always)]
            pub fn ch5fm(&mut self) -> CH5FM_W {
                CH5FM_W { w: self }
            }
            ///Bit 19 - processor 1 Transmit channel 4 free interrupt mask
            #[inline(always)]
            pub fn ch4fm(&mut self) -> CH4FM_W {
                CH4FM_W { w: self }
            }
            ///Bit 18 - processor 1 Transmit channel 3 free interrupt mask
            #[inline(always)]
            pub fn ch3fm(&mut self) -> CH3FM_W {
                CH3FM_W { w: self }
            }
            ///Bit 17 - processor 1 Transmit channel 2 free interrupt mask
            #[inline(always)]
            pub fn ch2fm(&mut self) -> CH2FM_W {
                CH2FM_W { w: self }
            }
            ///Bit 16 - processor 1 Transmit channel 1 free interrupt mask
            #[inline(always)]
            pub fn ch1fm(&mut self) -> CH1FM_W {
                CH1FM_W { w: self }
            }
            ///Bit 5 - processor 1 Receive channel 6 occupied interrupt enable
            #[inline(always)]
            pub fn ch6om(&mut self) -> CH6OM_W {
                CH6OM_W { w: self }
            }
            ///Bit 4 - processor 1 Receive channel 5 occupied interrupt enable
            #[inline(always)]
            pub fn ch5om(&mut self) -> CH5OM_W {
                CH5OM_W { w: self }
            }
            ///Bit 3 - processor 1 Receive channel 4 occupied interrupt enable
            #[inline(always)]
            pub fn ch4om(&mut self) -> CH4OM_W {
                CH4OM_W { w: self }
            }
            ///Bit 2 - processor 1 Receive channel 3 occupied interrupt enable
            #[inline(always)]
            pub fn ch3om(&mut self) -> CH3OM_W {
                CH3OM_W { w: self }
            }
            ///Bit 1 - processor 1 Receive channel 2 occupied interrupt enable
            #[inline(always)]
            pub fn ch2om(&mut self) -> CH2OM_W {
                CH2OM_W { w: self }
            }
            ///Bit 0 - processor 1 Receive channel 1 occupied interrupt enable
            #[inline(always)]
            pub fn ch1om(&mut self) -> CH1OM_W {
                CH1OM_W { w: self }
            }
        }
    }
    ///Status Set or Clear register CPU1
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1scr](c1scr) module
    pub type C1SCR = crate::Reg<u32, _C1SCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1SCR;
    ///`write(|w| ..)` method takes [c1scr::W](c1scr::W) writer structure
    impl crate::Writable for C1SCR {}
    ///Status Set or Clear register CPU1
    pub mod c1scr {
        ///Writer for register C1SCR
        pub type W = crate::W<u32, super::C1SCR>;
        ///Register C1SCR `reset()`'s with value 0
        impl crate::ResetValue for super::C1SCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `CH6S`
        pub struct CH6S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `CH5S`
        pub struct CH5S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `CH4S`
        pub struct CH4S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `CH3S`
        pub struct CH3S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `CH2S`
        pub struct CH2S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `CH1S`
        pub struct CH1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `CH6C`
        pub struct CH6C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `CH5C`
        pub struct CH5C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CH4C`
        pub struct CH4C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CH3C`
        pub struct CH3C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CH2C`
        pub struct CH2C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CH1C`
        pub struct CH1C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 21 - processor 1 Transmit channel 6 status set
            #[inline(always)]
            pub fn ch6s(&mut self) -> CH6S_W {
                CH6S_W { w: self }
            }
            ///Bit 20 - processor 1 Transmit channel 5 status set
            #[inline(always)]
            pub fn ch5s(&mut self) -> CH5S_W {
                CH5S_W { w: self }
            }
            ///Bit 19 - processor 1 Transmit channel 4 status set
            #[inline(always)]
            pub fn ch4s(&mut self) -> CH4S_W {
                CH4S_W { w: self }
            }
            ///Bit 18 - processor 1 Transmit channel 3 status set
            #[inline(always)]
            pub fn ch3s(&mut self) -> CH3S_W {
                CH3S_W { w: self }
            }
            ///Bit 17 - processor 1 Transmit channel 2 status set
            #[inline(always)]
            pub fn ch2s(&mut self) -> CH2S_W {
                CH2S_W { w: self }
            }
            ///Bit 16 - processor 1 Transmit channel 1 status set
            #[inline(always)]
            pub fn ch1s(&mut self) -> CH1S_W {
                CH1S_W { w: self }
            }
            ///Bit 5 - processor 1 Receive channel 6 status clear
            #[inline(always)]
            pub fn ch6c(&mut self) -> CH6C_W {
                CH6C_W { w: self }
            }
            ///Bit 4 - processor 1 Receive channel 5 status clear
            #[inline(always)]
            pub fn ch5c(&mut self) -> CH5C_W {
                CH5C_W { w: self }
            }
            ///Bit 3 - processor 1 Receive channel 4 status clear
            #[inline(always)]
            pub fn ch4c(&mut self) -> CH4C_W {
                CH4C_W { w: self }
            }
            ///Bit 2 - processor 1 Receive channel 3 status clear
            #[inline(always)]
            pub fn ch3c(&mut self) -> CH3C_W {
                CH3C_W { w: self }
            }
            ///Bit 1 - processor 1 Receive channel 2 status clear
            #[inline(always)]
            pub fn ch2c(&mut self) -> CH2C_W {
                CH2C_W { w: self }
            }
            ///Bit 0 - processor 1 Receive channel 1 status clear
            #[inline(always)]
            pub fn ch1c(&mut self) -> CH1C_W {
                CH1C_W { w: self }
            }
        }
    }
    ///CPU1 to CPU2 status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1toc2sr](c1toc2sr) module
    pub type C1TOC2SR = crate::Reg<u32, _C1TOC2SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1TOC2SR;
    ///`read()` method returns [c1toc2sr::R](c1toc2sr::R) reader structure
    impl crate::Readable for C1TOC2SR {}
    ///CPU1 to CPU2 status register
    pub mod c1toc2sr {
        ///Reader of register C1TOC2SR
        pub type R = crate::R<u32, super::C1TOC2SR>;
        ///Reader of field `CH6F`
        pub type CH6F_R = crate::R<bool, bool>;
        ///Reader of field `CH5F`
        pub type CH5F_R = crate::R<bool, bool>;
        ///Reader of field `CH4F`
        pub type CH4F_R = crate::R<bool, bool>;
        ///Reader of field `CH3F`
        pub type CH3F_R = crate::R<bool, bool>;
        ///Reader of field `CH2F`
        pub type CH2F_R = crate::R<bool, bool>;
        ///Reader of field `CH1F`
        pub type CH1F_R = crate::R<bool, bool>;
        impl R {
            ///Bit 5 - processor 1 transmit to process 2 Receive channel 6 status flag
            #[inline(always)]
            pub fn ch6f(&self) -> CH6F_R {
                CH6F_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - processor 1 transmit to process 2 Receive channel 5 status flag
            #[inline(always)]
            pub fn ch5f(&self) -> CH5F_R {
                CH5F_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - processor 1 transmit to process 2 Receive channel 4 status flag
            #[inline(always)]
            pub fn ch4f(&self) -> CH4F_R {
                CH4F_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - processor 1 transmit to process 2 Receive channel 3 status flag
            #[inline(always)]
            pub fn ch3f(&self) -> CH3F_R {
                CH3F_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - processor 1 transmit to process 2 Receive channel 2 status flag
            #[inline(always)]
            pub fn ch2f(&self) -> CH2F_R {
                CH2F_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - processor 1 transmit to process 2 Receive channel 1 status flag
            #[inline(always)]
            pub fn ch1f(&self) -> CH1F_R {
                CH1F_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///Control register CPU2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2cr](c2cr) module
    pub type C2CR = crate::Reg<u32, _C2CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2CR;
    ///`read()` method returns [c2cr::R](c2cr::R) reader structure
    impl crate::Readable for C2CR {}
    ///`write(|w| ..)` method takes [c2cr::W](c2cr::W) writer structure
    impl crate::Writable for C2CR {}
    ///Control register CPU2
    pub mod c2cr {
        ///Reader of register C2CR
        pub type R = crate::R<u32, super::C2CR>;
        ///Writer for register C2CR
        pub type W = crate::W<u32, super::C2CR>;
        ///Register C2CR `reset()`'s with value 0
        impl crate::ResetValue for super::C2CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TXFIE`
        pub type TXFIE_R = crate::R<bool, bool>;
        ///Write proxy for field `TXFIE`
        pub struct TXFIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TXFIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `RXOIE`
        pub type RXOIE_R = crate::R<bool, bool>;
        ///Write proxy for field `RXOIE`
        pub struct RXOIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RXOIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 16 - processor 2 Transmit channel free interrupt enable
            #[inline(always)]
            pub fn txfie(&self) -> TXFIE_R {
                TXFIE_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 0 - processor 2 Receive channel occupied interrupt enable
            #[inline(always)]
            pub fn rxoie(&self) -> RXOIE_R {
                RXOIE_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 16 - processor 2 Transmit channel free interrupt enable
            #[inline(always)]
            pub fn txfie(&mut self) -> TXFIE_W {
                TXFIE_W { w: self }
            }
            ///Bit 0 - processor 2 Receive channel occupied interrupt enable
            #[inline(always)]
            pub fn rxoie(&mut self) -> RXOIE_W {
                RXOIE_W { w: self }
            }
        }
    }
    ///Mask register CPU2
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2mr](c2mr) module
    pub type C2MR = crate::Reg<u32, _C2MR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2MR;
    ///`read()` method returns [c2mr::R](c2mr::R) reader structure
    impl crate::Readable for C2MR {}
    ///`write(|w| ..)` method takes [c2mr::W](c2mr::W) writer structure
    impl crate::Writable for C2MR {}
    ///Mask register CPU2
    pub mod c2mr {
        ///Reader of register C2MR
        pub type R = crate::R<u32, super::C2MR>;
        ///Writer for register C2MR
        pub type W = crate::W<u32, super::C2MR>;
        ///Register C2MR `reset()`'s with value 0xffff_ffff
        impl crate::ResetValue for super::C2MR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0xffff_ffff
            }
        }
        ///Reader of field `CH6FM`
        pub type CH6FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH6FM`
        pub struct CH6FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `CH5FM`
        pub type CH5FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH5FM`
        pub struct CH5FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `CH4FM`
        pub type CH4FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH4FM`
        pub struct CH4FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `CH3FM`
        pub type CH3FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH3FM`
        pub struct CH3FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `CH2FM`
        pub type CH2FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH2FM`
        pub struct CH2FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `CH1FM`
        pub type CH1FM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH1FM`
        pub struct CH1FM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1FM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `CH6OM`
        pub type CH6OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH6OM`
        pub struct CH6OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `CH5OM`
        pub type CH5OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH5OM`
        pub struct CH5OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `CH4OM`
        pub type CH4OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH4OM`
        pub struct CH4OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CH3OM`
        pub type CH3OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH3OM`
        pub struct CH3OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `CH2OM`
        pub type CH2OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH2OM`
        pub struct CH2OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CH1OM`
        pub type CH1OM_R = crate::R<bool, bool>;
        ///Write proxy for field `CH1OM`
        pub struct CH1OM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1OM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl R {
            ///Bit 21 - processor 2 Transmit channel 6 free interrupt mask
            #[inline(always)]
            pub fn ch6fm(&self) -> CH6FM_R {
                CH6FM_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 20 - processor 2 Transmit channel 5 free interrupt mask
            #[inline(always)]
            pub fn ch5fm(&self) -> CH5FM_R {
                CH5FM_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 19 - processor 2 Transmit channel 4 free interrupt mask
            #[inline(always)]
            pub fn ch4fm(&self) -> CH4FM_R {
                CH4FM_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 18 - processor 2 Transmit channel 3 free interrupt mask
            #[inline(always)]
            pub fn ch3fm(&self) -> CH3FM_R {
                CH3FM_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 17 - processor 2 Transmit channel 2 free interrupt mask
            #[inline(always)]
            pub fn ch2fm(&self) -> CH2FM_R {
                CH2FM_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 16 - processor 2 Transmit channel 1 free interrupt mask
            #[inline(always)]
            pub fn ch1fm(&self) -> CH1FM_R {
                CH1FM_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 5 - processor 2 Receive channel 6 occupied interrupt enable
            #[inline(always)]
            pub fn ch6om(&self) -> CH6OM_R {
                CH6OM_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - processor 2 Receive channel 5 occupied interrupt enable
            #[inline(always)]
            pub fn ch5om(&self) -> CH5OM_R {
                CH5OM_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - processor 2 Receive channel 4 occupied interrupt enable
            #[inline(always)]
            pub fn ch4om(&self) -> CH4OM_R {
                CH4OM_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - processor 2 Receive channel 3 occupied interrupt enable
            #[inline(always)]
            pub fn ch3om(&self) -> CH3OM_R {
                CH3OM_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - processor 2 Receive channel 2 occupied interrupt enable
            #[inline(always)]
            pub fn ch2om(&self) -> CH2OM_R {
                CH2OM_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - processor 2 Receive channel 1 occupied interrupt enable
            #[inline(always)]
            pub fn ch1om(&self) -> CH1OM_R {
                CH1OM_R::new((self.bits & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 21 - processor 2 Transmit channel 6 free interrupt mask
            #[inline(always)]
            pub fn ch6fm(&mut self) -> CH6FM_W {
                CH6FM_W { w: self }
            }
            ///Bit 20 - processor 2 Transmit channel 5 free interrupt mask
            #[inline(always)]
            pub fn ch5fm(&mut self) -> CH5FM_W {
                CH5FM_W { w: self }
            }
            ///Bit 19 - processor 2 Transmit channel 4 free interrupt mask
            #[inline(always)]
            pub fn ch4fm(&mut self) -> CH4FM_W {
                CH4FM_W { w: self }
            }
            ///Bit 18 - processor 2 Transmit channel 3 free interrupt mask
            #[inline(always)]
            pub fn ch3fm(&mut self) -> CH3FM_W {
                CH3FM_W { w: self }
            }
            ///Bit 17 - processor 2 Transmit channel 2 free interrupt mask
            #[inline(always)]
            pub fn ch2fm(&mut self) -> CH2FM_W {
                CH2FM_W { w: self }
            }
            ///Bit 16 - processor 2 Transmit channel 1 free interrupt mask
            #[inline(always)]
            pub fn ch1fm(&mut self) -> CH1FM_W {
                CH1FM_W { w: self }
            }
            ///Bit 5 - processor 2 Receive channel 6 occupied interrupt enable
            #[inline(always)]
            pub fn ch6om(&mut self) -> CH6OM_W {
                CH6OM_W { w: self }
            }
            ///Bit 4 - processor 2 Receive channel 5 occupied interrupt enable
            #[inline(always)]
            pub fn ch5om(&mut self) -> CH5OM_W {
                CH5OM_W { w: self }
            }
            ///Bit 3 - processor 2 Receive channel 4 occupied interrupt enable
            #[inline(always)]
            pub fn ch4om(&mut self) -> CH4OM_W {
                CH4OM_W { w: self }
            }
            ///Bit 2 - processor 2 Receive channel 3 occupied interrupt enable
            #[inline(always)]
            pub fn ch3om(&mut self) -> CH3OM_W {
                CH3OM_W { w: self }
            }
            ///Bit 1 - processor 2 Receive channel 2 occupied interrupt enable
            #[inline(always)]
            pub fn ch2om(&mut self) -> CH2OM_W {
                CH2OM_W { w: self }
            }
            ///Bit 0 - processor 2 Receive channel 1 occupied interrupt enable
            #[inline(always)]
            pub fn ch1om(&mut self) -> CH1OM_W {
                CH1OM_W { w: self }
            }
        }
    }
    ///Status Set or Clear register CPU2
    ///
    ///This register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2scr](c2scr) module
    pub type C2SCR = crate::Reg<u32, _C2SCR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2SCR;
    ///`write(|w| ..)` method takes [c2scr::W](c2scr::W) writer structure
    impl crate::Writable for C2SCR {}
    ///Status Set or Clear register CPU2
    pub mod c2scr {
        ///Writer for register C2SCR
        pub type W = crate::W<u32, super::C2SCR>;
        ///Register C2SCR `reset()`'s with value 0
        impl crate::ResetValue for super::C2SCR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Write proxy for field `CH6S`
        pub struct CH6S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Write proxy for field `CH5S`
        pub struct CH5S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Write proxy for field `CH4S`
        pub struct CH4S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Write proxy for field `CH3S`
        pub struct CH3S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Write proxy for field `CH2S`
        pub struct CH2S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Write proxy for field `CH1S`
        pub struct CH1S_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1S_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Write proxy for field `CH6C`
        pub struct CH6C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH6C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Write proxy for field `CH5C`
        pub struct CH5C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH5C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Write proxy for field `CH4C`
        pub struct CH4C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH4C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Write proxy for field `CH3C`
        pub struct CH3C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH3C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Write proxy for field `CH2C`
        pub struct CH2C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH2C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Write proxy for field `CH1C`
        pub struct CH1C_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CH1C_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        impl W {
            ///Bit 21 - processor 2 Transmit channel 6 status set
            #[inline(always)]
            pub fn ch6s(&mut self) -> CH6S_W {
                CH6S_W { w: self }
            }
            ///Bit 20 - processor 2 Transmit channel 5 status set
            #[inline(always)]
            pub fn ch5s(&mut self) -> CH5S_W {
                CH5S_W { w: self }
            }
            ///Bit 19 - processor 2 Transmit channel 4 status set
            #[inline(always)]
            pub fn ch4s(&mut self) -> CH4S_W {
                CH4S_W { w: self }
            }
            ///Bit 18 - processor 2 Transmit channel 3 status set
            #[inline(always)]
            pub fn ch3s(&mut self) -> CH3S_W {
                CH3S_W { w: self }
            }
            ///Bit 17 - processor 2 Transmit channel 2 status set
            #[inline(always)]
            pub fn ch2s(&mut self) -> CH2S_W {
                CH2S_W { w: self }
            }
            ///Bit 16 - processor 2 Transmit channel 1 status set
            #[inline(always)]
            pub fn ch1s(&mut self) -> CH1S_W {
                CH1S_W { w: self }
            }
            ///Bit 5 - processor 2 Receive channel 6 status clear
            #[inline(always)]
            pub fn ch6c(&mut self) -> CH6C_W {
                CH6C_W { w: self }
            }
            ///Bit 4 - processor 2 Receive channel 5 status clear
            #[inline(always)]
            pub fn ch5c(&mut self) -> CH5C_W {
                CH5C_W { w: self }
            }
            ///Bit 3 - processor 2 Receive channel 4 status clear
            #[inline(always)]
            pub fn ch4c(&mut self) -> CH4C_W {
                CH4C_W { w: self }
            }
            ///Bit 2 - processor 2 Receive channel 3 status clear
            #[inline(always)]
            pub fn ch3c(&mut self) -> CH3C_W {
                CH3C_W { w: self }
            }
            ///Bit 1 - processor 2 Receive channel 2 status clear
            #[inline(always)]
            pub fn ch2c(&mut self) -> CH2C_W {
                CH2C_W { w: self }
            }
            ///Bit 0 - processor 2 Receive channel 1 status clear
            #[inline(always)]
            pub fn ch1c(&mut self) -> CH1C_W {
                CH1C_W { w: self }
            }
        }
    }
    ///CPU2 to CPU1 status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2toc1sr](c2toc1sr) module
    pub type C2TOC1SR = crate::Reg<u32, _C2TOC1SR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2TOC1SR;
    ///`read()` method returns [c2toc1sr::R](c2toc1sr::R) reader structure
    impl crate::Readable for C2TOC1SR {}
    ///CPU2 to CPU1 status register
    pub mod c2toc1sr {
        ///Reader of register C2TOC1SR
        pub type R = crate::R<u32, super::C2TOC1SR>;
        ///Reader of field `CH6F`
        pub type CH6F_R = crate::R<bool, bool>;
        ///Reader of field `CH5F`
        pub type CH5F_R = crate::R<bool, bool>;
        ///Reader of field `CH4F`
        pub type CH4F_R = crate::R<bool, bool>;
        ///Reader of field `CH3F`
        pub type CH3F_R = crate::R<bool, bool>;
        ///Reader of field `CH2F`
        pub type CH2F_R = crate::R<bool, bool>;
        ///Reader of field `CH1F`
        pub type CH1F_R = crate::R<bool, bool>;
        impl R {
            ///Bit 5 - processor 2 transmit to process 1 Receive channel 6 status flag
            #[inline(always)]
            pub fn ch6f(&self) -> CH6F_R {
                CH6F_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 4 - processor 2 transmit to process 1 Receive channel 5 status flag
            #[inline(always)]
            pub fn ch5f(&self) -> CH5F_R {
                CH5F_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 3 - processor 2 transmit to process 1 Receive channel 4 status flag
            #[inline(always)]
            pub fn ch4f(&self) -> CH4F_R {
                CH4F_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 2 - processor 2 transmit to process 1 Receive channel 3 status flag
            #[inline(always)]
            pub fn ch3f(&self) -> CH3F_R {
                CH3F_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 1 - processor 2 transmit to process 1 Receive channel 2 status flag
            #[inline(always)]
            pub fn ch2f(&self) -> CH2F_R {
                CH2F_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 0 - processor 2 transmit to process 1 Receive channel 1 status flag
            #[inline(always)]
            pub fn ch1f(&self) -> CH1F_R {
                CH1F_R::new((self.bits & 0x01) != 0)
            }
        }
    }
    ///IPCC Hardware configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr](hwcfgr) module
    pub type HWCFGR = crate::Reg<u32, _HWCFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR;
    ///`read()` method returns [hwcfgr::R](hwcfgr::R) reader structure
    impl crate::Readable for HWCFGR {}
    ///IPCC Hardware configuration register
    pub mod hwcfgr {
        ///Reader of register HWCFGR
        pub type R = crate::R<u32, super::HWCFGR>;
        ///Reader of field `CHANNELS`
        pub type CHANNELS_R = crate::R<u8, u8>;
        impl R {
            ///Bits 0:7 - Number of channels per CPU supported by the IP, range 1 to 16
            #[inline(always)]
            pub fn channels(&self) -> CHANNELS_R {
                CHANNELS_R::new((self.bits & 0xff) as u8)
            }
        }
    }
    ///IPCC version register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [verr](verr) module
    pub type VERR = crate::Reg<u32, _VERR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _VERR;
    ///`read()` method returns [verr::R](verr::R) reader structure
    impl crate::Readable for VERR {}
    ///IPCC version register
    pub mod verr {
        ///Reader of register VERR
        pub type R = crate::R<u32, super::VERR>;
        ///Reader of field `MAJREV`
        pub type MAJREV_R = crate::R<u8, u8>;
        ///Reader of field `MINREV`
        pub type MINREV_R = crate::R<u8, u8>;
        impl R {
            ///Bits 4:7 - Major Revision
            #[inline(always)]
            pub fn majrev(&self) -> MAJREV_R {
                MAJREV_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            ///Bits 0:3 - Minor Revision
            #[inline(always)]
            pub fn minrev(&self) -> MINREV_R {
                MINREV_R::new((self.bits & 0x0f) as u8)
            }
        }
    }
    ///IPCC indentification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ipidr](ipidr) module
    pub type IPIDR = crate::Reg<u32, _IPIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IPIDR;
    ///`read()` method returns [ipidr::R](ipidr::R) reader structure
    impl crate::Readable for IPIDR {}
    ///IPCC indentification register
    pub mod ipidr {
        ///Reader of register IPIDR
        pub type R = crate::R<u32, super::IPIDR>;
        ///Reader of field `IPID`
        pub type IPID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Identification Code
            #[inline(always)]
            pub fn ipid(&self) -> IPID_R {
                IPID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///IPCC size indentification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sidr](sidr) module
    pub type SIDR = crate::Reg<u32, _SIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SIDR;
    ///`read()` method returns [sidr::R](sidr::R) reader structure
    impl crate::Readable for SIDR {}
    ///IPCC size indentification register
    pub mod sidr {
        ///Reader of register SIDR
        pub type R = crate::R<u32, super::SIDR>;
        ///Reader of field `SID`
        pub type SID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Size Identification Code
            #[inline(always)]
            pub fn sid(&self) -> SID_R {
                SID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
}
///External interrupt/event controller
pub struct EXTI {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for EXTI {}
impl EXTI {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const exti::RegisterBlock {
        0x5800_0800 as *const _
    }
}
impl Deref for EXTI {
    type Target = exti::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*EXTI::ptr() }
    }
}
///External interrupt/event controller
pub mod exti {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - rising trigger selection register
        pub rtsr1: RTSR1,
        ///0x04 - falling trigger selection register
        pub ftsr1: FTSR1,
        ///0x08 - software interrupt event register
        pub swier1: SWIER1,
        ///0x0c - EXTI pending register
        pub pr1: PR1,
        _reserved4: [u8; 16usize],
        ///0x20 - rising trigger selection register
        pub rtsr2: RTSR2,
        ///0x24 - falling trigger selection register
        pub ftsr2: FTSR2,
        ///0x28 - software interrupt event register
        pub swier2: SWIER2,
        ///0x2c - pending register
        pub pr2: PR2,
        _reserved8: [u8; 80usize],
        ///0x80 - CPUm wakeup with interrupt mask register
        pub imr1: IMR1,
        ///0x84 - CPUm wakeup with event mask register
        pub c1emr1: C1EMR1,
        _reserved10: [u8; 8usize],
        ///0x90 - CPUm wakeup with interrupt mask register
        pub c1imr2: C1IMR2,
        ///0x94 - CPUm wakeup with event mask register
        pub c1emr2: C1EMR2,
        _reserved12: [u8; 40usize],
        ///0xc0 - CPUm wakeup with interrupt mask register
        pub c2imr1: C2IMR1,
        ///0xc4 - CPUm wakeup with event mask register
        pub c2emr1: C2EMR1,
        _reserved14: [u8; 8usize],
        ///0xd0 - CPUm wakeup with interrupt mask register
        pub c2imr2: C2IMR2,
        ///0xd4 - CPUm wakeup with event mask register
        pub c2emr2: C2EMR2,
        _reserved16: [u8; 768usize],
        ///0x3d8 - EXTI Hardware configuration registers
        pub hwcfgr7: HWCFGR7,
        ///0x3dc - Hardware configuration registers
        pub hwcfgr6: HWCFGR6,
        ///0x3e0 - Hardware configuration registers
        pub hwcfgr5: HWCFGR5,
        ///0x3e4 - Hardware configuration registers
        pub hwcfgr4: HWCFGR4,
        ///0x3e8 - Hardware configuration registers
        pub hwcfgr3: HWCFGR3,
        ///0x3ec - Hardware configuration registers
        pub hwcfgr2: HWCFGR2,
        ///0x3f0 - Hardware configuration register 1
        pub hwcfgr1: HWCFGR1,
        ///0x3f4 - EXTI IP Version register
        pub verr: VERR,
        ///0x3f8 - Identification register
        pub ipidr: IPIDR,
        ///0x3fc - Size ID register
        pub sidr: SIDR,
    }
    ///rising trigger selection register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rtsr1](rtsr1) module
    pub type RTSR1 = crate::Reg<u32, _RTSR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RTSR1;
    ///`read()` method returns [rtsr1::R](rtsr1::R) reader structure
    impl crate::Readable for RTSR1 {}
    ///`write(|w| ..)` method takes [rtsr1::W](rtsr1::W) writer structure
    impl crate::Writable for RTSR1 {}
    ///rising trigger selection register
    pub mod rtsr1 {
        ///Reader of register RTSR1
        pub type R = crate::R<u32, super::RTSR1>;
        ///Writer for register RTSR1
        pub type W = crate::W<u32, super::RTSR1>;
        ///Register RTSR1 `reset()`'s with value 0
        impl crate::ResetValue for super::RTSR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RT`
        pub type RT_R = crate::R<u32, u32>;
        ///Write proxy for field `RT`
        pub struct RT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u32) & 0x003f_ffff);
                self.w
            }
        }
        ///Reader of field `RT_31`
        pub type RT_31_R = crate::R<bool, bool>;
        ///Write proxy for field `RT_31`
        pub struct RT_31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT_31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `RT0`
        pub type RT0_R = crate::R<bool, bool>;
        ///Write proxy for field `RT0`
        pub struct RT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `RT1`
        pub type RT1_R = crate::R<bool, bool>;
        ///Write proxy for field `RT1`
        pub struct RT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `RT2`
        pub type RT2_R = crate::R<bool, bool>;
        ///Write proxy for field `RT2`
        pub struct RT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `RT3`
        pub type RT3_R = crate::R<bool, bool>;
        ///Write proxy for field `RT3`
        pub struct RT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `RT4`
        pub type RT4_R = crate::R<bool, bool>;
        ///Write proxy for field `RT4`
        pub struct RT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `RT5`
        pub type RT5_R = crate::R<bool, bool>;
        ///Write proxy for field `RT5`
        pub struct RT5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `RT6`
        pub type RT6_R = crate::R<bool, bool>;
        ///Write proxy for field `RT6`
        pub struct RT6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `RT7`
        pub type RT7_R = crate::R<bool, bool>;
        ///Write proxy for field `RT7`
        pub struct RT7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `RT8`
        pub type RT8_R = crate::R<bool, bool>;
        ///Write proxy for field `RT8`
        pub struct RT8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `RT9`
        pub type RT9_R = crate::R<bool, bool>;
        ///Write proxy for field `RT9`
        pub struct RT9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `RT10`
        pub type RT10_R = crate::R<bool, bool>;
        ///Write proxy for field `RT10`
        pub struct RT10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `RT11`
        pub type RT11_R = crate::R<bool, bool>;
        ///Write proxy for field `RT11`
        pub struct RT11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `RT12`
        pub type RT12_R = crate::R<bool, bool>;
        ///Write proxy for field `RT12`
        pub struct RT12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `RT13`
        pub type RT13_R = crate::R<bool, bool>;
        ///Write proxy for field `RT13`
        pub struct RT13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `RT14`
        pub type RT14_R = crate::R<bool, bool>;
        ///Write proxy for field `RT14`
        pub struct RT14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `RT15`
        pub type RT15_R = crate::R<bool, bool>;
        ///Write proxy for field `RT15`
        pub struct RT15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `RT16`
        pub type RT16_R = crate::R<bool, bool>;
        ///Write proxy for field `RT16`
        pub struct RT16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `RT17`
        pub type RT17_R = crate::R<bool, bool>;
        ///Write proxy for field `RT17`
        pub struct RT17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `RT18`
        pub type RT18_R = crate::R<bool, bool>;
        ///Write proxy for field `RT18`
        pub struct RT18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `RT19`
        pub type RT19_R = crate::R<bool, bool>;
        ///Write proxy for field `RT19`
        pub struct RT19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `RT20`
        pub type RT20_R = crate::R<bool, bool>;
        ///Write proxy for field `RT20`
        pub struct RT20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `RT21`
        pub type RT21_R = crate::R<bool, bool>;
        ///Write proxy for field `RT21`
        pub struct RT21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `RT31`
        pub type RT31_R = crate::R<bool, bool>;
        ///Write proxy for field `RT31`
        pub struct RT31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:21 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt(&self) -> RT_R {
                RT_R::new((self.bits & 0x003f_ffff) as u32)
            }
            ///Bit 31 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt_31(&self) -> RT_31_R {
                RT_31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 0 - Rising trigger event configuration bit of configurable Event input 0.
            #[inline(always)]
            pub fn rt0(&self) -> RT0_R {
                RT0_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Rising trigger event configuration bit of configurable Event input 1.
            #[inline(always)]
            pub fn rt1(&self) -> RT1_R {
                RT1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Rising trigger event configuration bit of configurable Event input 2.
            #[inline(always)]
            pub fn rt2(&self) -> RT2_R {
                RT2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Rising trigger event configuration bit of configurable Event input 3.
            #[inline(always)]
            pub fn rt3(&self) -> RT3_R {
                RT3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Rising trigger event configuration bit of configurable Event input 4.
            #[inline(always)]
            pub fn rt4(&self) -> RT4_R {
                RT4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Rising trigger event configuration bit of configurable Event input 5.
            #[inline(always)]
            pub fn rt5(&self) -> RT5_R {
                RT5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Rising trigger event configuration bit of configurable Event input 6.
            #[inline(always)]
            pub fn rt6(&self) -> RT6_R {
                RT6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Rising trigger event configuration bit of configurable Event input 7.
            #[inline(always)]
            pub fn rt7(&self) -> RT7_R {
                RT7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Rising trigger event configuration bit of configurable Event input 8.
            #[inline(always)]
            pub fn rt8(&self) -> RT8_R {
                RT8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Rising trigger event configuration bit of configurable Event input 9.
            #[inline(always)]
            pub fn rt9(&self) -> RT9_R {
                RT9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Rising trigger event configuration bit of configurable Event input 10.
            #[inline(always)]
            pub fn rt10(&self) -> RT10_R {
                RT10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Rising trigger event configuration bit of configurable Event input 11.
            #[inline(always)]
            pub fn rt11(&self) -> RT11_R {
                RT11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Rising trigger event configuration bit of configurable Event input 12.
            #[inline(always)]
            pub fn rt12(&self) -> RT12_R {
                RT12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Rising trigger event configuration bit of configurable Event input 13.
            #[inline(always)]
            pub fn rt13(&self) -> RT13_R {
                RT13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Rising trigger event configuration bit of configurable Event input 14.
            #[inline(always)]
            pub fn rt14(&self) -> RT14_R {
                RT14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Rising trigger event configuration bit of configurable Event input 15.
            #[inline(always)]
            pub fn rt15(&self) -> RT15_R {
                RT15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Rising trigger event configuration bit of configurable Event input 16.
            #[inline(always)]
            pub fn rt16(&self) -> RT16_R {
                RT16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Rising trigger event configuration bit of configurable Event input 17.
            #[inline(always)]
            pub fn rt17(&self) -> RT17_R {
                RT17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - Rising trigger event configuration bit of configurable Event input 18.
            #[inline(always)]
            pub fn rt18(&self) -> RT18_R {
                RT18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - Rising trigger event configuration bit of configurable Event input 19.
            #[inline(always)]
            pub fn rt19(&self) -> RT19_R {
                RT19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 20 - Rising trigger event configuration bit of configurable Event input 20.
            #[inline(always)]
            pub fn rt20(&self) -> RT20_R {
                RT20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 21 - Rising trigger event configuration bit of configurable Event input 21.
            #[inline(always)]
            pub fn rt21(&self) -> RT21_R {
                RT21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 31 - Rising trigger event configuration bit of configurable Event input 31.
            #[inline(always)]
            pub fn rt31(&self) -> RT31_R {
                RT31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:21 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt(&mut self) -> RT_W {
                RT_W { w: self }
            }
            ///Bit 31 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt_31(&mut self) -> RT_31_W {
                RT_31_W { w: self }
            }
            ///Bit 0 - Rising trigger event configuration bit of configurable Event input 0.
            #[inline(always)]
            pub fn rt0(&mut self) -> RT0_W {
                RT0_W { w: self }
            }
            ///Bit 1 - Rising trigger event configuration bit of configurable Event input 1.
            #[inline(always)]
            pub fn rt1(&mut self) -> RT1_W {
                RT1_W { w: self }
            }
            ///Bit 2 - Rising trigger event configuration bit of configurable Event input 2.
            #[inline(always)]
            pub fn rt2(&mut self) -> RT2_W {
                RT2_W { w: self }
            }
            ///Bit 3 - Rising trigger event configuration bit of configurable Event input 3.
            #[inline(always)]
            pub fn rt3(&mut self) -> RT3_W {
                RT3_W { w: self }
            }
            ///Bit 4 - Rising trigger event configuration bit of configurable Event input 4.
            #[inline(always)]
            pub fn rt4(&mut self) -> RT4_W {
                RT4_W { w: self }
            }
            ///Bit 5 - Rising trigger event configuration bit of configurable Event input 5.
            #[inline(always)]
            pub fn rt5(&mut self) -> RT5_W {
                RT5_W { w: self }
            }
            ///Bit 6 - Rising trigger event configuration bit of configurable Event input 6.
            #[inline(always)]
            pub fn rt6(&mut self) -> RT6_W {
                RT6_W { w: self }
            }
            ///Bit 7 - Rising trigger event configuration bit of configurable Event input 7.
            #[inline(always)]
            pub fn rt7(&mut self) -> RT7_W {
                RT7_W { w: self }
            }
            ///Bit 8 - Rising trigger event configuration bit of configurable Event input 8.
            #[inline(always)]
            pub fn rt8(&mut self) -> RT8_W {
                RT8_W { w: self }
            }
            ///Bit 9 - Rising trigger event configuration bit of configurable Event input 9.
            #[inline(always)]
            pub fn rt9(&mut self) -> RT9_W {
                RT9_W { w: self }
            }
            ///Bit 10 - Rising trigger event configuration bit of configurable Event input 10.
            #[inline(always)]
            pub fn rt10(&mut self) -> RT10_W {
                RT10_W { w: self }
            }
            ///Bit 11 - Rising trigger event configuration bit of configurable Event input 11.
            #[inline(always)]
            pub fn rt11(&mut self) -> RT11_W {
                RT11_W { w: self }
            }
            ///Bit 12 - Rising trigger event configuration bit of configurable Event input 12.
            #[inline(always)]
            pub fn rt12(&mut self) -> RT12_W {
                RT12_W { w: self }
            }
            ///Bit 13 - Rising trigger event configuration bit of configurable Event input 13.
            #[inline(always)]
            pub fn rt13(&mut self) -> RT13_W {
                RT13_W { w: self }
            }
            ///Bit 14 - Rising trigger event configuration bit of configurable Event input 14.
            #[inline(always)]
            pub fn rt14(&mut self) -> RT14_W {
                RT14_W { w: self }
            }
            ///Bit 15 - Rising trigger event configuration bit of configurable Event input 15.
            #[inline(always)]
            pub fn rt15(&mut self) -> RT15_W {
                RT15_W { w: self }
            }
            ///Bit 16 - Rising trigger event configuration bit of configurable Event input 16.
            #[inline(always)]
            pub fn rt16(&mut self) -> RT16_W {
                RT16_W { w: self }
            }
            ///Bit 17 - Rising trigger event configuration bit of configurable Event input 17.
            #[inline(always)]
            pub fn rt17(&mut self) -> RT17_W {
                RT17_W { w: self }
            }
            ///Bit 18 - Rising trigger event configuration bit of configurable Event input 18.
            #[inline(always)]
            pub fn rt18(&mut self) -> RT18_W {
                RT18_W { w: self }
            }
            ///Bit 19 - Rising trigger event configuration bit of configurable Event input 19.
            #[inline(always)]
            pub fn rt19(&mut self) -> RT19_W {
                RT19_W { w: self }
            }
            ///Bit 20 - Rising trigger event configuration bit of configurable Event input 20.
            #[inline(always)]
            pub fn rt20(&mut self) -> RT20_W {
                RT20_W { w: self }
            }
            ///Bit 21 - Rising trigger event configuration bit of configurable Event input 21.
            #[inline(always)]
            pub fn rt21(&mut self) -> RT21_W {
                RT21_W { w: self }
            }
            ///Bit 31 - Rising trigger event configuration bit of configurable Event input 31.
            #[inline(always)]
            pub fn rt31(&mut self) -> RT31_W {
                RT31_W { w: self }
            }
        }
    }
    ///falling trigger selection register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ftsr1](ftsr1) module
    pub type FTSR1 = crate::Reg<u32, _FTSR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _FTSR1;
    ///`read()` method returns [ftsr1::R](ftsr1::R) reader structure
    impl crate::Readable for FTSR1 {}
    ///`write(|w| ..)` method takes [ftsr1::W](ftsr1::W) writer structure
    impl crate::Writable for FTSR1 {}
    ///falling trigger selection register
    pub mod ftsr1 {
        ///Reader of register FTSR1
        pub type R = crate::R<u32, super::FTSR1>;
        ///Writer for register FTSR1
        pub type W = crate::W<u32, super::FTSR1>;
        ///Register FTSR1 `reset()`'s with value 0
        impl crate::ResetValue for super::FTSR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `FT`
        pub type FT_R = crate::R<u32, u32>;
        ///Write proxy for field `FT`
        pub struct FT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u32) & 0x003f_ffff);
                self.w
            }
        }
        ///Reader of field `FT_31`
        pub type FT_31_R = crate::R<bool, bool>;
        ///Write proxy for field `FT_31`
        pub struct FT_31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT_31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        ///Reader of field `FT0`
        pub type FT0_R = crate::R<bool, bool>;
        ///Write proxy for field `FT0`
        pub struct FT0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `FT1`
        pub type FT1_R = crate::R<bool, bool>;
        ///Write proxy for field `FT1`
        pub struct FT1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `FT2`
        pub type FT2_R = crate::R<bool, bool>;
        ///Write proxy for field `FT2`
        pub struct FT2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `FT3`
        pub type FT3_R = crate::R<bool, bool>;
        ///Write proxy for field `FT3`
        pub struct FT3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `FT4`
        pub type FT4_R = crate::R<bool, bool>;
        ///Write proxy for field `FT4`
        pub struct FT4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `FT5`
        pub type FT5_R = crate::R<bool, bool>;
        ///Write proxy for field `FT5`
        pub struct FT5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `FT6`
        pub type FT6_R = crate::R<bool, bool>;
        ///Write proxy for field `FT6`
        pub struct FT6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `FT7`
        pub type FT7_R = crate::R<bool, bool>;
        ///Write proxy for field `FT7`
        pub struct FT7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `FT8`
        pub type FT8_R = crate::R<bool, bool>;
        ///Write proxy for field `FT8`
        pub struct FT8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `FT9`
        pub type FT9_R = crate::R<bool, bool>;
        ///Write proxy for field `FT9`
        pub struct FT9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `FT10`
        pub type FT10_R = crate::R<bool, bool>;
        ///Write proxy for field `FT10`
        pub struct FT10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `FT11`
        pub type FT11_R = crate::R<bool, bool>;
        ///Write proxy for field `FT11`
        pub struct FT11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `FT12`
        pub type FT12_R = crate::R<bool, bool>;
        ///Write proxy for field `FT12`
        pub struct FT12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `FT13`
        pub type FT13_R = crate::R<bool, bool>;
        ///Write proxy for field `FT13`
        pub struct FT13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `FT14`
        pub type FT14_R = crate::R<bool, bool>;
        ///Write proxy for field `FT14`
        pub struct FT14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `FT15`
        pub type FT15_R = crate::R<bool, bool>;
        ///Write proxy for field `FT15`
        pub struct FT15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `FT16`
        pub type FT16_R = crate::R<bool, bool>;
        ///Write proxy for field `FT16`
        pub struct FT16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `FT17`
        pub type FT17_R = crate::R<bool, bool>;
        ///Write proxy for field `FT17`
        pub struct FT17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `FT18`
        pub type FT18_R = crate::R<bool, bool>;
        ///Write proxy for field `FT18`
        pub struct FT18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `FT19`
        pub type FT19_R = crate::R<bool, bool>;
        ///Write proxy for field `FT19`
        pub struct FT19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `FT20`
        pub type FT20_R = crate::R<bool, bool>;
        ///Write proxy for field `FT20`
        pub struct FT20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `FT21`
        pub type FT21_R = crate::R<bool, bool>;
        ///Write proxy for field `FT21`
        pub struct FT21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `FT31`
        pub type FT31_R = crate::R<bool, bool>;
        ///Write proxy for field `FT31`
        pub struct FT31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:21 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft(&self) -> FT_R {
                FT_R::new((self.bits & 0x003f_ffff) as u32)
            }
            ///Bit 31 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft_31(&self) -> FT_31_R {
                FT_31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
            ///Bit 0 - Falling trigger event configuration bit of configurable Event input 0.
            #[inline(always)]
            pub fn ft0(&self) -> FT0_R {
                FT0_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Falling trigger event configuration bit of configurable Event input 1.
            #[inline(always)]
            pub fn ft1(&self) -> FT1_R {
                FT1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Falling trigger event configuration bit of configurable Event input 2.
            #[inline(always)]
            pub fn ft2(&self) -> FT2_R {
                FT2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Falling trigger event configuration bit of configurable Event input 3.
            #[inline(always)]
            pub fn ft3(&self) -> FT3_R {
                FT3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Falling trigger event configuration bit of configurable Event input 4.
            #[inline(always)]
            pub fn ft4(&self) -> FT4_R {
                FT4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Falling trigger event configuration bit of configurable Event input 5.
            #[inline(always)]
            pub fn ft5(&self) -> FT5_R {
                FT5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Falling trigger event configuration bit of configurable Event input 6.
            #[inline(always)]
            pub fn ft6(&self) -> FT6_R {
                FT6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Falling trigger event configuration bit of configurable Event input 7.
            #[inline(always)]
            pub fn ft7(&self) -> FT7_R {
                FT7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Falling trigger event configuration bit of configurable Event input 8.
            #[inline(always)]
            pub fn ft8(&self) -> FT8_R {
                FT8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Falling trigger event configuration bit of configurable Event input 9.
            #[inline(always)]
            pub fn ft9(&self) -> FT9_R {
                FT9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Falling trigger event configuration bit of configurable Event input 10.
            #[inline(always)]
            pub fn ft10(&self) -> FT10_R {
                FT10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Falling trigger event configuration bit of configurable Event input 11.
            #[inline(always)]
            pub fn ft11(&self) -> FT11_R {
                FT11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Falling trigger event configuration bit of configurable Event input 12.
            #[inline(always)]
            pub fn ft12(&self) -> FT12_R {
                FT12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Falling trigger event configuration bit of configurable Event input 13.
            #[inline(always)]
            pub fn ft13(&self) -> FT13_R {
                FT13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Falling trigger event configuration bit of configurable Event input 14.
            #[inline(always)]
            pub fn ft14(&self) -> FT14_R {
                FT14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Falling trigger event configuration bit of configurable Event input 15.
            #[inline(always)]
            pub fn ft15(&self) -> FT15_R {
                FT15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - Falling trigger event configuration bit of configurable Event input 16.
            #[inline(always)]
            pub fn ft16(&self) -> FT16_R {
                FT16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - Falling trigger event configuration bit of configurable Event input 17.
            #[inline(always)]
            pub fn ft17(&self) -> FT17_R {
                FT17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - Falling trigger event configuration bit of configurable Event input 18.
            #[inline(always)]
            pub fn ft18(&self) -> FT18_R {
                FT18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - Falling trigger event configuration bit of configurable Event input 19.
            #[inline(always)]
            pub fn ft19(&self) -> FT19_R {
                FT19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 20 - Falling trigger event configuration bit of configurable Event input 20.
            #[inline(always)]
            pub fn ft20(&self) -> FT20_R {
                FT20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 21 - Falling trigger event configuration bit of configurable Event input 21.
            #[inline(always)]
            pub fn ft21(&self) -> FT21_R {
                FT21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 31 - Falling trigger event configuration bit of configurable Event input 31.
            #[inline(always)]
            pub fn ft31(&self) -> FT31_R {
                FT31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:21 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft(&mut self) -> FT_W {
                FT_W { w: self }
            }
            ///Bit 31 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft_31(&mut self) -> FT_31_W {
                FT_31_W { w: self }
            }
            ///Bit 0 - Falling trigger event configuration bit of configurable Event input 0.
            #[inline(always)]
            pub fn ft0(&mut self) -> FT0_W {
                FT0_W { w: self }
            }
            ///Bit 1 - Falling trigger event configuration bit of configurable Event input 1.
            #[inline(always)]
            pub fn ft1(&mut self) -> FT1_W {
                FT1_W { w: self }
            }
            ///Bit 2 - Falling trigger event configuration bit of configurable Event input 2.
            #[inline(always)]
            pub fn ft2(&mut self) -> FT2_W {
                FT2_W { w: self }
            }
            ///Bit 3 - Falling trigger event configuration bit of configurable Event input 3.
            #[inline(always)]
            pub fn ft3(&mut self) -> FT3_W {
                FT3_W { w: self }
            }
            ///Bit 4 - Falling trigger event configuration bit of configurable Event input 4.
            #[inline(always)]
            pub fn ft4(&mut self) -> FT4_W {
                FT4_W { w: self }
            }
            ///Bit 5 - Falling trigger event configuration bit of configurable Event input 5.
            #[inline(always)]
            pub fn ft5(&mut self) -> FT5_W {
                FT5_W { w: self }
            }
            ///Bit 6 - Falling trigger event configuration bit of configurable Event input 6.
            #[inline(always)]
            pub fn ft6(&mut self) -> FT6_W {
                FT6_W { w: self }
            }
            ///Bit 7 - Falling trigger event configuration bit of configurable Event input 7.
            #[inline(always)]
            pub fn ft7(&mut self) -> FT7_W {
                FT7_W { w: self }
            }
            ///Bit 8 - Falling trigger event configuration bit of configurable Event input 8.
            #[inline(always)]
            pub fn ft8(&mut self) -> FT8_W {
                FT8_W { w: self }
            }
            ///Bit 9 - Falling trigger event configuration bit of configurable Event input 9.
            #[inline(always)]
            pub fn ft9(&mut self) -> FT9_W {
                FT9_W { w: self }
            }
            ///Bit 10 - Falling trigger event configuration bit of configurable Event input 10.
            #[inline(always)]
            pub fn ft10(&mut self) -> FT10_W {
                FT10_W { w: self }
            }
            ///Bit 11 - Falling trigger event configuration bit of configurable Event input 11.
            #[inline(always)]
            pub fn ft11(&mut self) -> FT11_W {
                FT11_W { w: self }
            }
            ///Bit 12 - Falling trigger event configuration bit of configurable Event input 12.
            #[inline(always)]
            pub fn ft12(&mut self) -> FT12_W {
                FT12_W { w: self }
            }
            ///Bit 13 - Falling trigger event configuration bit of configurable Event input 13.
            #[inline(always)]
            pub fn ft13(&mut self) -> FT13_W {
                FT13_W { w: self }
            }
            ///Bit 14 - Falling trigger event configuration bit of configurable Event input 14.
            #[inline(always)]
            pub fn ft14(&mut self) -> FT14_W {
                FT14_W { w: self }
            }
            ///Bit 15 - Falling trigger event configuration bit of configurable Event input 15.
            #[inline(always)]
            pub fn ft15(&mut self) -> FT15_W {
                FT15_W { w: self }
            }
            ///Bit 16 - Falling trigger event configuration bit of configurable Event input 16.
            #[inline(always)]
            pub fn ft16(&mut self) -> FT16_W {
                FT16_W { w: self }
            }
            ///Bit 17 - Falling trigger event configuration bit of configurable Event input 17.
            #[inline(always)]
            pub fn ft17(&mut self) -> FT17_W {
                FT17_W { w: self }
            }
            ///Bit 18 - Falling trigger event configuration bit of configurable Event input 18.
            #[inline(always)]
            pub fn ft18(&mut self) -> FT18_W {
                FT18_W { w: self }
            }
            ///Bit 19 - Falling trigger event configuration bit of configurable Event input 19.
            #[inline(always)]
            pub fn ft19(&mut self) -> FT19_W {
                FT19_W { w: self }
            }
            ///Bit 20 - Falling trigger event configuration bit of configurable Event input 20.
            #[inline(always)]
            pub fn ft20(&mut self) -> FT20_W {
                FT20_W { w: self }
            }
            ///Bit 21 - Falling trigger event configuration bit of configurable Event input 21.
            #[inline(always)]
            pub fn ft21(&mut self) -> FT21_W {
                FT21_W { w: self }
            }
            ///Bit 31 - Falling trigger event configuration bit of configurable Event input 31.
            #[inline(always)]
            pub fn ft31(&mut self) -> FT31_W {
                FT31_W { w: self }
            }
        }
    }
    ///software interrupt event register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [swier1](swier1) module
    pub type SWIER1 = crate::Reg<u32, _SWIER1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SWIER1;
    ///`read()` method returns [swier1::R](swier1::R) reader structure
    impl crate::Readable for SWIER1 {}
    ///`write(|w| ..)` method takes [swier1::W](swier1::W) writer structure
    impl crate::Writable for SWIER1 {}
    ///software interrupt event register
    pub mod swier1 {
        ///Reader of register SWIER1
        pub type R = crate::R<u32, super::SWIER1>;
        ///Writer for register SWIER1
        pub type W = crate::W<u32, super::SWIER1>;
        ///Register SWIER1 `reset()`'s with value 0
        impl crate::ResetValue for super::SWIER1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SWI`
        pub type SWI_R = crate::R<u32, u32>;
        ///Write proxy for field `SWI`
        pub struct SWI_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SWI_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u32) & 0x003f_ffff);
                self.w
            }
        }
        ///Reader of field `SWI_31`
        pub type SWI_31_R = crate::R<bool, bool>;
        ///Write proxy for field `SWI_31`
        pub struct SWI_31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SWI_31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:21 - Software interrupt on event
            #[inline(always)]
            pub fn swi(&self) -> SWI_R {
                SWI_R::new((self.bits & 0x003f_ffff) as u32)
            }
            ///Bit 31 - Software interrupt on event
            #[inline(always)]
            pub fn swi_31(&self) -> SWI_31_R {
                SWI_31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:21 - Software interrupt on event
            #[inline(always)]
            pub fn swi(&mut self) -> SWI_W {
                SWI_W { w: self }
            }
            ///Bit 31 - Software interrupt on event
            #[inline(always)]
            pub fn swi_31(&mut self) -> SWI_31_W {
                SWI_31_W { w: self }
            }
        }
    }
    ///EXTI pending register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pr1](pr1) module
    pub type PR1 = crate::Reg<u32, _PR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PR1;
    ///`read()` method returns [pr1::R](pr1::R) reader structure
    impl crate::Readable for PR1 {}
    ///`write(|w| ..)` method takes [pr1::W](pr1::W) writer structure
    impl crate::Writable for PR1 {}
    ///EXTI pending register
    pub mod pr1 {
        ///Reader of register PR1
        pub type R = crate::R<u32, super::PR1>;
        ///Writer for register PR1
        pub type W = crate::W<u32, super::PR1>;
        ///Register PR1 `reset()`'s with value 0
        impl crate::ResetValue for super::PR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PIF`
        pub type PIF_R = crate::R<u32, u32>;
        ///Write proxy for field `PIF`
        pub struct PIF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PIF_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x003f_ffff) | ((value as u32) & 0x003f_ffff);
                self.w
            }
        }
        ///Reader of field `PIF_31`
        pub type PIF_31_R = crate::R<bool, bool>;
        ///Write proxy for field `PIF_31`
        pub struct PIF_31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PIF_31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:21 - Configurable event inputs Pending bit
            #[inline(always)]
            pub fn pif(&self) -> PIF_R {
                PIF_R::new((self.bits & 0x003f_ffff) as u32)
            }
            ///Bit 31 - Configurable event inputs Pending bit
            #[inline(always)]
            pub fn pif_31(&self) -> PIF_31_R {
                PIF_31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:21 - Configurable event inputs Pending bit
            #[inline(always)]
            pub fn pif(&mut self) -> PIF_W {
                PIF_W { w: self }
            }
            ///Bit 31 - Configurable event inputs Pending bit
            #[inline(always)]
            pub fn pif_31(&mut self) -> PIF_31_W {
                PIF_31_W { w: self }
            }
        }
    }
    ///rising trigger selection register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [rtsr2](rtsr2) module
    pub type RTSR2 = crate::Reg<u32, _RTSR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _RTSR2;
    ///`read()` method returns [rtsr2::R](rtsr2::R) reader structure
    impl crate::Readable for RTSR2 {}
    ///`write(|w| ..)` method takes [rtsr2::W](rtsr2::W) writer structure
    impl crate::Writable for RTSR2 {}
    ///rising trigger selection register
    pub mod rtsr2 {
        ///Reader of register RTSR2
        pub type R = crate::R<u32, super::RTSR2>;
        ///Writer for register RTSR2
        pub type W = crate::W<u32, super::RTSR2>;
        ///Register RTSR2 `reset()`'s with value 0
        impl crate::ResetValue for super::RTSR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RT33`
        pub type RT33_R = crate::R<bool, bool>;
        ///Write proxy for field `RT33`
        pub struct RT33_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT33_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `RT40_41`
        pub type RT40_41_R = crate::R<u8, u8>;
        ///Write proxy for field `RT40_41`
        pub struct RT40_41_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RT40_41_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 1 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt33(&self) -> RT33_R {
                RT33_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bits 8:9 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt40_41(&self) -> RT40_41_R {
                RT40_41_R::new(((self.bits >> 8) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 1 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt33(&mut self) -> RT33_W {
                RT33_W { w: self }
            }
            ///Bits 8:9 - Rising trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn rt40_41(&mut self) -> RT40_41_W {
                RT40_41_W { w: self }
            }
        }
    }
    ///falling trigger selection register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ftsr2](ftsr2) module
    pub type FTSR2 = crate::Reg<u32, _FTSR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _FTSR2;
    ///`read()` method returns [ftsr2::R](ftsr2::R) reader structure
    impl crate::Readable for FTSR2 {}
    ///`write(|w| ..)` method takes [ftsr2::W](ftsr2::W) writer structure
    impl crate::Writable for FTSR2 {}
    ///falling trigger selection register
    pub mod ftsr2 {
        ///Reader of register FTSR2
        pub type R = crate::R<u32, super::FTSR2>;
        ///Writer for register FTSR2
        pub type W = crate::W<u32, super::FTSR2>;
        ///Register FTSR2 `reset()`'s with value 0
        impl crate::ResetValue for super::FTSR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `FT33`
        pub type FT33_R = crate::R<bool, bool>;
        ///Write proxy for field `FT33`
        pub struct FT33_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT33_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `FT40_41`
        pub type FT40_41_R = crate::R<u8, u8>;
        ///Write proxy for field `FT40_41`
        pub struct FT40_41_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FT40_41_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 1 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft33(&self) -> FT33_R {
                FT33_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bits 8:9 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft40_41(&self) -> FT40_41_R {
                FT40_41_R::new(((self.bits >> 8) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 1 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft33(&mut self) -> FT33_W {
                FT33_W { w: self }
            }
            ///Bits 8:9 - Falling trigger event configuration bit of Configurable Event input
            #[inline(always)]
            pub fn ft40_41(&mut self) -> FT40_41_W {
                FT40_41_W { w: self }
            }
        }
    }
    ///software interrupt event register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [swier2](swier2) module
    pub type SWIER2 = crate::Reg<u32, _SWIER2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SWIER2;
    ///`read()` method returns [swier2::R](swier2::R) reader structure
    impl crate::Readable for SWIER2 {}
    ///`write(|w| ..)` method takes [swier2::W](swier2::W) writer structure
    impl crate::Writable for SWIER2 {}
    ///software interrupt event register
    pub mod swier2 {
        ///Reader of register SWIER2
        pub type R = crate::R<u32, super::SWIER2>;
        ///Writer for register SWIER2
        pub type W = crate::W<u32, super::SWIER2>;
        ///Register SWIER2 `reset()`'s with value 0
        impl crate::ResetValue for super::SWIER2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SWI33`
        pub type SWI33_R = crate::R<bool, bool>;
        ///Write proxy for field `SWI33`
        pub struct SWI33_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SWI33_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `SWI40_41`
        pub type SWI40_41_R = crate::R<u8, u8>;
        ///Write proxy for field `SWI40_41`
        pub struct SWI40_41_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SWI40_41_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 1 - Software interrupt on event
            #[inline(always)]
            pub fn swi33(&self) -> SWI33_R {
                SWI33_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bits 8:9 - Software interrupt on event
            #[inline(always)]
            pub fn swi40_41(&self) -> SWI40_41_R {
                SWI40_41_R::new(((self.bits >> 8) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 1 - Software interrupt on event
            #[inline(always)]
            pub fn swi33(&mut self) -> SWI33_W {
                SWI33_W { w: self }
            }
            ///Bits 8:9 - Software interrupt on event
            #[inline(always)]
            pub fn swi40_41(&mut self) -> SWI40_41_W {
                SWI40_41_W { w: self }
            }
        }
    }
    ///pending register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [pr2](pr2) module
    pub type PR2 = crate::Reg<u32, _PR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _PR2;
    ///`read()` method returns [pr2::R](pr2::R) reader structure
    impl crate::Readable for PR2 {}
    ///`write(|w| ..)` method takes [pr2::W](pr2::W) writer structure
    impl crate::Writable for PR2 {}
    ///pending register
    pub mod pr2 {
        ///Reader of register PR2
        pub type R = crate::R<u32, super::PR2>;
        ///Writer for register PR2
        pub type W = crate::W<u32, super::PR2>;
        ///Register PR2 `reset()`'s with value 0
        impl crate::ResetValue for super::PR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `PIF33`
        pub type PIF33_R = crate::R<bool, bool>;
        ///Write proxy for field `PIF33`
        pub struct PIF33_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PIF33_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PIF40_41`
        pub type PIF40_41_R = crate::R<u8, u8>;
        ///Write proxy for field `PIF40_41`
        pub struct PIF40_41_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PIF40_41_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 1 - Configurable event inputs x+32 Pending bit.
            #[inline(always)]
            pub fn pif33(&self) -> PIF33_R {
                PIF33_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bits 8:9 - Configurable event inputs x+32 Pending bit.
            #[inline(always)]
            pub fn pif40_41(&self) -> PIF40_41_R {
                PIF40_41_R::new(((self.bits >> 8) & 0x03) as u8)
            }
        }
        impl W {
            ///Bit 1 - Configurable event inputs x+32 Pending bit.
            #[inline(always)]
            pub fn pif33(&mut self) -> PIF33_W {
                PIF33_W { w: self }
            }
            ///Bits 8:9 - Configurable event inputs x+32 Pending bit.
            #[inline(always)]
            pub fn pif40_41(&mut self) -> PIF40_41_W {
                PIF40_41_W { w: self }
            }
        }
    }
    ///CPUm wakeup with interrupt mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [imr1](imr1) module
    pub type IMR1 = crate::Reg<u32, _IMR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IMR1;
    ///`read()` method returns [imr1::R](imr1::R) reader structure
    impl crate::Readable for IMR1 {}
    ///`write(|w| ..)` method takes [imr1::W](imr1::W) writer structure
    impl crate::Writable for IMR1 {}
    ///CPUm wakeup with interrupt mask register
    pub mod imr1 {
        ///Reader of register IMR1
        pub type R = crate::R<u32, super::IMR1>;
        ///Writer for register IMR1
        pub type W = crate::W<u32, super::IMR1>;
        ///Register IMR1 `reset()`'s with value 0x7fc0_0000
        impl crate::ResetValue for super::IMR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x7fc0_0000
            }
        }
        ///Reader of field `IM`
        pub type IM_R = crate::R<u32, u32>;
        ///Write proxy for field `IM`
        pub struct IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        ///Reader of field `IM0`
        pub type IM0_R = crate::R<bool, bool>;
        ///Write proxy for field `IM0`
        pub struct IM0_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM0_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `IM1`
        pub type IM1_R = crate::R<bool, bool>;
        ///Write proxy for field `IM1`
        pub struct IM1_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM1_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `IM2`
        pub type IM2_R = crate::R<bool, bool>;
        ///Write proxy for field `IM2`
        pub struct IM2_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM2_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `IM3`
        pub type IM3_R = crate::R<bool, bool>;
        ///Write proxy for field `IM3`
        pub struct IM3_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM3_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `IM4`
        pub type IM4_R = crate::R<bool, bool>;
        ///Write proxy for field `IM4`
        pub struct IM4_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM4_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `IM5`
        pub type IM5_R = crate::R<bool, bool>;
        ///Write proxy for field `IM5`
        pub struct IM5_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM5_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `IM6`
        pub type IM6_R = crate::R<bool, bool>;
        ///Write proxy for field `IM6`
        pub struct IM6_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM6_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `IM7`
        pub type IM7_R = crate::R<bool, bool>;
        ///Write proxy for field `IM7`
        pub struct IM7_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM7_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `IM8`
        pub type IM8_R = crate::R<bool, bool>;
        ///Write proxy for field `IM8`
        pub struct IM8_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM8_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `IM9`
        pub type IM9_R = crate::R<bool, bool>;
        ///Write proxy for field `IM9`
        pub struct IM9_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM9_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `IM10`
        pub type IM10_R = crate::R<bool, bool>;
        ///Write proxy for field `IM10`
        pub struct IM10_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM10_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `IM11`
        pub type IM11_R = crate::R<bool, bool>;
        ///Write proxy for field `IM11`
        pub struct IM11_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM11_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `IM12`
        pub type IM12_R = crate::R<bool, bool>;
        ///Write proxy for field `IM12`
        pub struct IM12_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM12_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `IM13`
        pub type IM13_R = crate::R<bool, bool>;
        ///Write proxy for field `IM13`
        pub struct IM13_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM13_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `IM14`
        pub type IM14_R = crate::R<bool, bool>;
        ///Write proxy for field `IM14`
        pub struct IM14_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM14_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `IM15`
        pub type IM15_R = crate::R<bool, bool>;
        ///Write proxy for field `IM15`
        pub struct IM15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM15_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
                self.w
            }
        }
        ///Reader of field `IM16`
        pub type IM16_R = crate::R<bool, bool>;
        ///Write proxy for field `IM16`
        pub struct IM16_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM16_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        ///Reader of field `IM17`
        pub type IM17_R = crate::R<bool, bool>;
        ///Write proxy for field `IM17`
        pub struct IM17_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM17_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
                self.w
            }
        }
        ///Reader of field `IM18`
        pub type IM18_R = crate::R<bool, bool>;
        ///Write proxy for field `IM18`
        pub struct IM18_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM18_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
                self.w
            }
        }
        ///Reader of field `IM19`
        pub type IM19_R = crate::R<bool, bool>;
        ///Write proxy for field `IM19`
        pub struct IM19_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM19_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
                self.w
            }
        }
        ///Reader of field `IM20`
        pub type IM20_R = crate::R<bool, bool>;
        ///Write proxy for field `IM20`
        pub struct IM20_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM20_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
                self.w
            }
        }
        ///Reader of field `IM21`
        pub type IM21_R = crate::R<bool, bool>;
        ///Write proxy for field `IM21`
        pub struct IM21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM21_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
                self.w
            }
        }
        ///Reader of field `IM22`
        pub type IM22_R = crate::R<bool, bool>;
        ///Write proxy for field `IM22`
        pub struct IM22_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM22_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
                self.w
            }
        }
        ///Reader of field `IM23`
        pub type IM23_R = crate::R<bool, bool>;
        ///Write proxy for field `IM23`
        pub struct IM23_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM23_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
                self.w
            }
        }
        ///Reader of field `IM24`
        pub type IM24_R = crate::R<bool, bool>;
        ///Write proxy for field `IM24`
        pub struct IM24_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM24_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
                self.w
            }
        }
        ///Reader of field `IM25`
        pub type IM25_R = crate::R<bool, bool>;
        ///Write proxy for field `IM25`
        pub struct IM25_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM25_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
                self.w
            }
        }
        ///Reader of field `IM26`
        pub type IM26_R = crate::R<bool, bool>;
        ///Write proxy for field `IM26`
        pub struct IM26_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM26_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
                self.w
            }
        }
        ///Reader of field `IM27`
        pub type IM27_R = crate::R<bool, bool>;
        ///Write proxy for field `IM27`
        pub struct IM27_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM27_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
                self.w
            }
        }
        ///Reader of field `IM28`
        pub type IM28_R = crate::R<bool, bool>;
        ///Write proxy for field `IM28`
        pub struct IM28_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM28_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
                self.w
            }
        }
        ///Reader of field `IM29`
        pub type IM29_R = crate::R<bool, bool>;
        ///Write proxy for field `IM29`
        pub struct IM29_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM29_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
                self.w
            }
        }
        ///Reader of field `IM30`
        pub type IM30_R = crate::R<bool, bool>;
        ///Write proxy for field `IM30`
        pub struct IM30_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM30_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `IM31`
        pub type IM31_R = crate::R<bool, bool>;
        ///Write proxy for field `IM31`
        pub struct IM31_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM31_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&self) -> IM_R {
                IM_R::new((self.bits & 0xffff_ffff) as u32)
            }
            ///Bit 0 - CPU wakeup with interrupt mask on event input 0.
            #[inline(always)]
            pub fn im0(&self) -> IM0_R {
                IM0_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - CPU wakeup with interrupt mask on event input 1.
            #[inline(always)]
            pub fn im1(&self) -> IM1_R {
                IM1_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - CPU wakeup with interrupt mask on event input 2.
            #[inline(always)]
            pub fn im2(&self) -> IM2_R {
                IM2_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - CPU wakeup with interrupt mask on event input 3.
            #[inline(always)]
            pub fn im3(&self) -> IM3_R {
                IM3_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - CPU wakeup with interrupt mask on event input 4.
            #[inline(always)]
            pub fn im4(&self) -> IM4_R {
                IM4_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - CPU wakeup with interrupt mask on event input 5.
            #[inline(always)]
            pub fn im5(&self) -> IM5_R {
                IM5_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - CPU wakeup with interrupt mask on event input 6.
            #[inline(always)]
            pub fn im6(&self) -> IM6_R {
                IM6_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - CPU wakeup with interrupt mask on event input 7.
            #[inline(always)]
            pub fn im7(&self) -> IM7_R {
                IM7_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - CPU wakeup with interrupt mask on event input 8.
            #[inline(always)]
            pub fn im8(&self) -> IM8_R {
                IM8_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - CPU wakeup with interrupt mask on event input 9.
            #[inline(always)]
            pub fn im9(&self) -> IM9_R {
                IM9_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - CPU wakeup with interrupt mask on event input 10.
            #[inline(always)]
            pub fn im10(&self) -> IM10_R {
                IM10_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - CPU wakeup with interrupt mask on event input 11.
            #[inline(always)]
            pub fn im11(&self) -> IM11_R {
                IM11_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - CPU wakeup with interrupt mask on event input 12.
            #[inline(always)]
            pub fn im12(&self) -> IM12_R {
                IM12_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - CPU wakeup with interrupt mask on event input 13.
            #[inline(always)]
            pub fn im13(&self) -> IM13_R {
                IM13_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - CPU wakeup with interrupt mask on event input 14.
            #[inline(always)]
            pub fn im14(&self) -> IM14_R {
                IM14_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - CPU wakeup with interrupt mask on event input 15.
            #[inline(always)]
            pub fn im15(&self) -> IM15_R {
                IM15_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bit 16 - CPU wakeup with interrupt mask on event input 16.
            #[inline(always)]
            pub fn im16(&self) -> IM16_R {
                IM16_R::new(((self.bits >> 16) & 0x01) != 0)
            }
            ///Bit 17 - CPU wakeup with interrupt mask on event input 17.
            #[inline(always)]
            pub fn im17(&self) -> IM17_R {
                IM17_R::new(((self.bits >> 17) & 0x01) != 0)
            }
            ///Bit 18 - CPU wakeup with interrupt mask on event input 18.
            #[inline(always)]
            pub fn im18(&self) -> IM18_R {
                IM18_R::new(((self.bits >> 18) & 0x01) != 0)
            }
            ///Bit 19 - CPU wakeup with interrupt mask on event input 19.
            #[inline(always)]
            pub fn im19(&self) -> IM19_R {
                IM19_R::new(((self.bits >> 19) & 0x01) != 0)
            }
            ///Bit 20 - CPU wakeup with interrupt mask on event input 20.
            #[inline(always)]
            pub fn im20(&self) -> IM20_R {
                IM20_R::new(((self.bits >> 20) & 0x01) != 0)
            }
            ///Bit 21 - CPU wakeup with interrupt mask on event input 21.
            #[inline(always)]
            pub fn im21(&self) -> IM21_R {
                IM21_R::new(((self.bits >> 21) & 0x01) != 0)
            }
            ///Bit 22 - CPU wakeup with interrupt mask on event input 22.
            #[inline(always)]
            pub fn im22(&self) -> IM22_R {
                IM22_R::new(((self.bits >> 22) & 0x01) != 0)
            }
            ///Bit 23 - CPU wakeup with interrupt mask on event input 23.
            #[inline(always)]
            pub fn im23(&self) -> IM23_R {
                IM23_R::new(((self.bits >> 23) & 0x01) != 0)
            }
            ///Bit 24 - CPU wakeup with interrupt mask on event input 24.
            #[inline(always)]
            pub fn im24(&self) -> IM24_R {
                IM24_R::new(((self.bits >> 24) & 0x01) != 0)
            }
            ///Bit 25 - CPU wakeup with interrupt mask on event input 25.
            #[inline(always)]
            pub fn im25(&self) -> IM25_R {
                IM25_R::new(((self.bits >> 25) & 0x01) != 0)
            }
            ///Bit 26 - CPU wakeup with interrupt mask on event input 26.
            #[inline(always)]
            pub fn im26(&self) -> IM26_R {
                IM26_R::new(((self.bits >> 26) & 0x01) != 0)
            }
            ///Bit 27 - CPU wakeup with interrupt mask on event input 27.
            #[inline(always)]
            pub fn im27(&self) -> IM27_R {
                IM27_R::new(((self.bits >> 27) & 0x01) != 0)
            }
            ///Bit 28 - CPU wakeup with interrupt mask on event input 28.
            #[inline(always)]
            pub fn im28(&self) -> IM28_R {
                IM28_R::new(((self.bits >> 28) & 0x01) != 0)
            }
            ///Bit 29 - CPU wakeup with interrupt mask on event input 29.
            #[inline(always)]
            pub fn im29(&self) -> IM29_R {
                IM29_R::new(((self.bits >> 29) & 0x01) != 0)
            }
            ///Bit 30 - CPU wakeup with interrupt mask on event input 30.
            #[inline(always)]
            pub fn im30(&self) -> IM30_R {
                IM30_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - CPU wakeup with interrupt mask on event input 31.
            #[inline(always)]
            pub fn im31(&self) -> IM31_R {
                IM31_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&mut self) -> IM_W {
                IM_W { w: self }
            }
            ///Bit 0 - CPU wakeup with interrupt mask on event input 0.
            #[inline(always)]
            pub fn im0(&mut self) -> IM0_W {
                IM0_W { w: self }
            }
            ///Bit 1 - CPU wakeup with interrupt mask on event input 1.
            #[inline(always)]
            pub fn im1(&mut self) -> IM1_W {
                IM1_W { w: self }
            }
            ///Bit 2 - CPU wakeup with interrupt mask on event input 2.
            #[inline(always)]
            pub fn im2(&mut self) -> IM2_W {
                IM2_W { w: self }
            }
            ///Bit 3 - CPU wakeup with interrupt mask on event input 3.
            #[inline(always)]
            pub fn im3(&mut self) -> IM3_W {
                IM3_W { w: self }
            }
            ///Bit 4 - CPU wakeup with interrupt mask on event input 4.
            #[inline(always)]
            pub fn im4(&mut self) -> IM4_W {
                IM4_W { w: self }
            }
            ///Bit 5 - CPU wakeup with interrupt mask on event input 5.
            #[inline(always)]
            pub fn im5(&mut self) -> IM5_W {
                IM5_W { w: self }
            }
            ///Bit 6 - CPU wakeup with interrupt mask on event input 6.
            #[inline(always)]
            pub fn im6(&mut self) -> IM6_W {
                IM6_W { w: self }
            }
            ///Bit 7 - CPU wakeup with interrupt mask on event input 7.
            #[inline(always)]
            pub fn im7(&mut self) -> IM7_W {
                IM7_W { w: self }
            }
            ///Bit 8 - CPU wakeup with interrupt mask on event input 8.
            #[inline(always)]
            pub fn im8(&mut self) -> IM8_W {
                IM8_W { w: self }
            }
            ///Bit 9 - CPU wakeup with interrupt mask on event input 9.
            #[inline(always)]
            pub fn im9(&mut self) -> IM9_W {
                IM9_W { w: self }
            }
            ///Bit 10 - CPU wakeup with interrupt mask on event input 10.
            #[inline(always)]
            pub fn im10(&mut self) -> IM10_W {
                IM10_W { w: self }
            }
            ///Bit 11 - CPU wakeup with interrupt mask on event input 11.
            #[inline(always)]
            pub fn im11(&mut self) -> IM11_W {
                IM11_W { w: self }
            }
            ///Bit 12 - CPU wakeup with interrupt mask on event input 12.
            #[inline(always)]
            pub fn im12(&mut self) -> IM12_W {
                IM12_W { w: self }
            }
            ///Bit 13 - CPU wakeup with interrupt mask on event input 13.
            #[inline(always)]
            pub fn im13(&mut self) -> IM13_W {
                IM13_W { w: self }
            }
            ///Bit 14 - CPU wakeup with interrupt mask on event input 14.
            #[inline(always)]
            pub fn im14(&mut self) -> IM14_W {
                IM14_W { w: self }
            }
            ///Bit 15 - CPU wakeup with interrupt mask on event input 15.
            #[inline(always)]
            pub fn im15(&mut self) -> IM15_W {
                IM15_W { w: self }
            }
            ///Bit 16 - CPU wakeup with interrupt mask on event input 16.
            #[inline(always)]
            pub fn im16(&mut self) -> IM16_W {
                IM16_W { w: self }
            }
            ///Bit 17 - CPU wakeup with interrupt mask on event input 17.
            #[inline(always)]
            pub fn im17(&mut self) -> IM17_W {
                IM17_W { w: self }
            }
            ///Bit 18 - CPU wakeup with interrupt mask on event input 18.
            #[inline(always)]
            pub fn im18(&mut self) -> IM18_W {
                IM18_W { w: self }
            }
            ///Bit 19 - CPU wakeup with interrupt mask on event input 19.
            #[inline(always)]
            pub fn im19(&mut self) -> IM19_W {
                IM19_W { w: self }
            }
            ///Bit 20 - CPU wakeup with interrupt mask on event input 20.
            #[inline(always)]
            pub fn im20(&mut self) -> IM20_W {
                IM20_W { w: self }
            }
            ///Bit 21 - CPU wakeup with interrupt mask on event input 21.
            #[inline(always)]
            pub fn im21(&mut self) -> IM21_W {
                IM21_W { w: self }
            }
            ///Bit 22 - CPU wakeup with interrupt mask on event input 22.
            #[inline(always)]
            pub fn im22(&mut self) -> IM22_W {
                IM22_W { w: self }
            }
            ///Bit 23 - CPU wakeup with interrupt mask on event input 23.
            #[inline(always)]
            pub fn im23(&mut self) -> IM23_W {
                IM23_W { w: self }
            }
            ///Bit 24 - CPU wakeup with interrupt mask on event input 24.
            #[inline(always)]
            pub fn im24(&mut self) -> IM24_W {
                IM24_W { w: self }
            }
            ///Bit 25 - CPU wakeup with interrupt mask on event input 25.
            #[inline(always)]
            pub fn im25(&mut self) -> IM25_W {
                IM25_W { w: self }
            }
            ///Bit 26 - CPU wakeup with interrupt mask on event input 26.
            #[inline(always)]
            pub fn im26(&mut self) -> IM26_W {
                IM26_W { w: self }
            }
            ///Bit 27 - CPU wakeup with interrupt mask on event input 27.
            #[inline(always)]
            pub fn im27(&mut self) -> IM27_W {
                IM27_W { w: self }
            }
            ///Bit 28 - CPU wakeup with interrupt mask on event input 28.
            #[inline(always)]
            pub fn im28(&mut self) -> IM28_W {
                IM28_W { w: self }
            }
            ///Bit 29 - CPU wakeup with interrupt mask on event input 29.
            #[inline(always)]
            pub fn im29(&mut self) -> IM29_W {
                IM29_W { w: self }
            }
            ///Bit 30 - CPU wakeup with interrupt mask on event input 30.
            #[inline(always)]
            pub fn im30(&mut self) -> IM30_W {
                IM30_W { w: self }
            }
            ///Bit 31 - CPU wakeup with interrupt mask on event input 31.
            #[inline(always)]
            pub fn im31(&mut self) -> IM31_W {
                IM31_W { w: self }
            }
        }
    }
    ///CPUm wakeup with interrupt mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2imr1](c2imr1) module
    pub type C2IMR1 = crate::Reg<u32, _C2IMR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2IMR1;
    ///`read()` method returns [c2imr1::R](c2imr1::R) reader structure
    impl crate::Readable for C2IMR1 {}
    ///`write(|w| ..)` method takes [c2imr1::W](c2imr1::W) writer structure
    impl crate::Writable for C2IMR1 {}
    ///CPUm wakeup with interrupt mask register
    pub mod c2imr1 {
        ///Reader of register C2IMR1
        pub type R = crate::R<u32, super::C2IMR1>;
        ///Writer for register C2IMR1
        pub type W = crate::W<u32, super::C2IMR1>;
        ///Register C2IMR1 `reset()`'s with value 0x7fc0_0000
        impl crate::ResetValue for super::C2IMR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x7fc0_0000
            }
        }
        ///Reader of field `IM`
        pub type IM_R = crate::R<u32, u32>;
        ///Write proxy for field `IM`
        pub struct IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&self) -> IM_R {
                IM_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&mut self) -> IM_W {
                IM_W { w: self }
            }
        }
    }
    ///CPUm wakeup with event mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1emr1](c1emr1) module
    pub type C1EMR1 = crate::Reg<u32, _C1EMR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1EMR1;
    ///`read()` method returns [c1emr1::R](c1emr1::R) reader structure
    impl crate::Readable for C1EMR1 {}
    ///`write(|w| ..)` method takes [c1emr1::W](c1emr1::W) writer structure
    impl crate::Writable for C1EMR1 {}
    ///CPUm wakeup with event mask register
    pub mod c1emr1 {
        ///Reader of register C1EMR1
        pub type R = crate::R<u32, super::C1EMR1>;
        ///Writer for register C1EMR1
        pub type W = crate::W<u32, super::C1EMR1>;
        ///Register C1EMR1 `reset()`'s with value 0
        impl crate::ResetValue for super::C1EMR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EM0_15`
        pub type EM0_15_R = crate::R<u16, u16>;
        ///Write proxy for field `EM0_15`
        pub struct EM0_15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EM0_15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `EM17_21`
        pub type EM17_21_R = crate::R<u8, u8>;
        ///Write proxy for field `EM17_21`
        pub struct EM17_21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EM17_21_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 17)) | (((value as u32) & 0x1f) << 17);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em0_15(&self) -> EM0_15_R {
                EM0_15_R::new((self.bits & 0xffff) as u16)
            }
            ///Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em17_21(&self) -> EM17_21_R {
                EM17_21_R::new(((self.bits >> 17) & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em0_15(&mut self) -> EM0_15_W {
                EM0_15_W { w: self }
            }
            ///Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em17_21(&mut self) -> EM17_21_W {
                EM17_21_W { w: self }
            }
        }
    }
    ///CPUm wakeup with event mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2emr1](c2emr1) module
    pub type C2EMR1 = crate::Reg<u32, _C2EMR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2EMR1;
    ///`read()` method returns [c2emr1::R](c2emr1::R) reader structure
    impl crate::Readable for C2EMR1 {}
    ///`write(|w| ..)` method takes [c2emr1::W](c2emr1::W) writer structure
    impl crate::Writable for C2EMR1 {}
    ///CPUm wakeup with event mask register
    pub mod c2emr1 {
        ///Reader of register C2EMR1
        pub type R = crate::R<u32, super::C2EMR1>;
        ///Writer for register C2EMR1
        pub type W = crate::W<u32, super::C2EMR1>;
        ///Register C2EMR1 `reset()`'s with value 0
        impl crate::ResetValue for super::C2EMR1 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EM0_15`
        pub type EM0_15_R = crate::R<u16, u16>;
        ///Write proxy for field `EM0_15`
        pub struct EM0_15_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EM0_15_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `EM17_21`
        pub type EM17_21_R = crate::R<u8, u8>;
        ///Write proxy for field `EM17_21`
        pub struct EM17_21_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EM17_21_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 17)) | (((value as u32) & 0x1f) << 17);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em0_15(&self) -> EM0_15_R {
                EM0_15_R::new((self.bits & 0xffff) as u16)
            }
            ///Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em17_21(&self) -> EM17_21_R {
                EM17_21_R::new(((self.bits >> 17) & 0x1f) as u8)
            }
        }
        impl W {
            ///Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em0_15(&mut self) -> EM0_15_W {
                EM0_15_W { w: self }
            }
            ///Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em17_21(&mut self) -> EM17_21_W {
                EM17_21_W { w: self }
            }
        }
    }
    ///CPUm wakeup with interrupt mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1imr2](c1imr2) module
    pub type C1IMR2 = crate::Reg<u32, _C1IMR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1IMR2;
    ///`read()` method returns [c1imr2::R](c1imr2::R) reader structure
    impl crate::Readable for C1IMR2 {}
    ///`write(|w| ..)` method takes [c1imr2::W](c1imr2::W) writer structure
    impl crate::Writable for C1IMR2 {}
    ///CPUm wakeup with interrupt mask register
    pub mod c1imr2 {
        ///Reader of register C1IMR2
        pub type R = crate::R<u32, super::C1IMR2>;
        ///Writer for register C1IMR2
        pub type W = crate::W<u32, super::C1IMR2>;
        ///Register C1IMR2 `reset()`'s with value 0x0001_fcfd
        impl crate::ResetValue for super::C1IMR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0001_fcfd
            }
        }
        ///Reader of field `IM`
        pub type IM_R = crate::R<u32, u32>;
        ///Write proxy for field `IM`
        pub struct IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0001_ffff) | ((value as u32) & 0x0001_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&self) -> IM_R {
                IM_R::new((self.bits & 0x0001_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&mut self) -> IM_W {
                IM_W { w: self }
            }
        }
    }
    ///CPUm wakeup with interrupt mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2imr2](c2imr2) module
    pub type C2IMR2 = crate::Reg<u32, _C2IMR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2IMR2;
    ///`read()` method returns [c2imr2::R](c2imr2::R) reader structure
    impl crate::Readable for C2IMR2 {}
    ///`write(|w| ..)` method takes [c2imr2::W](c2imr2::W) writer structure
    impl crate::Writable for C2IMR2 {}
    ///CPUm wakeup with interrupt mask register
    pub mod c2imr2 {
        ///Reader of register C2IMR2
        pub type R = crate::R<u32, super::C2IMR2>;
        ///Writer for register C2IMR2
        pub type W = crate::W<u32, super::C2IMR2>;
        ///Register C2IMR2 `reset()`'s with value 0x0001_fcfd
        impl crate::ResetValue for super::C2IMR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x0001_fcfd
            }
        }
        ///Reader of field `IM`
        pub type IM_R = crate::R<u32, u32>;
        ///Write proxy for field `IM`
        pub struct IM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> IM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0001_ffff) | ((value as u32) & 0x0001_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&self) -> IM_R {
                IM_R::new((self.bits & 0x0001_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input
            #[inline(always)]
            pub fn im(&mut self) -> IM_W {
                IM_W { w: self }
            }
        }
    }
    ///CPUm wakeup with event mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c1emr2](c1emr2) module
    pub type C1EMR2 = crate::Reg<u32, _C1EMR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C1EMR2;
    ///`read()` method returns [c1emr2::R](c1emr2::R) reader structure
    impl crate::Readable for C1EMR2 {}
    ///`write(|w| ..)` method takes [c1emr2::W](c1emr2::W) writer structure
    impl crate::Writable for C1EMR2 {}
    ///CPUm wakeup with event mask register
    pub mod c1emr2 {
        ///Reader of register C1EMR2
        pub type R = crate::R<u32, super::C1EMR2>;
        ///Writer for register C1EMR2
        pub type W = crate::W<u32, super::C1EMR2>;
        ///Register C1EMR2 `reset()`'s with value 0
        impl crate::ResetValue for super::C1EMR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EM`
        pub type EM_R = crate::R<u8, u8>;
        ///Write proxy for field `EM`
        pub struct EM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        impl R {
            ///Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em(&self) -> EM_R {
                EM_R::new(((self.bits >> 8) & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em(&mut self) -> EM_W {
                EM_W { w: self }
            }
        }
    }
    ///CPUm wakeup with event mask register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [c2emr2](c2emr2) module
    pub type C2EMR2 = crate::Reg<u32, _C2EMR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _C2EMR2;
    ///`read()` method returns [c2emr2::R](c2emr2::R) reader structure
    impl crate::Readable for C2EMR2 {}
    ///`write(|w| ..)` method takes [c2emr2::W](c2emr2::W) writer structure
    impl crate::Writable for C2EMR2 {}
    ///CPUm wakeup with event mask register
    pub mod c2emr2 {
        ///Reader of register C2EMR2
        pub type R = crate::R<u32, super::C2EMR2>;
        ///Writer for register C2EMR2
        pub type W = crate::W<u32, super::C2EMR2>;
        ///Register C2EMR2 `reset()`'s with value 0
        impl crate::ResetValue for super::C2EMR2 {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EM`
        pub type EM_R = crate::R<u8, u8>;
        ///Write proxy for field `EM`
        pub struct EM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
                self.w
            }
        }
        impl R {
            ///Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em(&self) -> EM_R {
                EM_R::new(((self.bits >> 8) & 0x03) as u8)
            }
        }
        impl W {
            ///Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input
            #[inline(always)]
            pub fn em(&mut self) -> EM_W {
                EM_W { w: self }
            }
        }
    }
    ///Hardware configuration registers
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr5](hwcfgr5) module
    pub type HWCFGR5 = crate::Reg<u32, _HWCFGR5>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR5;
    ///`read()` method returns [hwcfgr5::R](hwcfgr5::R) reader structure
    impl crate::Readable for HWCFGR5 {}
    ///Hardware configuration registers
    pub mod hwcfgr5 {
        ///Reader of register HWCFGR5
        pub type R = crate::R<u32, super::HWCFGR5>;
        ///Reader of field `CPUEVENT`
        pub type CPUEVENT_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - HW configuration CPU event generation
            #[inline(always)]
            pub fn cpuevent(&self) -> CPUEVENT_R {
                CPUEVENT_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///Hardware configuration registers
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr6](hwcfgr6) module
    pub type HWCFGR6 = crate::Reg<u32, _HWCFGR6>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR6;
    ///`read()` method returns [hwcfgr6::R](hwcfgr6::R) reader structure
    impl crate::Readable for HWCFGR6 {}
    ///Hardware configuration registers
    pub mod hwcfgr6 {
        ///Reader of register HWCFGR6
        pub type R = crate::R<u32, super::HWCFGR6>;
        ///Reader of field `CPUEVENT`
        pub type CPUEVENT_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - HW configuration CPU event generation
            #[inline(always)]
            pub fn cpuevent(&self) -> CPUEVENT_R {
                CPUEVENT_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///EXTI Hardware configuration registers
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr7](hwcfgr7) module
    pub type HWCFGR7 = crate::Reg<u32, _HWCFGR7>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR7;
    ///`read()` method returns [hwcfgr7::R](hwcfgr7::R) reader structure
    impl crate::Readable for HWCFGR7 {}
    ///EXTI Hardware configuration registers
    pub mod hwcfgr7 {
        ///Reader of register HWCFGR7
        pub type R = crate::R<u32, super::HWCFGR7>;
        ///Reader of field `CPUEVENT`
        pub type CPUEVENT_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - HW configuration CPU event generation
            #[inline(always)]
            pub fn cpuevent(&self) -> CPUEVENT_R {
                CPUEVENT_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///Hardware configuration registers
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr2](hwcfgr2) module
    pub type HWCFGR2 = crate::Reg<u32, _HWCFGR2>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR2;
    ///`read()` method returns [hwcfgr2::R](hwcfgr2::R) reader structure
    impl crate::Readable for HWCFGR2 {}
    ///Hardware configuration registers
    pub mod hwcfgr2 {
        ///Reader of register HWCFGR2
        pub type R = crate::R<u32, super::HWCFGR2>;
        ///Reader of field `EVENT_TRG`
        pub type EVENT_TRG_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - HW configuration event trigger type
            #[inline(always)]
            pub fn event_trg(&self) -> EVENT_TRG_R {
                EVENT_TRG_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///Hardware configuration registers
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr3](hwcfgr3) module
    pub type HWCFGR3 = crate::Reg<u32, _HWCFGR3>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR3;
    ///`read()` method returns [hwcfgr3::R](hwcfgr3::R) reader structure
    impl crate::Readable for HWCFGR3 {}
    ///Hardware configuration registers
    pub mod hwcfgr3 {
        ///Reader of register HWCFGR3
        pub type R = crate::R<u32, super::HWCFGR3>;
        ///Reader of field `EVENT_TRG`
        pub type EVENT_TRG_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - HW configuration event trigger type
            #[inline(always)]
            pub fn event_trg(&self) -> EVENT_TRG_R {
                EVENT_TRG_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///Hardware configuration registers
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr4](hwcfgr4) module
    pub type HWCFGR4 = crate::Reg<u32, _HWCFGR4>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR4;
    ///`read()` method returns [hwcfgr4::R](hwcfgr4::R) reader structure
    impl crate::Readable for HWCFGR4 {}
    ///Hardware configuration registers
    pub mod hwcfgr4 {
        ///Reader of register HWCFGR4
        pub type R = crate::R<u32, super::HWCFGR4>;
        ///Reader of field `EVENT_TRG`
        pub type EVENT_TRG_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - HW configuration event trigger type
            #[inline(always)]
            pub fn event_trg(&self) -> EVENT_TRG_R {
                EVENT_TRG_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///Hardware configuration register 1
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [hwcfgr1](hwcfgr1) module
    pub type HWCFGR1 = crate::Reg<u32, _HWCFGR1>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _HWCFGR1;
    ///`read()` method returns [hwcfgr1::R](hwcfgr1::R) reader structure
    impl crate::Readable for HWCFGR1 {}
    ///Hardware configuration register 1
    pub mod hwcfgr1 {
        ///Reader of register HWCFGR1
        pub type R = crate::R<u32, super::HWCFGR1>;
        ///Reader of field `NBEVENTS`
        pub type NBEVENTS_R = crate::R<u8, u8>;
        ///Reader of field `NBCPUS`
        pub type NBCPUS_R = crate::R<u8, u8>;
        ///Reader of field `CPUEVTEN`
        pub type CPUEVTEN_R = crate::R<u8, u8>;
        impl R {
            ///Bits 0:7 - HW configuration number of event
            #[inline(always)]
            pub fn nbevents(&self) -> NBEVENTS_R {
                NBEVENTS_R::new((self.bits & 0xff) as u8)
            }
            ///Bits 8:11 - HW configuration number of CPUs
            #[inline(always)]
            pub fn nbcpus(&self) -> NBCPUS_R {
                NBCPUS_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            ///Bits 12:15 - HW configuration of CPU(m) event output enable
            #[inline(always)]
            pub fn cpuevten(&self) -> CPUEVTEN_R {
                CPUEVTEN_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
        }
    }
    ///EXTI IP Version register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [verr](verr) module
    pub type VERR = crate::Reg<u32, _VERR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _VERR;
    ///`read()` method returns [verr::R](verr::R) reader structure
    impl crate::Readable for VERR {}
    ///EXTI IP Version register
    pub mod verr {
        ///Reader of register VERR
        pub type R = crate::R<u32, super::VERR>;
        ///Reader of field `MINREV`
        pub type MINREV_R = crate::R<u8, u8>;
        ///Reader of field `MAJREV`
        pub type MAJREV_R = crate::R<u8, u8>;
        impl R {
            ///Bits 0:3 - Minor Revision number
            #[inline(always)]
            pub fn minrev(&self) -> MINREV_R {
                MINREV_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:7 - Major Revision number
            #[inline(always)]
            pub fn majrev(&self) -> MAJREV_R {
                MAJREV_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
        }
    }
    ///Identification register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ipidr](ipidr) module
    pub type IPIDR = crate::Reg<u32, _IPIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _IPIDR;
    ///`read()` method returns [ipidr::R](ipidr::R) reader structure
    impl crate::Readable for IPIDR {}
    ///Identification register
    pub mod ipidr {
        ///Reader of register IPIDR
        pub type R = crate::R<u32, super::IPIDR>;
        ///Reader of field `IPID`
        pub type IPID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - IP Identification
            #[inline(always)]
            pub fn ipid(&self) -> IPID_R {
                IPID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
    ///Size ID register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [sidr](sidr) module
    pub type SIDR = crate::Reg<u32, _SIDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _SIDR;
    ///`read()` method returns [sidr::R](sidr::R) reader structure
    impl crate::Readable for SIDR {}
    ///Size ID register
    pub mod sidr {
        ///Reader of register SIDR
        pub type R = crate::R<u32, super::SIDR>;
        ///Reader of field `SID`
        pub type SID_R = crate::R<u32, u32>;
        impl R {
            ///Bits 0:31 - Size Identification
            #[inline(always)]
            pub fn sid(&self) -> SID_R {
                SID_R::new((self.bits & 0xffff_ffff) as u32)
            }
        }
    }
}
///Clock recovery system
pub struct CRS {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for CRS {}
impl CRS {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const crs::RegisterBlock {
        0x4000_6000 as *const _
    }
}
impl Deref for CRS {
    type Target = crs::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*CRS::ptr() }
    }
}
///Clock recovery system
pub mod crs {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - CRS control register
        pub cr: CR,
        ///0x04 - CRS configuration register
        pub cfgr: CFGR,
        ///0x08 - CRS interrupt and status register
        pub isr: ISR,
        ///0x0c - CRS interrupt flag clear register
        pub icr: ICR,
    }
    ///CRS control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cr](cr) module
    pub type CR = crate::Reg<u32, _CR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CR;
    ///`read()` method returns [cr::R](cr::R) reader structure
    impl crate::Readable for CR {}
    ///`write(|w| ..)` method takes [cr::W](cr::W) writer structure
    impl crate::Writable for CR {}
    ///CRS control register
    pub mod cr {
        ///Reader of register CR
        pub type R = crate::R<u32, super::CR>;
        ///Writer for register CR
        pub type W = crate::W<u32, super::CR>;
        ///Register CR `reset()`'s with value 0x2000
        impl crate::ResetValue for super::CR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x2000
            }
        }
        ///Reader of field `SYNCOKIE`
        pub type SYNCOKIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SYNCOKIE`
        pub struct SYNCOKIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCOKIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `SYNCWARNIE`
        pub type SYNCWARNIE_R = crate::R<bool, bool>;
        ///Write proxy for field `SYNCWARNIE`
        pub struct SYNCWARNIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCWARNIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ERRIE`
        pub type ERRIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRIE`
        pub struct ERRIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ESYNCIE`
        pub type ESYNCIE_R = crate::R<bool, bool>;
        ///Write proxy for field `ESYNCIE`
        pub struct ESYNCIE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ESYNCIE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `CEN`
        pub type CEN_R = crate::R<bool, bool>;
        ///Write proxy for field `CEN`
        pub struct CEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `AUTOTRIMEN`
        pub type AUTOTRIMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `AUTOTRIMEN`
        pub struct AUTOTRIMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> AUTOTRIMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `SWSYNC`
        pub type SWSYNC_R = crate::R<bool, bool>;
        ///Write proxy for field `SWSYNC`
        pub struct SWSYNC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SWSYNC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `TRIM`
        pub type TRIM_R = crate::R<u8, u8>;
        ///Write proxy for field `TRIM`
        pub struct TRIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TRIM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x3f << 8)) | (((value as u32) & 0x3f) << 8);
                self.w
            }
        }
        impl R {
            ///Bit 0 - SYNC event OK interrupt enable
            #[inline(always)]
            pub fn syncokie(&self) -> SYNCOKIE_R {
                SYNCOKIE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - SYNC warning interrupt enable
            #[inline(always)]
            pub fn syncwarnie(&self) -> SYNCWARNIE_R {
                SYNCWARNIE_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Synchronization or trimming error interrupt enable
            #[inline(always)]
            pub fn errie(&self) -> ERRIE_R {
                ERRIE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Expected SYNC interrupt enable
            #[inline(always)]
            pub fn esyncie(&self) -> ESYNCIE_R {
                ESYNCIE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 5 - Frequency error counter enable
            #[inline(always)]
            pub fn cen(&self) -> CEN_R {
                CEN_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Automatic trimming enable
            #[inline(always)]
            pub fn autotrimen(&self) -> AUTOTRIMEN_R {
                AUTOTRIMEN_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Automatic trimming enable
            #[inline(always)]
            pub fn swsync(&self) -> SWSYNC_R {
                SWSYNC_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bits 8:13 - HSI48 oscillator smooth trimming
            #[inline(always)]
            pub fn trim(&self) -> TRIM_R {
                TRIM_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
        }
        impl W {
            ///Bit 0 - SYNC event OK interrupt enable
            #[inline(always)]
            pub fn syncokie(&mut self) -> SYNCOKIE_W {
                SYNCOKIE_W { w: self }
            }
            ///Bit 1 - SYNC warning interrupt enable
            #[inline(always)]
            pub fn syncwarnie(&mut self) -> SYNCWARNIE_W {
                SYNCWARNIE_W { w: self }
            }
            ///Bit 2 - Synchronization or trimming error interrupt enable
            #[inline(always)]
            pub fn errie(&mut self) -> ERRIE_W {
                ERRIE_W { w: self }
            }
            ///Bit 3 - Expected SYNC interrupt enable
            #[inline(always)]
            pub fn esyncie(&mut self) -> ESYNCIE_W {
                ESYNCIE_W { w: self }
            }
            ///Bit 5 - Frequency error counter enable
            #[inline(always)]
            pub fn cen(&mut self) -> CEN_W {
                CEN_W { w: self }
            }
            ///Bit 6 - Automatic trimming enable
            #[inline(always)]
            pub fn autotrimen(&mut self) -> AUTOTRIMEN_W {
                AUTOTRIMEN_W { w: self }
            }
            ///Bit 7 - Automatic trimming enable
            #[inline(always)]
            pub fn swsync(&mut self) -> SWSYNC_W {
                SWSYNC_W { w: self }
            }
            ///Bits 8:13 - HSI48 oscillator smooth trimming
            #[inline(always)]
            pub fn trim(&mut self) -> TRIM_W {
                TRIM_W { w: self }
            }
        }
    }
    ///CRS configuration register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cfgr](cfgr) module
    pub type CFGR = crate::Reg<u32, _CFGR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CFGR;
    ///`read()` method returns [cfgr::R](cfgr::R) reader structure
    impl crate::Readable for CFGR {}
    ///`write(|w| ..)` method takes [cfgr::W](cfgr::W) writer structure
    impl crate::Writable for CFGR {}
    ///CRS configuration register
    pub mod cfgr {
        ///Reader of register CFGR
        pub type R = crate::R<u32, super::CFGR>;
        ///Writer for register CFGR
        pub type W = crate::W<u32, super::CFGR>;
        ///Register CFGR `reset()`'s with value 0x2022_bb7f
        impl crate::ResetValue for super::CFGR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x2022_bb7f
            }
        }
        ///Reader of field `RELOAD`
        pub type RELOAD_R = crate::R<u16, u16>;
        ///Write proxy for field `RELOAD`
        pub struct RELOAD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RELOAD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
                self.w
            }
        }
        ///Reader of field `FELIM`
        pub type FELIM_R = crate::R<u8, u8>;
        ///Write proxy for field `FELIM`
        pub struct FELIM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FELIM_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
                self.w
            }
        }
        ///Reader of field `SYNCDIV`
        pub type SYNCDIV_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNCDIV`
        pub struct SYNCDIV_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCDIV_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x07 << 24)) | (((value as u32) & 0x07) << 24);
                self.w
            }
        }
        ///Reader of field `SYNCSRC`
        pub type SYNCSRC_R = crate::R<u8, u8>;
        ///Write proxy for field `SYNCSRC`
        pub struct SYNCSRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCSRC_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
                self.w
            }
        }
        ///Reader of field `SYNCPOL`
        pub type SYNCPOL_R = crate::R<bool, bool>;
        ///Write proxy for field `SYNCPOL`
        pub struct SYNCPOL_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCPOL_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:15 - Counter reload value
            #[inline(always)]
            pub fn reload(&self) -> RELOAD_R {
                RELOAD_R::new((self.bits & 0xffff) as u16)
            }
            ///Bits 16:23 - Frequency error limit
            #[inline(always)]
            pub fn felim(&self) -> FELIM_R {
                FELIM_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            ///Bits 24:26 - SYNCDIV
            #[inline(always)]
            pub fn syncdiv(&self) -> SYNCDIV_R {
                SYNCDIV_R::new(((self.bits >> 24) & 0x07) as u8)
            }
            ///Bits 28:29 - SYNC signal source selection
            #[inline(always)]
            pub fn syncsrc(&self) -> SYNCSRC_R {
                SYNCSRC_R::new(((self.bits >> 28) & 0x03) as u8)
            }
            ///Bit 31 - SYNC polarity selection
            #[inline(always)]
            pub fn syncpol(&self) -> SYNCPOL_R {
                SYNCPOL_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:15 - Counter reload value
            #[inline(always)]
            pub fn reload(&mut self) -> RELOAD_W {
                RELOAD_W { w: self }
            }
            ///Bits 16:23 - Frequency error limit
            #[inline(always)]
            pub fn felim(&mut self) -> FELIM_W {
                FELIM_W { w: self }
            }
            ///Bits 24:26 - SYNCDIV
            #[inline(always)]
            pub fn syncdiv(&mut self) -> SYNCDIV_W {
                SYNCDIV_W { w: self }
            }
            ///Bits 28:29 - SYNC signal source selection
            #[inline(always)]
            pub fn syncsrc(&mut self) -> SYNCSRC_W {
                SYNCSRC_W { w: self }
            }
            ///Bit 31 - SYNC polarity selection
            #[inline(always)]
            pub fn syncpol(&mut self) -> SYNCPOL_W {
                SYNCPOL_W { w: self }
            }
        }
    }
    ///CRS interrupt and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [isr](isr) module
    pub type ISR = crate::Reg<u32, _ISR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISR;
    ///`read()` method returns [isr::R](isr::R) reader structure
    impl crate::Readable for ISR {}
    ///CRS interrupt and status register
    pub mod isr {
        ///Reader of register ISR
        pub type R = crate::R<u32, super::ISR>;
        ///Reader of field `SYNCOKF`
        pub type SYNCOKF_R = crate::R<bool, bool>;
        ///Reader of field `SYNCWARNF`
        pub type SYNCWARNF_R = crate::R<bool, bool>;
        ///Reader of field `ERRF`
        pub type ERRF_R = crate::R<bool, bool>;
        ///Reader of field `ESYNCF`
        pub type ESYNCF_R = crate::R<bool, bool>;
        ///Reader of field `SYNCERR`
        pub type SYNCERR_R = crate::R<bool, bool>;
        ///Reader of field `SYNCMISS`
        pub type SYNCMISS_R = crate::R<bool, bool>;
        ///Reader of field `TRIMOVF`
        pub type TRIMOVF_R = crate::R<bool, bool>;
        ///Reader of field `FEDIR`
        pub type FEDIR_R = crate::R<bool, bool>;
        ///Reader of field `FECAP`
        pub type FECAP_R = crate::R<u16, u16>;
        impl R {
            ///Bit 0 - SYNC event OK flag
            #[inline(always)]
            pub fn syncokf(&self) -> SYNCOKF_R {
                SYNCOKF_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - SYNC warning flag
            #[inline(always)]
            pub fn syncwarnf(&self) -> SYNCWARNF_R {
                SYNCWARNF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Error flag
            #[inline(always)]
            pub fn errf(&self) -> ERRF_R {
                ERRF_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Expected SYNC flag
            #[inline(always)]
            pub fn esyncf(&self) -> ESYNCF_R {
                ESYNCF_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 8 - SYNC error
            #[inline(always)]
            pub fn syncerr(&self) -> SYNCERR_R {
                SYNCERR_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - SYNC missed
            #[inline(always)]
            pub fn syncmiss(&self) -> SYNCMISS_R {
                SYNCMISS_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - Trimming overflow or underflow
            #[inline(always)]
            pub fn trimovf(&self) -> TRIMOVF_R {
                TRIMOVF_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 15 - Frequency error direction
            #[inline(always)]
            pub fn fedir(&self) -> FEDIR_R {
                FEDIR_R::new(((self.bits >> 15) & 0x01) != 0)
            }
            ///Bits 16:31 - Frequency error capture
            #[inline(always)]
            pub fn fecap(&self) -> FECAP_R {
                FECAP_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
    }
    ///CRS interrupt flag clear register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [icr](icr) module
    pub type ICR = crate::Reg<u32, _ICR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ICR;
    ///`read()` method returns [icr::R](icr::R) reader structure
    impl crate::Readable for ICR {}
    ///`write(|w| ..)` method takes [icr::W](icr::W) writer structure
    impl crate::Writable for ICR {}
    ///CRS interrupt flag clear register
    pub mod icr {
        ///Reader of register ICR
        pub type R = crate::R<u32, super::ICR>;
        ///Writer for register ICR
        pub type W = crate::W<u32, super::ICR>;
        ///Register ICR `reset()`'s with value 0
        impl crate::ResetValue for super::ICR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `SYNCOKC`
        pub type SYNCOKC_R = crate::R<bool, bool>;
        ///Write proxy for field `SYNCOKC`
        pub struct SYNCOKC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCOKC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `SYNCWARNC`
        pub type SYNCWARNC_R = crate::R<bool, bool>;
        ///Write proxy for field `SYNCWARNC`
        pub struct SYNCWARNC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SYNCWARNC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `ERRC`
        pub type ERRC_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRC`
        pub struct ERRC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `ESYNCC`
        pub type ESYNCC_R = crate::R<bool, bool>;
        ///Write proxy for field `ESYNCC`
        pub struct ESYNCC_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ESYNCC_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
                self.w
            }
        }
        impl R {
            ///Bit 0 - SYNC event OK clear flag
            #[inline(always)]
            pub fn syncokc(&self) -> SYNCOKC_R {
                SYNCOKC_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - warning clear flag
            #[inline(always)]
            pub fn syncwarnc(&self) -> SYNCWARNC_R {
                SYNCWARNC_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Error clear flag
            #[inline(always)]
            pub fn errc(&self) -> ERRC_R {
                ERRC_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Expected SYNC clear flag
            #[inline(always)]
            pub fn esyncc(&self) -> ESYNCC_R {
                ESYNCC_R::new(((self.bits >> 3) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - SYNC event OK clear flag
            #[inline(always)]
            pub fn syncokc(&mut self) -> SYNCOKC_W {
                SYNCOKC_W { w: self }
            }
            ///Bit 1 - warning clear flag
            #[inline(always)]
            pub fn syncwarnc(&mut self) -> SYNCWARNC_W {
                SYNCWARNC_W { w: self }
            }
            ///Bit 2 - Error clear flag
            #[inline(always)]
            pub fn errc(&mut self) -> ERRC_W {
                ERRC_W { w: self }
            }
            ///Bit 3 - Expected SYNC clear flag
            #[inline(always)]
            pub fn esyncc(&mut self) -> ESYNCC_W {
                ESYNCC_W { w: self }
            }
        }
    }
}
///Universal serial bus full-speed device interface
pub struct USB {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for USB {}
impl USB {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const usb::RegisterBlock {
        0x4000_6800 as *const _
    }
}
impl Deref for USB {
    type Target = usb::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*USB::ptr() }
    }
}
///Universal serial bus full-speed device interface
pub mod usb {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - endpoint 0 register
        pub ep0r: EP0R,
        _reserved1: [u8; 2usize],
        ///0x04 - endpoint 1 register
        pub ep1r: EP1R,
        _reserved2: [u8; 2usize],
        ///0x08 - endpoint 2 register
        pub ep2r: EP2R,
        _reserved3: [u8; 2usize],
        ///0x0c - endpoint 3 register
        pub ep3r: EP3R,
        _reserved4: [u8; 2usize],
        ///0x10 - endpoint 4 register
        pub ep4r: EP4R,
        _reserved5: [u8; 2usize],
        ///0x14 - endpoint 5 register
        pub ep5r: EP5R,
        _reserved6: [u8; 2usize],
        ///0x18 - endpoint 6 register
        pub ep6r: EP6R,
        _reserved7: [u8; 2usize],
        ///0x1c - endpoint 7 register
        pub ep7r: EP7R,
        _reserved8: [u8; 34usize],
        ///0x40 - control register
        pub cntr: CNTR,
        _reserved9: [u8; 2usize],
        ///0x44 - interrupt status register
        pub istr: ISTR,
        _reserved10: [u8; 2usize],
        ///0x48 - frame number register
        pub fnr: FNR,
        _reserved11: [u8; 2usize],
        ///0x4c - device address
        pub daddr: DADDR,
        _reserved12: [u8; 2usize],
        ///0x50 - Buffer table address
        pub btable: BTABLE,
        ///0x52 - Transmission byte count 0
        pub count0_tx: COUNT0_TX,
        _reserved_14_lpmcsr: [u8; 2usize],
        ///0x56 - Reception byte count 0
        pub count0_rx: COUNT0_RX,
        ///0x58 - Battery charging detector(
        pub bcdr: BCDR,
        ///0x5a - Transmission byte count 0
        pub count1_tx: COUNT1_TX,
        ///0x5c - Reception buffer address 0
        pub addr1_rx: ADDR1_RX,
        ///0x5e - Reception byte count 0
        pub count1_rx: COUNT1_RX,
        _reserved20: [u8; 2usize],
        ///0x62 - Transmission byte count 0
        pub count2_tx: COUNT2_TX,
        ///0x64 - Reception buffer address 0
        pub addr2_rx: ADDR2_RX,
        ///0x66 - Reception byte count 0
        pub count2_rx: COUNT2_RX,
        _reserved23: [u8; 2usize],
        ///0x6a - Transmission byte count 0
        pub count3_tx: COUNT3_TX,
        ///0x6c - Reception buffer address 0
        pub addr3_rx: ADDR3_RX,
        ///0x6e - Reception byte count 0
        pub count3_rx: COUNT3_RX,
        _reserved26: [u8; 2usize],
        ///0x72 - Transmission byte count 0
        pub count4_tx: COUNT4_TX,
        ///0x74 - Reception buffer address 0
        pub addr4_rx: ADDR4_RX,
        ///0x76 - Reception byte count 0
        pub count4_rx: COUNT4_RX,
        _reserved29: [u8; 2usize],
        ///0x7a - Transmission byte count 0
        pub count5_tx: COUNT5_TX,
        ///0x7c - Reception buffer address 0
        pub addr5_rx: ADDR5_RX,
        ///0x7e - Reception byte count 0
        pub count5_rx: COUNT5_RX,
        _reserved32: [u8; 2usize],
        ///0x82 - Transmission byte count 0
        pub count6_tx: COUNT6_TX,
        ///0x84 - Reception buffer address 0
        pub addr6_rx: ADDR6_RX,
        ///0x86 - Reception byte count 0
        pub count6_rx: COUNT6_RX,
        _reserved35: [u8; 2usize],
        ///0x8a - Transmission byte count 0
        pub count7_tx: COUNT7_TX,
        ///0x8c - Reception buffer address 0
        pub addr7_rx: ADDR7_RX,
        ///0x8e - Reception byte count 0
        pub count7_rx: COUNT7_RX,
    }
    impl RegisterBlock {
        ///0x54 - control and status register
        #[inline(always)]
        pub fn lpmcsr(&self) -> &LPMCSR {
            unsafe { &*(((self as *const Self) as *const u8).add(84usize) as *const LPMCSR) }
        }
        ///0x54 - control and status register
        #[inline(always)]
        pub fn lpmcsr_mut(&self) -> &mut LPMCSR {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(84usize) as *mut LPMCSR) }
        }
        ///0x54 - Reception buffer address 0
        #[inline(always)]
        pub fn addr0_rx(&self) -> &ADDR0_RX {
            unsafe { &*(((self as *const Self) as *const u8).add(84usize) as *const ADDR0_RX) }
        }
        ///0x54 - Reception buffer address 0
        #[inline(always)]
        pub fn addr0_rx_mut(&self) -> &mut ADDR0_RX {
            unsafe { &mut *(((self as *const Self) as *mut u8).add(84usize) as *mut ADDR0_RX) }
        }
    }
    ///endpoint 0 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep0r](ep0r) module
    pub type EP0R = crate::Reg<u16, _EP0R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP0R;
    ///`read()` method returns [ep0r::R](ep0r::R) reader structure
    impl crate::Readable for EP0R {}
    ///`write(|w| ..)` method takes [ep0r::W](ep0r::W) writer structure
    impl crate::Writable for EP0R {}
    ///endpoint 0 register
    pub mod ep0r {
        ///Reader of register EP0R
        pub type R = crate::R<u16, super::EP0R>;
        ///Writer for register EP0R
        pub type W = crate::W<u16, super::EP0R>;
        ///Register EP0R `reset()`'s with value 0
        impl crate::ResetValue for super::EP0R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///endpoint 1 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep1r](ep1r) module
    pub type EP1R = crate::Reg<u16, _EP1R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP1R;
    ///`read()` method returns [ep1r::R](ep1r::R) reader structure
    impl crate::Readable for EP1R {}
    ///`write(|w| ..)` method takes [ep1r::W](ep1r::W) writer structure
    impl crate::Writable for EP1R {}
    ///endpoint 1 register
    pub mod ep1r {
        ///Reader of register EP1R
        pub type R = crate::R<u16, super::EP1R>;
        ///Writer for register EP1R
        pub type W = crate::W<u16, super::EP1R>;
        ///Register EP1R `reset()`'s with value 0
        impl crate::ResetValue for super::EP1R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///endpoint 2 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep2r](ep2r) module
    pub type EP2R = crate::Reg<u16, _EP2R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP2R;
    ///`read()` method returns [ep2r::R](ep2r::R) reader structure
    impl crate::Readable for EP2R {}
    ///`write(|w| ..)` method takes [ep2r::W](ep2r::W) writer structure
    impl crate::Writable for EP2R {}
    ///endpoint 2 register
    pub mod ep2r {
        ///Reader of register EP2R
        pub type R = crate::R<u16, super::EP2R>;
        ///Writer for register EP2R
        pub type W = crate::W<u16, super::EP2R>;
        ///Register EP2R `reset()`'s with value 0
        impl crate::ResetValue for super::EP2R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///endpoint 3 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep3r](ep3r) module
    pub type EP3R = crate::Reg<u16, _EP3R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP3R;
    ///`read()` method returns [ep3r::R](ep3r::R) reader structure
    impl crate::Readable for EP3R {}
    ///`write(|w| ..)` method takes [ep3r::W](ep3r::W) writer structure
    impl crate::Writable for EP3R {}
    ///endpoint 3 register
    pub mod ep3r {
        ///Reader of register EP3R
        pub type R = crate::R<u16, super::EP3R>;
        ///Writer for register EP3R
        pub type W = crate::W<u16, super::EP3R>;
        ///Register EP3R `reset()`'s with value 0
        impl crate::ResetValue for super::EP3R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///endpoint 4 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep4r](ep4r) module
    pub type EP4R = crate::Reg<u16, _EP4R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP4R;
    ///`read()` method returns [ep4r::R](ep4r::R) reader structure
    impl crate::Readable for EP4R {}
    ///`write(|w| ..)` method takes [ep4r::W](ep4r::W) writer structure
    impl crate::Writable for EP4R {}
    ///endpoint 4 register
    pub mod ep4r {
        ///Reader of register EP4R
        pub type R = crate::R<u16, super::EP4R>;
        ///Writer for register EP4R
        pub type W = crate::W<u16, super::EP4R>;
        ///Register EP4R `reset()`'s with value 0
        impl crate::ResetValue for super::EP4R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///endpoint 5 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep5r](ep5r) module
    pub type EP5R = crate::Reg<u16, _EP5R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP5R;
    ///`read()` method returns [ep5r::R](ep5r::R) reader structure
    impl crate::Readable for EP5R {}
    ///`write(|w| ..)` method takes [ep5r::W](ep5r::W) writer structure
    impl crate::Writable for EP5R {}
    ///endpoint 5 register
    pub mod ep5r {
        ///Reader of register EP5R
        pub type R = crate::R<u16, super::EP5R>;
        ///Writer for register EP5R
        pub type W = crate::W<u16, super::EP5R>;
        ///Register EP5R `reset()`'s with value 0
        impl crate::ResetValue for super::EP5R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///endpoint 6 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep6r](ep6r) module
    pub type EP6R = crate::Reg<u16, _EP6R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP6R;
    ///`read()` method returns [ep6r::R](ep6r::R) reader structure
    impl crate::Readable for EP6R {}
    ///`write(|w| ..)` method takes [ep6r::W](ep6r::W) writer structure
    impl crate::Writable for EP6R {}
    ///endpoint 6 register
    pub mod ep6r {
        ///Reader of register EP6R
        pub type R = crate::R<u16, super::EP6R>;
        ///Writer for register EP6R
        pub type W = crate::W<u16, super::EP6R>;
        ///Register EP6R `reset()`'s with value 0
        impl crate::ResetValue for super::EP6R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///endpoint 7 register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ep7r](ep7r) module
    pub type EP7R = crate::Reg<u16, _EP7R>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _EP7R;
    ///`read()` method returns [ep7r::R](ep7r::R) reader structure
    impl crate::Readable for EP7R {}
    ///`write(|w| ..)` method takes [ep7r::W](ep7r::W) writer structure
    impl crate::Writable for EP7R {}
    ///endpoint 7 register
    pub mod ep7r {
        ///Reader of register EP7R
        pub type R = crate::R<u16, super::EP7R>;
        ///Writer for register EP7R
        pub type W = crate::W<u16, super::EP7R>;
        ///Register EP7R `reset()`'s with value 0
        impl crate::ResetValue for super::EP7R {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EA`
        pub type EA_R = crate::R<u8, u8>;
        ///Write proxy for field `EA`
        pub struct EA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EA_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x0f) | ((value as u16) & 0x0f);
                self.w
            }
        }
        ///Reader of field `STAT_TX`
        pub type STAT_TX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_TX`
        pub struct STAT_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u16) & 0x03) << 4);
                self.w
            }
        }
        ///Reader of field `DTOG_TX`
        pub type DTOG_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_TX`
        pub struct DTOG_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
                self.w
            }
        }
        ///Reader of field `CTR_TX`
        pub type CTR_TX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_TX`
        pub struct CTR_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_TX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `EP_KIND`
        pub type EP_KIND_R = crate::R<bool, bool>;
        ///Write proxy for field `EP_KIND`
        pub struct EP_KIND_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_KIND_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `EP_TYPE`
        pub type EP_TYPE_R = crate::R<u8, u8>;
        ///Write proxy for field `EP_TYPE`
        pub struct EP_TYPE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EP_TYPE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
                self.w
            }
        }
        ///Reader of field `SETUP`
        pub type SETUP_R = crate::R<bool, bool>;
        ///Write proxy for field `SETUP`
        pub struct SETUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SETUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `STAT_RX`
        pub type STAT_RX_R = crate::R<u8, u8>;
        ///Write proxy for field `STAT_RX`
        pub struct STAT_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> STAT_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u16) & 0x03) << 12);
                self.w
            }
        }
        ///Reader of field `DTOG_RX`
        pub type DTOG_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `DTOG_RX`
        pub struct DTOG_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DTOG_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR_RX`
        pub type CTR_RX_R = crate::R<bool, bool>;
        ///Write proxy for field `CTR_RX`
        pub struct CTR_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTR_RX_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&self) -> EA_R {
                EA_R::new((self.bits & 0x0f) as u8)
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&self) -> STAT_TX_R {
                STAT_TX_R::new(((self.bits >> 4) & 0x03) as u8)
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&self) -> DTOG_TX_R {
                DTOG_TX_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&self) -> CTR_TX_R {
                CTR_TX_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&self) -> EP_KIND_R {
                EP_KIND_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&self) -> EP_TYPE_R {
                EP_TYPE_R::new(((self.bits >> 9) & 0x03) as u8)
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&self) -> SETUP_R {
                SETUP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&self) -> STAT_RX_R {
                STAT_RX_R::new(((self.bits >> 12) & 0x03) as u8)
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&self) -> DTOG_RX_R {
                DTOG_RX_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&self) -> CTR_RX_R {
                CTR_RX_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:3 - Endpoint address
            #[inline(always)]
            pub fn ea(&mut self) -> EA_W {
                EA_W { w: self }
            }
            ///Bits 4:5 - Status bits, for transmission transfers
            #[inline(always)]
            pub fn stat_tx(&mut self) -> STAT_TX_W {
                STAT_TX_W { w: self }
            }
            ///Bit 6 - Data Toggle, for transmission transfers
            #[inline(always)]
            pub fn dtog_tx(&mut self) -> DTOG_TX_W {
                DTOG_TX_W { w: self }
            }
            ///Bit 7 - Correct Transfer for transmission
            #[inline(always)]
            pub fn ctr_tx(&mut self) -> CTR_TX_W {
                CTR_TX_W { w: self }
            }
            ///Bit 8 - Endpoint kind
            #[inline(always)]
            pub fn ep_kind(&mut self) -> EP_KIND_W {
                EP_KIND_W { w: self }
            }
            ///Bits 9:10 - Endpoint type
            #[inline(always)]
            pub fn ep_type(&mut self) -> EP_TYPE_W {
                EP_TYPE_W { w: self }
            }
            ///Bit 11 - Setup transaction completed
            #[inline(always)]
            pub fn setup(&mut self) -> SETUP_W {
                SETUP_W { w: self }
            }
            ///Bits 12:13 - Status bits, for reception transfers
            #[inline(always)]
            pub fn stat_rx(&mut self) -> STAT_RX_W {
                STAT_RX_W { w: self }
            }
            ///Bit 14 - Data Toggle, for reception transfers
            #[inline(always)]
            pub fn dtog_rx(&mut self) -> DTOG_RX_W {
                DTOG_RX_W { w: self }
            }
            ///Bit 15 - Correct transfer for reception
            #[inline(always)]
            pub fn ctr_rx(&mut self) -> CTR_RX_W {
                CTR_RX_W { w: self }
            }
        }
    }
    ///control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cntr](cntr) module
    pub type CNTR = crate::Reg<u16, _CNTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CNTR;
    ///`read()` method returns [cntr::R](cntr::R) reader structure
    impl crate::Readable for CNTR {}
    ///`write(|w| ..)` method takes [cntr::W](cntr::W) writer structure
    impl crate::Writable for CNTR {}
    ///control register
    pub mod cntr {
        ///Reader of register CNTR
        pub type R = crate::R<u16, super::CNTR>;
        ///Writer for register CNTR
        pub type W = crate::W<u16, super::CNTR>;
        ///Register CNTR `reset()`'s with value 0x03
        impl crate::ResetValue for super::CNTR {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0x03
            }
        }
        ///Reader of field `FRES`
        pub type FRES_R = crate::R<bool, bool>;
        ///Write proxy for field `FRES`
        pub struct FRES_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FRES_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u16) & 0x01);
                self.w
            }
        }
        ///Reader of field `PDWN`
        pub type PDWN_R = crate::R<bool, bool>;
        ///Write proxy for field `PDWN`
        pub struct PDWN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PDWN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u16) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `LPMODE`
        pub type LPMODE_R = crate::R<bool, bool>;
        ///Write proxy for field `LPMODE`
        pub struct LPMODE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPMODE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u16) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `FSUSP`
        pub type FSUSP_R = crate::R<bool, bool>;
        ///Write proxy for field `FSUSP`
        pub struct FSUSP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> FSUSP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u16) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `RESUME`
        pub type RESUME_R = crate::R<bool, bool>;
        ///Write proxy for field `RESUME`
        pub struct RESUME_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RESUME_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u16) & 0x01) << 4);
                self.w
            }
        }
        ///Reader of field `L1RESUME`
        pub type L1RESUME_R = crate::R<bool, bool>;
        ///Write proxy for field `L1RESUME`
        pub struct L1RESUME_W<'a> {
            w: &'a mut W,
        }
        impl<'a> L1RESUME_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u16) & 0x01) << 5);
                self.w
            }
        }
        ///Reader of field `L1REQM`
        pub type L1REQM_R = crate::R<bool, bool>;
        ///Write proxy for field `L1REQM`
        pub struct L1REQM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> L1REQM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ESOFM`
        pub type ESOFM_R = crate::R<bool, bool>;
        ///Write proxy for field `ESOFM`
        pub struct ESOFM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ESOFM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `SOFM`
        pub type SOFM_R = crate::R<bool, bool>;
        ///Write proxy for field `SOFM`
        pub struct SOFM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOFM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u16) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `RESETM`
        pub type RESETM_R = crate::R<bool, bool>;
        ///Write proxy for field `RESETM`
        pub struct RESETM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RESETM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u16) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `SUSPM`
        pub type SUSPM_R = crate::R<bool, bool>;
        ///Write proxy for field `SUSPM`
        pub struct SUSPM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SUSPM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `WKUPM`
        pub type WKUPM_R = crate::R<bool, bool>;
        ///Write proxy for field `WKUPM`
        pub struct WKUPM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WKUPM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u16) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ERRM`
        pub type ERRM_R = crate::R<bool, bool>;
        ///Write proxy for field `ERRM`
        pub struct ERRM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERRM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u16) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PMAOVRM`
        pub type PMAOVRM_R = crate::R<bool, bool>;
        ///Write proxy for field `PMAOVRM`
        pub struct PMAOVRM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PMAOVRM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTRM`
        pub type CTRM_R = crate::R<bool, bool>;
        ///Write proxy for field `CTRM`
        pub struct CTRM_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CTRM_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Force USB Reset
            #[inline(always)]
            pub fn fres(&self) -> FRES_R {
                FRES_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Power down
            #[inline(always)]
            pub fn pdwn(&self) -> PDWN_R {
                PDWN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Low-power mode
            #[inline(always)]
            pub fn lpmode(&self) -> LPMODE_R {
                LPMODE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Force suspend
            #[inline(always)]
            pub fn fsusp(&self) -> FSUSP_R {
                FSUSP_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Resume request
            #[inline(always)]
            pub fn resume(&self) -> RESUME_R {
                RESUME_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - LPM L1 Resume request
            #[inline(always)]
            pub fn l1resume(&self) -> L1RESUME_R {
                L1RESUME_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 7 - LPM L1 state request interrupt mask
            #[inline(always)]
            pub fn l1reqm(&self) -> L1REQM_R {
                L1REQM_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Expected start of frame interrupt mask
            #[inline(always)]
            pub fn esofm(&self) -> ESOFM_R {
                ESOFM_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - Start of frame interrupt mask
            #[inline(always)]
            pub fn sofm(&self) -> SOFM_R {
                SOFM_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - USB reset interrupt mask
            #[inline(always)]
            pub fn resetm(&self) -> RESETM_R {
                RESETM_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Suspend mode interrupt mask
            #[inline(always)]
            pub fn suspm(&self) -> SUSPM_R {
                SUSPM_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Wakeup interrupt mask
            #[inline(always)]
            pub fn wkupm(&self) -> WKUPM_R {
                WKUPM_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Error interrupt mask
            #[inline(always)]
            pub fn errm(&self) -> ERRM_R {
                ERRM_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Packet memory area over / underrun interrupt mask
            #[inline(always)]
            pub fn pmaovrm(&self) -> PMAOVRM_R {
                PMAOVRM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer interrupt mask
            #[inline(always)]
            pub fn ctrm(&self) -> CTRM_R {
                CTRM_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Force USB Reset
            #[inline(always)]
            pub fn fres(&mut self) -> FRES_W {
                FRES_W { w: self }
            }
            ///Bit 1 - Power down
            #[inline(always)]
            pub fn pdwn(&mut self) -> PDWN_W {
                PDWN_W { w: self }
            }
            ///Bit 2 - Low-power mode
            #[inline(always)]
            pub fn lpmode(&mut self) -> LPMODE_W {
                LPMODE_W { w: self }
            }
            ///Bit 3 - Force suspend
            #[inline(always)]
            pub fn fsusp(&mut self) -> FSUSP_W {
                FSUSP_W { w: self }
            }
            ///Bit 4 - Resume request
            #[inline(always)]
            pub fn resume(&mut self) -> RESUME_W {
                RESUME_W { w: self }
            }
            ///Bit 5 - LPM L1 Resume request
            #[inline(always)]
            pub fn l1resume(&mut self) -> L1RESUME_W {
                L1RESUME_W { w: self }
            }
            ///Bit 7 - LPM L1 state request interrupt mask
            #[inline(always)]
            pub fn l1reqm(&mut self) -> L1REQM_W {
                L1REQM_W { w: self }
            }
            ///Bit 8 - Expected start of frame interrupt mask
            #[inline(always)]
            pub fn esofm(&mut self) -> ESOFM_W {
                ESOFM_W { w: self }
            }
            ///Bit 9 - Start of frame interrupt mask
            #[inline(always)]
            pub fn sofm(&mut self) -> SOFM_W {
                SOFM_W { w: self }
            }
            ///Bit 10 - USB reset interrupt mask
            #[inline(always)]
            pub fn resetm(&mut self) -> RESETM_W {
                RESETM_W { w: self }
            }
            ///Bit 11 - Suspend mode interrupt mask
            #[inline(always)]
            pub fn suspm(&mut self) -> SUSPM_W {
                SUSPM_W { w: self }
            }
            ///Bit 12 - Wakeup interrupt mask
            #[inline(always)]
            pub fn wkupm(&mut self) -> WKUPM_W {
                WKUPM_W { w: self }
            }
            ///Bit 13 - Error interrupt mask
            #[inline(always)]
            pub fn errm(&mut self) -> ERRM_W {
                ERRM_W { w: self }
            }
            ///Bit 14 - Packet memory area over / underrun interrupt mask
            #[inline(always)]
            pub fn pmaovrm(&mut self) -> PMAOVRM_W {
                PMAOVRM_W { w: self }
            }
            ///Bit 15 - Correct transfer interrupt mask
            #[inline(always)]
            pub fn ctrm(&mut self) -> CTRM_W {
                CTRM_W { w: self }
            }
        }
    }
    ///interrupt status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [istr](istr) module
    pub type ISTR = crate::Reg<u16, _ISTR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ISTR;
    ///`read()` method returns [istr::R](istr::R) reader structure
    impl crate::Readable for ISTR {}
    ///`write(|w| ..)` method takes [istr::W](istr::W) writer structure
    impl crate::Writable for ISTR {}
    ///interrupt status register
    pub mod istr {
        ///Reader of register ISTR
        pub type R = crate::R<u16, super::ISTR>;
        ///Writer for register ISTR
        pub type W = crate::W<u16, super::ISTR>;
        ///Register ISTR `reset()`'s with value 0
        impl crate::ResetValue for super::ISTR {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `EP_ID`
        pub type EP_ID_R = crate::R<u8, u8>;
        ///Reader of field `DIR`
        pub type DIR_R = crate::R<bool, bool>;
        ///Reader of field `L1REQ`
        pub type L1REQ_R = crate::R<bool, bool>;
        ///Write proxy for field `L1REQ`
        pub struct L1REQ_W<'a> {
            w: &'a mut W,
        }
        impl<'a> L1REQ_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        ///Reader of field `ESOF`
        pub type ESOF_R = crate::R<bool, bool>;
        ///Write proxy for field `ESOF`
        pub struct ESOF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ESOF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `SOF`
        pub type SOF_R = crate::R<bool, bool>;
        ///Write proxy for field `SOF`
        pub struct SOF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SOF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u16) & 0x01) << 9);
                self.w
            }
        }
        ///Reader of field `RESET`
        pub type RESET_R = crate::R<bool, bool>;
        ///Write proxy for field `RESET`
        pub struct RESET_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RESET_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u16) & 0x01) << 10);
                self.w
            }
        }
        ///Reader of field `SUSP`
        pub type SUSP_R = crate::R<bool, bool>;
        ///Write proxy for field `SUSP`
        pub struct SUSP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SUSP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u16) & 0x01) << 11);
                self.w
            }
        }
        ///Reader of field `WKUP`
        pub type WKUP_R = crate::R<bool, bool>;
        ///Write proxy for field `WKUP`
        pub struct WKUP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> WKUP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u16) & 0x01) << 12);
                self.w
            }
        }
        ///Reader of field `ERR`
        pub type ERR_R = crate::R<bool, bool>;
        ///Write proxy for field `ERR`
        pub struct ERR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ERR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u16) & 0x01) << 13);
                self.w
            }
        }
        ///Reader of field `PMAOVR`
        pub type PMAOVR_R = crate::R<bool, bool>;
        ///Write proxy for field `PMAOVR`
        pub struct PMAOVR_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PMAOVR_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
                self.w
            }
        }
        ///Reader of field `CTR`
        pub type CTR_R = crate::R<bool, bool>;
        impl R {
            ///Bits 0:3 - Endpoint Identifier
            #[inline(always)]
            pub fn ep_id(&self) -> EP_ID_R {
                EP_ID_R::new((self.bits & 0x0f) as u8)
            }
            ///Bit 4 - Direction of transaction
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 7 - LPM L1 state request
            #[inline(always)]
            pub fn l1req(&self) -> L1REQ_R {
                L1REQ_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 8 - Expected start frame
            #[inline(always)]
            pub fn esof(&self) -> ESOF_R {
                ESOF_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - start of frame
            #[inline(always)]
            pub fn sof(&self) -> SOF_R {
                SOF_R::new(((self.bits >> 9) & 0x01) != 0)
            }
            ///Bit 10 - reset request
            #[inline(always)]
            pub fn reset(&self) -> RESET_R {
                RESET_R::new(((self.bits >> 10) & 0x01) != 0)
            }
            ///Bit 11 - Suspend mode request
            #[inline(always)]
            pub fn susp(&self) -> SUSP_R {
                SUSP_R::new(((self.bits >> 11) & 0x01) != 0)
            }
            ///Bit 12 - Wakeup
            #[inline(always)]
            pub fn wkup(&self) -> WKUP_R {
                WKUP_R::new(((self.bits >> 12) & 0x01) != 0)
            }
            ///Bit 13 - Error
            #[inline(always)]
            pub fn err(&self) -> ERR_R {
                ERR_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Packet memory area over / underrun
            #[inline(always)]
            pub fn pmaovr(&self) -> PMAOVR_R {
                PMAOVR_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Correct transfer
            #[inline(always)]
            pub fn ctr(&self) -> CTR_R {
                CTR_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 7 - LPM L1 state request
            #[inline(always)]
            pub fn l1req(&mut self) -> L1REQ_W {
                L1REQ_W { w: self }
            }
            ///Bit 8 - Expected start frame
            #[inline(always)]
            pub fn esof(&mut self) -> ESOF_W {
                ESOF_W { w: self }
            }
            ///Bit 9 - start of frame
            #[inline(always)]
            pub fn sof(&mut self) -> SOF_W {
                SOF_W { w: self }
            }
            ///Bit 10 - reset request
            #[inline(always)]
            pub fn reset(&mut self) -> RESET_W {
                RESET_W { w: self }
            }
            ///Bit 11 - Suspend mode request
            #[inline(always)]
            pub fn susp(&mut self) -> SUSP_W {
                SUSP_W { w: self }
            }
            ///Bit 12 - Wakeup
            #[inline(always)]
            pub fn wkup(&mut self) -> WKUP_W {
                WKUP_W { w: self }
            }
            ///Bit 13 - Error
            #[inline(always)]
            pub fn err(&mut self) -> ERR_W {
                ERR_W { w: self }
            }
            ///Bit 14 - Packet memory area over / underrun
            #[inline(always)]
            pub fn pmaovr(&mut self) -> PMAOVR_W {
                PMAOVR_W { w: self }
            }
        }
    }
    ///frame number register
    ///
    ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [fnr](fnr) module
    pub type FNR = crate::Reg<u16, _FNR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _FNR;
    ///`read()` method returns [fnr::R](fnr::R) reader structure
    impl crate::Readable for FNR {}
    ///frame number register
    pub mod fnr {
        ///Reader of register FNR
        pub type R = crate::R<u16, super::FNR>;
        ///Reader of field `FN`
        pub type FN_R = crate::R<u16, u16>;
        ///Reader of field `LSOF`
        pub type LSOF_R = crate::R<u8, u8>;
        ///Reader of field `LCK`
        pub type LCK_R = crate::R<bool, bool>;
        ///Reader of field `RXDM`
        pub type RXDM_R = crate::R<bool, bool>;
        ///Reader of field `RXDP`
        pub type RXDP_R = crate::R<bool, bool>;
        impl R {
            ///Bits 0:10 - Frame number
            #[inline(always)]
            pub fn fn_(&self) -> FN_R {
                FN_R::new((self.bits & 0x07ff) as u16)
            }
            ///Bits 11:12 - Lost SOF
            #[inline(always)]
            pub fn lsof(&self) -> LSOF_R {
                LSOF_R::new(((self.bits >> 11) & 0x03) as u8)
            }
            ///Bit 13 - Locked
            #[inline(always)]
            pub fn lck(&self) -> LCK_R {
                LCK_R::new(((self.bits >> 13) & 0x01) != 0)
            }
            ///Bit 14 - Receive data - line status
            #[inline(always)]
            pub fn rxdm(&self) -> RXDM_R {
                RXDM_R::new(((self.bits >> 14) & 0x01) != 0)
            }
            ///Bit 15 - Receive data + line status
            #[inline(always)]
            pub fn rxdp(&self) -> RXDP_R {
                RXDP_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
    }
    ///device address
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [daddr](daddr) module
    pub type DADDR = crate::Reg<u16, _DADDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _DADDR;
    ///`read()` method returns [daddr::R](daddr::R) reader structure
    impl crate::Readable for DADDR {}
    ///`write(|w| ..)` method takes [daddr::W](daddr::W) writer structure
    impl crate::Writable for DADDR {}
    ///device address
    pub mod daddr {
        ///Reader of register DADDR
        pub type R = crate::R<u16, super::DADDR>;
        ///Writer for register DADDR
        pub type W = crate::W<u16, super::DADDR>;
        ///Register DADDR `reset()`'s with value 0
        impl crate::ResetValue for super::DADDR {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADD`
        pub type ADD_R = crate::R<u8, u8>;
        ///Write proxy for field `ADD`
        pub struct ADD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x7f) | ((value as u16) & 0x7f);
                self.w
            }
        }
        ///Reader of field `EF`
        pub type EF_R = crate::R<bool, bool>;
        ///Write proxy for field `EF`
        pub struct EF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> EF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
                self.w
            }
        }
        impl R {
            ///Bits 0:6 - Device address
            #[inline(always)]
            pub fn add(&self) -> ADD_R {
                ADD_R::new((self.bits & 0x7f) as u8)
            }
            ///Bit 7 - Enable function
            #[inline(always)]
            pub fn ef(&self) -> EF_R {
                EF_R::new(((self.bits >> 7) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:6 - Device address
            #[inline(always)]
            pub fn add(&mut self) -> ADD_W {
                ADD_W { w: self }
            }
            ///Bit 7 - Enable function
            #[inline(always)]
            pub fn ef(&mut self) -> EF_W {
                EF_W { w: self }
            }
        }
    }
    ///Buffer table address
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [btable](btable) module
    pub type BTABLE = crate::Reg<u16, _BTABLE>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BTABLE;
    ///`read()` method returns [btable::R](btable::R) reader structure
    impl crate::Readable for BTABLE {}
    ///`write(|w| ..)` method takes [btable::W](btable::W) writer structure
    impl crate::Writable for BTABLE {}
    ///Buffer table address
    pub mod btable {
        ///Reader of register BTABLE
        pub type R = crate::R<u16, super::BTABLE>;
        ///Writer for register BTABLE
        pub type W = crate::W<u16, super::BTABLE>;
        ///Register BTABLE `reset()`'s with value 0
        impl crate::ResetValue for super::BTABLE {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BTABLE`
        pub type BTABLE_R = crate::R<u16, u16>;
        ///Write proxy for field `BTABLE`
        pub struct BTABLE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BTABLE_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1fff << 3)) | (((value as u16) & 0x1fff) << 3);
                self.w
            }
        }
        impl R {
            ///Bits 3:15 - Buffer table
            #[inline(always)]
            pub fn btable(&self) -> BTABLE_R {
                BTABLE_R::new(((self.bits >> 3) & 0x1fff) as u16)
            }
        }
        impl W {
            ///Bits 3:15 - Buffer table
            #[inline(always)]
            pub fn btable(&mut self) -> BTABLE_W {
                BTABLE_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count0_tx](count0_tx) module
    pub type COUNT0_TX = crate::Reg<u16, _COUNT0_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT0_TX;
    ///`read()` method returns [count0_tx::R](count0_tx::R) reader structure
    impl crate::Readable for COUNT0_TX {}
    ///`write(|w| ..)` method takes [count0_tx::W](count0_tx::W) writer structure
    impl crate::Writable for COUNT0_TX {}
    ///Transmission byte count 0
    pub mod count0_tx {
        ///Reader of register COUNT0_TX
        pub type R = crate::R<u16, super::COUNT0_TX>;
        ///Writer for register COUNT0_TX
        pub type W = crate::W<u16, super::COUNT0_TX>;
        ///Register COUNT0_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT0_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT0_TX`
        pub type COUNT0_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT0_TX`
        pub struct COUNT0_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT0_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count0_tx(&self) -> COUNT0_TX_R {
                COUNT0_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count0_tx(&mut self) -> COUNT0_TX_W {
                COUNT0_TX_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count1_tx](count1_tx) module
    pub type COUNT1_TX = crate::Reg<u16, _COUNT1_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT1_TX;
    ///`read()` method returns [count1_tx::R](count1_tx::R) reader structure
    impl crate::Readable for COUNT1_TX {}
    ///`write(|w| ..)` method takes [count1_tx::W](count1_tx::W) writer structure
    impl crate::Writable for COUNT1_TX {}
    ///Transmission byte count 0
    pub mod count1_tx {
        ///Reader of register COUNT1_TX
        pub type R = crate::R<u16, super::COUNT1_TX>;
        ///Writer for register COUNT1_TX
        pub type W = crate::W<u16, super::COUNT1_TX>;
        ///Register COUNT1_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT1_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT1_TX`
        pub type COUNT1_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT1_TX`
        pub struct COUNT1_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT1_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count1_tx(&self) -> COUNT1_TX_R {
                COUNT1_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count1_tx(&mut self) -> COUNT1_TX_W {
                COUNT1_TX_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count2_tx](count2_tx) module
    pub type COUNT2_TX = crate::Reg<u16, _COUNT2_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT2_TX;
    ///`read()` method returns [count2_tx::R](count2_tx::R) reader structure
    impl crate::Readable for COUNT2_TX {}
    ///`write(|w| ..)` method takes [count2_tx::W](count2_tx::W) writer structure
    impl crate::Writable for COUNT2_TX {}
    ///Transmission byte count 0
    pub mod count2_tx {
        ///Reader of register COUNT2_TX
        pub type R = crate::R<u16, super::COUNT2_TX>;
        ///Writer for register COUNT2_TX
        pub type W = crate::W<u16, super::COUNT2_TX>;
        ///Register COUNT2_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT2_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT2_TX`
        pub type COUNT2_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT2_TX`
        pub struct COUNT2_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT2_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count2_tx(&self) -> COUNT2_TX_R {
                COUNT2_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count2_tx(&mut self) -> COUNT2_TX_W {
                COUNT2_TX_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count3_tx](count3_tx) module
    pub type COUNT3_TX = crate::Reg<u16, _COUNT3_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT3_TX;
    ///`read()` method returns [count3_tx::R](count3_tx::R) reader structure
    impl crate::Readable for COUNT3_TX {}
    ///`write(|w| ..)` method takes [count3_tx::W](count3_tx::W) writer structure
    impl crate::Writable for COUNT3_TX {}
    ///Transmission byte count 0
    pub mod count3_tx {
        ///Reader of register COUNT3_TX
        pub type R = crate::R<u16, super::COUNT3_TX>;
        ///Writer for register COUNT3_TX
        pub type W = crate::W<u16, super::COUNT3_TX>;
        ///Register COUNT3_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT3_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT3_TX`
        pub type COUNT3_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT3_TX`
        pub struct COUNT3_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT3_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count3_tx(&self) -> COUNT3_TX_R {
                COUNT3_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count3_tx(&mut self) -> COUNT3_TX_W {
                COUNT3_TX_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count4_tx](count4_tx) module
    pub type COUNT4_TX = crate::Reg<u16, _COUNT4_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT4_TX;
    ///`read()` method returns [count4_tx::R](count4_tx::R) reader structure
    impl crate::Readable for COUNT4_TX {}
    ///`write(|w| ..)` method takes [count4_tx::W](count4_tx::W) writer structure
    impl crate::Writable for COUNT4_TX {}
    ///Transmission byte count 0
    pub mod count4_tx {
        ///Reader of register COUNT4_TX
        pub type R = crate::R<u16, super::COUNT4_TX>;
        ///Writer for register COUNT4_TX
        pub type W = crate::W<u16, super::COUNT4_TX>;
        ///Register COUNT4_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT4_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT4_TX`
        pub type COUNT4_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT4_TX`
        pub struct COUNT4_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT4_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count4_tx(&self) -> COUNT4_TX_R {
                COUNT4_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count4_tx(&mut self) -> COUNT4_TX_W {
                COUNT4_TX_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count5_tx](count5_tx) module
    pub type COUNT5_TX = crate::Reg<u16, _COUNT5_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT5_TX;
    ///`read()` method returns [count5_tx::R](count5_tx::R) reader structure
    impl crate::Readable for COUNT5_TX {}
    ///`write(|w| ..)` method takes [count5_tx::W](count5_tx::W) writer structure
    impl crate::Writable for COUNT5_TX {}
    ///Transmission byte count 0
    pub mod count5_tx {
        ///Reader of register COUNT5_TX
        pub type R = crate::R<u16, super::COUNT5_TX>;
        ///Writer for register COUNT5_TX
        pub type W = crate::W<u16, super::COUNT5_TX>;
        ///Register COUNT5_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT5_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT5_TX`
        pub type COUNT5_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT5_TX`
        pub struct COUNT5_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT5_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count5_tx(&self) -> COUNT5_TX_R {
                COUNT5_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count5_tx(&mut self) -> COUNT5_TX_W {
                COUNT5_TX_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count6_tx](count6_tx) module
    pub type COUNT6_TX = crate::Reg<u16, _COUNT6_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT6_TX;
    ///`read()` method returns [count6_tx::R](count6_tx::R) reader structure
    impl crate::Readable for COUNT6_TX {}
    ///`write(|w| ..)` method takes [count6_tx::W](count6_tx::W) writer structure
    impl crate::Writable for COUNT6_TX {}
    ///Transmission byte count 0
    pub mod count6_tx {
        ///Reader of register COUNT6_TX
        pub type R = crate::R<u16, super::COUNT6_TX>;
        ///Writer for register COUNT6_TX
        pub type W = crate::W<u16, super::COUNT6_TX>;
        ///Register COUNT6_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT6_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT6_TX`
        pub type COUNT6_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT6_TX`
        pub struct COUNT6_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT6_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count6_tx(&self) -> COUNT6_TX_R {
                COUNT6_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count6_tx(&mut self) -> COUNT6_TX_W {
                COUNT6_TX_W { w: self }
            }
        }
    }
    ///Transmission byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count7_tx](count7_tx) module
    pub type COUNT7_TX = crate::Reg<u16, _COUNT7_TX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT7_TX;
    ///`read()` method returns [count7_tx::R](count7_tx::R) reader structure
    impl crate::Readable for COUNT7_TX {}
    ///`write(|w| ..)` method takes [count7_tx::W](count7_tx::W) writer structure
    impl crate::Writable for COUNT7_TX {}
    ///Transmission byte count 0
    pub mod count7_tx {
        ///Reader of register COUNT7_TX
        pub type R = crate::R<u16, super::COUNT7_TX>;
        ///Writer for register COUNT7_TX
        pub type W = crate::W<u16, super::COUNT7_TX>;
        ///Register COUNT7_TX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT7_TX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT7_TX`
        pub type COUNT7_TX_R = crate::R<u16, u16>;
        ///Write proxy for field `COUNT7_TX`
        pub struct COUNT7_TX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNT7_TX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x03ff) | ((value as u16) & 0x03ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count7_tx(&self) -> COUNT7_TX_R {
                COUNT7_TX_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            ///Bits 0:9 - Transmission byte count
            #[inline(always)]
            pub fn count7_tx(&mut self) -> COUNT7_TX_W {
                COUNT7_TX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr0_rx](addr0_rx) module
    pub type ADDR0_RX = crate::Reg<u16, _ADDR0_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR0_RX;
    ///`read()` method returns [addr0_rx::R](addr0_rx::R) reader structure
    impl crate::Readable for ADDR0_RX {}
    ///`write(|w| ..)` method takes [addr0_rx::W](addr0_rx::W) writer structure
    impl crate::Writable for ADDR0_RX {}
    ///Reception buffer address 0
    pub mod addr0_rx {
        ///Reader of register ADDR0_RX
        pub type R = crate::R<u16, super::ADDR0_RX>;
        ///Writer for register ADDR0_RX
        pub type W = crate::W<u16, super::ADDR0_RX>;
        ///Register ADDR0_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR0_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR0_RX`
        pub type ADDR0_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR0_RX`
        pub struct ADDR0_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR0_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr0_rx(&self) -> ADDR0_RX_R {
                ADDR0_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr0_rx(&mut self) -> ADDR0_RX_W {
                ADDR0_RX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr1_rx](addr1_rx) module
    pub type ADDR1_RX = crate::Reg<u16, _ADDR1_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR1_RX;
    ///`read()` method returns [addr1_rx::R](addr1_rx::R) reader structure
    impl crate::Readable for ADDR1_RX {}
    ///`write(|w| ..)` method takes [addr1_rx::W](addr1_rx::W) writer structure
    impl crate::Writable for ADDR1_RX {}
    ///Reception buffer address 0
    pub mod addr1_rx {
        ///Reader of register ADDR1_RX
        pub type R = crate::R<u16, super::ADDR1_RX>;
        ///Writer for register ADDR1_RX
        pub type W = crate::W<u16, super::ADDR1_RX>;
        ///Register ADDR1_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR1_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR1_RX`
        pub type ADDR1_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR1_RX`
        pub struct ADDR1_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR1_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr1_rx(&self) -> ADDR1_RX_R {
                ADDR1_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr1_rx(&mut self) -> ADDR1_RX_W {
                ADDR1_RX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr2_rx](addr2_rx) module
    pub type ADDR2_RX = crate::Reg<u16, _ADDR2_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR2_RX;
    ///`read()` method returns [addr2_rx::R](addr2_rx::R) reader structure
    impl crate::Readable for ADDR2_RX {}
    ///`write(|w| ..)` method takes [addr2_rx::W](addr2_rx::W) writer structure
    impl crate::Writable for ADDR2_RX {}
    ///Reception buffer address 0
    pub mod addr2_rx {
        ///Reader of register ADDR2_RX
        pub type R = crate::R<u16, super::ADDR2_RX>;
        ///Writer for register ADDR2_RX
        pub type W = crate::W<u16, super::ADDR2_RX>;
        ///Register ADDR2_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR2_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR2_RX`
        pub type ADDR2_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR2_RX`
        pub struct ADDR2_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR2_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr2_rx(&self) -> ADDR2_RX_R {
                ADDR2_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr2_rx(&mut self) -> ADDR2_RX_W {
                ADDR2_RX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr3_rx](addr3_rx) module
    pub type ADDR3_RX = crate::Reg<u16, _ADDR3_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR3_RX;
    ///`read()` method returns [addr3_rx::R](addr3_rx::R) reader structure
    impl crate::Readable for ADDR3_RX {}
    ///`write(|w| ..)` method takes [addr3_rx::W](addr3_rx::W) writer structure
    impl crate::Writable for ADDR3_RX {}
    ///Reception buffer address 0
    pub mod addr3_rx {
        ///Reader of register ADDR3_RX
        pub type R = crate::R<u16, super::ADDR3_RX>;
        ///Writer for register ADDR3_RX
        pub type W = crate::W<u16, super::ADDR3_RX>;
        ///Register ADDR3_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR3_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR3_RX`
        pub type ADDR3_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR3_RX`
        pub struct ADDR3_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR3_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr3_rx(&self) -> ADDR3_RX_R {
                ADDR3_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr3_rx(&mut self) -> ADDR3_RX_W {
                ADDR3_RX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr4_rx](addr4_rx) module
    pub type ADDR4_RX = crate::Reg<u16, _ADDR4_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR4_RX;
    ///`read()` method returns [addr4_rx::R](addr4_rx::R) reader structure
    impl crate::Readable for ADDR4_RX {}
    ///`write(|w| ..)` method takes [addr4_rx::W](addr4_rx::W) writer structure
    impl crate::Writable for ADDR4_RX {}
    ///Reception buffer address 0
    pub mod addr4_rx {
        ///Reader of register ADDR4_RX
        pub type R = crate::R<u16, super::ADDR4_RX>;
        ///Writer for register ADDR4_RX
        pub type W = crate::W<u16, super::ADDR4_RX>;
        ///Register ADDR4_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR4_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR4_RX`
        pub type ADDR4_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR4_RX`
        pub struct ADDR4_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR4_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr4_rx(&self) -> ADDR4_RX_R {
                ADDR4_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr4_rx(&mut self) -> ADDR4_RX_W {
                ADDR4_RX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr5_rx](addr5_rx) module
    pub type ADDR5_RX = crate::Reg<u16, _ADDR5_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR5_RX;
    ///`read()` method returns [addr5_rx::R](addr5_rx::R) reader structure
    impl crate::Readable for ADDR5_RX {}
    ///`write(|w| ..)` method takes [addr5_rx::W](addr5_rx::W) writer structure
    impl crate::Writable for ADDR5_RX {}
    ///Reception buffer address 0
    pub mod addr5_rx {
        ///Reader of register ADDR5_RX
        pub type R = crate::R<u16, super::ADDR5_RX>;
        ///Writer for register ADDR5_RX
        pub type W = crate::W<u16, super::ADDR5_RX>;
        ///Register ADDR5_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR5_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR5_RX`
        pub type ADDR5_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR5_RX`
        pub struct ADDR5_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR5_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr5_rx(&self) -> ADDR5_RX_R {
                ADDR5_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr5_rx(&mut self) -> ADDR5_RX_W {
                ADDR5_RX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr6_rx](addr6_rx) module
    pub type ADDR6_RX = crate::Reg<u16, _ADDR6_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR6_RX;
    ///`read()` method returns [addr6_rx::R](addr6_rx::R) reader structure
    impl crate::Readable for ADDR6_RX {}
    ///`write(|w| ..)` method takes [addr6_rx::W](addr6_rx::W) writer structure
    impl crate::Writable for ADDR6_RX {}
    ///Reception buffer address 0
    pub mod addr6_rx {
        ///Reader of register ADDR6_RX
        pub type R = crate::R<u16, super::ADDR6_RX>;
        ///Writer for register ADDR6_RX
        pub type W = crate::W<u16, super::ADDR6_RX>;
        ///Register ADDR6_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR6_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR6_RX`
        pub type ADDR6_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR6_RX`
        pub struct ADDR6_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR6_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr6_rx(&self) -> ADDR6_RX_R {
                ADDR6_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr6_rx(&mut self) -> ADDR6_RX_W {
                ADDR6_RX_W { w: self }
            }
        }
    }
    ///Reception buffer address 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [addr7_rx](addr7_rx) module
    pub type ADDR7_RX = crate::Reg<u16, _ADDR7_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ADDR7_RX;
    ///`read()` method returns [addr7_rx::R](addr7_rx::R) reader structure
    impl crate::Readable for ADDR7_RX {}
    ///`write(|w| ..)` method takes [addr7_rx::W](addr7_rx::W) writer structure
    impl crate::Writable for ADDR7_RX {}
    ///Reception buffer address 0
    pub mod addr7_rx {
        ///Reader of register ADDR7_RX
        pub type R = crate::R<u16, super::ADDR7_RX>;
        ///Writer for register ADDR7_RX
        pub type W = crate::W<u16, super::ADDR7_RX>;
        ///Register ADDR7_RX `reset()`'s with value 0
        impl crate::ResetValue for super::ADDR7_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ADDR7_RX`
        pub type ADDR7_RX_R = crate::R<u16, u16>;
        ///Write proxy for field `ADDR7_RX`
        pub struct ADDR7_RX_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ADDR7_RX_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u16) & 0x7fff) << 1);
                self.w
            }
        }
        impl R {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr7_rx(&self) -> ADDR7_RX_R {
                ADDR7_RX_R::new(((self.bits >> 1) & 0x7fff) as u16)
            }
        }
        impl W {
            ///Bits 1:15 - Reception buffer address
            #[inline(always)]
            pub fn addr7_rx(&mut self) -> ADDR7_RX_W {
                ADDR7_RX_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count0_rx](count0_rx) module
    pub type COUNT0_RX = crate::Reg<u16, _COUNT0_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT0_RX;
    ///`read()` method returns [count0_rx::R](count0_rx::R) reader structure
    impl crate::Readable for COUNT0_RX {}
    ///`write(|w| ..)` method takes [count0_rx::W](count0_rx::W) writer structure
    impl crate::Writable for COUNT0_RX {}
    ///Reception byte count 0
    pub mod count0_rx {
        ///Reader of register COUNT0_RX
        pub type R = crate::R<u16, super::COUNT0_RX>;
        ///Writer for register COUNT0_RX
        pub type W = crate::W<u16, super::COUNT0_RX>;
        ///Register COUNT0_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT0_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT0_RX`
        pub type COUNT0_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count0_rx(&self) -> COUNT0_RX_R {
                COUNT0_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count1_rx](count1_rx) module
    pub type COUNT1_RX = crate::Reg<u16, _COUNT1_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT1_RX;
    ///`read()` method returns [count1_rx::R](count1_rx::R) reader structure
    impl crate::Readable for COUNT1_RX {}
    ///`write(|w| ..)` method takes [count1_rx::W](count1_rx::W) writer structure
    impl crate::Writable for COUNT1_RX {}
    ///Reception byte count 0
    pub mod count1_rx {
        ///Reader of register COUNT1_RX
        pub type R = crate::R<u16, super::COUNT1_RX>;
        ///Writer for register COUNT1_RX
        pub type W = crate::W<u16, super::COUNT1_RX>;
        ///Register COUNT1_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT1_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT1_RX`
        pub type COUNT1_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count1_rx(&self) -> COUNT1_RX_R {
                COUNT1_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count2_rx](count2_rx) module
    pub type COUNT2_RX = crate::Reg<u16, _COUNT2_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT2_RX;
    ///`read()` method returns [count2_rx::R](count2_rx::R) reader structure
    impl crate::Readable for COUNT2_RX {}
    ///`write(|w| ..)` method takes [count2_rx::W](count2_rx::W) writer structure
    impl crate::Writable for COUNT2_RX {}
    ///Reception byte count 0
    pub mod count2_rx {
        ///Reader of register COUNT2_RX
        pub type R = crate::R<u16, super::COUNT2_RX>;
        ///Writer for register COUNT2_RX
        pub type W = crate::W<u16, super::COUNT2_RX>;
        ///Register COUNT2_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT2_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT2_RX`
        pub type COUNT2_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count2_rx(&self) -> COUNT2_RX_R {
                COUNT2_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count3_rx](count3_rx) module
    pub type COUNT3_RX = crate::Reg<u16, _COUNT3_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT3_RX;
    ///`read()` method returns [count3_rx::R](count3_rx::R) reader structure
    impl crate::Readable for COUNT3_RX {}
    ///`write(|w| ..)` method takes [count3_rx::W](count3_rx::W) writer structure
    impl crate::Writable for COUNT3_RX {}
    ///Reception byte count 0
    pub mod count3_rx {
        ///Reader of register COUNT3_RX
        pub type R = crate::R<u16, super::COUNT3_RX>;
        ///Writer for register COUNT3_RX
        pub type W = crate::W<u16, super::COUNT3_RX>;
        ///Register COUNT3_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT3_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT3_RX`
        pub type COUNT3_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count3_rx(&self) -> COUNT3_RX_R {
                COUNT3_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count4_rx](count4_rx) module
    pub type COUNT4_RX = crate::Reg<u16, _COUNT4_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT4_RX;
    ///`read()` method returns [count4_rx::R](count4_rx::R) reader structure
    impl crate::Readable for COUNT4_RX {}
    ///`write(|w| ..)` method takes [count4_rx::W](count4_rx::W) writer structure
    impl crate::Writable for COUNT4_RX {}
    ///Reception byte count 0
    pub mod count4_rx {
        ///Reader of register COUNT4_RX
        pub type R = crate::R<u16, super::COUNT4_RX>;
        ///Writer for register COUNT4_RX
        pub type W = crate::W<u16, super::COUNT4_RX>;
        ///Register COUNT4_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT4_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT4_RX`
        pub type COUNT4_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count4_rx(&self) -> COUNT4_RX_R {
                COUNT4_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count5_rx](count5_rx) module
    pub type COUNT5_RX = crate::Reg<u16, _COUNT5_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT5_RX;
    ///`read()` method returns [count5_rx::R](count5_rx::R) reader structure
    impl crate::Readable for COUNT5_RX {}
    ///`write(|w| ..)` method takes [count5_rx::W](count5_rx::W) writer structure
    impl crate::Writable for COUNT5_RX {}
    ///Reception byte count 0
    pub mod count5_rx {
        ///Reader of register COUNT5_RX
        pub type R = crate::R<u16, super::COUNT5_RX>;
        ///Writer for register COUNT5_RX
        pub type W = crate::W<u16, super::COUNT5_RX>;
        ///Register COUNT5_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT5_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT5_RX`
        pub type COUNT5_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count5_rx(&self) -> COUNT5_RX_R {
                COUNT5_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count6_rx](count6_rx) module
    pub type COUNT6_RX = crate::Reg<u16, _COUNT6_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT6_RX;
    ///`read()` method returns [count6_rx::R](count6_rx::R) reader structure
    impl crate::Readable for COUNT6_RX {}
    ///`write(|w| ..)` method takes [count6_rx::W](count6_rx::W) writer structure
    impl crate::Writable for COUNT6_RX {}
    ///Reception byte count 0
    pub mod count6_rx {
        ///Reader of register COUNT6_RX
        pub type R = crate::R<u16, super::COUNT6_RX>;
        ///Writer for register COUNT6_RX
        pub type W = crate::W<u16, super::COUNT6_RX>;
        ///Register COUNT6_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT6_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT6_RX`
        pub type COUNT6_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count6_rx(&self) -> COUNT6_RX_R {
                COUNT6_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///Reception byte count 0
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [count7_rx](count7_rx) module
    pub type COUNT7_RX = crate::Reg<u16, _COUNT7_RX>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _COUNT7_RX;
    ///`read()` method returns [count7_rx::R](count7_rx::R) reader structure
    impl crate::Readable for COUNT7_RX {}
    ///`write(|w| ..)` method takes [count7_rx::W](count7_rx::W) writer structure
    impl crate::Writable for COUNT7_RX {}
    ///Reception byte count 0
    pub mod count7_rx {
        ///Reader of register COUNT7_RX
        pub type R = crate::R<u16, super::COUNT7_RX>;
        ///Writer for register COUNT7_RX
        pub type W = crate::W<u16, super::COUNT7_RX>;
        ///Register COUNT7_RX `reset()`'s with value 0
        impl crate::ResetValue for super::COUNT7_RX {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `COUNT7_RX`
        pub type COUNT7_RX_R = crate::R<u16, u16>;
        ///Reader of field `NUM_BLOCK`
        pub type NUM_BLOCK_R = crate::R<u8, u8>;
        ///Write proxy for field `NUM_BLOCK`
        pub struct NUM_BLOCK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NUM_BLOCK_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u16) & 0x1f) << 10);
                self.w
            }
        }
        ///Reader of field `BL_SIZE`
        pub type BL_SIZE_R = crate::R<bool, bool>;
        ///Write proxy for field `BL_SIZE`
        pub struct BL_SIZE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BL_SIZE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bits 0:9 - Reception byte count
            #[inline(always)]
            pub fn count7_rx(&self) -> COUNT7_RX_R {
                COUNT7_RX_R::new((self.bits & 0x03ff) as u16)
            }
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&self) -> NUM_BLOCK_R {
                NUM_BLOCK_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&self) -> BL_SIZE_R {
                BL_SIZE_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 10:14 - Number of blocks
            #[inline(always)]
            pub fn num_block(&mut self) -> NUM_BLOCK_W {
                NUM_BLOCK_W { w: self }
            }
            ///Bit 15 - Block size
            #[inline(always)]
            pub fn bl_size(&mut self) -> BL_SIZE_W {
                BL_SIZE_W { w: self }
            }
        }
    }
    ///control and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [lpmcsr](lpmcsr) module
    pub type LPMCSR = crate::Reg<u16, _LPMCSR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LPMCSR;
    ///`read()` method returns [lpmcsr::R](lpmcsr::R) reader structure
    impl crate::Readable for LPMCSR {}
    ///`write(|w| ..)` method takes [lpmcsr::W](lpmcsr::W) writer structure
    impl crate::Writable for LPMCSR {}
    ///control and status register
    pub mod lpmcsr {
        ///Reader of register LPMCSR
        pub type R = crate::R<u16, super::LPMCSR>;
        ///Writer for register LPMCSR
        pub type W = crate::W<u16, super::LPMCSR>;
        ///Register LPMCSR `reset()`'s with value 0
        impl crate::ResetValue for super::LPMCSR {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `LPMEN`
        pub type LPMEN_R = crate::R<bool, bool>;
        ///Write proxy for field `LPMEN`
        pub struct LPMEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPMEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u16) & 0x01);
                self.w
            }
        }
        ///Reader of field `LPMACK`
        pub type LPMACK_R = crate::R<bool, bool>;
        ///Write proxy for field `LPMACK`
        pub struct LPMACK_W<'a> {
            w: &'a mut W,
        }
        impl<'a> LPMACK_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u16) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `REMWAKE`
        pub type REMWAKE_R = crate::R<bool, bool>;
        ///Write proxy for field `REMWAKE`
        pub struct REMWAKE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> REMWAKE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u16) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `BESL`
        pub type BESL_R = crate::R<u8, u8>;
        impl R {
            ///Bit 0 - LPM support enable
            #[inline(always)]
            pub fn lpmen(&self) -> LPMEN_R {
                LPMEN_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - LPM Token acknowledge enable
            #[inline(always)]
            pub fn lpmack(&self) -> LPMACK_R {
                LPMACK_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 3 - RemoteWake value
            #[inline(always)]
            pub fn remwake(&self) -> REMWAKE_R {
                REMWAKE_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bits 4:7 - BESL value
            #[inline(always)]
            pub fn besl(&self) -> BESL_R {
                BESL_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bit 0 - LPM support enable
            #[inline(always)]
            pub fn lpmen(&mut self) -> LPMEN_W {
                LPMEN_W { w: self }
            }
            ///Bit 1 - LPM Token acknowledge enable
            #[inline(always)]
            pub fn lpmack(&mut self) -> LPMACK_W {
                LPMACK_W { w: self }
            }
            ///Bit 3 - RemoteWake value
            #[inline(always)]
            pub fn remwake(&mut self) -> REMWAKE_W {
                REMWAKE_W { w: self }
            }
        }
    }
    ///Battery charging detector(
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [bcdr](bcdr) module
    pub type BCDR = crate::Reg<u16, _BCDR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _BCDR;
    ///`read()` method returns [bcdr::R](bcdr::R) reader structure
    impl crate::Readable for BCDR {}
    ///`write(|w| ..)` method takes [bcdr::W](bcdr::W) writer structure
    impl crate::Writable for BCDR {}
    ///Battery charging detector(
    pub mod bcdr {
        ///Reader of register BCDR
        pub type R = crate::R<u16, super::BCDR>;
        ///Writer for register BCDR
        pub type W = crate::W<u16, super::BCDR>;
        ///Register BCDR `reset()`'s with value 0
        impl crate::ResetValue for super::BCDR {
            type Type = u16;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `BCDEN`
        pub type BCDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `BCDEN`
        pub struct BCDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> BCDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u16) & 0x01);
                self.w
            }
        }
        ///Reader of field `DCDEN`
        pub type DCDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `DCDEN`
        pub struct DCDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DCDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u16) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `PDEN`
        pub type PDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `PDEN`
        pub struct PDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> PDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u16) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `SDEN`
        pub type SDEN_R = crate::R<bool, bool>;
        ///Write proxy for field `SDEN`
        pub struct SDEN_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SDEN_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u16) & 0x01) << 3);
                self.w
            }
        }
        ///Reader of field `DCDET`
        pub type DCDET_R = crate::R<bool, bool>;
        ///Reader of field `PDET`
        pub type PDET_R = crate::R<bool, bool>;
        ///Reader of field `SDET`
        pub type SDET_R = crate::R<bool, bool>;
        ///Reader of field `PS2DET`
        pub type PS2DET_R = crate::R<bool, bool>;
        ///Reader of field `DPPU`
        pub type DPPU_R = crate::R<bool, bool>;
        ///Write proxy for field `DPPU`
        pub struct DPPU_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DPPU_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Battery charging detector (BCD) enable
            #[inline(always)]
            pub fn bcden(&self) -> BCDEN_R {
                BCDEN_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - Data contact detection (DCD) mode enable
            #[inline(always)]
            pub fn dcden(&self) -> DCDEN_R {
                DCDEN_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Primary detection (PD) mode enable
            #[inline(always)]
            pub fn pden(&self) -> PDEN_R {
                PDEN_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 3 - Secondary detection (SD) mode enable
            #[inline(always)]
            pub fn sden(&self) -> SDEN_R {
                SDEN_R::new(((self.bits >> 3) & 0x01) != 0)
            }
            ///Bit 4 - Data contact detection (DCD) status
            #[inline(always)]
            pub fn dcdet(&self) -> DCDET_R {
                DCDET_R::new(((self.bits >> 4) & 0x01) != 0)
            }
            ///Bit 5 - Primary detection (PD) status
            #[inline(always)]
            pub fn pdet(&self) -> PDET_R {
                PDET_R::new(((self.bits >> 5) & 0x01) != 0)
            }
            ///Bit 6 - Secondary detection (SD) status
            #[inline(always)]
            pub fn sdet(&self) -> SDET_R {
                SDET_R::new(((self.bits >> 6) & 0x01) != 0)
            }
            ///Bit 7 - DM pull-up detection status
            #[inline(always)]
            pub fn ps2det(&self) -> PS2DET_R {
                PS2DET_R::new(((self.bits >> 7) & 0x01) != 0)
            }
            ///Bit 15 - DP pull-up control
            #[inline(always)]
            pub fn dppu(&self) -> DPPU_R {
                DPPU_R::new(((self.bits >> 15) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Battery charging detector (BCD) enable
            #[inline(always)]
            pub fn bcden(&mut self) -> BCDEN_W {
                BCDEN_W { w: self }
            }
            ///Bit 1 - Data contact detection (DCD) mode enable
            #[inline(always)]
            pub fn dcden(&mut self) -> DCDEN_W {
                DCDEN_W { w: self }
            }
            ///Bit 2 - Primary detection (PD) mode enable
            #[inline(always)]
            pub fn pden(&mut self) -> PDEN_W {
                PDEN_W { w: self }
            }
            ///Bit 3 - Secondary detection (SD) mode enable
            #[inline(always)]
            pub fn sden(&mut self) -> SDEN_W {
                SDEN_W { w: self }
            }
            ///Bit 15 - DP pull-up control
            #[inline(always)]
            pub fn dppu(&mut self) -> DPPU_W {
                DPPU_W { w: self }
            }
        }
    }
}
///SysTick timer
pub struct STK {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for STK {}
impl STK {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const stk::RegisterBlock {
        0xe000_e010 as *const _
    }
}
impl Deref for STK {
    type Target = stk::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*STK::ptr() }
    }
}
///SysTick timer
pub mod stk {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - SysTick control and status register
        pub ctrl: CTRL,
        ///0x04 - SysTick reload value register
        pub load: LOAD,
        ///0x08 - SysTick current value register
        pub val: VAL,
        ///0x0c - SysTick calibration value register
        pub calib: CALIB,
    }
    ///SysTick control and status register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [ctrl](ctrl) module
    pub type CTRL = crate::Reg<u32, _CTRL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CTRL;
    ///`read()` method returns [ctrl::R](ctrl::R) reader structure
    impl crate::Readable for CTRL {}
    ///`write(|w| ..)` method takes [ctrl::W](ctrl::W) writer structure
    impl crate::Writable for CTRL {}
    ///SysTick control and status register
    pub mod ctrl {
        ///Reader of register CTRL
        pub type R = crate::R<u32, super::CTRL>;
        ///Writer for register CTRL
        pub type W = crate::W<u32, super::CTRL>;
        ///Register CTRL `reset()`'s with value 0
        impl crate::ResetValue for super::CTRL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `ENABLE`
        pub type ENABLE_R = crate::R<bool, bool>;
        ///Write proxy for field `ENABLE`
        pub struct ENABLE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> ENABLE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `TICKINT`
        pub type TICKINT_R = crate::R<bool, bool>;
        ///Write proxy for field `TICKINT`
        pub struct TICKINT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TICKINT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `CLKSOURCE`
        pub type CLKSOURCE_R = crate::R<bool, bool>;
        ///Write proxy for field `CLKSOURCE`
        pub struct CLKSOURCE_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CLKSOURCE_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `COUNTFLAG`
        pub type COUNTFLAG_R = crate::R<bool, bool>;
        ///Write proxy for field `COUNTFLAG`
        pub struct COUNTFLAG_W<'a> {
            w: &'a mut W,
        }
        impl<'a> COUNTFLAG_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
                self.w
            }
        }
        impl R {
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - SysTick exception request enable
            #[inline(always)]
            pub fn tickint(&self) -> TICKINT_R {
                TICKINT_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - Clock source selection
            #[inline(always)]
            pub fn clksource(&self) -> CLKSOURCE_R {
                CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 16 - COUNTFLAG
            #[inline(always)]
            pub fn countflag(&self) -> COUNTFLAG_R {
                COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - Counter enable
            #[inline(always)]
            pub fn enable(&mut self) -> ENABLE_W {
                ENABLE_W { w: self }
            }
            ///Bit 1 - SysTick exception request enable
            #[inline(always)]
            pub fn tickint(&mut self) -> TICKINT_W {
                TICKINT_W { w: self }
            }
            ///Bit 2 - Clock source selection
            #[inline(always)]
            pub fn clksource(&mut self) -> CLKSOURCE_W {
                CLKSOURCE_W { w: self }
            }
            ///Bit 16 - COUNTFLAG
            #[inline(always)]
            pub fn countflag(&mut self) -> COUNTFLAG_W {
                COUNTFLAG_W { w: self }
            }
        }
    }
    ///SysTick reload value register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [load](load) module
    pub type LOAD = crate::Reg<u32, _LOAD>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _LOAD;
    ///`read()` method returns [load::R](load::R) reader structure
    impl crate::Readable for LOAD {}
    ///`write(|w| ..)` method takes [load::W](load::W) writer structure
    impl crate::Writable for LOAD {}
    ///SysTick reload value register
    pub mod load {
        ///Reader of register LOAD
        pub type R = crate::R<u32, super::LOAD>;
        ///Writer for register LOAD
        pub type W = crate::W<u32, super::LOAD>;
        ///Register LOAD `reset()`'s with value 0
        impl crate::ResetValue for super::LOAD {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `RELOAD`
        pub type RELOAD_R = crate::R<u32, u32>;
        ///Write proxy for field `RELOAD`
        pub struct RELOAD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> RELOAD_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x00ff_ffff) | ((value as u32) & 0x00ff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:23 - RELOAD value
            #[inline(always)]
            pub fn reload(&self) -> RELOAD_R {
                RELOAD_R::new((self.bits & 0x00ff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:23 - RELOAD value
            #[inline(always)]
            pub fn reload(&mut self) -> RELOAD_W {
                RELOAD_W { w: self }
            }
        }
    }
    ///SysTick current value register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [val](val) module
    pub type VAL = crate::Reg<u32, _VAL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _VAL;
    ///`read()` method returns [val::R](val::R) reader structure
    impl crate::Readable for VAL {}
    ///`write(|w| ..)` method takes [val::W](val::W) writer structure
    impl crate::Writable for VAL {}
    ///SysTick current value register
    pub mod val {
        ///Reader of register VAL
        pub type R = crate::R<u32, super::VAL>;
        ///Writer for register VAL
        pub type W = crate::W<u32, super::VAL>;
        ///Register VAL `reset()`'s with value 0
        impl crate::ResetValue for super::VAL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CURRENT`
        pub type CURRENT_R = crate::R<u32, u32>;
        ///Write proxy for field `CURRENT`
        pub struct CURRENT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CURRENT_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x00ff_ffff) | ((value as u32) & 0x00ff_ffff);
                self.w
            }
        }
        impl R {
            ///Bits 0:23 - Current counter value
            #[inline(always)]
            pub fn current(&self) -> CURRENT_R {
                CURRENT_R::new((self.bits & 0x00ff_ffff) as u32)
            }
        }
        impl W {
            ///Bits 0:23 - Current counter value
            #[inline(always)]
            pub fn current(&mut self) -> CURRENT_W {
                CURRENT_W { w: self }
            }
        }
    }
    ///SysTick calibration value register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [calib](calib) module
    pub type CALIB = crate::Reg<u32, _CALIB>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CALIB;
    ///`read()` method returns [calib::R](calib::R) reader structure
    impl crate::Readable for CALIB {}
    ///`write(|w| ..)` method takes [calib::W](calib::W) writer structure
    impl crate::Writable for CALIB {}
    ///SysTick calibration value register
    pub mod calib {
        ///Reader of register CALIB
        pub type R = crate::R<u32, super::CALIB>;
        ///Writer for register CALIB
        pub type W = crate::W<u32, super::CALIB>;
        ///Register CALIB `reset()`'s with value 0
        impl crate::ResetValue for super::CALIB {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `TENMS`
        pub type TENMS_R = crate::R<u32, u32>;
        ///Write proxy for field `TENMS`
        pub struct TENMS_W<'a> {
            w: &'a mut W,
        }
        impl<'a> TENMS_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u32) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x00ff_ffff) | ((value as u32) & 0x00ff_ffff);
                self.w
            }
        }
        ///Reader of field `SKEW`
        pub type SKEW_R = crate::R<bool, bool>;
        ///Write proxy for field `SKEW`
        pub struct SKEW_W<'a> {
            w: &'a mut W,
        }
        impl<'a> SKEW_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
                self.w
            }
        }
        ///Reader of field `NOREF`
        pub type NOREF_R = crate::R<bool, bool>;
        ///Write proxy for field `NOREF`
        pub struct NOREF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> NOREF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
                self.w
            }
        }
        impl R {
            ///Bits 0:23 - Calibration value
            #[inline(always)]
            pub fn tenms(&self) -> TENMS_R {
                TENMS_R::new((self.bits & 0x00ff_ffff) as u32)
            }
            ///Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
            #[inline(always)]
            pub fn skew(&self) -> SKEW_R {
                SKEW_R::new(((self.bits >> 30) & 0x01) != 0)
            }
            ///Bit 31 - NOREF flag. Reads as zero
            #[inline(always)]
            pub fn noref(&self) -> NOREF_R {
                NOREF_R::new(((self.bits >> 31) & 0x01) != 0)
            }
        }
        impl W {
            ///Bits 0:23 - Calibration value
            #[inline(always)]
            pub fn tenms(&mut self) -> TENMS_W {
                TENMS_W { w: self }
            }
            ///Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
            #[inline(always)]
            pub fn skew(&mut self) -> SKEW_W {
                SKEW_W { w: self }
            }
            ///Bit 31 - NOREF flag. Reads as zero
            #[inline(always)]
            pub fn noref(&mut self) -> NOREF_W {
                NOREF_W { w: self }
            }
        }
    }
}
///Nested vectored interrupt controller
pub struct NVIC_STIR {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for NVIC_STIR {}
impl NVIC_STIR {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const nvic_stir::RegisterBlock {
        0xe000_ef00 as *const _
    }
}
impl Deref for NVIC_STIR {
    type Target = nvic_stir::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*NVIC_STIR::ptr() }
    }
}
///Nested vectored interrupt controller
pub mod nvic_stir {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Software trigger interrupt register
        pub stir: STIR,
    }
    ///Software trigger interrupt register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [stir](stir) module
    pub type STIR = crate::Reg<u32, _STIR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _STIR;
    ///`read()` method returns [stir::R](stir::R) reader structure
    impl crate::Readable for STIR {}
    ///`write(|w| ..)` method takes [stir::W](stir::W) writer structure
    impl crate::Writable for STIR {}
    ///Software trigger interrupt register
    pub mod stir {
        ///Reader of register STIR
        pub type R = crate::R<u32, super::STIR>;
        ///Writer for register STIR
        pub type W = crate::W<u32, super::STIR>;
        ///Register STIR `reset()`'s with value 0
        impl crate::ResetValue for super::STIR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `INTID`
        pub type INTID_R = crate::R<u16, u16>;
        ///Write proxy for field `INTID`
        pub struct INTID_W<'a> {
            w: &'a mut W,
        }
        impl<'a> INTID_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u16) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
                self.w
            }
        }
        impl R {
            ///Bits 0:8 - Software generated interrupt ID
            #[inline(always)]
            pub fn intid(&self) -> INTID_R {
                INTID_R::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            ///Bits 0:8 - Software generated interrupt ID
            #[inline(always)]
            pub fn intid(&mut self) -> INTID_W {
                INTID_W { w: self }
            }
        }
    }
}
///System control block ACTLR
pub struct SCB_ACTRL {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SCB_ACTRL {}
impl SCB_ACTRL {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const scb_actrl::RegisterBlock {
        0xe000_e008 as *const _
    }
}
impl Deref for SCB_ACTRL {
    type Target = scb_actrl::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*SCB_ACTRL::ptr() }
    }
}
///System control block ACTLR
pub mod scb_actrl {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Auxiliary control register
        pub actrl: ACTRL,
    }
    ///Auxiliary control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [actrl](actrl) module
    pub type ACTRL = crate::Reg<u32, _ACTRL>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _ACTRL;
    ///`read()` method returns [actrl::R](actrl::R) reader structure
    impl crate::Readable for ACTRL {}
    ///`write(|w| ..)` method takes [actrl::W](actrl::W) writer structure
    impl crate::Writable for ACTRL {}
    ///Auxiliary control register
    pub mod actrl {
        ///Reader of register ACTRL
        pub type R = crate::R<u32, super::ACTRL>;
        ///Writer for register ACTRL
        pub type W = crate::W<u32, super::ACTRL>;
        ///Register ACTRL `reset()`'s with value 0
        impl crate::ResetValue for super::ACTRL {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `DISMCYCINT`
        pub type DISMCYCINT_R = crate::R<bool, bool>;
        ///Write proxy for field `DISMCYCINT`
        pub struct DISMCYCINT_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DISMCYCINT_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
                self.w
            }
        }
        ///Reader of field `DISDEFWBUF`
        pub type DISDEFWBUF_R = crate::R<bool, bool>;
        ///Write proxy for field `DISDEFWBUF`
        pub struct DISDEFWBUF_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DISDEFWBUF_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
                self.w
            }
        }
        ///Reader of field `DISFOLD`
        pub type DISFOLD_R = crate::R<bool, bool>;
        ///Write proxy for field `DISFOLD`
        pub struct DISFOLD_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DISFOLD_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
                self.w
            }
        }
        ///Reader of field `DISFPCA`
        pub type DISFPCA_R = crate::R<bool, bool>;
        ///Write proxy for field `DISFPCA`
        pub struct DISFPCA_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DISFPCA_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
                self.w
            }
        }
        ///Reader of field `DISOOFP`
        pub type DISOOFP_R = crate::R<bool, bool>;
        ///Write proxy for field `DISOOFP`
        pub struct DISOOFP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> DISOOFP_W<'a> {
            ///Sets the field bit
            #[inline(always)]
            pub fn set_bit(self) -> &'a mut W {
                self.bit(true)
            }
            ///Clears the field bit
            #[inline(always)]
            pub fn clear_bit(self) -> &'a mut W {
                self.bit(false)
            }
            ///Writes raw bits to the field
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
                self.w
            }
        }
        impl R {
            ///Bit 0 - DISMCYCINT
            #[inline(always)]
            pub fn dismcycint(&self) -> DISMCYCINT_R {
                DISMCYCINT_R::new((self.bits & 0x01) != 0)
            }
            ///Bit 1 - DISDEFWBUF
            #[inline(always)]
            pub fn disdefwbuf(&self) -> DISDEFWBUF_R {
                DISDEFWBUF_R::new(((self.bits >> 1) & 0x01) != 0)
            }
            ///Bit 2 - DISFOLD
            #[inline(always)]
            pub fn disfold(&self) -> DISFOLD_R {
                DISFOLD_R::new(((self.bits >> 2) & 0x01) != 0)
            }
            ///Bit 8 - DISFPCA
            #[inline(always)]
            pub fn disfpca(&self) -> DISFPCA_R {
                DISFPCA_R::new(((self.bits >> 8) & 0x01) != 0)
            }
            ///Bit 9 - DISOOFP
            #[inline(always)]
            pub fn disoofp(&self) -> DISOOFP_R {
                DISOOFP_R::new(((self.bits >> 9) & 0x01) != 0)
            }
        }
        impl W {
            ///Bit 0 - DISMCYCINT
            #[inline(always)]
            pub fn dismcycint(&mut self) -> DISMCYCINT_W {
                DISMCYCINT_W { w: self }
            }
            ///Bit 1 - DISDEFWBUF
            #[inline(always)]
            pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W {
                DISDEFWBUF_W { w: self }
            }
            ///Bit 2 - DISFOLD
            #[inline(always)]
            pub fn disfold(&mut self) -> DISFOLD_W {
                DISFOLD_W { w: self }
            }
            ///Bit 8 - DISFPCA
            #[inline(always)]
            pub fn disfpca(&mut self) -> DISFPCA_W {
                DISFPCA_W { w: self }
            }
            ///Bit 9 - DISOOFP
            #[inline(always)]
            pub fn disoofp(&mut self) -> DISOOFP_W {
                DISOOFP_W { w: self }
            }
        }
    }
}
///Floating point unit CPACR
pub struct FPU_CPACR {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for FPU_CPACR {}
impl FPU_CPACR {
    ///Returns a pointer to the register block
    #[inline(always)]
    pub const fn ptr() -> *const fpu_cpacr::RegisterBlock {
        0xe000_ed88 as *const _
    }
}
impl Deref for FPU_CPACR {
    type Target = fpu_cpacr::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*FPU_CPACR::ptr() }
    }
}
///Floating point unit CPACR
pub mod fpu_cpacr {
    ///Register block
    #[repr(C)]
    pub struct RegisterBlock {
        ///0x00 - Coprocessor access control register
        pub cpacr: CPACR,
    }
    ///Coprocessor access control register
    ///
    ///This register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
    ///
    ///For information about available fields see [cpacr](cpacr) module
    pub type CPACR = crate::Reg<u32, _CPACR>;
    #[allow(missing_docs)]
    #[doc(hidden)]
    pub struct _CPACR;
    ///`read()` method returns [cpacr::R](cpacr::R) reader structure
    impl crate::Readable for CPACR {}
    ///`write(|w| ..)` method takes [cpacr::W](cpacr::W) writer structure
    impl crate::Writable for CPACR {}
    ///Coprocessor access control register
    pub mod cpacr {
        ///Reader of register CPACR
        pub type R = crate::R<u32, super::CPACR>;
        ///Writer for register CPACR
        pub type W = crate::W<u32, super::CPACR>;
        ///Register CPACR `reset()`'s with value 0
        impl crate::ResetValue for super::CPACR {
            type Type = u32;
            #[inline(always)]
            fn reset_value() -> Self::Type {
                0
            }
        }
        ///Reader of field `CP`
        pub type CP_R = crate::R<u8, u8>;
        ///Write proxy for field `CP`
        pub struct CP_W<'a> {
            w: &'a mut W,
        }
        impl<'a> CP_W<'a> {
            ///Writes raw bits to the field
            #[inline(always)]
            pub unsafe fn bits(self, value: u8) -> &'a mut W {
                self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
                self.w
            }
        }
        impl R {
            ///Bits 20:23 - CP
            #[inline(always)]
            pub fn cp(&self) -> CP_R {
                CP_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
        }
        impl W {
            ///Bits 20:23 - CP
            #[inline(always)]
            pub fn cp(&mut self) -> CP_W {
                CP_W { w: self }
            }
        }
    }
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
///All the peripherals
#[allow(non_snake_case)]
pub struct Peripherals {
    ///DMA1
    pub DMA1: DMA1,
    ///DMA2
    pub DMA2: DMA2,
    ///DMAMUX1
    pub DMAMUX1: DMAMUX1,
    ///CRC
    pub CRC: CRC,
    ///LCD
    pub LCD: LCD,
    ///TSC
    pub TSC: TSC,
    ///IWDG
    pub IWDG: IWDG,
    ///WWDG
    pub WWDG: WWDG,
    ///COMP
    pub COMP: COMP,
    ///I2C1
    pub I2C1: I2C1,
    ///I2C3
    pub I2C3: I2C3,
    ///FLASH
    pub FLASH: FLASH,
    ///QUADSPI
    pub QUADSPI: QUADSPI,
    ///RCC
    pub RCC: RCC,
    ///PWR
    pub PWR: PWR,
    ///SYSCFG
    pub SYSCFG: SYSCFG,
    ///RNG
    pub RNG: RNG,
    ///AES1
    pub AES1: AES1,
    ///AES2
    pub AES2: AES2,
    ///HSEM
    pub HSEM: HSEM,
    ///ADC
    pub ADC: ADC,
    ///GPIOA
    pub GPIOA: GPIOA,
    ///GPIOB
    pub GPIOB: GPIOB,
    ///GPIOC
    pub GPIOC: GPIOC,
    ///GPIOD
    pub GPIOD: GPIOD,
    ///GPIOE
    pub GPIOE: GPIOE,
    ///GPIOH
    pub GPIOH: GPIOH,
    ///SAI1
    pub SAI1: SAI1,
    ///TIM2
    pub TIM2: TIM2,
    ///TIM16
    pub TIM16: TIM16,
    ///TIM17
    pub TIM17: TIM17,
    ///TIM1
    pub TIM1: TIM1,
    ///LPTIM1
    pub LPTIM1: LPTIM1,
    ///LPTIM2
    pub LPTIM2: LPTIM2,
    ///USART1
    pub USART1: USART1,
    ///LPUART1
    pub LPUART1: LPUART1,
    ///SPI1
    pub SPI1: SPI1,
    ///SPI2
    pub SPI2: SPI2,
    ///VREFBUF
    pub VREFBUF: VREFBUF,
    ///RTC
    pub RTC: RTC,
    ///DBGMCU
    pub DBGMCU: DBGMCU,
    ///PKA
    pub PKA: PKA,
    ///IPCC
    pub IPCC: IPCC,
    ///EXTI
    pub EXTI: EXTI,
    ///CRS
    pub CRS: CRS,
    ///USB
    pub USB: USB,
    ///STK
    pub STK: STK,
    ///NVIC_STIR
    pub NVIC_STIR: NVIC_STIR,
    ///SCB_ACTRL
    pub SCB_ACTRL: SCB_ACTRL,
    ///FPU_CPACR
    pub FPU_CPACR: FPU_CPACR,
}
impl Peripherals {
    ///Returns all the peripherals *once*
    #[inline]
    pub fn take() -> Option<Self> {
        cortex_m::interrupt::free(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                None
            } else {
                Some(unsafe { Peripherals::steal() })
            }
        })
    }
    ///Unchecked version of `Peripherals::take`
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            DMA1: DMA1 {
                _marker: PhantomData,
            },
            DMA2: DMA2 {
                _marker: PhantomData,
            },
            DMAMUX1: DMAMUX1 {
                _marker: PhantomData,
            },
            CRC: CRC {
                _marker: PhantomData,
            },
            LCD: LCD {
                _marker: PhantomData,
            },
            TSC: TSC {
                _marker: PhantomData,
            },
            IWDG: IWDG {
                _marker: PhantomData,
            },
            WWDG: WWDG {
                _marker: PhantomData,
            },
            COMP: COMP {
                _marker: PhantomData,
            },
            I2C1: I2C1 {
                _marker: PhantomData,
            },
            I2C3: I2C3 {
                _marker: PhantomData,
            },
            FLASH: FLASH {
                _marker: PhantomData,
            },
            QUADSPI: QUADSPI {
                _marker: PhantomData,
            },
            RCC: RCC {
                _marker: PhantomData,
            },
            PWR: PWR {
                _marker: PhantomData,
            },
            SYSCFG: SYSCFG {
                _marker: PhantomData,
            },
            RNG: RNG {
                _marker: PhantomData,
            },
            AES1: AES1 {
                _marker: PhantomData,
            },
            AES2: AES2 {
                _marker: PhantomData,
            },
            HSEM: HSEM {
                _marker: PhantomData,
            },
            ADC: ADC {
                _marker: PhantomData,
            },
            GPIOA: GPIOA {
                _marker: PhantomData,
            },
            GPIOB: GPIOB {
                _marker: PhantomData,
            },
            GPIOC: GPIOC {
                _marker: PhantomData,
            },
            GPIOD: GPIOD {
                _marker: PhantomData,
            },
            GPIOE: GPIOE {
                _marker: PhantomData,
            },
            GPIOH: GPIOH {
                _marker: PhantomData,
            },
            SAI1: SAI1 {
                _marker: PhantomData,
            },
            TIM2: TIM2 {
                _marker: PhantomData,
            },
            TIM16: TIM16 {
                _marker: PhantomData,
            },
            TIM17: TIM17 {
                _marker: PhantomData,
            },
            TIM1: TIM1 {
                _marker: PhantomData,
            },
            LPTIM1: LPTIM1 {
                _marker: PhantomData,
            },
            LPTIM2: LPTIM2 {
                _marker: PhantomData,
            },
            USART1: USART1 {
                _marker: PhantomData,
            },
            LPUART1: LPUART1 {
                _marker: PhantomData,
            },
            SPI1: SPI1 {
                _marker: PhantomData,
            },
            SPI2: SPI2 {
                _marker: PhantomData,
            },
            VREFBUF: VREFBUF {
                _marker: PhantomData,
            },
            RTC: RTC {
                _marker: PhantomData,
            },
            DBGMCU: DBGMCU {
                _marker: PhantomData,
            },
            PKA: PKA {
                _marker: PhantomData,
            },
            IPCC: IPCC {
                _marker: PhantomData,
            },
            EXTI: EXTI {
                _marker: PhantomData,
            },
            CRS: CRS {
                _marker: PhantomData,
            },
            USB: USB {
                _marker: PhantomData,
            },
            STK: STK {
                _marker: PhantomData,
            },
            NVIC_STIR: NVIC_STIR {
                _marker: PhantomData,
            },
            SCB_ACTRL: SCB_ACTRL {
                _marker: PhantomData,
            },
            FPU_CPACR: FPU_CPACR {
                _marker: PhantomData,
            },
        }
    }
}