Struct stm32wb_stm32hal::stm32wb55::tim17::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub cr1: CR1,
    pub cr2: CR2,
    pub dier: DIER,
    pub sr: SR,
    pub egr: EGR,
    pub ccmr1_output: CCMR1_OUTPUT,
    pub ccmr1_input: CCMR1_INPUT,
    pub ccer: CCER,
    pub cnt: CNT,
    pub psc: PSC,
    pub arr: ARR,
    pub rcr: RCR,
    pub ccr1: CCR1,
    pub bdtr: BDTR,
    pub dcr: DCR,
    pub dmar: DMAR,
    pub or: OR,
    pub af1: AF1,
}

Register block

Fields

cr1: CR1

0x00 - control register 1

cr2: CR2

0x04 - control register 2

dier: DIER

0x08 - DMA/Interrupt enable register

sr: SR

0x0c - status register

egr: EGR

0x10 - event generation register

ccmr1_output: CCMR1_OUTPUT

0x14 - capture/compare mode register (output mode)

ccmr1_input: CCMR1_INPUT

0x18 - capture/compare mode register 1 (input mode)

ccer: CCER

0x1c - capture/compare enable register

cnt: CNT

0x20 - counter

psc: PSC

0x24 - prescaler

arr: ARR

0x28 - auto-reload register

rcr: RCR

0x2c - repetition counter register

ccr1: CCR1

0x30 - capture/compare register 1

bdtr: BDTR

0x34 - break and dead-time register

dcr: DCR

0x38 - DMA control register

dmar: DMAR

0x3c - DMA address for full transfer

or: OR

0x40 - TIM16 option register 1

af1: AF1

0x44 - TIM17 option register 1