Type Definition stm32wb_stm32hal::stm32wb55::rcc::ahb2smenr::R [−][src]
pub type R = R<u32, AHB2SMENR>;
Expand description
Reader of register AHB2SMENR
Implementations
Bit 16 - CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
Bit 13 - CPU1 ADC clocks enable during Sleep and Stop modes
Bit 7 - CPU1 IO port H clocks enable during Sleep and Stop modes
Bit 4 - CPU1 IO port E clocks enable during Sleep and Stop modes
Bit 3 - CPU1 IO port D clocks enable during Sleep and Stop modes
Bit 2 - CPU1 IO port C clocks enable during Sleep and Stop modes
Bit 1 - CPU1 IO port B clocks enable during Sleep and Stop modes
Bit 0 - CPU1 IO port A clocks enable during Sleep and Stop modes