Module tim4

TIM4

Modules

arr

TIM4 auto-reload register

bdtr

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

ccer

TIM4 capture/compare enable register

ccmr3

The channels 5 and 6 can only be configured in output. Output compare mode:

ccmr1alternate4

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

ccmr2alternate20

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

ccr1

TIM4 capture/compare register 1

ccr2

TIM4 capture/compare register 2

ccr3

TIM4 capture/compare register 3

ccr4

TIM4 capture/compare register 4

ccr5

TIM4 capture/compare register 5

ccr6

TIM4 capture/compare register 6

cnt

TIM4 counter

cr1

TIM4 control register 1

cr2

TIM4 control register 2

dcr

TIM4 DMA control register

dier

TIM4 DMA/interrupt enable register

dmar

TIM4 DMA address for full transfer

egr

TIM4 event generation register

psc

TIM4 prescaler

rcr

TIM4 repetition counter register

smcr

TIM4 slave mode control register

sr

TIM4 status register

Structs

RegisterBlock

Register block

Type Aliases

ARR

ARR (rw) register accessor: TIM4 auto-reload register

BDTR

BDTR (rw) register accessor: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

CCER

CCER (rw) register accessor: TIM4 capture/compare enable register

CCMR3

CCMR3 (rw) register accessor: The channels 5 and 6 can only be configured in output. Output compare mode:

CCMR1ALTERNATE4

CCMR1ALTERNATE4 (rw) register accessor: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

CCMR2ALTERNATE20

CCMR2ALTERNATE20 (rw) register accessor: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

CCR1

CCR1 (rw) register accessor: TIM4 capture/compare register 1

CCR2

CCR2 (rw) register accessor: TIM4 capture/compare register 2

CCR3

CCR3 (rw) register accessor: TIM4 capture/compare register 3

CCR4

CCR4 (rw) register accessor: TIM4 capture/compare register 4

CCR5

CCR5 (rw) register accessor: TIM4 capture/compare register 5

CCR6

CCR6 (rw) register accessor: TIM4 capture/compare register 6

CNT

CNT (rw) register accessor: TIM4 counter

CR1

CR1 (rw) register accessor: TIM4 control register 1

CR2

CR2 (rw) register accessor: TIM4 control register 2

DCR

DCR (rw) register accessor: TIM4 DMA control register

DIER

DIER (rw) register accessor: TIM4 DMA/interrupt enable register

DMAR

DMAR (rw) register accessor: TIM4 DMA address for full transfer

EGR

EGR (w) register accessor: TIM4 event generation register

PSC

PSC (rw) register accessor: TIM4 prescaler

RCR

RCR (rw) register accessor: TIM4 repetition counter register

SMCR

SMCR (rw) register accessor: TIM4 slave mode control register

SR

SR (rw) register accessor: TIM4 status register