Struct stm32mp1::stm32mp157::otg::otg_haintmsk::OTG_HAINTMSK_SPEC

pub struct OTG_HAINTMSK_SPEC;

The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see otg_haintmsk module

Trait Implementations

impl Readable for OTG_HAINTMSK_SPEC

read() method returns otg_haintmsk::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for OTG_HAINTMSK_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for OTG_HAINTMSK_SPEC

reset() method sets OTG_HAINTMSK to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for OTG_HAINTMSK_SPEC

write(|w| ..) method takes otg_haintmsk::W writer structure

type Writer = W

Writer type argument to write, et al.