Module stm32mp1::stm32mp157::otg
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OTG
Modules
This is a register containing the Product ID as reset value.
When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).
The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set.
This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
OTG device control register
OTG device each endpoint interrupt register
There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG device IN endpoint 0 DMA address register
OTG device IN endpoint 1 DMA address register
OTG device IN endpoint 2 DMA address register
OTG device IN endpoint 3 DMA address register
OTG device IN endpoint 4 DMA address register
OTG device IN endpoint 5 DMA address register
OTG device IN endpoint 6 DMA address register
OTG device IN endpoint 7 DMA address register
OTG device IN endpoint 8 DMA address register
This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx).
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
The application must modify this register before enabling endpoint 0.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG device IN endpoint transmit FIFO 1 size register
OTG device IN endpoint transmit FIFO 2 size register
OTG device IN endpoint transmit FIFO 3 size register
OTG device IN endpoint transmit FIFO 4 size register
OTG device IN endpoint transmit FIFO 5 size register
OTG device IN endpoint transmit FIFO 6 size register
OTG device IN endpoint transmit FIFO 7 size register
OTG device IN endpoint transmit FIFO 8 size register
This section describes the OTG_DOEPCTL0 register.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG device OUT endpoint 0 DMA address register
OTG device OUT endpoint 1 DMA address register
OTG device OUT endpoint 2 DMA address register
OTG device OUT endpoint 3 DMA address register
OTG device OUT endpoint 4 DMA address register
OTG device OUT endpoint 5 DMA address register
OTG device OUT endpoint 6 DMA address register
OTG device OUT endpoint 7 DMA address register
OTG device OUT endpoint 8 DMA address register
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
The application must modify this register before enabling endpoint 0.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register.
OTG device threshold control register
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
This register specifies the VBUS discharge time after VBUS pulsing during SRP.
This register specifies the VBUS pulsing time during SRP.
This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
OTG general core configuration register
This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
OTG core LPM configuration register
The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
The application uses this register to reset various hardware features inside the core.
The application can program the RAM size that must be allocated to the Rx FIFO.
This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted.
This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
OTG host channel 0 characteristics register
OTG host channel 1 characteristics register
OTG host channel 2 characteristics register
OTG host channel 3 characteristics register
OTG host channel 4 characteristics register
OTG host channel 5 characteristics register
OTG host channel 6 characteristics register
OTG host channel 7 characteristics register
OTG host channel 8 characteristics register
OTG host channel 9 characteristics register
OTG host channel 10 characteristics register
OTG host channel 11 characteristics register
OTG host channel 12 characteristics register
OTG host channel 13 characteristics register
OTG host channel 14 characteristics register
OTG host channel 15 characteristics register
OTG host channel 0 DMA address register in buffer DMA [alternate]
OTG host channel 1 DMA address register in buffer DMA [alternate]
OTG host channel 2 DMA address register in buffer DMA [alternate]
OTG host channel 3 DMA address register in buffer DMA [alternate]
OTG host channel 4 DMA address register in buffer DMA [alternate]
OTG host channel 5 DMA address register in buffer DMA [alternate]
OTG host channel 6 DMA address register in buffer DMA [alternate]
OTG host channel 7 DMA address register in buffer DMA [alternate]
OTG host channel 8 DMA address register in buffer DMA [alternate]
OTG host channel 9 DMA address register in buffer DMA [alternate]
OTG host channel 10 DMA address register in buffer DMA [alternate]
OTG host channel 11 DMA address register in buffer DMA [alternate]
OTG host channel 12 DMA address register in buffer DMA [alternate]
OTG host channel 13 DMA address register in buffer DMA [alternate]
OTG host channel 14 DMA address register in buffer DMA [alternate]
OTG host channel 15 DMA address register in buffer DMA [alternate]
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
OTG host channel-n DMA address buffer register
This register configures the core after power-on. Do not make changes to this register after initializing the host.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
This register reflects the mask for each channel status described in the previous section.
OTG host channel 0 split control register
OTG host channel 1 split control register
OTG host channel 2 split control register
OTG host channel 3 split control register
OTG host channel 4 split control register
OTG host channel 5 split control register
OTG host channel 6 split control register
OTG host channel 7 split control register
OTG host channel 8 split control register
OTG host channel 9 split control register
OTG host channel 10 split control register
OTG host channel 11 split control register
OTG host channel 12 split control register
OTG host channel 13 split control register
OTG host channel 14 split control register
OTG host channel 15 split control register
OTG host channel 0 transfer size register
OTG host channel 1 transfer size register
OTG host channel 2 transfer size register
OTG host channel 3 transfer size register
OTG host channel 4 transfer size register
OTG host channel 5 transfer size register
OTG host channel 6 transfer size register
OTG host channel 7 transfer size register
OTG host channel 8 transfer size register
OTG host channel 9 transfer size register
OTG host channel 10 transfer size register
OTG host channel 11 transfer size register
OTG host channel 12 transfer size register
OTG host channel 13 transfer size register
OTG host channel 14 transfer size register
OTG host channel 15 transfer size register
This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
This register holds the starting address of the frame list information (scatter/gather mode).
This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
Host mode
In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
OTG host periodic transmit FIFO size register
This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
This register is available in host and device modes.
Structs
Register block
Type Definitions
OTG_CID register accessor: an alias for Reg<OTG_CID_SPEC>
OTG_DAINT register accessor: an alias for Reg<OTG_DAINT_SPEC>
OTG_DAINTMSK register accessor: an alias for Reg<OTG_DAINTMSK_SPEC>
OTG_DCFG register accessor: an alias for Reg<OTG_DCFG_SPEC>
OTG_DCTL register accessor: an alias for Reg<OTG_DCTL_SPEC>
OTG_DEACHINT register accessor: an alias for Reg<OTG_DEACHINT_SPEC>
OTG_DEACHINTMSK register accessor: an alias for Reg<OTG_DEACHINTMSK_SPEC>
OTG_DIEPCTL0 register accessor: an alias for Reg<OTG_DIEPCTL0_SPEC>
OTG_DIEPCTL1 register accessor: an alias for Reg<OTG_DIEPCTL1_SPEC>
OTG_DIEPCTL2 register accessor: an alias for Reg<OTG_DIEPCTL2_SPEC>
OTG_DIEPCTL3 register accessor: an alias for Reg<OTG_DIEPCTL3_SPEC>
OTG_DIEPCTL4 register accessor: an alias for Reg<OTG_DIEPCTL4_SPEC>
OTG_DIEPCTL5 register accessor: an alias for Reg<OTG_DIEPCTL5_SPEC>
OTG_DIEPCTL6 register accessor: an alias for Reg<OTG_DIEPCTL6_SPEC>
OTG_DIEPCTL7 register accessor: an alias for Reg<OTG_DIEPCTL7_SPEC>
OTG_DIEPCTL8 register accessor: an alias for Reg<OTG_DIEPCTL8_SPEC>
OTG_DIEPDMA0 register accessor: an alias for Reg<OTG_DIEPDMA0_SPEC>
OTG_DIEPDMA1 register accessor: an alias for Reg<OTG_DIEPDMA1_SPEC>
OTG_DIEPDMA2 register accessor: an alias for Reg<OTG_DIEPDMA2_SPEC>
OTG_DIEPDMA3 register accessor: an alias for Reg<OTG_DIEPDMA3_SPEC>
OTG_DIEPDMA4 register accessor: an alias for Reg<OTG_DIEPDMA4_SPEC>
OTG_DIEPDMA5 register accessor: an alias for Reg<OTG_DIEPDMA5_SPEC>
OTG_DIEPDMA6 register accessor: an alias for Reg<OTG_DIEPDMA6_SPEC>
OTG_DIEPDMA7 register accessor: an alias for Reg<OTG_DIEPDMA7_SPEC>
OTG_DIEPDMA8 register accessor: an alias for Reg<OTG_DIEPDMA8_SPEC>
OTG_DIEPEMPMSK register accessor: an alias for Reg<OTG_DIEPEMPMSK_SPEC>
OTG_DIEPINT0 register accessor: an alias for Reg<OTG_DIEPINT0_SPEC>
OTG_DIEPINT1 register accessor: an alias for Reg<OTG_DIEPINT1_SPEC>
OTG_DIEPINT2 register accessor: an alias for Reg<OTG_DIEPINT2_SPEC>
OTG_DIEPINT3 register accessor: an alias for Reg<OTG_DIEPINT3_SPEC>
OTG_DIEPINT4 register accessor: an alias for Reg<OTG_DIEPINT4_SPEC>
OTG_DIEPINT5 register accessor: an alias for Reg<OTG_DIEPINT5_SPEC>
OTG_DIEPINT6 register accessor: an alias for Reg<OTG_DIEPINT6_SPEC>
OTG_DIEPINT7 register accessor: an alias for Reg<OTG_DIEPINT7_SPEC>
OTG_DIEPINT8 register accessor: an alias for Reg<OTG_DIEPINT8_SPEC>
OTG_DIEPMSK register accessor: an alias for Reg<OTG_DIEPMSK_SPEC>
OTG_DIEPTSIZ0 register accessor: an alias for Reg<OTG_DIEPTSIZ0_SPEC>
OTG_DIEPTSIZ1 register accessor: an alias for Reg<OTG_DIEPTSIZ1_SPEC>
OTG_DIEPTSIZ2 register accessor: an alias for Reg<OTG_DIEPTSIZ2_SPEC>
OTG_DIEPTSIZ3 register accessor: an alias for Reg<OTG_DIEPTSIZ3_SPEC>
OTG_DIEPTSIZ4 register accessor: an alias for Reg<OTG_DIEPTSIZ4_SPEC>
OTG_DIEPTSIZ5 register accessor: an alias for Reg<OTG_DIEPTSIZ5_SPEC>
OTG_DIEPTSIZ6 register accessor: an alias for Reg<OTG_DIEPTSIZ6_SPEC>
OTG_DIEPTSIZ7 register accessor: an alias for Reg<OTG_DIEPTSIZ7_SPEC>
OTG_DIEPTSIZ8 register accessor: an alias for Reg<OTG_DIEPTSIZ8_SPEC>
OTG_DIEPTXF1 register accessor: an alias for Reg<OTG_DIEPTXF1_SPEC>
OTG_DIEPTXF2 register accessor: an alias for Reg<OTG_DIEPTXF2_SPEC>
OTG_DIEPTXF3 register accessor: an alias for Reg<OTG_DIEPTXF3_SPEC>
OTG_DIEPTXF4 register accessor: an alias for Reg<OTG_DIEPTXF4_SPEC>
OTG_DIEPTXF5 register accessor: an alias for Reg<OTG_DIEPTXF5_SPEC>
OTG_DIEPTXF6 register accessor: an alias for Reg<OTG_DIEPTXF6_SPEC>
OTG_DIEPTXF7 register accessor: an alias for Reg<OTG_DIEPTXF7_SPEC>
OTG_DIEPTXF8 register accessor: an alias for Reg<OTG_DIEPTXF8_SPEC>
OTG_DOEPCTL0 register accessor: an alias for Reg<OTG_DOEPCTL0_SPEC>
OTG_DOEPCTL1 register accessor: an alias for Reg<OTG_DOEPCTL1_SPEC>
OTG_DOEPCTL2 register accessor: an alias for Reg<OTG_DOEPCTL2_SPEC>
OTG_DOEPCTL3 register accessor: an alias for Reg<OTG_DOEPCTL3_SPEC>
OTG_DOEPCTL4 register accessor: an alias for Reg<OTG_DOEPCTL4_SPEC>
OTG_DOEPCTL5 register accessor: an alias for Reg<OTG_DOEPCTL5_SPEC>
OTG_DOEPCTL6 register accessor: an alias for Reg<OTG_DOEPCTL6_SPEC>
OTG_DOEPCTL7 register accessor: an alias for Reg<OTG_DOEPCTL7_SPEC>
OTG_DOEPCTL8 register accessor: an alias for Reg<OTG_DOEPCTL8_SPEC>
OTG_DOEPDMA0 register accessor: an alias for Reg<OTG_DOEPDMA0_SPEC>
OTG_DOEPDMA1 register accessor: an alias for Reg<OTG_DOEPDMA1_SPEC>
OTG_DOEPDMA2 register accessor: an alias for Reg<OTG_DOEPDMA2_SPEC>
OTG_DOEPDMA3 register accessor: an alias for Reg<OTG_DOEPDMA3_SPEC>
OTG_DOEPDMA4 register accessor: an alias for Reg<OTG_DOEPDMA4_SPEC>
OTG_DOEPDMA5 register accessor: an alias for Reg<OTG_DOEPDMA5_SPEC>
OTG_DOEPDMA6 register accessor: an alias for Reg<OTG_DOEPDMA6_SPEC>
OTG_DOEPDMA7 register accessor: an alias for Reg<OTG_DOEPDMA7_SPEC>
OTG_DOEPDMA8 register accessor: an alias for Reg<OTG_DOEPDMA8_SPEC>
OTG_DOEPINT0 register accessor: an alias for Reg<OTG_DOEPINT0_SPEC>
OTG_DOEPINT1 register accessor: an alias for Reg<OTG_DOEPINT1_SPEC>
OTG_DOEPINT2 register accessor: an alias for Reg<OTG_DOEPINT2_SPEC>
OTG_DOEPINT3 register accessor: an alias for Reg<OTG_DOEPINT3_SPEC>
OTG_DOEPINT4 register accessor: an alias for Reg<OTG_DOEPINT4_SPEC>
OTG_DOEPINT5 register accessor: an alias for Reg<OTG_DOEPINT5_SPEC>
OTG_DOEPINT6 register accessor: an alias for Reg<OTG_DOEPINT6_SPEC>
OTG_DOEPINT7 register accessor: an alias for Reg<OTG_DOEPINT7_SPEC>
OTG_DOEPINT8 register accessor: an alias for Reg<OTG_DOEPINT8_SPEC>
OTG_DOEPMSK register accessor: an alias for Reg<OTG_DOEPMSK_SPEC>
OTG_DOEPTSIZ0 register accessor: an alias for Reg<OTG_DOEPTSIZ0_SPEC>
OTG_DOEPTSIZ1 register accessor: an alias for Reg<OTG_DOEPTSIZ1_SPEC>
OTG_DOEPTSIZ2 register accessor: an alias for Reg<OTG_DOEPTSIZ2_SPEC>
OTG_DOEPTSIZ3 register accessor: an alias for Reg<OTG_DOEPTSIZ3_SPEC>
OTG_DOEPTSIZ4 register accessor: an alias for Reg<OTG_DOEPTSIZ4_SPEC>
OTG_DOEPTSIZ5 register accessor: an alias for Reg<OTG_DOEPTSIZ5_SPEC>
OTG_DOEPTSIZ6 register accessor: an alias for Reg<OTG_DOEPTSIZ6_SPEC>
OTG_DOEPTSIZ7 register accessor: an alias for Reg<OTG_DOEPTSIZ7_SPEC>
OTG_DOEPTSIZ8 register accessor: an alias for Reg<OTG_DOEPTSIZ8_SPEC>
OTG_DSTS register accessor: an alias for Reg<OTG_DSTS_SPEC>
OTG_DTHRCTL register accessor: an alias for Reg<OTG_DTHRCTL_SPEC>
OTG_DTXFSTS0 register accessor: an alias for Reg<OTG_DTXFSTS0_SPEC>
OTG_DTXFSTS1 register accessor: an alias for Reg<OTG_DTXFSTS1_SPEC>
OTG_DTXFSTS2 register accessor: an alias for Reg<OTG_DTXFSTS2_SPEC>
OTG_DTXFSTS3 register accessor: an alias for Reg<OTG_DTXFSTS3_SPEC>
OTG_DTXFSTS4 register accessor: an alias for Reg<OTG_DTXFSTS4_SPEC>
OTG_DTXFSTS5 register accessor: an alias for Reg<OTG_DTXFSTS5_SPEC>
OTG_DTXFSTS6 register accessor: an alias for Reg<OTG_DTXFSTS6_SPEC>
OTG_DTXFSTS7 register accessor: an alias for Reg<OTG_DTXFSTS7_SPEC>
OTG_DTXFSTS8 register accessor: an alias for Reg<OTG_DTXFSTS8_SPEC>
OTG_DVBUSDIS register accessor: an alias for Reg<OTG_DVBUSDIS_SPEC>
OTG_DVBUSPULSE register accessor: an alias for Reg<OTG_DVBUSPULSE_SPEC>
OTG_GAHBCFG register accessor: an alias for Reg<OTG_GAHBCFG_SPEC>
OTG_GCCFG register accessor: an alias for Reg<OTG_GCCFG_SPEC>
OTG_GINTMSK register accessor: an alias for Reg<OTG_GINTMSK_SPEC>
OTG_GINTSTS register accessor: an alias for Reg<OTG_GINTSTS_SPEC>
OTG_GLPMCFG register accessor: an alias for Reg<OTG_GLPMCFG_SPEC>
OTG_GOTGCTL register accessor: an alias for Reg<OTG_GOTGCTL_SPEC>
OTG_GOTGINT register accessor: an alias for Reg<OTG_GOTGINT_SPEC>
OTG_GRSTCTL register accessor: an alias for Reg<OTG_GRSTCTL_SPEC>
OTG_GRXFSIZ register accessor: an alias for Reg<OTG_GRXFSIZ_SPEC>
OTG_GRXSTSP register accessor: an alias for Reg<OTG_GRXSTSP_SPEC>
OTG_GRXSTSR register accessor: an alias for Reg<OTG_GRXSTSR_SPEC>
OTG_GUSBCFG register accessor: an alias for Reg<OTG_GUSBCFG_SPEC>
OTG_HAINT register accessor: an alias for Reg<OTG_HAINT_SPEC>
OTG_HAINTMSK register accessor: an alias for Reg<OTG_HAINTMSK_SPEC>
OTG_HCCHAR0 register accessor: an alias for Reg<OTG_HCCHAR0_SPEC>
OTG_HCCHAR1 register accessor: an alias for Reg<OTG_HCCHAR1_SPEC>
OTG_HCCHAR2 register accessor: an alias for Reg<OTG_HCCHAR2_SPEC>
OTG_HCCHAR3 register accessor: an alias for Reg<OTG_HCCHAR3_SPEC>
OTG_HCCHAR4 register accessor: an alias for Reg<OTG_HCCHAR4_SPEC>
OTG_HCCHAR5 register accessor: an alias for Reg<OTG_HCCHAR5_SPEC>
OTG_HCCHAR6 register accessor: an alias for Reg<OTG_HCCHAR6_SPEC>
OTG_HCCHAR7 register accessor: an alias for Reg<OTG_HCCHAR7_SPEC>
OTG_HCCHAR8 register accessor: an alias for Reg<OTG_HCCHAR8_SPEC>
OTG_HCCHAR9 register accessor: an alias for Reg<OTG_HCCHAR9_SPEC>
OTG_HCCHAR10 register accessor: an alias for Reg<OTG_HCCHAR10_SPEC>
OTG_HCCHAR11 register accessor: an alias for Reg<OTG_HCCHAR11_SPEC>
OTG_HCCHAR12 register accessor: an alias for Reg<OTG_HCCHAR12_SPEC>
OTG_HCCHAR13 register accessor: an alias for Reg<OTG_HCCHAR13_SPEC>
OTG_HCCHAR14 register accessor: an alias for Reg<OTG_HCCHAR14_SPEC>
OTG_HCCHAR15 register accessor: an alias for Reg<OTG_HCCHAR15_SPEC>
OTG_HCDMA0 register accessor: an alias for Reg<OTG_HCDMA0_SPEC>
OTG_HCDMA1 register accessor: an alias for Reg<OTG_HCDMA1_SPEC>
OTG_HCDMA2 register accessor: an alias for Reg<OTG_HCDMA2_SPEC>
OTG_HCDMA3 register accessor: an alias for Reg<OTG_HCDMA3_SPEC>
OTG_HCDMA4 register accessor: an alias for Reg<OTG_HCDMA4_SPEC>
OTG_HCDMA5 register accessor: an alias for Reg<OTG_HCDMA5_SPEC>
OTG_HCDMA6 register accessor: an alias for Reg<OTG_HCDMA6_SPEC>
OTG_HCDMA7 register accessor: an alias for Reg<OTG_HCDMA7_SPEC>
OTG_HCDMA8 register accessor: an alias for Reg<OTG_HCDMA8_SPEC>
OTG_HCDMA9 register accessor: an alias for Reg<OTG_HCDMA9_SPEC>
OTG_HCDMA10 register accessor: an alias for Reg<OTG_HCDMA10_SPEC>
OTG_HCDMA11 register accessor: an alias for Reg<OTG_HCDMA11_SPEC>
OTG_HCDMA12 register accessor: an alias for Reg<OTG_HCDMA12_SPEC>
OTG_HCDMA13 register accessor: an alias for Reg<OTG_HCDMA13_SPEC>
OTG_HCDMA14 register accessor: an alias for Reg<OTG_HCDMA14_SPEC>
OTG_HCDMA15 register accessor: an alias for Reg<OTG_HCDMA15_SPEC>
OTG_HCDMAB0 register accessor: an alias for Reg<OTG_HCDMAB0_SPEC>
OTG_HCDMAB1 register accessor: an alias for Reg<OTG_HCDMAB1_SPEC>
OTG_HCDMAB2 register accessor: an alias for Reg<OTG_HCDMAB2_SPEC>
OTG_HCDMAB3 register accessor: an alias for Reg<OTG_HCDMAB3_SPEC>
OTG_HCDMAB4 register accessor: an alias for Reg<OTG_HCDMAB4_SPEC>
OTG_HCDMAB5 register accessor: an alias for Reg<OTG_HCDMAB5_SPEC>
OTG_HCDMAB6 register accessor: an alias for Reg<OTG_HCDMAB6_SPEC>
OTG_HCDMAB7 register accessor: an alias for Reg<OTG_HCDMAB7_SPEC>
OTG_HCDMAB8 register accessor: an alias for Reg<OTG_HCDMAB8_SPEC>
OTG_HCDMAB9 register accessor: an alias for Reg<OTG_HCDMAB9_SPEC>
OTG_HCDMAB10 register accessor: an alias for Reg<OTG_HCDMAB10_SPEC>
OTG_HCDMAB11 register accessor: an alias for Reg<OTG_HCDMAB11_SPEC>
OTG_HCDMAB12 register accessor: an alias for Reg<OTG_HCDMAB12_SPEC>
OTG_HCDMAB13 register accessor: an alias for Reg<OTG_HCDMAB13_SPEC>
OTG_HCDMAB14 register accessor: an alias for Reg<OTG_HCDMAB14_SPEC>
OTG_HCDMAB15 register accessor: an alias for Reg<OTG_HCDMAB15_SPEC>
OTG_HCFG register accessor: an alias for Reg<OTG_HCFG_SPEC>
OTG_HCINT0 register accessor: an alias for Reg<OTG_HCINT0_SPEC>
OTG_HCINT1 register accessor: an alias for Reg<OTG_HCINT1_SPEC>
OTG_HCINT2 register accessor: an alias for Reg<OTG_HCINT2_SPEC>
OTG_HCINT3 register accessor: an alias for Reg<OTG_HCINT3_SPEC>
OTG_HCINT4 register accessor: an alias for Reg<OTG_HCINT4_SPEC>
OTG_HCINT5 register accessor: an alias for Reg<OTG_HCINT5_SPEC>
OTG_HCINT6 register accessor: an alias for Reg<OTG_HCINT6_SPEC>
OTG_HCINT7 register accessor: an alias for Reg<OTG_HCINT7_SPEC>
OTG_HCINT8 register accessor: an alias for Reg<OTG_HCINT8_SPEC>
OTG_HCINT9 register accessor: an alias for Reg<OTG_HCINT9_SPEC>
OTG_HCINT10 register accessor: an alias for Reg<OTG_HCINT10_SPEC>
OTG_HCINT11 register accessor: an alias for Reg<OTG_HCINT11_SPEC>
OTG_HCINT12 register accessor: an alias for Reg<OTG_HCINT12_SPEC>
OTG_HCINT13 register accessor: an alias for Reg<OTG_HCINT13_SPEC>
OTG_HCINT14 register accessor: an alias for Reg<OTG_HCINT14_SPEC>
OTG_HCINT15 register accessor: an alias for Reg<OTG_HCINT15_SPEC>
OTG_HCINTMSK0 register accessor: an alias for Reg<OTG_HCINTMSK0_SPEC>
OTG_HCINTMSK1 register accessor: an alias for Reg<OTG_HCINTMSK1_SPEC>
OTG_HCINTMSK2 register accessor: an alias for Reg<OTG_HCINTMSK2_SPEC>
OTG_HCINTMSK3 register accessor: an alias for Reg<OTG_HCINTMSK3_SPEC>
OTG_HCINTMSK4 register accessor: an alias for Reg<OTG_HCINTMSK4_SPEC>
OTG_HCINTMSK5 register accessor: an alias for Reg<OTG_HCINTMSK5_SPEC>
OTG_HCINTMSK6 register accessor: an alias for Reg<OTG_HCINTMSK6_SPEC>
OTG_HCINTMSK7 register accessor: an alias for Reg<OTG_HCINTMSK7_SPEC>
OTG_HCINTMSK8 register accessor: an alias for Reg<OTG_HCINTMSK8_SPEC>
OTG_HCINTMSK9 register accessor: an alias for Reg<OTG_HCINTMSK9_SPEC>
OTG_HCINTMSK10 register accessor: an alias for Reg<OTG_HCINTMSK10_SPEC>
OTG_HCINTMSK11 register accessor: an alias for Reg<OTG_HCINTMSK11_SPEC>
OTG_HCINTMSK12 register accessor: an alias for Reg<OTG_HCINTMSK12_SPEC>
OTG_HCINTMSK13 register accessor: an alias for Reg<OTG_HCINTMSK13_SPEC>
OTG_HCINTMSK14 register accessor: an alias for Reg<OTG_HCINTMSK14_SPEC>
OTG_HCINTMSK15 register accessor: an alias for Reg<OTG_HCINTMSK15_SPEC>
OTG_HCSPLT0 register accessor: an alias for Reg<OTG_HCSPLT0_SPEC>
OTG_HCSPLT1 register accessor: an alias for Reg<OTG_HCSPLT1_SPEC>
OTG_HCSPLT2 register accessor: an alias for Reg<OTG_HCSPLT2_SPEC>
OTG_HCSPLT3 register accessor: an alias for Reg<OTG_HCSPLT3_SPEC>
OTG_HCSPLT4 register accessor: an alias for Reg<OTG_HCSPLT4_SPEC>
OTG_HCSPLT5 register accessor: an alias for Reg<OTG_HCSPLT5_SPEC>
OTG_HCSPLT6 register accessor: an alias for Reg<OTG_HCSPLT6_SPEC>
OTG_HCSPLT7 register accessor: an alias for Reg<OTG_HCSPLT7_SPEC>
OTG_HCSPLT8 register accessor: an alias for Reg<OTG_HCSPLT8_SPEC>
OTG_HCSPLT9 register accessor: an alias for Reg<OTG_HCSPLT9_SPEC>
OTG_HCSPLT10 register accessor: an alias for Reg<OTG_HCSPLT10_SPEC>
OTG_HCSPLT11 register accessor: an alias for Reg<OTG_HCSPLT11_SPEC>
OTG_HCSPLT12 register accessor: an alias for Reg<OTG_HCSPLT12_SPEC>
OTG_HCSPLT13 register accessor: an alias for Reg<OTG_HCSPLT13_SPEC>
OTG_HCSPLT14 register accessor: an alias for Reg<OTG_HCSPLT14_SPEC>
OTG_HCSPLT15 register accessor: an alias for Reg<OTG_HCSPLT15_SPEC>
OTG_HCTSIZ0 register accessor: an alias for Reg<OTG_HCTSIZ0_SPEC>
OTG_HCTSIZ1 register accessor: an alias for Reg<OTG_HCTSIZ1_SPEC>
OTG_HCTSIZ2 register accessor: an alias for Reg<OTG_HCTSIZ2_SPEC>
OTG_HCTSIZ3 register accessor: an alias for Reg<OTG_HCTSIZ3_SPEC>
OTG_HCTSIZ4 register accessor: an alias for Reg<OTG_HCTSIZ4_SPEC>
OTG_HCTSIZ5 register accessor: an alias for Reg<OTG_HCTSIZ5_SPEC>
OTG_HCTSIZ6 register accessor: an alias for Reg<OTG_HCTSIZ6_SPEC>
OTG_HCTSIZ7 register accessor: an alias for Reg<OTG_HCTSIZ7_SPEC>
OTG_HCTSIZ8 register accessor: an alias for Reg<OTG_HCTSIZ8_SPEC>
OTG_HCTSIZ9 register accessor: an alias for Reg<OTG_HCTSIZ9_SPEC>
OTG_HCTSIZ10 register accessor: an alias for Reg<OTG_HCTSIZ10_SPEC>
OTG_HCTSIZ11 register accessor: an alias for Reg<OTG_HCTSIZ11_SPEC>
OTG_HCTSIZ12 register accessor: an alias for Reg<OTG_HCTSIZ12_SPEC>
OTG_HCTSIZ13 register accessor: an alias for Reg<OTG_HCTSIZ13_SPEC>
OTG_HCTSIZ14 register accessor: an alias for Reg<OTG_HCTSIZ14_SPEC>
OTG_HCTSIZ15 register accessor: an alias for Reg<OTG_HCTSIZ15_SPEC>
OTG_HFIR register accessor: an alias for Reg<OTG_HFIR_SPEC>
OTG_HFLBADDR register accessor: an alias for Reg<OTG_HFLBADDR_SPEC>
OTG_HFNUM register accessor: an alias for Reg<OTG_HFNUM_SPEC>
OTG_HNPTXFSIZ register accessor: an alias for Reg<OTG_HNPTXFSIZ_SPEC>
OTG_HNPTXSTS register accessor: an alias for Reg<OTG_HNPTXSTS_SPEC>
OTG_HPRT register accessor: an alias for Reg<OTG_HPRT_SPEC>
OTG_HPTXFSIZ register accessor: an alias for Reg<OTG_HPTXFSIZ_SPEC>
OTG_HPTXSTS register accessor: an alias for Reg<OTG_HPTXSTS_SPEC>
OTG_HS_DIEPEACHMSK1 register accessor: an alias for Reg<OTG_HS_DIEPEACHMSK1_SPEC>
OTG_HS_DOEPEACHMSK1 register accessor: an alias for Reg<OTG_HS_DOEPEACHMSK1_SPEC>
OTG_PCGCCTL register accessor: an alias for Reg<OTG_PCGCCTL_SPEC>