Struct stm32mp1::stm32mp157::eth_mac_mmc::eth_macl3l4c0r::ETH_MACL3L4C0R_SPEC

pub struct ETH_MACL3L4C0R_SPEC;

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see eth_macl3l4c0r module

Trait Implementations

impl Readable for ETH_MACL3L4C0R_SPEC

read() method returns eth_macl3l4c0r::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for ETH_MACL3L4C0R_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for ETH_MACL3L4C0R_SPEC

reset() method sets ETH_MACL3L4C0R to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for ETH_MACL3L4C0R_SPEC

write(|w| ..) method takes eth_macl3l4c0r::W writer structure

type Writer = W

Writer type argument to write, et al.