Module stm32mp1::stm32mp157::eth_mac_mmc::eth_macl3l4c0r

source · [−]

Expand description

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.

Structs

ETH_MACL3L4C0R_SPEC

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.

Register ETH_MACL3L4C0R reader

Register ETH_MACL3L4C0R writer

Type Definitions

Field L3DAIM0 reader - L3DAIM0

Field L3DAIM0 writer - L3DAIM0

Field L3DAM0 reader - L3DAM0

Field L3DAM0 writer - L3DAM0

Field L3HDBM0 reader - L3HDBM0

Field L3HDBM0 writer - L3HDBM0

Field L3HSBM0 reader - L3HSBM0

Field L3HSBM0 writer - L3HSBM0

Field L3PEN0 reader - L3PEN0

Field L3PEN0 writer - L3PEN0

Field L3SAIM0 reader - L3SAIM0

Field L3SAIM0 writer - L3SAIM0

Field L3SAM0 reader - L3SAM0

Field L3SAM0 writer - L3SAM0

Field L4DPIM0 reader - L4DPIM0

Field L4DPIM0 writer - L4DPIM0

Field L4DPM0 reader - L4DPM0

Field L4DPM0 writer - L4DPM0

Field L4PEN0 reader - L4PEN0

Field L4PEN0 writer - L4PEN0

Field L4SPIM0 reader - L4SPIM0

Field L4SPIM0 writer - L4SPIM0

Field L4SPM0 reader - L4SPM0

Field L4SPM0 writer - L4SPM0