Struct stm32g0::stm32g0c1::rng::rng_sr::W [−][src]
pub struct W(_);
Expand description
Register RNG_SR
writer
Implementations
Bit 5 - Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.
Bit 6 - Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.
Methods from Deref<Target = W<RNG_SR_SPEC>>
Trait Implementations
Performs the conversion.