Struct stm32g0::stm32g0c1::rng::rng_sr::CEIS_W

pub struct CEIS_W<'a> { /* fields omitted */ }

Field CEIS writer - Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.

Implementations

impl<'a> CEIS_W<'a>

pub fn variant(self, variant: CEIS_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

The RNG clock is correct (fRNGCLK> fHCLK/32)

pub fn b_0x1(self) -> &'a mut W

The RNG has been detected too slow (fRNGCLK< fHCLK/32)

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field