Struct stm32g0::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 11:13 - Timer base

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 16 - Flash User area empty

pub fn dbg_swen(&mut self) -> DBG_SWEN_W<'_>

Bit 18 - Debug access software enable

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&mut self) -> BSY_W<'_>

Bit 16 - Busy

pub fn cfgbsy(&mut self) -> CFGBSY_W<'_>

Bit 18 - Programming or erase configuration busy.

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:8 - Page number

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn sec_prot(&mut self) -> SEC_PROT_W<'_>

Bit 28 - Securable memory area protection enable

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn boren(&mut self) -> BOREN_W<'_>

Bit 8 - BOR reset Level

pub fn borf_lev(&mut self) -> BORF_LEV_W<'_>

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&mut self) -> BORR_LEV_W<'_>

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&mut self) -> NRSTS_HDW_W<'_>

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&mut self) -> RAM_PARITY_CHECK_W<'_>

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&mut self) -> NBOOT_SEL_W<'_>

Bit 24 - nBOOT_SEL

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 25 - Boot configuration

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&mut self) -> NRST_MODE_W<'_>

Bits 27:28 - NRST_MODE

pub fn irhen(&mut self) -> IRHEN_W<'_>

Bit 29 - Internal reset holder enable bit

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI16 clock enable

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&mut self) -> HSIRDY_W<'_>

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&mut self) -> HSIDIV_W<'_>

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> HSERDY_W<'_>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

pub fn pllrdy(&mut self) -> PLLRDY_W<'_>

Bit 25 - PLL clock ready flag

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 8:14 - HSI16 clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn ppre(&mut self) -> PPRE_W<'_>

Bits 12:14 - APB prescaler

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 8:11 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:2 - System clock switch

impl W<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - PLL input clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl W<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&mut self) -> PLLSYSRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn pllsysrdyc(&mut self) -> PLLSYSRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&mut self) -> DMARST_W<'_>

Bit 0 - DMA1 reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - FLITF reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

impl W<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 0 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 1 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 2 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 3 - I/O port D reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 5 - I/O port F reset

impl W<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 timer reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn dbgrst(&mut self) -> DBGRST_W<'_>

Bit 27 - Debug support reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

impl W<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 15 - TIM14 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 20 - ADC reset

impl W<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 0 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 1 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 2 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 3 - I/O port D clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 5 - I/O port F clock enable

impl W<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

impl W<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - RTC APB clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - WWDG clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn dbgen(&mut self) -> DBGEN_W<'_>

Bit 27 - Debug support clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

impl W<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 15 - TIM14 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM16 timer clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 20 - ADC clock enable

impl W<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&mut self) -> IOPASMEN_W<'_>

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&mut self) -> IOPBSMEN_W<'_>

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&mut self) -> IOPCSMEN_W<'_>

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&mut self) -> IOPDSMEN_W<'_>

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&mut self) -> IOPFSMEN_W<'_>

Bit 5 - I/O port F clock enable during Sleep mode

impl W<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&mut self) -> DMASMEN_W<'_>

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&mut self) -> SRAMSMEN_W<'_>

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&mut self) -> TIM3SMEN_W<'_>

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&mut self) -> DBGSMEN_W<'_>

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&mut self) -> TIM14SMEN_W<'_>

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&mut self) -> ADCSMEN_W<'_>

Bit 20 - ADC clock enable during Sleep mode

impl W<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&mut self) -> I2S2SEL_W<'_>

Bits 14:15 - I2S1 clock source selection

pub fn tim1sel(&mut self) -> TIM1SEL_W<'_>

Bit 22 - TIM1 clock source selection

pub fn rngsel(&mut self) -> RNGSEL_W<'_>

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&mut self) -> RNGDIV_W<'_>

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 30:31 - ADCs clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

pub fn lserdy(&mut self) -> LSERDY_W<'_>

Bit 1 - LSE oscillator ready

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - CSS on LSE enable

pub fn lsecssd(&mut self) -> LSECSSD_W<'_>

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - RTC domain software reset

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low-speed clock output selection

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

pub fn lsirdy(&mut self) -> LSIRDY_W<'_>

Bit 1 - LSI oscillator ready

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flags

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - Pin reset flag

pub fn pwrrstf(&mut self) -> PWRRSTF_W<'_>

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&mut self) -> FPD_LPSLP_W<'_>

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&mut self) -> FPD_LPRUN_W<'_>

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&mut self) -> FPD_STOP_W<'_>

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

pub fn pvdft(&mut self) -> PVDFT_W<'_>

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&mut self) -> PVDRT_W<'_>

Bits 4:6 - Power voltage detector rising threshold selection

impl W<u32, Reg<u32, _CR3>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&mut self) -> EWUP6_W<'_>

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&mut self) -> ULPEN_W<'_>

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line

impl W<u32, Reg<u32, _CR4>>

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&mut self) -> WP6_W<'_>

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

impl W<u32, Reg<u32, _SCR>>

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 8 - Clear standby flag

pub fn cwuf6(&mut self) -> CWUF6_W<'_>

Bit 5 - Clear wakeup flag 6

pub fn cwuf5(&mut self) -> CWUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn cwuf4(&mut self) -> CWUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn cwuf2(&mut self) -> CWUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn cwuf1(&mut self) -> CWUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Clear channel 1 global interrupt flag

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Clear channel 1 transfer complete flag

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Clear channel 1 half transfer flag

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Clear channel 1 transfer error flag

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Clear channel 2 global interrupt flag

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Clear channel 2 transfer complete flag

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Clear channel 2 half transfer flag

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Clear channel 2 transfer error flag

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Clear channel 3 global interrupt flag

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Clear channel 3 transfer complete flag

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Clear channel 3 half transfer flag

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Clear channel 3 transfer error flag

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Clear channel 4 global interrupt flag

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Clear channel 4 transfer complete flag

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Clear channel 4 half transfer flag

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Clear channel 4 transfer error flag

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Clear channel 5 global interrupt flag

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Clear channel 5 transfer complete flag

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Clear channel 5 half transfer flag

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Clear channel 5 transfer error flag

impl W<u32, Reg<u32, _C0CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C1CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C2CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C3CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C4CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C5CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C6CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _RG0CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG1CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG2CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG3CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RGCFR>>

pub fn cof(&mut self) -> COF_W<'_>

Bits 0:3 - Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:31 - General-purpose 32-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn crc_init(&mut self) -> CRC_INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _RPR1>>

pub fn rpif0(&mut self) -> RPIF0_W<'_>

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&mut self) -> RPIF1_W<'_>

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&mut self) -> RPIF2_W<'_>

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&mut self) -> RPIF3_W<'_>

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&mut self) -> RPIF4_W<'_>

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&mut self) -> RPIF5_W<'_>

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&mut self) -> RPIF6_W<'_>

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&mut self) -> RPIF7_W<'_>

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&mut self) -> RPIF8_W<'_>

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&mut self) -> RPIF9_W<'_>

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&mut self) -> RPIF10_W<'_>

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&mut self) -> RPIF11_W<'_>

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&mut self) -> RPIF12_W<'_>

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&mut self) -> RPIF13_W<'_>

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&mut self) -> RPIF14_W<'_>

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&mut self) -> RPIF15_W<'_>

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&mut self) -> RPIF16_W<'_>

Bit 16 - configurable event inputs x rising edge Pending bit.

impl W<u32, Reg<u32, _FPR1>>

pub fn fpif0(&mut self) -> FPIF0_W<'_>

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&mut self) -> FPIF1_W<'_>

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&mut self) -> FPIF2_W<'_>

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&mut self) -> FPIF3_W<'_>

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&mut self) -> FPIF4_W<'_>

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&mut self) -> FPIF5_W<'_>

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&mut self) -> FPIF6_W<'_>

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&mut self) -> FPIF7_W<'_>

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&mut self) -> FPIF8_W<'_>

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&mut self) -> FPIF9_W<'_>

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&mut self) -> FPIF10_W<'_>

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&mut self) -> FPIF11_W<'_>

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&mut self) -> FPIF12_W<'_>

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&mut self) -> FPIF13_W<'_>

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&mut self) -> FPIF14_W<'_>

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&mut self) -> FPIF15_W<'_>

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&mut self) -> FPIF16_W<'_>

Bit 16 - configurable event inputs x falling edge pending bit.

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _IMR1>>

pub fn im0(&mut self) -> IM0_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&mut self) -> IM1_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&mut self) -> IM2_W<'_>

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&mut self) -> IM3_W<'_>

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&mut self) -> IM4_W<'_>

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&mut self) -> IM5_W<'_>

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&mut self) -> IM6_W<'_>

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&mut self) -> IM7_W<'_>

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&mut self) -> IM8_W<'_>

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&mut self) -> IM9_W<'_>

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&mut self) -> IM10_W<'_>

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&mut self) -> IM11_W<'_>

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&mut self) -> IM12_W<'_>

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&mut self) -> IM13_W<'_>

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&mut self) -> IM14_W<'_>

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&mut self) -> IM15_W<'_>

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&mut self) -> IM16_W<'_>

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im19(&mut self) -> IM19_W<'_>

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&mut self) -> IM20_W<'_>

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&mut self) -> IM21_W<'_>

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&mut self) -> IM22_W<'_>

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&mut self) -> IM23_W<'_>

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&mut self) -> IM24_W<'_>

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&mut self) -> IM25_W<'_>

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&mut self) -> IM26_W<'_>

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im28(&mut self) -> IM28_W<'_>

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&mut self) -> IM29_W<'_>

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&mut self) -> IM30_W<'_>

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&mut self) -> IM31_W<'_>

Bit 31 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR1>>

pub fn em0(&mut self) -> EM0_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&mut self) -> EM1_W<'_>

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&mut self) -> EM2_W<'_>

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&mut self) -> EM3_W<'_>

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&mut self) -> EM4_W<'_>

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&mut self) -> EM5_W<'_>

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&mut self) -> EM6_W<'_>

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&mut self) -> EM7_W<'_>

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&mut self) -> EM8_W<'_>

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&mut self) -> EM9_W<'_>

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&mut self) -> EM10_W<'_>

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&mut self) -> EM11_W<'_>

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&mut self) -> EM12_W<'_>

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&mut self) -> EM13_W<'_>

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&mut self) -> EM14_W<'_>

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&mut self) -> EM15_W<'_>

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&mut self) -> EM16_W<'_>

Bit 16 - CPU wakeup with event mask on event input

pub fn em19(&mut self) -> EM19_W<'_>

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&mut self) -> EM21_W<'_>

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&mut self) -> EM23_W<'_>

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&mut self) -> EM25_W<'_>

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&mut self) -> EM26_W<'_>

Bit 26 - CPU wakeup with event mask on event input

pub fn em28(&mut self) -> EM28_W<'_>

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&mut self) -> EM29_W<'_>

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&mut self) -> EM30_W<'_>

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&mut self) -> EM31_W<'_>

Bit 31 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - selects input

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - DEDT

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>

Bit 0 - Synchronous Slave mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&mut self) -> BRR_4_15_W<'_>

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&mut self) -> BRR_0_3_W<'_>

Bits 0:3 - BRR_0_3

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn udrcf(&mut self) -> UDRCF_W<'_>

Bit 13 - SPI slave underrun clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>

Bit 7 - Transmission complete before Guard time clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn txfecf(&mut self) -> TXFECF_W<'_>

Bit 5 - TXFIFO empty clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - standard selection

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn se2(&mut self) -> SE2_W<'_>

Bit 10 - I2S enable

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

impl W<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - linear prescaler

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts_4(&mut self) -> TS_4_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn ts(&mut self) -> TS_W<'_>

Bits 20:21 - Trigger selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&mut self) -> SBIF_W<'_>

Bit 13 - System Break interrupt flag

pub fn cc5if(&mut self) -> CC5IF_W<'_>

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&mut self) -> CC6IF_W<'_>

Bit 17 - Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3(&mut self) -> CCR3_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4(&mut self) -> CCR4_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bk2dsrm(&mut self) -> BK2DSRM_W<'_>

Bit 27 - Break2 Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

pub fn bk2id(&mut self) -> BK2ID_W<'_>

Bit 29 - Break2 bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&mut self) -> OCREF_CLR_W<'_>

Bit 0 - Ocref_clr source selection

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr5(&mut self) -> CCR5_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr6(&mut self) -> CCR6_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _AF2>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel3_0(&mut self) -> TI1SEL3_0_W<'_>

Bits 0:3 - selects TI1[0] to TI1[15] input

pub fn ti2sel3_0(&mut self) -> TI2SEL3_0_W<'_>

Bits 8:11 - selects TI2[0] to TI2[15] input

pub fn ti3sel3_0(&mut self) -> TI3SEL3_0_W<'_>

Bits 16:19 - selects TI3[0] to TI3[15] input

pub fn ti4sel3_0(&mut self) -> TI4SEL3_0_W<'_>

Bits 24:27 - selects TI4[0] to TI4[15] input

impl W<u32, Reg<u32, _ISR>>

pub fn ccrdy(&mut self) -> CCRDY_W<'_>

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&mut self) -> EOCAL_W<'_>

Bit 11 - End Of Calibration flag

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - ADC group regular overrun flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADC ready flag

impl W<u32, Reg<u32, _IER>>

pub fn ccrdyie(&mut self) -> CCRDYIE_W<'_>

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADC ready interrupt

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADC calibration

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADC voltage regulator enable

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADC group regular conversion stop

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADC group regular conversion start

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADC disable

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADC enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&mut self) -> CHSELRMOD_W<'_>

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - Auto-off mode

pub fn wait(&mut self) -> WAIT_W<'_>

Bit 14 - Wait conversion mode

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - ADC group regular overrun configuration

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:8 - ADC group regular external trigger source

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ADC data alignement

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - ADC data resolution

pub fn scandir(&mut self) -> SCANDIR_W<'_>

Bit 2 - Scan sequence direction

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - ADC DMA transfer enable

impl W<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 30:31 - ADC clock mode

pub fn lftrig(&mut self) -> LFTRIG_W<'_>

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&mut self) -> OVSE_W<'_>

Bit 0 - ADC oversampler enable on scope ADC group regular

impl W<u32, Reg<u32, _SMPR>>

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 0:2 - Sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 4:6 - Sampling time selection

pub fn smpsel(&mut self) -> SMPSEL_W<'_>

Bits 8:26 - Channel sampling time selection

impl W<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - ADC analog watchdog 1 threshold low

impl W<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:11 - ADC analog watchdog 2 threshold low

impl W<u32, Reg<u32, _CHSELR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 0:18 - Channel-x selection

impl W<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:3 - conversion of the sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 4:7 - conversion of the sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 8:11 - conversion of the sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 12:15 - conversion of the sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 16:19 - conversion of the sequence

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 20:23 - conversion of the sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 24:27 - conversion of the sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 28:31 - conversion of the sequence

impl W<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:11 - ADC analog watchdog 3 threshold high

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact(&mut self) -> CALFACT_W<'_>

Bits 0:6 - ADC calibration factor in single-ended mode

impl W<u32, Reg<u32, _CCR>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&mut self) -> I2C_PAX_FMP_W<'_>

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&mut self) -> I2C_PBX_FMP_W<'_>

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&mut self) -> IR_MOD_W<'_>

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&mut self) -> IR_POL_W<'_>

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - Memory mapping selection bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&mut self) -> ECC_LOCK_W<'_>

Bit 3 - ECC error lock bit

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity error flag

pub fn pa1_cden(&mut self) -> PA1_CDEN_W<'_>

Bit 16 - PA1_CDEN

pub fn pa3_cden(&mut self) -> PA3_CDEN_W<'_>

Bit 17 - PA3_CDEN

pub fn pa5_cden(&mut self) -> PA5_CDEN_W<'_>

Bit 18 - PA5_CDEN

pub fn pa6_cden(&mut self) -> PA6_CDEN_W<'_>

Bit 19 - PA6_CDEN

pub fn pa13_cden(&mut self) -> PA13_CDEN_W<'_>

Bit 20 - PA13_CDEN

pub fn pb0_cden(&mut self) -> PB0_CDEN_W<'_>

Bit 21 - PB0_CDEN

pub fn pb1_cden(&mut self) -> PB1_CDEN_W<'_>

Bit 22 - PB1_CDEN

pub fn pb2_cden(&mut self) -> PB2_CDEN_W<'_>

Bit 23 - PB2_CDEN

impl W<u32, Reg<u32, _CR1>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - TAMP1E

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 1 - TAMP2E

pub fn itamp1e(&mut self) -> ITAMP1E_W<'_>

Bit 16 - ITAMP1E

pub fn itamp3e(&mut self) -> ITAMP3E_W<'_>

Bit 18 - ITAMP3E

pub fn itamp4e(&mut self) -> ITAMP4E_W<'_>

Bit 19 - ITAMP4E

pub fn itamp5e(&mut self) -> ITAMP5E_W<'_>

Bit 20 - ITAMP5E

pub fn itamp6e(&mut self) -> ITAMP6E_W<'_>

Bit 21 - ITAMP6E

impl W<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&mut self) -> TAMP1NOER_W<'_>

Bit 0 - TAMP1NOER

pub fn tamp2noer(&mut self) -> TAMP2NOER_W<'_>

Bit 1 - TAMP2NOER

pub fn tamp1msk(&mut self) -> TAMP1MSK_W<'_>

Bit 16 - TAMP1MSK

pub fn tamp2msk(&mut self) -> TAMP2MSK_W<'_>

Bit 17 - TAMP2MSK

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 24 - TAMP1TRG

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 25 - TAMP2TRG

impl W<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 0:2 - TAMPFREQ

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 3:4 - TAMPFLT

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 7 - TAMPPUDIS

impl W<u32, Reg<u32, _IER>>

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 0 - TAMP1IE

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 1 - TAMP2IE

pub fn itamp1ie(&mut self) -> ITAMP1IE_W<'_>

Bit 16 - ITAMP1IE

pub fn itamp3ie(&mut self) -> ITAMP3IE_W<'_>

Bit 18 - ITAMP3IE

pub fn itamp4ie(&mut self) -> ITAMP4IE_W<'_>

Bit 19 - ITAMP4IE

pub fn itamp5ie(&mut self) -> ITAMP5IE_W<'_>

Bit 20 - ITAMP5IE

pub fn itamp6ie(&mut self) -> ITAMP6IE_W<'_>

Bit 21 - ITAMP6IE

impl W<u32, Reg<u32, _SCR>>

pub fn ctamp1f(&mut self) -> CTAMP1F_W<'_>

Bit 0 - CTAMP1F

pub fn ctamp2f(&mut self) -> CTAMP2F_W<'_>

Bit 1 - CTAMP2F

pub fn citamp1f(&mut self) -> CITAMP1F_W<'_>

Bit 16 - CITAMP1F

pub fn citamp3f(&mut self) -> CITAMP3F_W<'_>

Bit 18 - CITAMP3F

pub fn citamp4f(&mut self) -> CITAMP4F_W<'_>

Bit 19 - CITAMP4F

pub fn citamp5f(&mut self) -> CITAMP5F_W<'_>

Bit 20 - CITAMP5F

pub fn citamp6f(&mut self) -> CITAMP6F_W<'_>

Bit 21 - CITAMP6F

pub fn citamp7f(&mut self) -> CITAMP7F_W<'_>

Bit 22 - CITAMP7F

impl W<u32, Reg<u32, _BKP0R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP1R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP2R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP3R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP4R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&mut self) -> OA1_0_W<'_>

Bit 0 - Interface address

pub fn oa1_7_1(&mut self) -> OA1_7_1_W<'_>

Bits 1:7 - Interface address

pub fn oa1_8_9(&mut self) -> OA1_8_9_W<'_>

Bits 8:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _ICSR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - WUCKSEL

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - TSEDGE

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - REFCKON

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - BYPSHAD

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - FMT

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - ALRAE

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - ALRBE

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - WUTE

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - TSE

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - ALRAIE

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - ALRBIE

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - WUTIE

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - TSIE

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - ADD1H

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - SUB1H

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - BKP

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - COSEL

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - POL

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - OSEL

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - COE

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - ITSE

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 25 - TAMPTS

pub fn tampoe(&mut self) -> TAMPOE_W<'_>

Bit 26 - TAMPOE

pub fn tampalrm_pu(&mut self) -> TAMPALRM_PU_W<'_>

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&mut self) -> TAMPALRM_TYPE_W<'_>

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&mut self) -> OUT2EN_W<'_>

Bit 31 - OUT2EN

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _SCR>>

pub fn calraf(&mut self) -> CALRAF_W<'_>

Bit 0 - CALRAF

pub fn calrbf(&mut self) -> CALRBF_W<'_>

Bit 1 - CALRBF

pub fn cwutf(&mut self) -> CWUTF_W<'_>

Bit 2 - CWUTF

pub fn ctsf(&mut self) -> CTSF_W<'_>

Bit 3 - CTSF

pub fn ctsovf(&mut self) -> CTSOVF_W<'_>

Bit 4 - CTSOVF

pub fn citsf(&mut self) -> CITSF_W<'_>

Bit 5 - CITSF

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&mut self) -> ICPCS_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _TISEL>>

pub fn tisel(&mut self) -> TISEL_W<'_>

Bits 0:3 - TI1[0] to TI1[15] input selection

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&mut self) -> TS_4_3_W<'_>

Bits 20:21 - Trigger selection

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&mut self) -> CNT_L_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&mut self) -> ARR_L_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&mut self) -> CCR1_L_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&mut self) -> CCR2_H_W<'_>

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&mut self) -> CCR2_L_W<'_>

Bits 0:15 - Low Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&mut self) -> CCR3_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&mut self) -> CCR3_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&mut self) -> CCR4_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&mut self) -> CCR4_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&mut self) -> IOCREF_CLR_W<'_>

Bit 0 - IOCREF_CLR

impl W<u32, Reg<u32, _AF1>>

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:17 - External trigger source selection

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - TI1SEL

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - TI2SEL

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrs(&mut self) -> VRS_W<'_>

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl W<u32, Reg<u32, _CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl W<u32, Reg<u32, _CR>>

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby mode

impl W<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - TIM2 counter stopped when core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Window watchdog counter stopped when core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Independent watchdog counter stopped when core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted

impl W<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - DBG_TIM17_STOP

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 11:13 - Timer base

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 16 - Flash User area empty

pub fn dbg_swen(&mut self) -> DBG_SWEN_W<'_>

Bit 18 - Debug access software enable

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&mut self) -> BSY_W<'_>

Bit 16 - Busy

pub fn cfgbsy(&mut self) -> CFGBSY_W<'_>

Bit 18 - Programming or erase configuration busy.

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:8 - Page number

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn sec_prot(&mut self) -> SEC_PROT_W<'_>

Bit 28 - Securable memory area protection enable

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn boren(&mut self) -> BOREN_W<'_>

Bit 8 - BOR reset Level

pub fn borf_lev(&mut self) -> BORF_LEV_W<'_>

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&mut self) -> BORR_LEV_W<'_>

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&mut self) -> NRSTS_HDW_W<'_>

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&mut self) -> RAM_PARITY_CHECK_W<'_>

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&mut self) -> NBOOT_SEL_W<'_>

Bit 24 - nBOOT_SEL

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 25 - Boot configuration

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&mut self) -> NRST_MODE_W<'_>

Bits 27:28 - NRST_MODE

pub fn irhen(&mut self) -> IRHEN_W<'_>

Bit 29 - Internal reset holder enable bit

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI16 clock enable

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&mut self) -> HSIRDY_W<'_>

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&mut self) -> HSIDIV_W<'_>

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> HSERDY_W<'_>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

pub fn pllrdy(&mut self) -> PLLRDY_W<'_>

Bit 25 - PLL clock ready flag

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 8:14 - HSI16 clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn ppre(&mut self) -> PPRE_W<'_>

Bits 12:14 - APB prescaler

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 8:11 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:2 - System clock switch

impl W<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - PLL input clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl W<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&mut self) -> PLLSYSRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn pllsysrdyc(&mut self) -> PLLSYSRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&mut self) -> DMARST_W<'_>

Bit 0 - DMA1 reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - FLITF reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

impl W<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 0 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 1 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 2 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 3 - I/O port D reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 5 - I/O port F reset

impl W<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 timer reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn lpuart1rst(&mut self) -> LPUART1RST_W<'_>

Bit 20 - LPUART1 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn dbgrst(&mut self) -> DBGRST_W<'_>

Bit 27 - Debug support reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn lptim2rst(&mut self) -> LPTIM2RST_W<'_>

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>

Bit 31 - Low Power Timer 1 reset

impl W<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 15 - TIM14 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 20 - ADC reset

impl W<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 0 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 1 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 2 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 3 - I/O port D clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 5 - I/O port F clock enable

impl W<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

impl W<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - RTC APB clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - WWDG clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn dbgen(&mut self) -> DBGEN_W<'_>

Bit 27 - Debug support clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - LPTIM1 clock enable

impl W<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 15 - TIM14 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM16 timer clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 20 - ADC clock enable

impl W<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&mut self) -> IOPASMEN_W<'_>

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&mut self) -> IOPBSMEN_W<'_>

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&mut self) -> IOPCSMEN_W<'_>

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&mut self) -> IOPDSMEN_W<'_>

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&mut self) -> IOPFSMEN_W<'_>

Bit 5 - I/O port F clock enable during Sleep mode

impl W<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&mut self) -> DMASMEN_W<'_>

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&mut self) -> SRAMSMEN_W<'_>

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&mut self) -> TIM3SMEN_W<'_>

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&mut self) -> DBGSMEN_W<'_>

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&mut self) -> TIM14SMEN_W<'_>

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&mut self) -> ADCSMEN_W<'_>

Bit 20 - ADC clock enable during Sleep mode

impl W<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<'_>

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&mut self) -> I2S2SEL_W<'_>

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<'_>

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&mut self) -> TIM1SEL_W<'_>

Bit 22 - TIM1 clock source selection

pub fn rngsel(&mut self) -> RNGSEL_W<'_>

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&mut self) -> RNGDIV_W<'_>

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 30:31 - ADCs clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

pub fn lserdy(&mut self) -> LSERDY_W<'_>

Bit 1 - LSE oscillator ready

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - CSS on LSE enable

pub fn lsecssd(&mut self) -> LSECSSD_W<'_>

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - RTC domain software reset

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low-speed clock output selection

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

pub fn lsirdy(&mut self) -> LSIRDY_W<'_>

Bit 1 - LSI oscillator ready

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flags

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - Pin reset flag

pub fn pwrrstf(&mut self) -> PWRRSTF_W<'_>

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&mut self) -> FPD_LPSLP_W<'_>

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&mut self) -> FPD_LPRUN_W<'_>

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&mut self) -> FPD_STOP_W<'_>

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

pub fn pvdft(&mut self) -> PVDFT_W<'_>

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&mut self) -> PVDRT_W<'_>

Bits 4:6 - Power voltage detector rising threshold selection

impl W<u32, Reg<u32, _CR3>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&mut self) -> EWUP6_W<'_>

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&mut self) -> ULPEN_W<'_>

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line

impl W<u32, Reg<u32, _CR4>>

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&mut self) -> WP6_W<'_>

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

impl W<u32, Reg<u32, _SCR>>

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 8 - Clear standby flag

pub fn cwuf6(&mut self) -> CWUF6_W<'_>

Bit 5 - Clear wakeup flag 6

pub fn cwuf5(&mut self) -> CWUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn cwuf4(&mut self) -> CWUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn cwuf2(&mut self) -> CWUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn cwuf1(&mut self) -> CWUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Clear channel 1 global interrupt flag

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Clear channel 1 transfer complete flag

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Clear channel 1 half transfer flag

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Clear channel 1 transfer error flag

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Clear channel 2 global interrupt flag

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Clear channel 2 transfer complete flag

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Clear channel 2 half transfer flag

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Clear channel 2 transfer error flag

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Clear channel 3 global interrupt flag

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Clear channel 3 transfer complete flag

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Clear channel 3 half transfer flag

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Clear channel 3 transfer error flag

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Clear channel 4 global interrupt flag

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Clear channel 4 transfer complete flag

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Clear channel 4 half transfer flag

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Clear channel 4 transfer error flag

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Clear channel 5 global interrupt flag

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Clear channel 5 transfer complete flag

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Clear channel 5 half transfer flag

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Clear channel 5 transfer error flag

impl W<u32, Reg<u32, _C0CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C1CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C2CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C3CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C4CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C5CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C6CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _RG0CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG1CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG2CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG3CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RGCFR>>

pub fn cof(&mut self) -> COF_W<'_>

Bits 0:3 - Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:31 - General-purpose 32-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn crc_init(&mut self) -> CRC_INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _RPR1>>

pub fn rpif0(&mut self) -> RPIF0_W<'_>

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&mut self) -> RPIF1_W<'_>

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&mut self) -> RPIF2_W<'_>

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&mut self) -> RPIF3_W<'_>

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&mut self) -> RPIF4_W<'_>

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&mut self) -> RPIF5_W<'_>

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&mut self) -> RPIF6_W<'_>

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&mut self) -> RPIF7_W<'_>

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&mut self) -> RPIF8_W<'_>

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&mut self) -> RPIF9_W<'_>

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&mut self) -> RPIF10_W<'_>

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&mut self) -> RPIF11_W<'_>

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&mut self) -> RPIF12_W<'_>

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&mut self) -> RPIF13_W<'_>

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&mut self) -> RPIF14_W<'_>

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&mut self) -> RPIF15_W<'_>

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&mut self) -> RPIF16_W<'_>

Bit 16 - configurable event inputs x rising edge Pending bit.

impl W<u32, Reg<u32, _FPR1>>

pub fn fpif0(&mut self) -> FPIF0_W<'_>

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&mut self) -> FPIF1_W<'_>

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&mut self) -> FPIF2_W<'_>

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&mut self) -> FPIF3_W<'_>

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&mut self) -> FPIF4_W<'_>

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&mut self) -> FPIF5_W<'_>

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&mut self) -> FPIF6_W<'_>

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&mut self) -> FPIF7_W<'_>

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&mut self) -> FPIF8_W<'_>

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&mut self) -> FPIF9_W<'_>

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&mut self) -> FPIF10_W<'_>

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&mut self) -> FPIF11_W<'_>

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&mut self) -> FPIF12_W<'_>

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&mut self) -> FPIF13_W<'_>

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&mut self) -> FPIF14_W<'_>

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&mut self) -> FPIF15_W<'_>

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&mut self) -> FPIF16_W<'_>

Bit 16 - configurable event inputs x falling edge pending bit.

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _IMR1>>

pub fn im0(&mut self) -> IM0_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&mut self) -> IM1_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&mut self) -> IM2_W<'_>

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&mut self) -> IM3_W<'_>

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&mut self) -> IM4_W<'_>

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&mut self) -> IM5_W<'_>

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&mut self) -> IM6_W<'_>

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&mut self) -> IM7_W<'_>

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&mut self) -> IM8_W<'_>

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&mut self) -> IM9_W<'_>

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&mut self) -> IM10_W<'_>

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&mut self) -> IM11_W<'_>

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&mut self) -> IM12_W<'_>

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&mut self) -> IM13_W<'_>

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&mut self) -> IM14_W<'_>

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&mut self) -> IM15_W<'_>

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&mut self) -> IM16_W<'_>

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im19(&mut self) -> IM19_W<'_>

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&mut self) -> IM20_W<'_>

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&mut self) -> IM21_W<'_>

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&mut self) -> IM22_W<'_>

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&mut self) -> IM23_W<'_>

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&mut self) -> IM24_W<'_>

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&mut self) -> IM25_W<'_>

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&mut self) -> IM26_W<'_>

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im28(&mut self) -> IM28_W<'_>

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&mut self) -> IM29_W<'_>

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&mut self) -> IM30_W<'_>

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&mut self) -> IM31_W<'_>

Bit 31 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR1>>

pub fn em0(&mut self) -> EM0_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&mut self) -> EM1_W<'_>

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&mut self) -> EM2_W<'_>

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&mut self) -> EM3_W<'_>

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&mut self) -> EM4_W<'_>

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&mut self) -> EM5_W<'_>

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&mut self) -> EM6_W<'_>

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&mut self) -> EM7_W<'_>

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&mut self) -> EM8_W<'_>

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&mut self) -> EM9_W<'_>

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&mut self) -> EM10_W<'_>

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&mut self) -> EM11_W<'_>

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&mut self) -> EM12_W<'_>

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&mut self) -> EM13_W<'_>

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&mut self) -> EM14_W<'_>

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&mut self) -> EM15_W<'_>

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&mut self) -> EM16_W<'_>

Bit 16 - CPU wakeup with event mask on event input

pub fn em19(&mut self) -> EM19_W<'_>

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&mut self) -> EM21_W<'_>

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&mut self) -> EM23_W<'_>

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&mut self) -> EM25_W<'_>

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&mut self) -> EM26_W<'_>

Bit 26 - CPU wakeup with event mask on event input

pub fn em28(&mut self) -> EM28_W<'_>

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&mut self) -> EM29_W<'_>

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&mut self) -> EM30_W<'_>

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&mut self) -> EM31_W<'_>

Bit 31 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - selects input

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - DEDT

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>

Bit 0 - Synchronous Slave mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&mut self) -> BRR_4_15_W<'_>

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&mut self) -> BRR_0_3_W<'_>

Bits 0:3 - BRR_0_3

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn udrcf(&mut self) -> UDRCF_W<'_>

Bit 13 - SPI slave underrun clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>

Bit 7 - Transmission complete before Guard time clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn txfecf(&mut self) -> TXFECF_W<'_>

Bit 5 - TXFIFO empty clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - standard selection

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn se2(&mut self) -> SE2_W<'_>

Bit 10 - I2S enable

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

impl W<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - linear prescaler

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts_4(&mut self) -> TS_4_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn ts(&mut self) -> TS_W<'_>

Bits 20:21 - Trigger selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&mut self) -> SBIF_W<'_>

Bit 13 - System Break interrupt flag

pub fn cc5if(&mut self) -> CC5IF_W<'_>

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&mut self) -> CC6IF_W<'_>

Bit 17 - Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3(&mut self) -> CCR3_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4(&mut self) -> CCR4_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bk2dsrm(&mut self) -> BK2DSRM_W<'_>

Bit 27 - Break2 Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

pub fn bk2id(&mut self) -> BK2ID_W<'_>

Bit 29 - Break2 bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&mut self) -> OCREF_CLR_W<'_>

Bit 0 - Ocref_clr source selection

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr5(&mut self) -> CCR5_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr6(&mut self) -> CCR6_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _AF2>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel3_0(&mut self) -> TI1SEL3_0_W<'_>

Bits 0:3 - selects TI1[0] to TI1[15] input

pub fn ti2sel3_0(&mut self) -> TI2SEL3_0_W<'_>

Bits 8:11 - selects TI2[0] to TI2[15] input

pub fn ti3sel3_0(&mut self) -> TI3SEL3_0_W<'_>

Bits 16:19 - selects TI3[0] to TI3[15] input

pub fn ti4sel3_0(&mut self) -> TI4SEL3_0_W<'_>

Bits 24:27 - selects TI4[0] to TI4[15] input

impl W<u32, Reg<u32, _ISR>>

pub fn ccrdy(&mut self) -> CCRDY_W<'_>

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&mut self) -> EOCAL_W<'_>

Bit 11 - End Of Calibration flag

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - ADC group regular overrun flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADC ready flag

impl W<u32, Reg<u32, _IER>>

pub fn ccrdyie(&mut self) -> CCRDYIE_W<'_>

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADC ready interrupt

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADC calibration

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADC voltage regulator enable

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADC group regular conversion stop

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADC group regular conversion start

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADC disable

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADC enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&mut self) -> CHSELRMOD_W<'_>

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - Auto-off mode

pub fn wait(&mut self) -> WAIT_W<'_>

Bit 14 - Wait conversion mode

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - ADC group regular overrun configuration

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:8 - ADC group regular external trigger source

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ADC data alignement

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - ADC data resolution

pub fn scandir(&mut self) -> SCANDIR_W<'_>

Bit 2 - Scan sequence direction

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - ADC DMA transfer enable

impl W<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 30:31 - ADC clock mode

pub fn lftrig(&mut self) -> LFTRIG_W<'_>

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&mut self) -> OVSE_W<'_>

Bit 0 - ADC oversampler enable on scope ADC group regular

impl W<u32, Reg<u32, _SMPR>>

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 0:2 - Sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 4:6 - Sampling time selection

pub fn smpsel(&mut self) -> SMPSEL_W<'_>

Bits 8:26 - Channel sampling time selection

impl W<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - ADC analog watchdog 1 threshold low

impl W<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:11 - ADC analog watchdog 2 threshold low

impl W<u32, Reg<u32, _CHSELR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 0:18 - Channel-x selection

impl W<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:3 - conversion of the sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 4:7 - conversion of the sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 8:11 - conversion of the sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 12:15 - conversion of the sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 16:19 - conversion of the sequence

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 20:23 - conversion of the sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 24:27 - conversion of the sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 28:31 - conversion of the sequence

impl W<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:11 - ADC analog watchdog 3 threshold high

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact(&mut self) -> CALFACT_W<'_>

Bits 0:6 - ADC calibration factor in single-ended mode

impl W<u32, Reg<u32, _CCR>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&mut self) -> I2C_PAX_FMP_W<'_>

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&mut self) -> I2C_PBX_FMP_W<'_>

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&mut self) -> IR_MOD_W<'_>

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&mut self) -> IR_POL_W<'_>

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - Memory mapping selection bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&mut self) -> ECC_LOCK_W<'_>

Bit 3 - ECC error lock bit

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity error flag

pub fn pa1_cden(&mut self) -> PA1_CDEN_W<'_>

Bit 16 - PA1_CDEN

pub fn pa3_cden(&mut self) -> PA3_CDEN_W<'_>

Bit 17 - PA3_CDEN

pub fn pa5_cden(&mut self) -> PA5_CDEN_W<'_>

Bit 18 - PA5_CDEN

pub fn pa6_cden(&mut self) -> PA6_CDEN_W<'_>

Bit 19 - PA6_CDEN

pub fn pa13_cden(&mut self) -> PA13_CDEN_W<'_>

Bit 20 - PA13_CDEN

pub fn pb0_cden(&mut self) -> PB0_CDEN_W<'_>

Bit 21 - PB0_CDEN

pub fn pb1_cden(&mut self) -> PB1_CDEN_W<'_>

Bit 22 - PB1_CDEN

pub fn pb2_cden(&mut self) -> PB2_CDEN_W<'_>

Bit 23 - PB2_CDEN

impl W<u32, Reg<u32, _CR1>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - TAMP1E

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 1 - TAMP2E

pub fn itamp1e(&mut self) -> ITAMP1E_W<'_>

Bit 16 - ITAMP1E

pub fn itamp3e(&mut self) -> ITAMP3E_W<'_>

Bit 18 - ITAMP3E

pub fn itamp4e(&mut self) -> ITAMP4E_W<'_>

Bit 19 - ITAMP4E

pub fn itamp5e(&mut self) -> ITAMP5E_W<'_>

Bit 20 - ITAMP5E

pub fn itamp6e(&mut self) -> ITAMP6E_W<'_>

Bit 21 - ITAMP6E

impl W<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&mut self) -> TAMP1NOER_W<'_>

Bit 0 - TAMP1NOER

pub fn tamp2noer(&mut self) -> TAMP2NOER_W<'_>

Bit 1 - TAMP2NOER

pub fn tamp1msk(&mut self) -> TAMP1MSK_W<'_>

Bit 16 - TAMP1MSK

pub fn tamp2msk(&mut self) -> TAMP2MSK_W<'_>

Bit 17 - TAMP2MSK

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 24 - TAMP1TRG

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 25 - TAMP2TRG

impl W<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 0:2 - TAMPFREQ

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 3:4 - TAMPFLT

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 7 - TAMPPUDIS

impl W<u32, Reg<u32, _IER>>

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 0 - TAMP1IE

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 1 - TAMP2IE

pub fn itamp1ie(&mut self) -> ITAMP1IE_W<'_>

Bit 16 - ITAMP1IE

pub fn itamp3ie(&mut self) -> ITAMP3IE_W<'_>

Bit 18 - ITAMP3IE

pub fn itamp4ie(&mut self) -> ITAMP4IE_W<'_>

Bit 19 - ITAMP4IE

pub fn itamp5ie(&mut self) -> ITAMP5IE_W<'_>

Bit 20 - ITAMP5IE

pub fn itamp6ie(&mut self) -> ITAMP6IE_W<'_>

Bit 21 - ITAMP6IE

impl W<u32, Reg<u32, _SCR>>

pub fn ctamp1f(&mut self) -> CTAMP1F_W<'_>

Bit 0 - CTAMP1F

pub fn ctamp2f(&mut self) -> CTAMP2F_W<'_>

Bit 1 - CTAMP2F

pub fn citamp1f(&mut self) -> CITAMP1F_W<'_>

Bit 16 - CITAMP1F

pub fn citamp3f(&mut self) -> CITAMP3F_W<'_>

Bit 18 - CITAMP3F

pub fn citamp4f(&mut self) -> CITAMP4F_W<'_>

Bit 19 - CITAMP4F

pub fn citamp5f(&mut self) -> CITAMP5F_W<'_>

Bit 20 - CITAMP5F

pub fn citamp6f(&mut self) -> CITAMP6F_W<'_>

Bit 21 - CITAMP6F

pub fn citamp7f(&mut self) -> CITAMP7F_W<'_>

Bit 22 - CITAMP7F

impl W<u32, Reg<u32, _BKP0R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP1R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP2R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP3R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP4R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn rstare(&mut self) -> RSTARE_W<'_>

Bit 4 - Reset after read enable

pub fn countrst(&mut self) -> COUNTRST_W<'_>

Bit 3 - Counter reset

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&mut self) -> IN2SEL_W<'_>

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&mut self) -> IN1SEL_W<'_>

Bits 0:1 - LPTIMx Input 1 selection

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT0

pub fn dedt0(&mut self) -> DEDT0_W<'_>

Bits 16:20 - DEDT0

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:19 - BRR

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&mut self) -> OA1_0_W<'_>

Bit 0 - Interface address

pub fn oa1_7_1(&mut self) -> OA1_7_1_W<'_>

Bits 1:7 - Interface address

pub fn oa1_8_9(&mut self) -> OA1_8_9_W<'_>

Bits 8:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _ICSR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - WUCKSEL

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - TSEDGE

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - REFCKON

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - BYPSHAD

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - FMT

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - ALRAE

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - ALRBE

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - WUTE

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - TSE

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - ALRAIE

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - ALRBIE

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - WUTIE

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - TSIE

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - ADD1H

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - SUB1H

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - BKP

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - COSEL

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - POL

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - OSEL

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - COE

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - ITSE

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 25 - TAMPTS

pub fn tampoe(&mut self) -> TAMPOE_W<'_>

Bit 26 - TAMPOE

pub fn tampalrm_pu(&mut self) -> TAMPALRM_PU_W<'_>

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&mut self) -> TAMPALRM_TYPE_W<'_>

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&mut self) -> OUT2EN_W<'_>

Bit 31 - OUT2EN

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _SCR>>

pub fn calraf(&mut self) -> CALRAF_W<'_>

Bit 0 - CALRAF

pub fn calrbf(&mut self) -> CALRBF_W<'_>

Bit 1 - CALRBF

pub fn cwutf(&mut self) -> CWUTF_W<'_>

Bit 2 - CWUTF

pub fn ctsf(&mut self) -> CTSF_W<'_>

Bit 3 - CTSF

pub fn ctsovf(&mut self) -> CTSOVF_W<'_>

Bit 4 - CTSOVF

pub fn citsf(&mut self) -> CITSF_W<'_>

Bit 5 - CITSF

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&mut self) -> ICPCS_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _TISEL>>

pub fn tisel(&mut self) -> TISEL_W<'_>

Bits 0:3 - TI1[0] to TI1[15] input selection

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&mut self) -> TS_4_3_W<'_>

Bits 20:21 - Trigger selection

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&mut self) -> CNT_L_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&mut self) -> ARR_L_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&mut self) -> CCR1_L_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&mut self) -> CCR2_H_W<'_>

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&mut self) -> CCR2_L_W<'_>

Bits 0:15 - Low Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&mut self) -> CCR3_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&mut self) -> CCR3_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&mut self) -> CCR4_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&mut self) -> CCR4_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&mut self) -> IOCREF_CLR_W<'_>

Bit 0 - IOCREF_CLR

impl W<u32, Reg<u32, _AF1>>

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:17 - External trigger source selection

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - TI1SEL

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - TI2SEL

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrs(&mut self) -> VRS_W<'_>

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl W<u32, Reg<u32, _CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl W<u32, Reg<u32, _CR>>

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby mode

impl W<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - TIM2 counter stopped when core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Window watchdog counter stopped when core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Independent watchdog counter stopped when core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 30 - LPTIM2 counter stopped when core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - LPTIM1 counter stopped when core is halted

impl W<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - DBG_TIM17_STOP

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 11:13 - Timer base

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 16 - Flash User area empty

pub fn dbg_swen(&mut self) -> DBG_SWEN_W<'_>

Bit 18 - Debug access software enable

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&mut self) -> BSY_W<'_>

Bit 16 - Busy

pub fn cfgbsy(&mut self) -> CFGBSY_W<'_>

Bit 18 - Programming or erase configuration busy.

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:8 - Page number

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn sec_prot(&mut self) -> SEC_PROT_W<'_>

Bit 28 - Securable memory area protection enable

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn boren(&mut self) -> BOREN_W<'_>

Bit 8 - BOR reset Level

pub fn borf_lev(&mut self) -> BORF_LEV_W<'_>

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&mut self) -> BORR_LEV_W<'_>

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&mut self) -> NRSTS_HDW_W<'_>

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&mut self) -> RAM_PARITY_CHECK_W<'_>

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&mut self) -> NBOOT_SEL_W<'_>

Bit 24 - nBOOT_SEL

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 25 - Boot configuration

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&mut self) -> NRST_MODE_W<'_>

Bits 27:28 - NRST_MODE

pub fn irhen(&mut self) -> IRHEN_W<'_>

Bit 29 - Internal reset holder enable bit

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI16 clock enable

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&mut self) -> HSIRDY_W<'_>

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&mut self) -> HSIDIV_W<'_>

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> HSERDY_W<'_>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

pub fn pllrdy(&mut self) -> PLLRDY_W<'_>

Bit 25 - PLL clock ready flag

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 8:14 - HSI16 clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn ppre(&mut self) -> PPRE_W<'_>

Bits 12:14 - APB prescaler

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 8:11 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:2 - System clock switch

impl W<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - PLL input clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl W<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&mut self) -> PLLSYSRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn pllsysrdyc(&mut self) -> PLLSYSRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&mut self) -> DMARST_W<'_>

Bit 0 - DMA1 reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - FLITF reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

pub fn aesrst(&mut self) -> AESRST_W<'_>

Bit 16 - AES hardware accelerator reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 18 - Random number generator reset

impl W<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 0 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 1 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 2 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 3 - I/O port D reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 5 - I/O port F reset

impl W<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 timer reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn lpuart1rst(&mut self) -> LPUART1RST_W<'_>

Bit 20 - LPUART1 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn dbgrst(&mut self) -> DBGRST_W<'_>

Bit 27 - Debug support reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn lptim2rst(&mut self) -> LPTIM2RST_W<'_>

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>

Bit 31 - Low Power Timer 1 reset

impl W<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 15 - TIM14 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 20 - ADC reset

impl W<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 0 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 1 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 2 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 3 - I/O port D clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 5 - I/O port F clock enable

impl W<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

pub fn aesen(&mut self) -> AESEN_W<'_>

Bit 16 - AES hardware accelerator

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 18 - Random number generator clock enable

impl W<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - RTC APB clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - WWDG clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn dbgen(&mut self) -> DBGEN_W<'_>

Bit 27 - Debug support clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - LPTIM1 clock enable

impl W<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 15 - TIM14 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM16 timer clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 20 - ADC clock enable

impl W<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&mut self) -> IOPASMEN_W<'_>

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&mut self) -> IOPBSMEN_W<'_>

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&mut self) -> IOPCSMEN_W<'_>

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&mut self) -> IOPDSMEN_W<'_>

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&mut self) -> IOPFSMEN_W<'_>

Bit 5 - I/O port F clock enable during Sleep mode

impl W<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&mut self) -> DMASMEN_W<'_>

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&mut self) -> SRAMSMEN_W<'_>

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

pub fn aessmen(&mut self) -> AESSMEN_W<'_>

Bit 16 - AES hardware accelerator clock enable during Sleep mode

pub fn rngsmen(&mut self) -> RNGSMEN_W<'_>

Bit 18 - Random number generator clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&mut self) -> TIM3SMEN_W<'_>

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&mut self) -> DBGSMEN_W<'_>

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&mut self) -> TIM14SMEN_W<'_>

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&mut self) -> ADCSMEN_W<'_>

Bit 20 - ADC clock enable during Sleep mode

impl W<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<'_>

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&mut self) -> I2S2SEL_W<'_>

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<'_>

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&mut self) -> TIM1SEL_W<'_>

Bit 22 - TIM1 clock source selection

pub fn rngsel(&mut self) -> RNGSEL_W<'_>

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&mut self) -> RNGDIV_W<'_>

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 30:31 - ADCs clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

pub fn lserdy(&mut self) -> LSERDY_W<'_>

Bit 1 - LSE oscillator ready

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - CSS on LSE enable

pub fn lsecssd(&mut self) -> LSECSSD_W<'_>

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - RTC domain software reset

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low-speed clock output selection

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

pub fn lsirdy(&mut self) -> LSIRDY_W<'_>

Bit 1 - LSI oscillator ready

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flags

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - Pin reset flag

pub fn pwrrstf(&mut self) -> PWRRSTF_W<'_>

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&mut self) -> FPD_LPSLP_W<'_>

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&mut self) -> FPD_LPRUN_W<'_>

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&mut self) -> FPD_STOP_W<'_>

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

pub fn pvdft(&mut self) -> PVDFT_W<'_>

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&mut self) -> PVDRT_W<'_>

Bits 4:6 - Power voltage detector rising threshold selection

impl W<u32, Reg<u32, _CR3>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&mut self) -> EWUP6_W<'_>

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&mut self) -> ULPEN_W<'_>

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line

impl W<u32, Reg<u32, _CR4>>

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&mut self) -> WP6_W<'_>

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

impl W<u32, Reg<u32, _SCR>>

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 8 - Clear standby flag

pub fn cwuf6(&mut self) -> CWUF6_W<'_>

Bit 5 - Clear wakeup flag 6

pub fn cwuf5(&mut self) -> CWUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn cwuf4(&mut self) -> CWUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn cwuf2(&mut self) -> CWUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn cwuf1(&mut self) -> CWUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Clear channel 1 global interrupt flag

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Clear channel 1 transfer complete flag

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Clear channel 1 half transfer flag

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Clear channel 1 transfer error flag

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Clear channel 2 global interrupt flag

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Clear channel 2 transfer complete flag

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Clear channel 2 half transfer flag

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Clear channel 2 transfer error flag

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Clear channel 3 global interrupt flag

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Clear channel 3 transfer complete flag

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Clear channel 3 half transfer flag

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Clear channel 3 transfer error flag

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Clear channel 4 global interrupt flag

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Clear channel 4 transfer complete flag

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Clear channel 4 half transfer flag

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Clear channel 4 transfer error flag

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Clear channel 5 global interrupt flag

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Clear channel 5 transfer complete flag

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Clear channel 5 half transfer flag

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Clear channel 5 transfer error flag

impl W<u32, Reg<u32, _C0CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C1CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C2CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C3CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C4CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C5CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _C6CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _RG0CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG1CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG2CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RG3CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _RGCFR>>

pub fn cof(&mut self) -> COF_W<'_>

Bits 0:3 - Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _CR>>

pub fn npblb(&mut self) -> NPBLB_W<'_>

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&mut self) -> KEYSIZE_W<'_>

Bit 18 - Key size selection

pub fn chmod2(&mut self) -> CHMOD2_W<'_>

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&mut self) -> GCMPH_W<'_>

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&mut self) -> CHMOD10_W<'_>

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&mut self) -> MODE_W<'_>

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&mut self) -> AES_KEYR4_W<'_>

Bits 0:31 - AES key register (MSB key [159:128])

impl W<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&mut self) -> AES_KEYR5_W<'_>

Bits 0:31 - AES key register (MSB key [191:160])

impl W<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&mut self) -> AES_KEYR6_W<'_>

Bits 0:31 - AES key register (MSB key [223:192])

impl W<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&mut self) -> AES_KEYR7_W<'_>

Bits 0:31 - AES key register (MSB key [255:224])

impl W<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&mut self) -> AES_SUSP0R_W<'_>

Bits 0:31 - AES suspend register 0

impl W<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&mut self) -> AES_SUSP1R_W<'_>

Bits 0:31 - AES suspend register 1

impl W<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&mut self) -> AES_SUSP2R_W<'_>

Bits 0:31 - AES suspend register 2

impl W<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&mut self) -> AES_SUSP3R_W<'_>

Bits 0:31 - AES suspend register 3

impl W<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&mut self) -> AES_SUSP4R_W<'_>

Bits 0:31 - AES suspend register 4

impl W<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&mut self) -> AES_SUSP5R_W<'_>

Bits 0:31 - AES suspend register 5

impl W<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&mut self) -> AES_SUSP6R_W<'_>

Bits 0:31 - AES suspend register 6

impl W<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&mut self) -> AES_SUSP7R_W<'_>

Bits 0:31 - AES suspend register 7

impl W<u32, Reg<u32, _CR>>

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn ced(&mut self) -> CED_W<'_>

Bit 5 - Clock error detection

pub fn byp(&mut self) -> BYP_W<'_>

Bit 6 - Bypass mode enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:31 - General-purpose 32-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn crc_init(&mut self) -> CRC_INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _RPR1>>

pub fn rpif0(&mut self) -> RPIF0_W<'_>

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&mut self) -> RPIF1_W<'_>

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&mut self) -> RPIF2_W<'_>

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&mut self) -> RPIF3_W<'_>

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&mut self) -> RPIF4_W<'_>

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&mut self) -> RPIF5_W<'_>

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&mut self) -> RPIF6_W<'_>

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&mut self) -> RPIF7_W<'_>

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&mut self) -> RPIF8_W<'_>

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&mut self) -> RPIF9_W<'_>

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&mut self) -> RPIF10_W<'_>

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&mut self) -> RPIF11_W<'_>

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&mut self) -> RPIF12_W<'_>

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&mut self) -> RPIF13_W<'_>

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&mut self) -> RPIF14_W<'_>

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&mut self) -> RPIF15_W<'_>

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&mut self) -> RPIF16_W<'_>

Bit 16 - configurable event inputs x rising edge Pending bit.

impl W<u32, Reg<u32, _FPR1>>

pub fn fpif0(&mut self) -> FPIF0_W<'_>

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&mut self) -> FPIF1_W<'_>

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&mut self) -> FPIF2_W<'_>

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&mut self) -> FPIF3_W<'_>

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&mut self) -> FPIF4_W<'_>

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&mut self) -> FPIF5_W<'_>

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&mut self) -> FPIF6_W<'_>

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&mut self) -> FPIF7_W<'_>

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&mut self) -> FPIF8_W<'_>

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&mut self) -> FPIF9_W<'_>

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&mut self) -> FPIF10_W<'_>

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&mut self) -> FPIF11_W<'_>

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&mut self) -> FPIF12_W<'_>

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&mut self) -> FPIF13_W<'_>

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&mut self) -> FPIF14_W<'_>

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&mut self) -> FPIF15_W<'_>

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&mut self) -> FPIF16_W<'_>

Bit 16 - configurable event inputs x falling edge pending bit.

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _IMR1>>

pub fn im0(&mut self) -> IM0_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&mut self) -> IM1_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&mut self) -> IM2_W<'_>

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&mut self) -> IM3_W<'_>

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&mut self) -> IM4_W<'_>

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&mut self) -> IM5_W<'_>

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&mut self) -> IM6_W<'_>

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&mut self) -> IM7_W<'_>

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&mut self) -> IM8_W<'_>

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&mut self) -> IM9_W<'_>

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&mut self) -> IM10_W<'_>

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&mut self) -> IM11_W<'_>

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&mut self) -> IM12_W<'_>

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&mut self) -> IM13_W<'_>

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&mut self) -> IM14_W<'_>

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&mut self) -> IM15_W<'_>

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&mut self) -> IM16_W<'_>

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im19(&mut self) -> IM19_W<'_>

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&mut self) -> IM20_W<'_>

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&mut self) -> IM21_W<'_>

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&mut self) -> IM22_W<'_>

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&mut self) -> IM23_W<'_>

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&mut self) -> IM24_W<'_>

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&mut self) -> IM25_W<'_>

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&mut self) -> IM26_W<'_>

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im28(&mut self) -> IM28_W<'_>

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&mut self) -> IM29_W<'_>

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&mut self) -> IM30_W<'_>

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&mut self) -> IM31_W<'_>

Bit 31 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR1>>

pub fn em0(&mut self) -> EM0_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&mut self) -> EM1_W<'_>

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&mut self) -> EM2_W<'_>

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&mut self) -> EM3_W<'_>

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&mut self) -> EM4_W<'_>

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&mut self) -> EM5_W<'_>

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&mut self) -> EM6_W<'_>

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&mut self) -> EM7_W<'_>

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&mut self) -> EM8_W<'_>

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&mut self) -> EM9_W<'_>

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&mut self) -> EM10_W<'_>

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&mut self) -> EM11_W<'_>

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&mut self) -> EM12_W<'_>

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&mut self) -> EM13_W<'_>

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&mut self) -> EM14_W<'_>

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&mut self) -> EM15_W<'_>

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&mut self) -> EM16_W<'_>

Bit 16 - CPU wakeup with event mask on event input

pub fn em19(&mut self) -> EM19_W<'_>

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&mut self) -> EM21_W<'_>

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&mut self) -> EM23_W<'_>

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&mut self) -> EM25_W<'_>

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&mut self) -> EM26_W<'_>

Bit 26 - CPU wakeup with event mask on event input

pub fn em28(&mut self) -> EM28_W<'_>

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&mut self) -> EM29_W<'_>

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&mut self) -> EM30_W<'_>

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&mut self) -> EM31_W<'_>

Bit 31 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - selects input

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - DEDT

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>

Bit 0 - Synchronous Slave mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&mut self) -> BRR_4_15_W<'_>

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&mut self) -> BRR_0_3_W<'_>

Bits 0:3 - BRR_0_3

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn udrcf(&mut self) -> UDRCF_W<'_>

Bit 13 - SPI slave underrun clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>

Bit 7 - Transmission complete before Guard time clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn txfecf(&mut self) -> TXFECF_W<'_>

Bit 5 - TXFIFO empty clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - standard selection

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn se2(&mut self) -> SE2_W<'_>

Bit 10 - I2S enable

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

impl W<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - linear prescaler

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts_4(&mut self) -> TS_4_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn ts(&mut self) -> TS_W<'_>

Bits 20:21 - Trigger selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&mut self) -> SBIF_W<'_>

Bit 13 - System Break interrupt flag

pub fn cc5if(&mut self) -> CC5IF_W<'_>

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&mut self) -> CC6IF_W<'_>

Bit 17 - Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3(&mut self) -> CCR3_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4(&mut self) -> CCR4_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bk2dsrm(&mut self) -> BK2DSRM_W<'_>

Bit 27 - Break2 Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

pub fn bk2id(&mut self) -> BK2ID_W<'_>

Bit 29 - Break2 bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&mut self) -> OCREF_CLR_W<'_>

Bit 0 - Ocref_clr source selection

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr5(&mut self) -> CCR5_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr6(&mut self) -> CCR6_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _AF2>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel3_0(&mut self) -> TI1SEL3_0_W<'_>

Bits 0:3 - selects TI1[0] to TI1[15] input

pub fn ti2sel3_0(&mut self) -> TI2SEL3_0_W<'_>

Bits 8:11 - selects TI2[0] to TI2[15] input

pub fn ti3sel3_0(&mut self) -> TI3SEL3_0_W<'_>

Bits 16:19 - selects TI3[0] to TI3[15] input

pub fn ti4sel3_0(&mut self) -> TI4SEL3_0_W<'_>

Bits 24:27 - selects TI4[0] to TI4[15] input

impl W<u32, Reg<u32, _ISR>>

pub fn ccrdy(&mut self) -> CCRDY_W<'_>

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&mut self) -> EOCAL_W<'_>

Bit 11 - End Of Calibration flag

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - ADC group regular overrun flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADC ready flag

impl W<u32, Reg<u32, _IER>>

pub fn ccrdyie(&mut self) -> CCRDYIE_W<'_>

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADC ready interrupt

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADC calibration

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADC voltage regulator enable

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADC group regular conversion stop

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADC group regular conversion start

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADC disable

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADC enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&mut self) -> CHSELRMOD_W<'_>

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - Auto-off mode

pub fn wait(&mut self) -> WAIT_W<'_>

Bit 14 - Wait conversion mode

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - ADC group regular overrun configuration

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:8 - ADC group regular external trigger source

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ADC data alignement

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - ADC data resolution

pub fn scandir(&mut self) -> SCANDIR_W<'_>

Bit 2 - Scan sequence direction

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - ADC DMA transfer enable

impl W<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 30:31 - ADC clock mode

pub fn lftrig(&mut self) -> LFTRIG_W<'_>

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&mut self) -> OVSE_W<'_>

Bit 0 - ADC oversampler enable on scope ADC group regular

impl W<u32, Reg<u32, _SMPR>>

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 0:2 - Sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 4:6 - Sampling time selection

pub fn smpsel(&mut self) -> SMPSEL_W<'_>

Bits 8:26 - Channel sampling time selection

impl W<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - ADC analog watchdog 1 threshold low

impl W<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:11 - ADC analog watchdog 2 threshold low

impl W<u32, Reg<u32, _CHSELR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 0:18 - Channel-x selection

impl W<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:3 - conversion of the sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 4:7 - conversion of the sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 8:11 - conversion of the sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 12:15 - conversion of the sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 16:19 - conversion of the sequence

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 20:23 - conversion of the sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 24:27 - conversion of the sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 28:31 - conversion of the sequence

impl W<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:11 - ADC analog watchdog 3 threshold high

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact(&mut self) -> CALFACT_W<'_>

Bits 0:6 - ADC calibration factor in single-ended mode

impl W<u32, Reg<u32, _CCR>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&mut self) -> I2C_PAX_FMP_W<'_>

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&mut self) -> I2C_PBX_FMP_W<'_>

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&mut self) -> IR_MOD_W<'_>

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&mut self) -> IR_POL_W<'_>

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - Memory mapping selection bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&mut self) -> ECC_LOCK_W<'_>

Bit 3 - ECC error lock bit

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity error flag

pub fn pa1_cden(&mut self) -> PA1_CDEN_W<'_>

Bit 16 - PA1_CDEN

pub fn pa3_cden(&mut self) -> PA3_CDEN_W<'_>

Bit 17 - PA3_CDEN

pub fn pa5_cden(&mut self) -> PA5_CDEN_W<'_>

Bit 18 - PA5_CDEN

pub fn pa6_cden(&mut self) -> PA6_CDEN_W<'_>

Bit 19 - PA6_CDEN

pub fn pa13_cden(&mut self) -> PA13_CDEN_W<'_>

Bit 20 - PA13_CDEN

pub fn pb0_cden(&mut self) -> PB0_CDEN_W<'_>

Bit 21 - PB0_CDEN

pub fn pb1_cden(&mut self) -> PB1_CDEN_W<'_>

Bit 22 - PB1_CDEN

pub fn pb2_cden(&mut self) -> PB2_CDEN_W<'_>

Bit 23 - PB2_CDEN

impl W<u32, Reg<u32, _CR1>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - TAMP1E

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 1 - TAMP2E

pub fn itamp1e(&mut self) -> ITAMP1E_W<'_>

Bit 16 - ITAMP1E

pub fn itamp3e(&mut self) -> ITAMP3E_W<'_>

Bit 18 - ITAMP3E

pub fn itamp4e(&mut self) -> ITAMP4E_W<'_>

Bit 19 - ITAMP4E

pub fn itamp5e(&mut self) -> ITAMP5E_W<'_>

Bit 20 - ITAMP5E

pub fn itamp6e(&mut self) -> ITAMP6E_W<'_>

Bit 21 - ITAMP6E

impl W<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&mut self) -> TAMP1NOER_W<'_>

Bit 0 - TAMP1NOER

pub fn tamp2noer(&mut self) -> TAMP2NOER_W<'_>

Bit 1 - TAMP2NOER

pub fn tamp1msk(&mut self) -> TAMP1MSK_W<'_>

Bit 16 - TAMP1MSK

pub fn tamp2msk(&mut self) -> TAMP2MSK_W<'_>

Bit 17 - TAMP2MSK

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 24 - TAMP1TRG

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 25 - TAMP2TRG

impl W<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 0:2 - TAMPFREQ

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 3:4 - TAMPFLT

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 7 - TAMPPUDIS

impl W<u32, Reg<u32, _IER>>

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 0 - TAMP1IE

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 1 - TAMP2IE

pub fn itamp1ie(&mut self) -> ITAMP1IE_W<'_>

Bit 16 - ITAMP1IE

pub fn itamp3ie(&mut self) -> ITAMP3IE_W<'_>

Bit 18 - ITAMP3IE

pub fn itamp4ie(&mut self) -> ITAMP4IE_W<'_>

Bit 19 - ITAMP4IE

pub fn itamp5ie(&mut self) -> ITAMP5IE_W<'_>

Bit 20 - ITAMP5IE

pub fn itamp6ie(&mut self) -> ITAMP6IE_W<'_>

Bit 21 - ITAMP6IE

impl W<u32, Reg<u32, _SCR>>

pub fn ctamp1f(&mut self) -> CTAMP1F_W<'_>

Bit 0 - CTAMP1F

pub fn ctamp2f(&mut self) -> CTAMP2F_W<'_>

Bit 1 - CTAMP2F

pub fn citamp1f(&mut self) -> CITAMP1F_W<'_>

Bit 16 - CITAMP1F

pub fn citamp3f(&mut self) -> CITAMP3F_W<'_>

Bit 18 - CITAMP3F

pub fn citamp4f(&mut self) -> CITAMP4F_W<'_>

Bit 19 - CITAMP4F

pub fn citamp5f(&mut self) -> CITAMP5F_W<'_>

Bit 20 - CITAMP5F

pub fn citamp6f(&mut self) -> CITAMP6F_W<'_>

Bit 21 - CITAMP6F

pub fn citamp7f(&mut self) -> CITAMP7F_W<'_>

Bit 22 - CITAMP7F

impl W<u32, Reg<u32, _BKP0R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP1R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP2R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP3R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP4R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn rstare(&mut self) -> RSTARE_W<'_>

Bit 4 - Reset after read enable

pub fn countrst(&mut self) -> COUNTRST_W<'_>

Bit 3 - Counter reset

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&mut self) -> IN2SEL_W<'_>

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&mut self) -> IN1SEL_W<'_>

Bits 0:1 - LPTIMx Input 1 selection

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT0

pub fn dedt0(&mut self) -> DEDT0_W<'_>

Bits 16:20 - DEDT0

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:19 - BRR

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&mut self) -> OA1_0_W<'_>

Bit 0 - Interface address

pub fn oa1_7_1(&mut self) -> OA1_7_1_W<'_>

Bits 1:7 - Interface address

pub fn oa1_8_9(&mut self) -> OA1_8_9_W<'_>

Bits 8:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _ICSR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - WUCKSEL

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - TSEDGE

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - REFCKON

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - BYPSHAD

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - FMT

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - ALRAE

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - ALRBE

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - WUTE

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - TSE

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - ALRAIE

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - ALRBIE

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - WUTIE

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - TSIE

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - ADD1H

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - SUB1H

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - BKP

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - COSEL

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - POL

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - OSEL

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - COE

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - ITSE

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 25 - TAMPTS

pub fn tampoe(&mut self) -> TAMPOE_W<'_>

Bit 26 - TAMPOE

pub fn tampalrm_pu(&mut self) -> TAMPALRM_PU_W<'_>

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&mut self) -> TAMPALRM_TYPE_W<'_>

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&mut self) -> OUT2EN_W<'_>

Bit 31 - OUT2EN

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _SCR>>

pub fn calraf(&mut self) -> CALRAF_W<'_>

Bit 0 - CALRAF

pub fn calrbf(&mut self) -> CALRBF_W<'_>

Bit 1 - CALRBF

pub fn cwutf(&mut self) -> CWUTF_W<'_>

Bit 2 - CWUTF

pub fn ctsf(&mut self) -> CTSF_W<'_>

Bit 3 - CTSF

pub fn ctsovf(&mut self) -> CTSOVF_W<'_>

Bit 4 - CTSOVF

pub fn citsf(&mut self) -> CITSF_W<'_>

Bit 5 - CITSF

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&mut self) -> ICPCS_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _TISEL>>

pub fn tisel(&mut self) -> TISEL_W<'_>

Bits 0:3 - TI1[0] to TI1[15] input selection

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&mut self) -> TS_4_3_W<'_>

Bits 20:21 - Trigger selection

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&mut self) -> CNT_L_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&mut self) -> ARR_L_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&mut self) -> CCR1_L_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&mut self) -> CCR2_H_W<'_>

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&mut self) -> CCR2_L_W<'_>

Bits 0:15 - Low Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&mut self) -> CCR3_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&mut self) -> CCR3_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&mut self) -> CCR4_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&mut self) -> CCR4_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&mut self) -> IOCREF_CLR_W<'_>

Bit 0 - IOCREF_CLR

impl W<u32, Reg<u32, _AF1>>

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:17 - External trigger source selection

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - TI1SEL

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - TI2SEL

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrs(&mut self) -> VRS_W<'_>

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl W<u32, Reg<u32, _CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl W<u32, Reg<u32, _CR>>

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby mode

impl W<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - TIM2 counter stopped when core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Window watchdog counter stopped when core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Independent watchdog counter stopped when core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 30 - LPTIM2 counter stopped when core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - LPTIM1 counter stopped when core is halted

impl W<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - DBG_TIM17_STOP

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _HWCFGR>>

pub fn window(&mut self) -> WINDOW_W<'_>

Bits 0:3 - Support of Window function

pub fn pr_default(&mut self) -> PR_DEFAULT_W<'_>

Bits 4:7 - Prescaler default value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 11:13 - Timer base

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 16 - Flash User area empty

pub fn dbg_swen(&mut self) -> DBG_SWEN_W<'_>

Bit 18 - Debug access software enable

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&mut self) -> BSY_W<'_>

Bit 16 - Busy

pub fn cfgbsy(&mut self) -> CFGBSY_W<'_>

Bit 18 - Programming or erase configuration busy.

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:8 - Page number

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn sec_prot(&mut self) -> SEC_PROT_W<'_>

Bit 28 - Securable memory area protection enable

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn boren(&mut self) -> BOREN_W<'_>

Bit 8 - BOR reset Level

pub fn borf_lev(&mut self) -> BORF_LEV_W<'_>

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&mut self) -> BORR_LEV_W<'_>

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&mut self) -> NRSTS_HDW_W<'_>

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&mut self) -> RAM_PARITY_CHECK_W<'_>

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&mut self) -> NBOOT_SEL_W<'_>

Bit 24 - nBOOT_SEL

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 25 - Boot configuration

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&mut self) -> NRST_MODE_W<'_>

Bits 27:28 - NRST_MODE

pub fn irhen(&mut self) -> IRHEN_W<'_>

Bit 29 - Internal reset holder enable bit

impl W<u32, Reg<u32, _CR>>

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

impl W<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_timer2_stop(&mut self) -> DBG_TIMER2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_timer6_stop(&mut self) -> DBG_TIMER6_STOP_W<'_>

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 30 - Clocking of LPTIMER2 counter when the core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - Clocking of LPTIMER1 counter when the core is halted

impl W<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - DBG_TIM1_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 16 - DBG_TIM15_STOP

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - DBG_TIM17_STOP

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI16 clock enable

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&mut self) -> HSIRDY_W<'_>

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&mut self) -> HSIDIV_W<'_>

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> HSERDY_W<'_>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

pub fn pllrdy(&mut self) -> PLLRDY_W<'_>

Bit 25 - PLL clock ready flag

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 8:14 - HSI16 clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn ppre(&mut self) -> PPRE_W<'_>

Bits 12:14 - APB prescaler

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 8:11 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:2 - System clock switch

impl W<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - PLL input clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl W<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&mut self) -> PLLSYSRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn pllsysrdyc(&mut self) -> PLLSYSRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&mut self) -> DMARST_W<'_>

Bit 0 - DMA1 reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - FLITF reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

impl W<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 0 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 1 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 2 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 3 - I/O port D reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 5 - I/O port F reset

impl W<u32, Reg<u32, _APBRSTR1>>

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 timer reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6 timer reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7 timer reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn usart4rst(&mut self) -> USART4RST_W<'_>

Bit 19 - USART4 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn dbgrst(&mut self) -> DBGRST_W<'_>

Bit 27 - Debug support reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

impl W<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 15 - TIM14 timer reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 20 - ADC reset

impl W<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 0 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 1 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 2 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 3 - I/O port D clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 5 - I/O port F clock enable

impl W<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

impl W<u32, Reg<u32, _APBENR1>>

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6 timer clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - RTC APB clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - WWDG clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3 clock enable

pub fn usart4en(&mut self) -> USART4EN_W<'_>

Bit 19 - USART4 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn dbgen(&mut self) -> DBGEN_W<'_>

Bit 27 - Debug support clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

impl W<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 15 - TIM14 timer clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM16 timer clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 20 - ADC clock enable

impl W<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&mut self) -> IOPASMEN_W<'_>

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&mut self) -> IOPBSMEN_W<'_>

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&mut self) -> IOPCSMEN_W<'_>

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&mut self) -> IOPDSMEN_W<'_>

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&mut self) -> IOPFSMEN_W<'_>

Bit 5 - I/O port F clock enable during Sleep mode

impl W<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&mut self) -> DMASMEN_W<'_>

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&mut self) -> SRAMSMEN_W<'_>

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR1>>

pub fn tim3smen(&mut self) -> TIM3SMEN_W<'_>

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn tim6smen(&mut self) -> TIM6SMEN_W<'_>

Bit 4 - TIM6 timer clock enable during Sleep mode

pub fn tim7smen(&mut self) -> TIM7SMEN_W<'_>

Bit 5 - TIM7 timer clock enable during Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3smen(&mut self) -> USART3SMEN_W<'_>

Bit 18 - USART3 clock enable during Sleep mode

pub fn usart4smen(&mut self) -> USART4SMEN_W<'_>

Bit 19 - USART4 clock enable during Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&mut self) -> DBGSMEN_W<'_>

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&mut self) -> TIM14SMEN_W<'_>

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim15smen(&mut self) -> TIM15SMEN_W<'_>

Bit 16 - TIM15 timer clock enable during Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&mut self) -> ADCSMEN_W<'_>

Bit 20 - ADC clock enable during Sleep mode

impl W<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn usart2sel(&mut self) -> USART2SEL_W<'_>

Bits 2:3 - USART2 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&mut self) -> I2S2SEL_W<'_>

Bits 14:15 - I2S1 clock source selection

pub fn tim1sel(&mut self) -> TIM1SEL_W<'_>

Bit 22 - TIM1 clock source selection

pub fn tim15sel(&mut self) -> TIM15SEL_W<'_>

Bit 24 - TIM15 clock source selection

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 30:31 - ADCs clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

pub fn lserdy(&mut self) -> LSERDY_W<'_>

Bit 1 - LSE oscillator ready

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - CSS on LSE enable

pub fn lsecssd(&mut self) -> LSECSSD_W<'_>

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - RTC domain software reset

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low-speed clock output selection

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

pub fn lsirdy(&mut self) -> LSIRDY_W<'_>

Bit 1 - LSI oscillator ready

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flags

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - Pin reset flag

pub fn pwrrstf(&mut self) -> PWRRSTF_W<'_>

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&mut self) -> FPD_LPSLP_W<'_>

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&mut self) -> FPD_LPRUN_W<'_>

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&mut self) -> FPD_STOP_W<'_>

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

pub fn pvdft(&mut self) -> PVDFT_W<'_>

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&mut self) -> PVDRT_W<'_>

Bits 4:6 - Power voltage detector rising threshold selection

impl W<u32, Reg<u32, _CR3>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&mut self) -> EWUP6_W<'_>

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&mut self) -> ULPEN_W<'_>

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line

impl W<u32, Reg<u32, _CR4>>

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&mut self) -> WP6_W<'_>

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

impl W<u32, Reg<u32, _SCR>>

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 8 - Clear standby flag

pub fn cwuf6(&mut self) -> CWUF6_W<'_>

Bit 5 - Clear wakeup flag 6

pub fn cwuf5(&mut self) -> CWUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn cwuf4(&mut self) -> CWUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn cwuf2(&mut self) -> CWUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn cwuf1(&mut self) -> CWUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Clear channel 1 global interrupt flag

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Clear channel 1 transfer complete flag

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Clear channel 1 half transfer flag

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Clear channel 1 transfer error flag

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Clear channel 2 global interrupt flag

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Clear channel 2 transfer complete flag

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Clear channel 2 half transfer flag

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Clear channel 2 transfer error flag

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Clear channel 3 global interrupt flag

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Clear channel 3 transfer complete flag

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Clear channel 3 half transfer flag

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Clear channel 3 transfer error flag

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Clear channel 4 global interrupt flag

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Clear channel 4 transfer complete flag

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Clear channel 4 half transfer flag

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Clear channel 4 transfer error flag

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Clear channel 5 global interrupt flag

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Clear channel 5 transfer complete flag

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Clear channel 5 half transfer flag

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Clear channel 5 transfer error flag

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Clear channel 6 global interrupt flag

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Clear channel 6 transfer complete flag

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Clear channel 6 half transfer flag

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Clear channel 6 transfer error flag

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Clear channel 7 global interrupt flag

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Clear channel 7 transfer complete flag

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Clear channel 7 half transfer flag

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Clear channel 7 transfer error flag

impl W<u32, Reg<u32, _DMAMUX_C0CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C1CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C2CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C3CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C4CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C5CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C6CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_RG0CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG1CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG2CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG3CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RGCFR>>

pub fn cof(&mut self) -> COF_W<'_>

Bits 0:3 - Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.

impl W<u32, Reg<u32, _DMAMUX_CFR>>

pub fn csof(&mut self) -> CSOF_W<'_>

Bits 0:6 - Clear synchronization overrun event flag

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:31 - General-purpose 32-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn crc_init(&mut self) -> CRC_INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _RPR1>>

pub fn rpif0(&mut self) -> RPIF0_W<'_>

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&mut self) -> RPIF1_W<'_>

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&mut self) -> RPIF2_W<'_>

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&mut self) -> RPIF3_W<'_>

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&mut self) -> RPIF4_W<'_>

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&mut self) -> RPIF5_W<'_>

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&mut self) -> RPIF6_W<'_>

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&mut self) -> RPIF7_W<'_>

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&mut self) -> RPIF8_W<'_>

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&mut self) -> RPIF9_W<'_>

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&mut self) -> RPIF10_W<'_>

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&mut self) -> RPIF11_W<'_>

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&mut self) -> RPIF12_W<'_>

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&mut self) -> RPIF13_W<'_>

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&mut self) -> RPIF14_W<'_>

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&mut self) -> RPIF15_W<'_>

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&mut self) -> RPIF16_W<'_>

Bit 16 - configurable event inputs x rising edge Pending bit.

pub fn rpif17(&mut self) -> RPIF17_W<'_>

Bit 17 - configurable event inputs x rising edge Pending bit.

pub fn rpif18(&mut self) -> RPIF18_W<'_>

Bit 18 - configurable event inputs x rising edge Pending bit.

impl W<u32, Reg<u32, _FPR1>>

pub fn fpif0(&mut self) -> FPIF0_W<'_>

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&mut self) -> FPIF1_W<'_>

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&mut self) -> FPIF2_W<'_>

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&mut self) -> FPIF3_W<'_>

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&mut self) -> FPIF4_W<'_>

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&mut self) -> FPIF5_W<'_>

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&mut self) -> FPIF6_W<'_>

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&mut self) -> FPIF7_W<'_>

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&mut self) -> FPIF8_W<'_>

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&mut self) -> FPIF9_W<'_>

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&mut self) -> FPIF10_W<'_>

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&mut self) -> FPIF11_W<'_>

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&mut self) -> FPIF12_W<'_>

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&mut self) -> FPIF13_W<'_>

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&mut self) -> FPIF14_W<'_>

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&mut self) -> FPIF15_W<'_>

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&mut self) -> FPIF16_W<'_>

Bit 16 - configurable event inputs x falling edge pending bit.

pub fn fpif17(&mut self) -> FPIF17_W<'_>

Bit 17 - configurable event inputs x falling edge pending bit.

pub fn fpif18(&mut self) -> FPIF18_W<'_>

Bit 18 - configurable event inputs x falling edge pending bit.

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _IMR1>>

pub fn im0(&mut self) -> IM0_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&mut self) -> IM1_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&mut self) -> IM2_W<'_>

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&mut self) -> IM3_W<'_>

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&mut self) -> IM4_W<'_>

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&mut self) -> IM5_W<'_>

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&mut self) -> IM6_W<'_>

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&mut self) -> IM7_W<'_>

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&mut self) -> IM8_W<'_>

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&mut self) -> IM9_W<'_>

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&mut self) -> IM10_W<'_>

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&mut self) -> IM11_W<'_>

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&mut self) -> IM12_W<'_>

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&mut self) -> IM13_W<'_>

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&mut self) -> IM14_W<'_>

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&mut self) -> IM15_W<'_>

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&mut self) -> IM16_W<'_>

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im17(&mut self) -> IM17_W<'_>

Bit 17 - CPU wakeup with interrupt mask on event input

pub fn im18(&mut self) -> IM18_W<'_>

Bit 18 - CPU wakeup with interrupt mask on event input

pub fn im19(&mut self) -> IM19_W<'_>

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&mut self) -> IM20_W<'_>

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&mut self) -> IM21_W<'_>

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&mut self) -> IM22_W<'_>

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&mut self) -> IM23_W<'_>

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&mut self) -> IM24_W<'_>

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&mut self) -> IM25_W<'_>

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&mut self) -> IM26_W<'_>

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im27(&mut self) -> IM27_W<'_>

Bit 27 - CPU wakeup with interrupt mask on event input

pub fn im28(&mut self) -> IM28_W<'_>

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&mut self) -> IM29_W<'_>

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&mut self) -> IM30_W<'_>

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&mut self) -> IM31_W<'_>

Bit 31 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR1>>

pub fn em0(&mut self) -> EM0_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&mut self) -> EM1_W<'_>

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&mut self) -> EM2_W<'_>

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&mut self) -> EM3_W<'_>

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&mut self) -> EM4_W<'_>

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&mut self) -> EM5_W<'_>

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&mut self) -> EM6_W<'_>

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&mut self) -> EM7_W<'_>

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&mut self) -> EM8_W<'_>

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&mut self) -> EM9_W<'_>

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&mut self) -> EM10_W<'_>

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&mut self) -> EM11_W<'_>

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&mut self) -> EM12_W<'_>

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&mut self) -> EM13_W<'_>

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&mut self) -> EM14_W<'_>

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&mut self) -> EM15_W<'_>

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&mut self) -> EM16_W<'_>

Bit 16 - CPU wakeup with event mask on event input

pub fn em17(&mut self) -> EM17_W<'_>

Bit 17 - CPU wakeup with event mask on event input

pub fn em18(&mut self) -> EM18_W<'_>

Bit 18 - CPU wakeup with event mask on event input

pub fn em19(&mut self) -> EM19_W<'_>

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&mut self) -> EM21_W<'_>

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&mut self) -> EM23_W<'_>

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&mut self) -> EM25_W<'_>

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&mut self) -> EM26_W<'_>

Bit 26 - CPU wakeup with event mask on event input

pub fn em27(&mut self) -> EM27_W<'_>

Bit 27 - CPU wakeup with event mask on event input

pub fn em28(&mut self) -> EM28_W<'_>

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&mut self) -> EM29_W<'_>

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&mut self) -> EM30_W<'_>

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&mut self) -> EM31_W<'_>

Bit 31 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _IMR2>>

pub fn im32(&mut self) -> IM32_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im33(&mut self) -> IM33_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR2>>

pub fn em32(&mut self) -> EM32_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em33(&mut self) -> EM33_W<'_>

Bit 1 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _HWCFGR7>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR6>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR5>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR4>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _HWCFGR3>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - selects input

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - DEDT

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>

Bit 0 - Synchronous Slave mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&mut self) -> BRR_4_15_W<'_>

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&mut self) -> BRR_0_3_W<'_>

Bits 0:3 - BRR_0_3

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn udrcf(&mut self) -> UDRCF_W<'_>

Bit 13 - SPI slave underrun clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>

Bit 7 - Transmission complete before Guard time clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn txfecf(&mut self) -> TXFECF_W<'_>

Bit 5 - TXFIFO empty clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - standard selection

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn se2(&mut self) -> SE2_W<'_>

Bit 10 - I2S enable

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

impl W<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - linear prescaler

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts_4(&mut self) -> TS_4_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn ts(&mut self) -> TS_W<'_>

Bits 20:21 - Trigger selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&mut self) -> SBIF_W<'_>

Bit 13 - System Break interrupt flag

pub fn cc5if(&mut self) -> CC5IF_W<'_>

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&mut self) -> CC6IF_W<'_>

Bit 17 - Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3(&mut self) -> CCR3_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4(&mut self) -> CCR4_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bk2dsrm(&mut self) -> BK2DSRM_W<'_>

Bit 27 - Break2 Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

pub fn bk2id(&mut self) -> BK2ID_W<'_>

Bit 29 - Break2 bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&mut self) -> OCREF_CLR_W<'_>

Bit 0 - Ocref_clr source selection

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr5(&mut self) -> CCR5_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr6(&mut self) -> CCR6_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _AF2>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _ISR>>

pub fn ccrdy(&mut self) -> CCRDY_W<'_>

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&mut self) -> EOCAL_W<'_>

Bit 11 - End Of Calibration flag

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - ADC group regular overrun flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADC ready flag

impl W<u32, Reg<u32, _IER>>

pub fn ccrdyie(&mut self) -> CCRDYIE_W<'_>

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADC ready interrupt

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADC calibration

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADC voltage regulator enable

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADC group regular conversion stop

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADC group regular conversion start

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADC disable

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADC enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&mut self) -> CHSELRMOD_W<'_>

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - Auto-off mode

pub fn wait(&mut self) -> WAIT_W<'_>

Bit 14 - Wait conversion mode

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - ADC group regular overrun configuration

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:8 - ADC group regular external trigger source

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ADC data alignement

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - ADC data resolution

pub fn scandir(&mut self) -> SCANDIR_W<'_>

Bit 2 - Scan sequence direction

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - ADC DMA transfer enable

impl W<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 30:31 - ADC clock mode

pub fn lftrig(&mut self) -> LFTRIG_W<'_>

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&mut self) -> OVSE_W<'_>

Bit 0 - ADC oversampler enable on scope ADC group regular

impl W<u32, Reg<u32, _SMPR>>

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 0:2 - Sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 4:6 - Sampling time selection

pub fn smpsel(&mut self) -> SMPSEL_W<'_>

Bits 8:26 - Channel sampling time selection

impl W<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - ADC analog watchdog 1 threshold low

impl W<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:11 - ADC analog watchdog 2 threshold low

impl W<u32, Reg<u32, _CHSELR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 0:18 - Channel-x selection

impl W<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:3 - conversion of the sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 4:7 - conversion of the sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 8:11 - conversion of the sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 12:15 - conversion of the sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 16:19 - conversion of the sequence

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 20:23 - conversion of the sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 24:27 - conversion of the sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 28:31 - conversion of the sequence

impl W<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:11 - ADC analog watchdog 3 threshold high

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact(&mut self) -> CALFACT_W<'_>

Bits 0:6 - ADC calibration factor in single-ended mode

impl W<u32, Reg<u32, _CCR>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _HWCFGR6>>

pub fn chmap20(&mut self) -> CHMAP20_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap21(&mut self) -> CHMAP21_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap22(&mut self) -> CHMAP22_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap23(&mut self) -> CHMAP23_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR5>>

pub fn chmap19(&mut self) -> CHMAP19_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap18(&mut self) -> CHMAP18_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap17(&mut self) -> CHMAP17_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap16(&mut self) -> CHMAP16_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR4>>

pub fn chmap15(&mut self) -> CHMAP15_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap14(&mut self) -> CHMAP14_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap13(&mut self) -> CHMAP13_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap12(&mut self) -> CHMAP12_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR3>>

pub fn chmap11(&mut self) -> CHMAP11_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap10(&mut self) -> CHMAP10_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap9(&mut self) -> CHMAP9_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap8(&mut self) -> CHMAP8_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn chmap7(&mut self) -> CHMAP7_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap6(&mut self) -> CHMAP6_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap5(&mut self) -> CHMAP5_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap4(&mut self) -> CHMAP4_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR1>>

pub fn chmap3(&mut self) -> CHMAP3_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap2(&mut self) -> CHMAP2_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap1(&mut self) -> CHMAP1_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap0(&mut self) -> CHMAP0_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _CR1>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - TAMP1E

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 1 - TAMP2E

pub fn itamp1e(&mut self) -> ITAMP1E_W<'_>

Bit 16 - ITAMP1E

pub fn itamp3e(&mut self) -> ITAMP3E_W<'_>

Bit 18 - ITAMP3E

pub fn itamp4e(&mut self) -> ITAMP4E_W<'_>

Bit 19 - ITAMP4E

pub fn itamp5e(&mut self) -> ITAMP5E_W<'_>

Bit 20 - ITAMP5E

pub fn itamp6e(&mut self) -> ITAMP6E_W<'_>

Bit 21 - ITAMP6E

impl W<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&mut self) -> TAMP1NOER_W<'_>

Bit 0 - TAMP1NOER

pub fn tamp2noer(&mut self) -> TAMP2NOER_W<'_>

Bit 1 - TAMP2NOER

pub fn tamp1msk(&mut self) -> TAMP1MSK_W<'_>

Bit 16 - TAMP1MSK

pub fn tamp2msk(&mut self) -> TAMP2MSK_W<'_>

Bit 17 - TAMP2MSK

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 24 - TAMP1TRG

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 25 - TAMP2TRG

impl W<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 0:2 - TAMPFREQ

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 3:4 - TAMPFLT

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 7 - TAMPPUDIS

impl W<u32, Reg<u32, _IER>>

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 0 - TAMP1IE

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 1 - TAMP2IE

pub fn itamp1ie(&mut self) -> ITAMP1IE_W<'_>

Bit 16 - ITAMP1IE

pub fn itamp3ie(&mut self) -> ITAMP3IE_W<'_>

Bit 18 - ITAMP3IE

pub fn itamp4ie(&mut self) -> ITAMP4IE_W<'_>

Bit 19 - ITAMP4IE

pub fn itamp5ie(&mut self) -> ITAMP5IE_W<'_>

Bit 20 - ITAMP5IE

pub fn itamp6ie(&mut self) -> ITAMP6IE_W<'_>

Bit 21 - ITAMP6IE

impl W<u32, Reg<u32, _SCR>>

pub fn ctamp1f(&mut self) -> CTAMP1F_W<'_>

Bit 0 - CTAMP1F

pub fn ctamp2f(&mut self) -> CTAMP2F_W<'_>

Bit 1 - CTAMP2F

pub fn citamp1f(&mut self) -> CITAMP1F_W<'_>

Bit 16 - CITAMP1F

pub fn citamp3f(&mut self) -> CITAMP3F_W<'_>

Bit 18 - CITAMP3F

pub fn citamp4f(&mut self) -> CITAMP4F_W<'_>

Bit 19 - CITAMP4F

pub fn citamp5f(&mut self) -> CITAMP5F_W<'_>

Bit 20 - CITAMP5F

pub fn citamp6f(&mut self) -> CITAMP6F_W<'_>

Bit 21 - CITAMP6F

pub fn citamp7f(&mut self) -> CITAMP7F_W<'_>

Bit 22 - CITAMP7F

impl W<u32, Reg<u32, _BKP0R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP1R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP2R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP3R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP4R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&mut self) -> OA1_0_W<'_>

Bit 0 - Interface address

pub fn oa1_7_1(&mut self) -> OA1_7_1_W<'_>

Bits 1:7 - Interface address

pub fn oa1_8_9(&mut self) -> OA1_8_9_W<'_>

Bits 8:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _ICSR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - WUCKSEL

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - TSEDGE

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - REFCKON

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - BYPSHAD

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - FMT

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - ALRAE

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - ALRBE

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - WUTE

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - TSE

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - ALRAIE

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - ALRBIE

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - WUTIE

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - TSIE

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - ADD1H

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - SUB1H

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - BKP

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - COSEL

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - POL

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - OSEL

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - COE

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - ITSE

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 25 - TAMPTS

pub fn tampoe(&mut self) -> TAMPOE_W<'_>

Bit 26 - TAMPOE

pub fn tampalrm_pu(&mut self) -> TAMPALRM_PU_W<'_>

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&mut self) -> TAMPALRM_TYPE_W<'_>

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&mut self) -> OUT2EN_W<'_>

Bit 31 - OUT2EN

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _SCR>>

pub fn calraf(&mut self) -> CALRAF_W<'_>

Bit 0 - CALRAF

pub fn calrbf(&mut self) -> CALRBF_W<'_>

Bit 1 - CALRBF

pub fn cwutf(&mut self) -> CWUTF_W<'_>

Bit 2 - CWUTF

pub fn ctsf(&mut self) -> CTSF_W<'_>

Bit 3 - CTSF

pub fn ctsovf(&mut self) -> CTSOVF_W<'_>

Bit 4 - CTSOVF

pub fn citsf(&mut self) -> CITSF_W<'_>

Bit 5 - CITSF

impl W<u32, Reg<u32, _HWCFGR>>

pub fn alarmb(&mut self) -> ALARMB_W<'_>

Bits 0:3 - ALARMB

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bits 4:7 - WAKEUP

pub fn smooth_calib(&mut self) -> SMOOTH_CALIB_W<'_>

Bits 8:11 - SMOOTH_CALIB

pub fn timestamp(&mut self) -> TIMESTAMP_W<'_>

Bits 12:15 - TIMESTAMP

pub fn optionreg_out(&mut self) -> OPTIONREG_OUT_W<'_>

Bits 16:23 - OPTIONREG_OUT

pub fn trust_zone(&mut self) -> TRUST_ZONE_W<'_>

Bits 24:27 - TRUST_ZONE

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&mut self) -> ICPCS_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _TISEL>>

pub fn tisel(&mut self) -> TISEL_W<'_>

Bits 0:3 - TI1[0] to TI1[15] input selection

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&mut self) -> TS_4_3_W<'_>

Bits 20:21 - Trigger selection

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&mut self) -> CNT_L_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&mut self) -> ARR_L_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&mut self) -> CCR1_L_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&mut self) -> CCR2_H_W<'_>

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&mut self) -> CCR2_L_W<'_>

Bits 0:15 - Low Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&mut self) -> CCR3_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&mut self) -> CCR3_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&mut self) -> CCR4_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&mut self) -> CCR4_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&mut self) -> IOCREF_CLR_W<'_>

Bit 0 - IOCREF_CLR

impl W<u32, Reg<u32, _AF1>>

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:17 - External trigger source selection

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - TI1SEL

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - TI2SEL

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _HWCFGR>>

pub fn window(&mut self) -> WINDOW_W<'_>

Bits 0:3 - Support of Window function

pub fn pr_default(&mut self) -> PR_DEFAULT_W<'_>

Bits 4:7 - Prescaler default value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 11:13 - Timer base

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 16 - Flash User area empty

pub fn dbg_swen(&mut self) -> DBG_SWEN_W<'_>

Bit 18 - Debug access software enable

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&mut self) -> BSY_W<'_>

Bit 16 - Busy

pub fn cfgbsy(&mut self) -> CFGBSY_W<'_>

Bit 18 - Programming or erase configuration busy.

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:8 - Page number

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn sec_prot(&mut self) -> SEC_PROT_W<'_>

Bit 28 - Securable memory area protection enable

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn boren(&mut self) -> BOREN_W<'_>

Bit 8 - BOR reset Level

pub fn borf_lev(&mut self) -> BORF_LEV_W<'_>

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&mut self) -> BORR_LEV_W<'_>

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&mut self) -> NRSTS_HDW_W<'_>

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&mut self) -> RAM_PARITY_CHECK_W<'_>

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&mut self) -> NBOOT_SEL_W<'_>

Bit 24 - nBOOT_SEL

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 25 - Boot configuration

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&mut self) -> NRST_MODE_W<'_>

Bits 27:28 - NRST_MODE

pub fn irhen(&mut self) -> IRHEN_W<'_>

Bit 29 - Internal reset holder enable bit

impl W<u32, Reg<u32, _CR>>

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

impl W<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_timer2_stop(&mut self) -> DBG_TIMER2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_timer6_stop(&mut self) -> DBG_TIMER6_STOP_W<'_>

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 30 - Clocking of LPTIMER2 counter when the core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - Clocking of LPTIMER1 counter when the core is halted

impl W<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - DBG_TIM1_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 16 - DBG_TIM15_STOP

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - DBG_TIM17_STOP

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI16 clock enable

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&mut self) -> HSIRDY_W<'_>

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&mut self) -> HSIDIV_W<'_>

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> HSERDY_W<'_>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

pub fn pllrdy(&mut self) -> PLLRDY_W<'_>

Bit 25 - PLL clock ready flag

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 8:14 - HSI16 clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn ppre(&mut self) -> PPRE_W<'_>

Bits 12:14 - APB prescaler

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 8:11 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:2 - System clock switch

impl W<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - PLL input clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl W<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&mut self) -> PLLSYSRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn pllsysrdyc(&mut self) -> PLLSYSRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&mut self) -> DMARST_W<'_>

Bit 0 - DMA1 reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - FLITF reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

impl W<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 0 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 1 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 2 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 3 - I/O port D reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 5 - I/O port F reset

impl W<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 timer reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6 timer reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7 timer reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn usart4rst(&mut self) -> USART4RST_W<'_>

Bit 19 - USART4 reset

pub fn lpuart1rst(&mut self) -> LPUART1RST_W<'_>

Bit 20 - LPUART1 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn cecrst(&mut self) -> CECRST_W<'_>

Bit 24 - HDMI CEC reset

pub fn ucpd1rst(&mut self) -> UCPD1RST_W<'_>

Bit 25 - UCPD1 reset

pub fn ucpd2rst(&mut self) -> UCPD2RST_W<'_>

Bit 26 - UCPD2 reset

pub fn dbgrst(&mut self) -> DBGRST_W<'_>

Bit 27 - Debug support reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dac1rst(&mut self) -> DAC1RST_W<'_>

Bit 29 - DAC1 interface reset

pub fn lptim2rst(&mut self) -> LPTIM2RST_W<'_>

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>

Bit 31 - Low Power Timer 1 reset

impl W<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 15 - TIM14 timer reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 20 - ADC reset

impl W<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 0 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 1 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 2 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 3 - I/O port D clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 5 - I/O port F clock enable

impl W<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

impl W<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6 timer clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - RTC APB clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - WWDG clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3 clock enable

pub fn usart4en(&mut self) -> USART4EN_W<'_>

Bit 19 - USART4 clock enable

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn cecen(&mut self) -> CECEN_W<'_>

Bit 24 - HDMI CEC clock enable

pub fn ucpd1en(&mut self) -> UCPD1EN_W<'_>

Bit 25 - UCPD1 clock enable

pub fn ucpd2en(&mut self) -> UCPD2EN_W<'_>

Bit 26 - UCPD2 clock enable

pub fn dbgen(&mut self) -> DBGEN_W<'_>

Bit 27 - Debug support clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dac1en(&mut self) -> DAC1EN_W<'_>

Bit 29 - DAC1 interface clock enable

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - LPTIM1 clock enable

impl W<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 15 - TIM14 timer clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM16 timer clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 20 - ADC clock enable

impl W<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&mut self) -> IOPASMEN_W<'_>

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&mut self) -> IOPBSMEN_W<'_>

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&mut self) -> IOPCSMEN_W<'_>

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&mut self) -> IOPDSMEN_W<'_>

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&mut self) -> IOPFSMEN_W<'_>

Bit 5 - I/O port F clock enable during Sleep mode

impl W<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&mut self) -> DMASMEN_W<'_>

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&mut self) -> SRAMSMEN_W<'_>

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&mut self) -> TIM3SMEN_W<'_>

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn tim6smen(&mut self) -> TIM6SMEN_W<'_>

Bit 4 - TIM6 timer clock enable during Sleep mode

pub fn tim7smen(&mut self) -> TIM7SMEN_W<'_>

Bit 5 - TIM7 timer clock enable during Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3smen(&mut self) -> USART3SMEN_W<'_>

Bit 18 - USART3 clock enable during Sleep mode

pub fn usart4smen(&mut self) -> USART4SMEN_W<'_>

Bit 19 - USART4 clock enable during Sleep mode

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn cecsmen(&mut self) -> CECSMEN_W<'_>

Bit 24 - HDMI CEC clock enable during Sleep mode

pub fn ucpd1smen(&mut self) -> UCPD1SMEN_W<'_>

Bit 25 - UCPD1 clock enable during Sleep mode

pub fn ucpd2smen(&mut self) -> UCPD2SMEN_W<'_>

Bit 26 - UCPD2 clock enable during Sleep mode

pub fn dbgsmen(&mut self) -> DBGSMEN_W<'_>

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn dac1smen(&mut self) -> DAC1SMEN_W<'_>

Bit 29 - DAC1 interface clock enable during Sleep mode

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&mut self) -> TIM14SMEN_W<'_>

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim15smen(&mut self) -> TIM15SMEN_W<'_>

Bit 16 - TIM15 timer clock enable during Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&mut self) -> ADCSMEN_W<'_>

Bit 20 - ADC clock enable during Sleep mode

impl W<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn usart2sel(&mut self) -> USART2SEL_W<'_>

Bits 2:3 - USART2 clock source selection

pub fn cecsel(&mut self) -> CECSEL_W<'_>

Bit 6 - HDMI CEC clock source selection

pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<'_>

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&mut self) -> I2S2SEL_W<'_>

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<'_>

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&mut self) -> TIM1SEL_W<'_>

Bit 22 - TIM1 clock source selection

pub fn tim15sel(&mut self) -> TIM15SEL_W<'_>

Bit 24 - TIM15 clock source selection

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 30:31 - ADCs clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

pub fn lserdy(&mut self) -> LSERDY_W<'_>

Bit 1 - LSE oscillator ready

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - CSS on LSE enable

pub fn lsecssd(&mut self) -> LSECSSD_W<'_>

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - RTC domain software reset

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low-speed clock output selection

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

pub fn lsirdy(&mut self) -> LSIRDY_W<'_>

Bit 1 - LSI oscillator ready

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flags

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - Pin reset flag

pub fn pwrrstf(&mut self) -> PWRRSTF_W<'_>

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&mut self) -> FPD_LPSLP_W<'_>

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&mut self) -> FPD_LPRUN_W<'_>

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&mut self) -> FPD_STOP_W<'_>

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

pub fn pvdft(&mut self) -> PVDFT_W<'_>

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&mut self) -> PVDRT_W<'_>

Bits 4:6 - Power voltage detector rising threshold selection

impl W<u32, Reg<u32, _CR3>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&mut self) -> EWUP6_W<'_>

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&mut self) -> ULPEN_W<'_>

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line

impl W<u32, Reg<u32, _CR4>>

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&mut self) -> WP6_W<'_>

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

impl W<u32, Reg<u32, _SCR>>

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 8 - Clear standby flag

pub fn cwuf6(&mut self) -> CWUF6_W<'_>

Bit 5 - Clear wakeup flag 6

pub fn cwuf5(&mut self) -> CWUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn cwuf4(&mut self) -> CWUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn cwuf2(&mut self) -> CWUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn cwuf1(&mut self) -> CWUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Clear channel 1 global interrupt flag

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Clear channel 1 transfer complete flag

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Clear channel 1 half transfer flag

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Clear channel 1 transfer error flag

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Clear channel 2 global interrupt flag

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Clear channel 2 transfer complete flag

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Clear channel 2 half transfer flag

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Clear channel 2 transfer error flag

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Clear channel 3 global interrupt flag

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Clear channel 3 transfer complete flag

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Clear channel 3 half transfer flag

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Clear channel 3 transfer error flag

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Clear channel 4 global interrupt flag

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Clear channel 4 transfer complete flag

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Clear channel 4 half transfer flag

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Clear channel 4 transfer error flag

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Clear channel 5 global interrupt flag

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Clear channel 5 transfer complete flag

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Clear channel 5 half transfer flag

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Clear channel 5 transfer error flag

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Clear channel 6 global interrupt flag

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Clear channel 6 transfer complete flag

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Clear channel 6 half transfer flag

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Clear channel 6 transfer error flag

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Clear channel 7 global interrupt flag

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Clear channel 7 transfer complete flag

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Clear channel 7 half transfer flag

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Clear channel 7 transfer error flag

impl W<u32, Reg<u32, _DMAMUX_C0CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C1CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C2CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C3CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C4CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C5CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C6CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_RG0CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG1CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG2CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG3CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RGCFR>>

pub fn cof(&mut self) -> COF_W<'_>

Bits 0:3 - Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.

impl W<u32, Reg<u32, _DMAMUX_CFR>>

pub fn csof(&mut self) -> CSOF_W<'_>

Bits 0:6 - Clear synchronization overrun event flag

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:31 - General-purpose 32-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn crc_init(&mut self) -> CRC_INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _RPR1>>

pub fn rpif0(&mut self) -> RPIF0_W<'_>

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&mut self) -> RPIF1_W<'_>

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&mut self) -> RPIF2_W<'_>

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&mut self) -> RPIF3_W<'_>

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&mut self) -> RPIF4_W<'_>

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&mut self) -> RPIF5_W<'_>

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&mut self) -> RPIF6_W<'_>

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&mut self) -> RPIF7_W<'_>

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&mut self) -> RPIF8_W<'_>

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&mut self) -> RPIF9_W<'_>

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&mut self) -> RPIF10_W<'_>

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&mut self) -> RPIF11_W<'_>

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&mut self) -> RPIF12_W<'_>

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&mut self) -> RPIF13_W<'_>

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&mut self) -> RPIF14_W<'_>

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&mut self) -> RPIF15_W<'_>

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&mut self) -> RPIF16_W<'_>

Bit 16 - configurable event inputs x rising edge Pending bit.

pub fn rpif17(&mut self) -> RPIF17_W<'_>

Bit 17 - configurable event inputs x rising edge Pending bit.

pub fn rpif18(&mut self) -> RPIF18_W<'_>

Bit 18 - configurable event inputs x rising edge Pending bit.

impl W<u32, Reg<u32, _FPR1>>

pub fn fpif0(&mut self) -> FPIF0_W<'_>

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&mut self) -> FPIF1_W<'_>

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&mut self) -> FPIF2_W<'_>

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&mut self) -> FPIF3_W<'_>

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&mut self) -> FPIF4_W<'_>

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&mut self) -> FPIF5_W<'_>

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&mut self) -> FPIF6_W<'_>

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&mut self) -> FPIF7_W<'_>

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&mut self) -> FPIF8_W<'_>

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&mut self) -> FPIF9_W<'_>

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&mut self) -> FPIF10_W<'_>

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&mut self) -> FPIF11_W<'_>

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&mut self) -> FPIF12_W<'_>

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&mut self) -> FPIF13_W<'_>

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&mut self) -> FPIF14_W<'_>

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&mut self) -> FPIF15_W<'_>

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&mut self) -> FPIF16_W<'_>

Bit 16 - configurable event inputs x falling edge pending bit.

pub fn fpif17(&mut self) -> FPIF17_W<'_>

Bit 17 - configurable event inputs x falling edge pending bit.

pub fn fpif18(&mut self) -> FPIF18_W<'_>

Bit 18 - configurable event inputs x falling edge pending bit.

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _IMR1>>

pub fn im0(&mut self) -> IM0_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&mut self) -> IM1_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&mut self) -> IM2_W<'_>

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&mut self) -> IM3_W<'_>

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&mut self) -> IM4_W<'_>

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&mut self) -> IM5_W<'_>

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&mut self) -> IM6_W<'_>

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&mut self) -> IM7_W<'_>

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&mut self) -> IM8_W<'_>

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&mut self) -> IM9_W<'_>

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&mut self) -> IM10_W<'_>

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&mut self) -> IM11_W<'_>

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&mut self) -> IM12_W<'_>

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&mut self) -> IM13_W<'_>

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&mut self) -> IM14_W<'_>

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&mut self) -> IM15_W<'_>

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&mut self) -> IM16_W<'_>

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im17(&mut self) -> IM17_W<'_>

Bit 17 - CPU wakeup with interrupt mask on event input

pub fn im18(&mut self) -> IM18_W<'_>

Bit 18 - CPU wakeup with interrupt mask on event input

pub fn im19(&mut self) -> IM19_W<'_>

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&mut self) -> IM20_W<'_>

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&mut self) -> IM21_W<'_>

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&mut self) -> IM22_W<'_>

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&mut self) -> IM23_W<'_>

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&mut self) -> IM24_W<'_>

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&mut self) -> IM25_W<'_>

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&mut self) -> IM26_W<'_>

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im27(&mut self) -> IM27_W<'_>

Bit 27 - CPU wakeup with interrupt mask on event input

pub fn im28(&mut self) -> IM28_W<'_>

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&mut self) -> IM29_W<'_>

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&mut self) -> IM30_W<'_>

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&mut self) -> IM31_W<'_>

Bit 31 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR1>>

pub fn em0(&mut self) -> EM0_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&mut self) -> EM1_W<'_>

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&mut self) -> EM2_W<'_>

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&mut self) -> EM3_W<'_>

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&mut self) -> EM4_W<'_>

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&mut self) -> EM5_W<'_>

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&mut self) -> EM6_W<'_>

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&mut self) -> EM7_W<'_>

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&mut self) -> EM8_W<'_>

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&mut self) -> EM9_W<'_>

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&mut self) -> EM10_W<'_>

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&mut self) -> EM11_W<'_>

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&mut self) -> EM12_W<'_>

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&mut self) -> EM13_W<'_>

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&mut self) -> EM14_W<'_>

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&mut self) -> EM15_W<'_>

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&mut self) -> EM16_W<'_>

Bit 16 - CPU wakeup with event mask on event input

pub fn em17(&mut self) -> EM17_W<'_>

Bit 17 - CPU wakeup with event mask on event input

pub fn em18(&mut self) -> EM18_W<'_>

Bit 18 - CPU wakeup with event mask on event input

pub fn em19(&mut self) -> EM19_W<'_>

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&mut self) -> EM21_W<'_>

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&mut self) -> EM23_W<'_>

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&mut self) -> EM25_W<'_>

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&mut self) -> EM26_W<'_>

Bit 26 - CPU wakeup with event mask on event input

pub fn em27(&mut self) -> EM27_W<'_>

Bit 27 - CPU wakeup with event mask on event input

pub fn em28(&mut self) -> EM28_W<'_>

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&mut self) -> EM29_W<'_>

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&mut self) -> EM30_W<'_>

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&mut self) -> EM31_W<'_>

Bit 31 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _IMR2>>

pub fn im32(&mut self) -> IM32_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im33(&mut self) -> IM33_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR2>>

pub fn em32(&mut self) -> EM32_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em33(&mut self) -> EM33_W<'_>

Bit 1 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _HWCFGR7>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR6>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR5>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR4>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _HWCFGR3>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - selects input

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - selects input

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output idle state 2 (OC2 output)

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/slave mode

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/Compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/Compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 complementary output polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - BKF

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - BKDSRM

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 29 - BKBID

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - selects input

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - selects input

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - DEDT

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>

Bit 0 - Synchronous Slave mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&mut self) -> BRR_4_15_W<'_>

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&mut self) -> BRR_0_3_W<'_>

Bits 0:3 - BRR_0_3

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn udrcf(&mut self) -> UDRCF_W<'_>

Bit 13 - SPI slave underrun clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>

Bit 7 - Transmission complete before Guard time clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn txfecf(&mut self) -> TXFECF_W<'_>

Bit 5 - TXFIFO empty clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - standard selection

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn se2(&mut self) -> SE2_W<'_>

Bit 10 - I2S enable

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

impl W<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - linear prescaler

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts_4(&mut self) -> TS_4_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn ts(&mut self) -> TS_W<'_>

Bits 20:21 - Trigger selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&mut self) -> SBIF_W<'_>

Bit 13 - System Break interrupt flag

pub fn cc5if(&mut self) -> CC5IF_W<'_>

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&mut self) -> CC6IF_W<'_>

Bit 17 - Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3(&mut self) -> CCR3_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4(&mut self) -> CCR4_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bk2dsrm(&mut self) -> BK2DSRM_W<'_>

Bit 27 - Break2 Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

pub fn bk2id(&mut self) -> BK2ID_W<'_>

Bit 29 - Break2 bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&mut self) -> OCREF_CLR_W<'_>

Bit 0 - Ocref_clr source selection

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr5(&mut self) -> CCR5_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr6(&mut self) -> CCR6_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _AF2>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _ISR>>

pub fn ccrdy(&mut self) -> CCRDY_W<'_>

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&mut self) -> EOCAL_W<'_>

Bit 11 - End Of Calibration flag

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - ADC group regular overrun flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADC ready flag

impl W<u32, Reg<u32, _IER>>

pub fn ccrdyie(&mut self) -> CCRDYIE_W<'_>

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADC ready interrupt

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADC calibration

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADC voltage regulator enable

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADC group regular conversion stop

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADC group regular conversion start

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADC disable

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADC enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&mut self) -> CHSELRMOD_W<'_>

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - Auto-off mode

pub fn wait(&mut self) -> WAIT_W<'_>

Bit 14 - Wait conversion mode

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - ADC group regular overrun configuration

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:8 - ADC group regular external trigger source

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ADC data alignement

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - ADC data resolution

pub fn scandir(&mut self) -> SCANDIR_W<'_>

Bit 2 - Scan sequence direction

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - ADC DMA transfer enable

impl W<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 30:31 - ADC clock mode

pub fn lftrig(&mut self) -> LFTRIG_W<'_>

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&mut self) -> OVSE_W<'_>

Bit 0 - ADC oversampler enable on scope ADC group regular

impl W<u32, Reg<u32, _SMPR>>

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 0:2 - Sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 4:6 - Sampling time selection

pub fn smpsel(&mut self) -> SMPSEL_W<'_>

Bits 8:26 - Channel sampling time selection

impl W<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - ADC analog watchdog 1 threshold low

impl W<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:11 - ADC analog watchdog 2 threshold low

impl W<u32, Reg<u32, _CHSELR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 0:18 - Channel-x selection

impl W<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:3 - conversion of the sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 4:7 - conversion of the sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 8:11 - conversion of the sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 12:15 - conversion of the sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 16:19 - conversion of the sequence

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 20:23 - conversion of the sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 24:27 - conversion of the sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 28:31 - conversion of the sequence

impl W<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:11 - ADC analog watchdog 3 threshold high

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact(&mut self) -> CALFACT_W<'_>

Bits 0:6 - ADC calibration factor in single-ended mode

impl W<u32, Reg<u32, _CCR>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _HWCFGR6>>

pub fn chmap20(&mut self) -> CHMAP20_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap21(&mut self) -> CHMAP21_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap22(&mut self) -> CHMAP22_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap23(&mut self) -> CHMAP23_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR5>>

pub fn chmap19(&mut self) -> CHMAP19_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap18(&mut self) -> CHMAP18_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap17(&mut self) -> CHMAP17_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap16(&mut self) -> CHMAP16_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR4>>

pub fn chmap15(&mut self) -> CHMAP15_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap14(&mut self) -> CHMAP14_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap13(&mut self) -> CHMAP13_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap12(&mut self) -> CHMAP12_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR3>>

pub fn chmap11(&mut self) -> CHMAP11_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap10(&mut self) -> CHMAP10_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap9(&mut self) -> CHMAP9_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap8(&mut self) -> CHMAP8_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn chmap7(&mut self) -> CHMAP7_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap6(&mut self) -> CHMAP6_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap5(&mut self) -> CHMAP5_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap4(&mut self) -> CHMAP4_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR1>>

pub fn chmap3(&mut self) -> CHMAP3_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap2(&mut self) -> CHMAP2_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap1(&mut self) -> CHMAP1_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap0(&mut self) -> CHMAP0_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _COMP1_CSR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&mut self) -> INMSEL_W<'_>

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&mut self) -> INPSEL_W<'_>

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&mut self) -> WINMODE_W<'_>

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&mut self) -> WINOUT_W<'_>

Bit 14 - Comparator 2 output selector

pub fn polarity(&mut self) -> POLARITY_W<'_>

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&mut self) -> PWRMODE_W<'_>

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&mut self) -> BLANKSEL_W<'_>

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&mut self) -> VALUE_W<'_>

Bit 30 - Comparator 2 output status

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - COMP2_CSR register lock

impl W<u32, Reg<u32, _COMP2_CSR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&mut self) -> INMSEL_W<'_>

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&mut self) -> INPSEL_W<'_>

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&mut self) -> WINMODE_W<'_>

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&mut self) -> WINOUT_W<'_>

Bit 14 - Comparator 2 output selector

pub fn polarity(&mut self) -> POLARITY_W<'_>

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&mut self) -> PWRMODE_W<'_>

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&mut self) -> BLANKSEL_W<'_>

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&mut self) -> VALUE_W<'_>

Bit 30 - Comparator 2 output status

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - COMP2_CSR register lock

impl W<u32, Reg<u32, _VREFBUF_CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrs(&mut self) -> VRS_W<'_>

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl W<u32, Reg<u32, _VREFBUF_CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl W<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&mut self) -> I2C_PAX_FMP_W<'_>

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&mut self) -> I2C_PBX_FMP_W<'_>

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn ucpd2_strobe(&mut self) -> UCPD2_STROBE_W<'_>

Bit 10 - Strobe signal bit for UCPD2

pub fn ucpd1_strobe(&mut self) -> UCPD1_STROBE_W<'_>

Bit 9 - Strobe signal bit for UCPD1

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&mut self) -> IR_MOD_W<'_>

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&mut self) -> IR_POL_W<'_>

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - Memory mapping selection bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&mut self) -> ECC_LOCK_W<'_>

Bit 3 - ECC error lock bit

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity error flag

impl W<u32, Reg<u32, _CR1>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - TAMP1E

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 1 - TAMP2E

pub fn itamp1e(&mut self) -> ITAMP1E_W<'_>

Bit 16 - ITAMP1E

pub fn itamp3e(&mut self) -> ITAMP3E_W<'_>

Bit 18 - ITAMP3E

pub fn itamp4e(&mut self) -> ITAMP4E_W<'_>

Bit 19 - ITAMP4E

pub fn itamp5e(&mut self) -> ITAMP5E_W<'_>

Bit 20 - ITAMP5E

pub fn itamp6e(&mut self) -> ITAMP6E_W<'_>

Bit 21 - ITAMP6E

impl W<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&mut self) -> TAMP1NOER_W<'_>

Bit 0 - TAMP1NOER

pub fn tamp2noer(&mut self) -> TAMP2NOER_W<'_>

Bit 1 - TAMP2NOER

pub fn tamp1msk(&mut self) -> TAMP1MSK_W<'_>

Bit 16 - TAMP1MSK

pub fn tamp2msk(&mut self) -> TAMP2MSK_W<'_>

Bit 17 - TAMP2MSK

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 24 - TAMP1TRG

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 25 - TAMP2TRG

impl W<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 0:2 - TAMPFREQ

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 3:4 - TAMPFLT

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 7 - TAMPPUDIS

impl W<u32, Reg<u32, _IER>>

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 0 - TAMP1IE

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 1 - TAMP2IE

pub fn itamp1ie(&mut self) -> ITAMP1IE_W<'_>

Bit 16 - ITAMP1IE

pub fn itamp3ie(&mut self) -> ITAMP3IE_W<'_>

Bit 18 - ITAMP3IE

pub fn itamp4ie(&mut self) -> ITAMP4IE_W<'_>

Bit 19 - ITAMP4IE

pub fn itamp5ie(&mut self) -> ITAMP5IE_W<'_>

Bit 20 - ITAMP5IE

pub fn itamp6ie(&mut self) -> ITAMP6IE_W<'_>

Bit 21 - ITAMP6IE

impl W<u32, Reg<u32, _SCR>>

pub fn ctamp1f(&mut self) -> CTAMP1F_W<'_>

Bit 0 - CTAMP1F

pub fn ctamp2f(&mut self) -> CTAMP2F_W<'_>

Bit 1 - CTAMP2F

pub fn citamp1f(&mut self) -> CITAMP1F_W<'_>

Bit 16 - CITAMP1F

pub fn citamp3f(&mut self) -> CITAMP3F_W<'_>

Bit 18 - CITAMP3F

pub fn citamp4f(&mut self) -> CITAMP4F_W<'_>

Bit 19 - CITAMP4F

pub fn citamp5f(&mut self) -> CITAMP5F_W<'_>

Bit 20 - CITAMP5F

pub fn citamp6f(&mut self) -> CITAMP6F_W<'_>

Bit 21 - CITAMP6F

pub fn citamp7f(&mut self) -> CITAMP7F_W<'_>

Bit 22 - CITAMP7F

impl W<u32, Reg<u32, _BKP0R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP1R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP2R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP3R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP4R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CFG1>>

pub fn hbitclkdiv(&mut self) -> HBITCLKDIV_W<'_>

Bits 0:5 - HBITCLKDIV

pub fn ifrgap(&mut self) -> IFRGAP_W<'_>

Bits 6:10 - IFRGAP

pub fn transwin(&mut self) -> TRANSWIN_W<'_>

Bits 11:15 - TRANSWIN

pub fn psc_usbpdclk(&mut self) -> PSC_USBPDCLK_W<'_>

Bits 17:19 - PSC_USBPDCLK

pub fn rxordseten(&mut self) -> RXORDSETEN_W<'_>

Bits 20:28 - RXORDSETEN

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 29 - TXDMAEN

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 30 - RXDMAEN:

pub fn ucpden(&mut self) -> UCPDEN_W<'_>

Bit 31 - UCPDEN

impl W<u32, Reg<u32, _CFG2>>

pub fn rxfiltdis(&mut self) -> RXFILTDIS_W<'_>

Bit 0 - RXFILTDIS

pub fn rxfilt2n3(&mut self) -> RXFILT2N3_W<'_>

Bit 1 - RXFILT2N3

pub fn forceclk(&mut self) -> FORCECLK_W<'_>

Bit 2 - FORCECLK

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 3 - WUPEN

impl W<u32, Reg<u32, _CFG3>>

pub fn trim1_ng_ccrpd(&mut self) -> TRIM1_NG_CCRPD_W<'_>

Bits 0:3 - TRIM1_NG_CCRPD

pub fn trim1_ng_cc1a5(&mut self) -> TRIM1_NG_CC1A5_W<'_>

Bits 4:8 - TRIM1_NG_CC1A5

pub fn trim1_ng_cc3a0(&mut self) -> TRIM1_NG_CC3A0_W<'_>

Bits 9:12 - TRIM1_NG_CC3A0

pub fn trim2_ng_ccrpd(&mut self) -> TRIM2_NG_CCRPD_W<'_>

Bits 16:19 - TRIM2_NG_CCRPD

pub fn trim2_ng_cc1a5(&mut self) -> TRIM2_NG_CC1A5_W<'_>

Bits 20:24 - TRIM2_NG_CC1A5

pub fn trim2_ng_cc3a0(&mut self) -> TRIM2_NG_CC3A0_W<'_>

Bits 25:28 - TRIM2_NG_CC3A0

impl W<u32, Reg<u32, _CR>>

pub fn txmode(&mut self) -> TXMODE_W<'_>

Bits 0:1 - TXMODE

pub fn txsend(&mut self) -> TXSEND_W<'_>

Bit 2 - TXSEND

pub fn txhrst(&mut self) -> TXHRST_W<'_>

Bit 3 - TXHRST

pub fn rxmode(&mut self) -> RXMODE_W<'_>

Bit 4 - RXMODE

pub fn phyrxen(&mut self) -> PHYRXEN_W<'_>

Bit 5 - PHYRXEN

pub fn phyccsel(&mut self) -> PHYCCSEL_W<'_>

Bit 6 - PHYCCSEL

pub fn anasubmode(&mut self) -> ANASUBMODE_W<'_>

Bits 7:8 - ANASUBMODE

pub fn anamode(&mut self) -> ANAMODE_W<'_>

Bit 9 - ANAMODE

pub fn ccenable(&mut self) -> CCENABLE_W<'_>

Bits 10:11 - CCENABLE

pub fn dbatten(&mut self) -> DBATTEN_W<'_>

Bit 15 - DBATTEN

pub fn frsrxen(&mut self) -> FRSRXEN_W<'_>

Bit 16 - FRSRXEN

pub fn frstx(&mut self) -> FRSTX_W<'_>

Bit 17 - FRSTX

pub fn rdch(&mut self) -> RDCH_W<'_>

Bit 18 - RDCH

pub fn cc1tcdis(&mut self) -> CC1TCDIS_W<'_>

Bit 20 - CC1TCDIS

pub fn cc2tcdis(&mut self) -> CC2TCDIS_W<'_>

Bit 21 - CC2TCDIS

impl W<u32, Reg<u32, _IMR>>

pub fn txisie(&mut self) -> TXISIE_W<'_>

Bit 0 - TXISIE

pub fn txmsgdiscie(&mut self) -> TXMSGDISCIE_W<'_>

Bit 1 - TXMSGDISCIE

pub fn txmsgsentie(&mut self) -> TXMSGSENTIE_W<'_>

Bit 2 - TXMSGSENTIE

pub fn txmsgabtie(&mut self) -> TXMSGABTIE_W<'_>

Bit 3 - TXMSGABTIE

pub fn hrstdiscie(&mut self) -> HRSTDISCIE_W<'_>

Bit 4 - HRSTDISCIE

pub fn hrstsentie(&mut self) -> HRSTSENTIE_W<'_>

Bit 5 - HRSTSENTIE

pub fn txundie(&mut self) -> TXUNDIE_W<'_>

Bit 6 - TXUNDIE

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 8 - RXNEIE

pub fn rxorddetie(&mut self) -> RXORDDETIE_W<'_>

Bit 9 - RXORDDETIE

pub fn rxhrstdetie(&mut self) -> RXHRSTDETIE_W<'_>

Bit 10 - RXHRSTDETIE

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>

Bit 11 - RXOVRIE

pub fn rxmsgendie(&mut self) -> RXMSGENDIE_W<'_>

Bit 12 - RXMSGENDIE

pub fn typecevt1ie(&mut self) -> TYPECEVT1IE_W<'_>

Bit 14 - TYPECEVT1IE

pub fn typecevt2ie(&mut self) -> TYPECEVT2IE_W<'_>

Bit 15 - TYPECEVT2IE

pub fn frsevtie(&mut self) -> FRSEVTIE_W<'_>

Bit 20 - FRSEVTIE

impl W<u32, Reg<u32, _ICR>>

pub fn txmsgdisccf(&mut self) -> TXMSGDISCCF_W<'_>

Bit 1 - TXMSGDISCCF

pub fn txmsgsentcf(&mut self) -> TXMSGSENTCF_W<'_>

Bit 2 - TXMSGSENTCF

pub fn txmsgabtcf(&mut self) -> TXMSGABTCF_W<'_>

Bit 3 - TXMSGABTCF

pub fn hrstdisccf(&mut self) -> HRSTDISCCF_W<'_>

Bit 4 - HRSTDISCCF

pub fn hrstsentcf(&mut self) -> HRSTSENTCF_W<'_>

Bit 5 - HRSTSENTCF

pub fn txundcf(&mut self) -> TXUNDCF_W<'_>

Bit 6 - TXUNDCF

pub fn rxorddetcf(&mut self) -> RXORDDETCF_W<'_>

Bit 9 - RXORDDETCF

pub fn rxhrstdetcf(&mut self) -> RXHRSTDETCF_W<'_>

Bit 10 - RXHRSTDETCF

pub fn rxovrcf(&mut self) -> RXOVRCF_W<'_>

Bit 11 - RXOVRCF

pub fn rxmsgendcf(&mut self) -> RXMSGENDCF_W<'_>

Bit 12 - RXMSGENDCF

pub fn typecevt1cf(&mut self) -> TYPECEVT1CF_W<'_>

Bit 14 - TYPECEVT1CF

pub fn typecevt2cf(&mut self) -> TYPECEVT2CF_W<'_>

Bit 15 - TYPECEVT2CF

pub fn frsevtcf(&mut self) -> FRSEVTCF_W<'_>

Bit 20 - FRSEVTCF

impl W<u32, Reg<u32, _TX_ORDSET>>

pub fn txordset(&mut self) -> TXORDSET_W<'_>

Bits 0:19 - TXORDSET

impl W<u32, Reg<u32, _TX_PAYSZ>>

pub fn txpaysz(&mut self) -> TXPAYSZ_W<'_>

Bits 0:9 - TXPAYSZ

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TXDATA

impl W<u32, Reg<u32, _RX_PAYSZ>>

pub fn rxpaysz(&mut self) -> RXPAYSZ_W<'_>

Bits 0:9 - RXPAYSZ

impl W<u32, Reg<u32, _RX_ORDEXT1>>

pub fn rxsopx1(&mut self) -> RXSOPX1_W<'_>

Bits 0:19 - RXSOPX1

impl W<u32, Reg<u32, _RX_ORDEXT2>>

pub fn rxsopx2(&mut self) -> RXSOPX2_W<'_>

Bits 0:19 - RXSOPX2

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn rstare(&mut self) -> RSTARE_W<'_>

Bit 4 - Reset after read enable

pub fn countrst(&mut self) -> COUNTRST_W<'_>

Bit 3 - Counter reset

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&mut self) -> IN2SEL_W<'_>

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&mut self) -> IN1SEL_W<'_>

Bits 0:1 - LPTIMx Input 1 selection

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT0

pub fn dedt0(&mut self) -> DEDT0_W<'_>

Bits 16:20 - DEDT0

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:19 - BRR

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn cfg1(&mut self) -> CFG1_W<'_>

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&mut self) -> CFG2_W<'_>

Bits 4:7 - LUART hardware configuration 2

impl W<u32, Reg<u32, _HWCFGR1>>

pub fn cfg1(&mut self) -> CFG1_W<'_>

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&mut self) -> CFG2_W<'_>

Bits 4:7 - LUART hardware configuration 2

pub fn cfg3(&mut self) -> CFG3_W<'_>

Bits 8:11 - LUART hardware configuration 1

pub fn cfg4(&mut self) -> CFG4_W<'_>

Bits 12:15 - LUART hardware configuration 2

pub fn cfg5(&mut self) -> CFG5_W<'_>

Bits 16:19 - LUART hardware configuration 2

pub fn cfg6(&mut self) -> CFG6_W<'_>

Bits 20:23 - LUART hardware configuration 2

pub fn cfg7(&mut self) -> CFG7_W<'_>

Bits 24:27 - LUART hardware configuration 2

pub fn cfg8(&mut self) -> CFG8_W<'_>

Bits 28:31 - LUART hardware configuration 2

impl W<u32, Reg<u32, _CEC_CR>>

pub fn cecen(&mut self) -> CECEN_W<'_>

Bit 0 - CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.

pub fn txsom(&mut self) -> TXSOM_W<'_>

Bit 1 - Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception

pub fn txeom(&mut self) -> TXEOM_W<'_>

Bit 2 - Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message)

impl W<u32, Reg<u32, _CEC_CFGR>>

pub fn sft(&mut self) -> SFT_W<'_>

Bits 0:2 - Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods

pub fn rxtol(&mut self) -> RXTOL_W<'_>

Bit 3 - Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall

pub fn brestp(&mut self) -> BRESTP_W<'_>

Bit 4 - Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software.

pub fn bregen(&mut self) -> BREGEN_W<'_>

Bit 5 - Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0

pub fn lbpegen(&mut self) -> LBPEGEN_W<'_>

Bit 6 - Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0

pub fn brdnogen(&mut self) -> BRDNOGEN_W<'_>

Bit 7 - Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software.

pub fn sftopt(&mut self) -> SFTOPT_W<'_>

Bit 8 - SFT Option Bit The SFTOPT bit is set and cleared by software.

pub fn oar(&mut self) -> OAR_W<'_>

Bits 16:30 - Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.

pub fn lstn(&mut self) -> LSTN_W<'_>

Bit 31 - Listen mode LSTN bit is set and cleared by software.

impl W<u32, Reg<u32, _CEC_TXDR>>

pub fn txd(&mut self) -> TXD_W<'_>

Bits 0:7 - Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1

impl W<u32, Reg<u32, _CEC_ISR>>

pub fn rxbr(&mut self) -> RXBR_W<'_>

Bit 0 - Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1.

pub fn rxend(&mut self) -> RXEND_W<'_>

Bit 1 - End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1.

pub fn rxovr(&mut self) -> RXOVR_W<'_>

Bit 2 - Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1.

pub fn bre(&mut self) -> BRE_W<'_>

Bit 3 - Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1.

pub fn sbpe(&mut self) -> SBPE_W<'_>

Bit 4 - Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1.

pub fn lbpe(&mut self) -> LBPE_W<'_>

Bit 5 - Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1.

pub fn rxacke(&mut self) -> RXACKE_W<'_>

Bit 6 - Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1.

pub fn arblst(&mut self) -> ARBLST_W<'_>

Bit 7 - Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1.

pub fn txbr(&mut self) -> TXBR_W<'_>

Bit 8 - Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1.

pub fn txend(&mut self) -> TXEND_W<'_>

Bit 9 - End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1.

pub fn txudr(&mut self) -> TXUDR_W<'_>

Bit 10 - Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 11 - Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1.

pub fn txacke(&mut self) -> TXACKE_W<'_>

Bit 12 - Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1.

impl W<u32, Reg<u32, _CEC_IER>>

pub fn rxbrie(&mut self) -> RXBRIE_W<'_>

Bit 0 - Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software.

pub fn rxendie(&mut self) -> RXENDIE_W<'_>

Bit 1 - End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software.

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>

Bit 2 - Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software.

pub fn breie(&mut self) -> BREIE_W<'_>

Bit 3 - Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software.

pub fn sbpeie(&mut self) -> SBPEIE_W<'_>

Bit 4 - Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software.

pub fn lbpeie(&mut self) -> LBPEIE_W<'_>

Bit 5 - Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software.

pub fn rxackie(&mut self) -> RXACKIE_W<'_>

Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software.

pub fn arblstie(&mut self) -> ARBLSTIE_W<'_>

Bit 7 - Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software.

pub fn txbrie(&mut self) -> TXBRIE_W<'_>

Bit 8 - Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software.

pub fn txendie(&mut self) -> TXENDIE_W<'_>

Bit 9 - Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software.

pub fn txudrie(&mut self) -> TXUDRIE_W<'_>

Bit 10 - Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software.

pub fn txerrie(&mut self) -> TXERRIE_W<'_>

Bit 11 - Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software.

pub fn txackie(&mut self) -> TXACKIE_W<'_>

Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software.

impl W<u32, Reg<u32, _DAC_CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 1 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 2:5 - DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable This bit is set and cleared by software.

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.

pub fn cen1(&mut self) -> CEN1_W<'_>

Bit 14 - DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 17 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 18:21 - DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable This bit is set and cleared by software.

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.

pub fn cen2(&mut self) -> CEN2_W<'_>

Bit 30 - DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

impl W<u32, Reg<u32, _DAC_SWTRGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.

impl W<u32, Reg<u32, _DAC_DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl W<u32, Reg<u32, _DAC_DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl W<u32, Reg<u32, _DAC_DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

impl W<u32, Reg<u32, _DAC_DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

impl W<u32, Reg<u32, _DAC_CCR>>

pub fn otrim1(&mut self) -> OTRIM1_W<'_>

Bits 0:4 - DAC Channel 1 offset trimming value

pub fn otrim2(&mut self) -> OTRIM2_W<'_>

Bits 16:20 - DAC Channel 2 offset trimming value

impl W<u32, Reg<u32, _DAC_MCR>>

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 0:2 - DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 16:18 - DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode

impl W<u32, Reg<u32, _DAC_SHSR1>>

pub fn tsample1(&mut self) -> TSAMPLE1_W<'_>

Bits 0:9 - DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.

impl W<u32, Reg<u32, _DAC_SHSR2>>

pub fn tsample2(&mut self) -> TSAMPLE2_W<'_>

Bits 0:9 - DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.

impl W<u32, Reg<u32, _DAC_SHHR>>

pub fn thold1(&mut self) -> THOLD1_W<'_>

Bits 0:9 - DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI

pub fn thold2(&mut self) -> THOLD2_W<'_>

Bits 16:25 - DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI

impl W<u32, Reg<u32, _DAC_SHRR>>

pub fn trefresh1(&mut self) -> TREFRESH1_W<'_>

Bits 0:7 - DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

pub fn trefresh2(&mut self) -> TREFRESH2_W<'_>

Bits 16:23 - DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

impl W<u32, Reg<u32, _IP_HWCFGR0>>

pub fn dual(&mut self) -> DUAL_W<'_>

Bits 0:3 - Dual DAC capability

pub fn lfsr(&mut self) -> LFSR_W<'_>

Bits 4:7 - Pseudonoise wave generation capability

pub fn triangle(&mut self) -> TRIANGLE_W<'_>

Bits 8:11 - Triangle wave generation capability

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:15 - Sample and hold mode capability

pub fn or_cfg(&mut self) -> OR_CFG_W<'_>

Bits 16:23 - option register bit width

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&mut self) -> OA1_0_W<'_>

Bit 0 - Interface address

pub fn oa1_7_1(&mut self) -> OA1_7_1_W<'_>

Bits 1:7 - Interface address

pub fn oa1_8_9(&mut self) -> OA1_8_9_W<'_>

Bits 8:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _ICSR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - WUCKSEL

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - TSEDGE

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - REFCKON

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - BYPSHAD

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - FMT

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - ALRAE

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - ALRBE

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - WUTE

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - TSE

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - ALRAIE

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - ALRBIE

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - WUTIE

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - TSIE

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - ADD1H

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - SUB1H

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - BKP

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - COSEL

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - POL

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - OSEL

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - COE

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - ITSE

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 25 - TAMPTS

pub fn tampoe(&mut self) -> TAMPOE_W<'_>

Bit 26 - TAMPOE

pub fn tampalrm_pu(&mut self) -> TAMPALRM_PU_W<'_>

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&mut self) -> TAMPALRM_TYPE_W<'_>

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&mut self) -> OUT2EN_W<'_>

Bit 31 - OUT2EN

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _SCR>>

pub fn calraf(&mut self) -> CALRAF_W<'_>

Bit 0 - CALRAF

pub fn calrbf(&mut self) -> CALRBF_W<'_>

Bit 1 - CALRBF

pub fn cwutf(&mut self) -> CWUTF_W<'_>

Bit 2 - CWUTF

pub fn ctsf(&mut self) -> CTSF_W<'_>

Bit 3 - CTSF

pub fn ctsovf(&mut self) -> CTSOVF_W<'_>

Bit 4 - CTSOVF

pub fn citsf(&mut self) -> CITSF_W<'_>

Bit 5 - CITSF

impl W<u32, Reg<u32, _HWCFGR>>

pub fn alarmb(&mut self) -> ALARMB_W<'_>

Bits 0:3 - ALARMB

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bits 4:7 - WAKEUP

pub fn smooth_calib(&mut self) -> SMOOTH_CALIB_W<'_>

Bits 8:11 - SMOOTH_CALIB

pub fn timestamp(&mut self) -> TIMESTAMP_W<'_>

Bits 12:15 - TIMESTAMP

pub fn optionreg_out(&mut self) -> OPTIONREG_OUT_W<'_>

Bits 16:23 - OPTIONREG_OUT

pub fn trust_zone(&mut self) -> TRUST_ZONE_W<'_>

Bits 24:27 - TRUST_ZONE

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&mut self) -> ICPCS_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _TISEL>>

pub fn tisel(&mut self) -> TISEL_W<'_>

Bits 0:3 - TI1[0] to TI1[15] input selection

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&mut self) -> TS_4_3_W<'_>

Bits 20:21 - Trigger selection

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&mut self) -> CNT_L_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&mut self) -> ARR_L_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&mut self) -> CCR1_L_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&mut self) -> CCR2_H_W<'_>

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&mut self) -> CCR2_L_W<'_>

Bits 0:15 - Low Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&mut self) -> CCR3_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&mut self) -> CCR3_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&mut self) -> CCR4_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&mut self) -> CCR4_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&mut self) -> IOCREF_CLR_W<'_>

Bit 0 - IOCREF_CLR

impl W<u32, Reg<u32, _AF1>>

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:17 - External trigger source selection

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - TI1SEL

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - TI2SEL

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _HWCFGR>>

pub fn window(&mut self) -> WINDOW_W<'_>

Bits 0:3 - Support of Window function

pub fn pr_default(&mut self) -> PR_DEFAULT_W<'_>

Bits 4:7 - Prescaler default value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 11:13 - Timer base

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 16 - Flash User area empty

pub fn dbg_swen(&mut self) -> DBG_SWEN_W<'_>

Bit 18 - Debug access software enable

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&mut self) -> BSY_W<'_>

Bit 16 - Busy

pub fn cfgbsy(&mut self) -> CFGBSY_W<'_>

Bit 18 - Programming or erase configuration busy.

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:8 - Page number

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn sec_prot(&mut self) -> SEC_PROT_W<'_>

Bit 28 - Securable memory area protection enable

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn boren(&mut self) -> BOREN_W<'_>

Bit 8 - BOR reset Level

pub fn borf_lev(&mut self) -> BORF_LEV_W<'_>

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&mut self) -> BORR_LEV_W<'_>

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&mut self) -> NRSTS_HDW_W<'_>

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&mut self) -> RAM_PARITY_CHECK_W<'_>

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&mut self) -> NBOOT_SEL_W<'_>

Bit 24 - nBOOT_SEL

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 25 - Boot configuration

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&mut self) -> NRST_MODE_W<'_>

Bits 27:28 - NRST_MODE

pub fn irhen(&mut self) -> IRHEN_W<'_>

Bit 29 - Internal reset holder enable bit

impl W<u32, Reg<u32, _CR>>

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

impl W<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_timer2_stop(&mut self) -> DBG_TIMER2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_timer6_stop(&mut self) -> DBG_TIMER6_STOP_W<'_>

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 30 - Clocking of LPTIMER2 counter when the core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - Clocking of LPTIMER1 counter when the core is halted

impl W<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - DBG_TIM1_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 16 - DBG_TIM15_STOP

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - DBG_TIM17_STOP

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI16 clock enable

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&mut self) -> HSIRDY_W<'_>

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&mut self) -> HSIDIV_W<'_>

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hserdy(&mut self) -> HSERDY_W<'_>

Bit 17 - HSE clock ready flag

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

pub fn pllrdy(&mut self) -> PLLRDY_W<'_>

Bit 25 - PLL clock ready flag

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 8:14 - HSI16 clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn ppre(&mut self) -> PPRE_W<'_>

Bits 12:14 - APB prescaler

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 8:11 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:2 - System clock switch

impl W<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - PLL input clock source

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl W<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&mut self) -> PLLSYSRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn pllsysrdyc(&mut self) -> PLLSYSRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&mut self) -> DMARST_W<'_>

Bit 0 - DMA1 reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - FLITF reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

pub fn aesrst(&mut self) -> AESRST_W<'_>

Bit 16 - AES hardware accelerator reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 18 - Random number generator reset

impl W<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 0 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 1 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 2 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 3 - I/O port D reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 5 - I/O port F reset

impl W<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 timer reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6 timer reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7 timer reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn usart4rst(&mut self) -> USART4RST_W<'_>

Bit 19 - USART4 reset

pub fn lpuart1rst(&mut self) -> LPUART1RST_W<'_>

Bit 20 - LPUART1 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn cecrst(&mut self) -> CECRST_W<'_>

Bit 24 - HDMI CEC reset

pub fn ucpd1rst(&mut self) -> UCPD1RST_W<'_>

Bit 25 - UCPD1 reset

pub fn ucpd2rst(&mut self) -> UCPD2RST_W<'_>

Bit 26 - UCPD2 reset

pub fn dbgrst(&mut self) -> DBGRST_W<'_>

Bit 27 - Debug support reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dac1rst(&mut self) -> DAC1RST_W<'_>

Bit 29 - DAC1 interface reset

pub fn lptim2rst(&mut self) -> LPTIM2RST_W<'_>

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>

Bit 31 - Low Power Timer 1 reset

impl W<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 15 - TIM14 timer reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 20 - ADC reset

impl W<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 0 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 1 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 2 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 3 - I/O port D clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 5 - I/O port F clock enable

impl W<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

pub fn aesen(&mut self) -> AESEN_W<'_>

Bit 16 - AES hardware accelerator

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 18 - Random number generator clock enable

impl W<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6 timer clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - RTC APB clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - WWDG clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3 clock enable

pub fn usart4en(&mut self) -> USART4EN_W<'_>

Bit 19 - USART4 clock enable

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn cecen(&mut self) -> CECEN_W<'_>

Bit 24 - HDMI CEC clock enable

pub fn ucpd1en(&mut self) -> UCPD1EN_W<'_>

Bit 25 - UCPD1 clock enable

pub fn ucpd2en(&mut self) -> UCPD2EN_W<'_>

Bit 26 - UCPD2 clock enable

pub fn dbgen(&mut self) -> DBGEN_W<'_>

Bit 27 - Debug support clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dac1en(&mut self) -> DAC1EN_W<'_>

Bit 29 - DAC1 interface clock enable

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - LPTIM1 clock enable

impl W<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 15 - TIM14 timer clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM16 timer clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 20 - ADC clock enable

impl W<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&mut self) -> IOPASMEN_W<'_>

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&mut self) -> IOPBSMEN_W<'_>

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&mut self) -> IOPCSMEN_W<'_>

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&mut self) -> IOPDSMEN_W<'_>

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&mut self) -> IOPFSMEN_W<'_>

Bit 5 - I/O port F clock enable during Sleep mode

impl W<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&mut self) -> DMASMEN_W<'_>

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&mut self) -> SRAMSMEN_W<'_>

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CRC clock enable during Sleep mode

pub fn aessmen(&mut self) -> AESSMEN_W<'_>

Bit 16 - AES hardware accelerator clock enable during Sleep mode

pub fn rngsmen(&mut self) -> RNGSMEN_W<'_>

Bit 18 - Random number generator clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&mut self) -> TIM3SMEN_W<'_>

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn tim6smen(&mut self) -> TIM6SMEN_W<'_>

Bit 4 - TIM6 timer clock enable during Sleep mode

pub fn tim7smen(&mut self) -> TIM7SMEN_W<'_>

Bit 5 - TIM7 timer clock enable during Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3smen(&mut self) -> USART3SMEN_W<'_>

Bit 18 - USART3 clock enable during Sleep mode

pub fn usart4smen(&mut self) -> USART4SMEN_W<'_>

Bit 19 - USART4 clock enable during Sleep mode

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clock enable during Sleep mode

pub fn cecsmen(&mut self) -> CECSMEN_W<'_>

Bit 24 - HDMI CEC clock enable during Sleep mode

pub fn ucpd1smen(&mut self) -> UCPD1SMEN_W<'_>

Bit 25 - UCPD1 clock enable during Sleep mode

pub fn ucpd2smen(&mut self) -> UCPD2SMEN_W<'_>

Bit 26 - UCPD2 clock enable during Sleep mode

pub fn dbgsmen(&mut self) -> DBGSMEN_W<'_>

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clock enable during Sleep mode

pub fn dac1smen(&mut self) -> DAC1SMEN_W<'_>

Bit 29 - DAC1 interface clock enable during Sleep mode

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl W<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&mut self) -> TIM14SMEN_W<'_>

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim15smen(&mut self) -> TIM15SMEN_W<'_>

Bit 16 - TIM15 timer clock enable during Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&mut self) -> ADCSMEN_W<'_>

Bit 20 - ADC clock enable during Sleep mode

impl W<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn usart2sel(&mut self) -> USART2SEL_W<'_>

Bits 2:3 - USART2 clock source selection

pub fn cecsel(&mut self) -> CECSEL_W<'_>

Bit 6 - HDMI CEC clock source selection

pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<'_>

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&mut self) -> I2S2SEL_W<'_>

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<'_>

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&mut self) -> TIM1SEL_W<'_>

Bit 22 - TIM1 clock source selection

pub fn tim15sel(&mut self) -> TIM15SEL_W<'_>

Bit 24 - TIM15 clock source selection

pub fn rngsel(&mut self) -> RNGSEL_W<'_>

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&mut self) -> RNGDIV_W<'_>

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 30:31 - ADCs clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

pub fn lserdy(&mut self) -> LSERDY_W<'_>

Bit 1 - LSE oscillator ready

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - CSS on LSE enable

pub fn lsecssd(&mut self) -> LSECSSD_W<'_>

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - RTC domain software reset

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low-speed clock output selection

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

pub fn lsirdy(&mut self) -> LSIRDY_W<'_>

Bit 1 - LSI oscillator ready

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flags

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - Pin reset flag

pub fn pwrrstf(&mut self) -> PWRRSTF_W<'_>

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&mut self) -> FPD_LPSLP_W<'_>

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&mut self) -> FPD_LPRUN_W<'_>

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&mut self) -> FPD_STOP_W<'_>

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

pub fn pvdft(&mut self) -> PVDFT_W<'_>

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&mut self) -> PVDRT_W<'_>

Bits 4:6 - Power voltage detector rising threshold selection

impl W<u32, Reg<u32, _CR3>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&mut self) -> EWUP6_W<'_>

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&mut self) -> ULPEN_W<'_>

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line

impl W<u32, Reg<u32, _CR4>>

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&mut self) -> WP6_W<'_>

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

impl W<u32, Reg<u32, _SCR>>

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 8 - Clear standby flag

pub fn cwuf6(&mut self) -> CWUF6_W<'_>

Bit 5 - Clear wakeup flag 6

pub fn cwuf5(&mut self) -> CWUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn cwuf4(&mut self) -> CWUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn cwuf2(&mut self) -> CWUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn cwuf1(&mut self) -> CWUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Clear channel 1 global interrupt flag

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Clear channel 1 transfer complete flag

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Clear channel 1 half transfer flag

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Clear channel 1 transfer error flag

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Clear channel 2 global interrupt flag

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Clear channel 2 transfer complete flag

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Clear channel 2 half transfer flag

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Clear channel 2 transfer error flag

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Clear channel 3 global interrupt flag

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Clear channel 3 transfer complete flag

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Clear channel 3 half transfer flag

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Clear channel 3 transfer error flag

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Clear channel 4 global interrupt flag

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Clear channel 4 transfer complete flag

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Clear channel 4 half transfer flag

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Clear channel 4 transfer error flag

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Clear channel 5 global interrupt flag

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Clear channel 5 transfer complete flag

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Clear channel 5 half transfer flag

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Clear channel 5 transfer error flag

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Clear channel 6 global interrupt flag

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Clear channel 6 transfer complete flag

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Clear channel 6 half transfer flag

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Clear channel 6 transfer error flag

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Clear channel 7 global interrupt flag

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Clear channel 7 transfer complete flag

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Clear channel 7 half transfer flag

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Clear channel 7 transfer error flag

impl W<u32, Reg<u32, _DMAMUX_C0CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C1CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C2CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C3CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C4CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C5CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_C6CR>>

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - Input DMA request line selected

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event generation enable/disable

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - Synchronization input selected

impl W<u32, Reg<u32, _DMAMUX_RG0CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG1CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG2CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RG3CR>>

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - DMA request trigger input selected

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl W<u32, Reg<u32, _DMAMUX_RGCFR>>

pub fn cof(&mut self) -> COF_W<'_>

Bits 0:3 - Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.

impl W<u32, Reg<u32, _DMAMUX_CFR>>

pub fn csof(&mut self) -> CSOF_W<'_>

Bits 0:6 - Clear synchronization overrun event flag

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _CR>>

pub fn npblb(&mut self) -> NPBLB_W<'_>

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&mut self) -> KEYSIZE_W<'_>

Bit 18 - Key size selection

pub fn chmod2(&mut self) -> CHMOD2_W<'_>

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&mut self) -> GCMPH_W<'_>

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&mut self) -> CHMOD10_W<'_>

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&mut self) -> MODE_W<'_>

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&mut self) -> AES_KEYR4_W<'_>

Bits 0:31 - AES key register (MSB key [159:128])

impl W<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&mut self) -> AES_KEYR5_W<'_>

Bits 0:31 - AES key register (MSB key [191:160])

impl W<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&mut self) -> AES_KEYR6_W<'_>

Bits 0:31 - AES key register (MSB key [223:192])

impl W<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&mut self) -> AES_KEYR7_W<'_>

Bits 0:31 - AES key register (MSB key [255:224])

impl W<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&mut self) -> AES_SUSP0R_W<'_>

Bits 0:31 - AES suspend register 0

impl W<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&mut self) -> AES_SUSP1R_W<'_>

Bits 0:31 - AES suspend register 1

impl W<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&mut self) -> AES_SUSP2R_W<'_>

Bits 0:31 - AES suspend register 2

impl W<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&mut self) -> AES_SUSP3R_W<'_>

Bits 0:31 - AES suspend register 3

impl W<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&mut self) -> AES_SUSP4R_W<'_>

Bits 0:31 - AES suspend register 4

impl W<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&mut self) -> AES_SUSP5R_W<'_>

Bits 0:31 - AES suspend register 5

impl W<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&mut self) -> AES_SUSP6R_W<'_>

Bits 0:31 - AES suspend register 6

impl W<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&mut self) -> AES_SUSP7R_W<'_>

Bits 0:31 - AES suspend register 7

impl W<u32, Reg<u32, _CR>>

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn ced(&mut self) -> CED_W<'_>

Bit 5 - Clock error detection

pub fn byp(&mut self) -> BYP_W<'_>

Bit 6 - Bypass mode enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:31 - General-purpose 32-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn crc_init(&mut self) -> CRC_INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _RPR1>>

pub fn rpif0(&mut self) -> RPIF0_W<'_>

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&mut self) -> RPIF1_W<'_>

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&mut self) -> RPIF2_W<'_>

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&mut self) -> RPIF3_W<'_>

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&mut self) -> RPIF4_W<'_>

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&mut self) -> RPIF5_W<'_>

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&mut self) -> RPIF6_W<'_>

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&mut self) -> RPIF7_W<'_>

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&mut self) -> RPIF8_W<'_>

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&mut self) -> RPIF9_W<'_>

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&mut self) -> RPIF10_W<'_>

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&mut self) -> RPIF11_W<'_>

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&mut self) -> RPIF12_W<'_>

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&mut self) -> RPIF13_W<'_>

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&mut self) -> RPIF14_W<'_>

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&mut self) -> RPIF15_W<'_>

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&mut self) -> RPIF16_W<'_>

Bit 16 - configurable event inputs x rising edge Pending bit.

pub fn rpif17(&mut self) -> RPIF17_W<'_>

Bit 17 - configurable event inputs x rising edge Pending bit.

pub fn rpif18(&mut self) -> RPIF18_W<'_>

Bit 18 - configurable event inputs x rising edge Pending bit.

impl W<u32, Reg<u32, _FPR1>>

pub fn fpif0(&mut self) -> FPIF0_W<'_>

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&mut self) -> FPIF1_W<'_>

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&mut self) -> FPIF2_W<'_>

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&mut self) -> FPIF3_W<'_>

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&mut self) -> FPIF4_W<'_>

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&mut self) -> FPIF5_W<'_>

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&mut self) -> FPIF6_W<'_>

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&mut self) -> FPIF7_W<'_>

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&mut self) -> FPIF8_W<'_>

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&mut self) -> FPIF9_W<'_>

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&mut self) -> FPIF10_W<'_>

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&mut self) -> FPIF11_W<'_>

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&mut self) -> FPIF12_W<'_>

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&mut self) -> FPIF13_W<'_>

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&mut self) -> FPIF14_W<'_>

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&mut self) -> FPIF15_W<'_>

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&mut self) -> FPIF16_W<'_>

Bit 16 - configurable event inputs x falling edge pending bit.

pub fn fpif17(&mut self) -> FPIF17_W<'_>

Bit 17 - configurable event inputs x falling edge pending bit.

pub fn fpif18(&mut self) -> FPIF18_W<'_>

Bit 18 - configurable event inputs x falling edge pending bit.

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&mut self) -> EXTI0_7_W<'_>

Bits 0:7 - GPIO port selection

pub fn exti8_15(&mut self) -> EXTI8_15_W<'_>

Bits 8:15 - GPIO port selection

pub fn exti16_23(&mut self) -> EXTI16_23_W<'_>

Bits 16:23 - GPIO port selection

pub fn exti24_31(&mut self) -> EXTI24_31_W<'_>

Bits 24:31 - GPIO port selection

impl W<u32, Reg<u32, _IMR1>>

pub fn im0(&mut self) -> IM0_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&mut self) -> IM1_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&mut self) -> IM2_W<'_>

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&mut self) -> IM3_W<'_>

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&mut self) -> IM4_W<'_>

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&mut self) -> IM5_W<'_>

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&mut self) -> IM6_W<'_>

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&mut self) -> IM7_W<'_>

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&mut self) -> IM8_W<'_>

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&mut self) -> IM9_W<'_>

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&mut self) -> IM10_W<'_>

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&mut self) -> IM11_W<'_>

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&mut self) -> IM12_W<'_>

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&mut self) -> IM13_W<'_>

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&mut self) -> IM14_W<'_>

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&mut self) -> IM15_W<'_>

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&mut self) -> IM16_W<'_>

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im17(&mut self) -> IM17_W<'_>

Bit 17 - CPU wakeup with interrupt mask on event input

pub fn im18(&mut self) -> IM18_W<'_>

Bit 18 - CPU wakeup with interrupt mask on event input

pub fn im19(&mut self) -> IM19_W<'_>

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&mut self) -> IM20_W<'_>

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&mut self) -> IM21_W<'_>

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&mut self) -> IM22_W<'_>

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&mut self) -> IM23_W<'_>

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&mut self) -> IM24_W<'_>

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&mut self) -> IM25_W<'_>

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&mut self) -> IM26_W<'_>

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im27(&mut self) -> IM27_W<'_>

Bit 27 - CPU wakeup with interrupt mask on event input

pub fn im28(&mut self) -> IM28_W<'_>

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&mut self) -> IM29_W<'_>

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&mut self) -> IM30_W<'_>

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&mut self) -> IM31_W<'_>

Bit 31 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR1>>

pub fn em0(&mut self) -> EM0_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&mut self) -> EM1_W<'_>

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&mut self) -> EM2_W<'_>

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&mut self) -> EM3_W<'_>

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&mut self) -> EM4_W<'_>

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&mut self) -> EM5_W<'_>

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&mut self) -> EM6_W<'_>

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&mut self) -> EM7_W<'_>

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&mut self) -> EM8_W<'_>

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&mut self) -> EM9_W<'_>

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&mut self) -> EM10_W<'_>

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&mut self) -> EM11_W<'_>

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&mut self) -> EM12_W<'_>

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&mut self) -> EM13_W<'_>

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&mut self) -> EM14_W<'_>

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&mut self) -> EM15_W<'_>

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&mut self) -> EM16_W<'_>

Bit 16 - CPU wakeup with event mask on event input

pub fn em17(&mut self) -> EM17_W<'_>

Bit 17 - CPU wakeup with event mask on event input

pub fn em18(&mut self) -> EM18_W<'_>

Bit 18 - CPU wakeup with event mask on event input

pub fn em19(&mut self) -> EM19_W<'_>

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&mut self) -> EM21_W<'_>

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&mut self) -> EM23_W<'_>

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&mut self) -> EM25_W<'_>

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&mut self) -> EM26_W<'_>

Bit 26 - CPU wakeup with event mask on event input

pub fn em27(&mut self) -> EM27_W<'_>

Bit 27 - CPU wakeup with event mask on event input

pub fn em28(&mut self) -> EM28_W<'_>

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&mut self) -> EM29_W<'_>

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&mut self) -> EM30_W<'_>

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&mut self) -> EM31_W<'_>

Bit 31 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _IMR2>>

pub fn im32(&mut self) -> IM32_W<'_>

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im33(&mut self) -> IM33_W<'_>

Bit 1 - CPU wakeup with interrupt mask on event input

impl W<u32, Reg<u32, _EMR2>>

pub fn em32(&mut self) -> EM32_W<'_>

Bit 0 - CPU wakeup with event mask on event input

pub fn em33(&mut self) -> EM33_W<'_>

Bit 1 - CPU wakeup with event mask on event input

impl W<u32, Reg<u32, _HWCFGR7>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR6>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR5>>

pub fn cpuevent(&mut self) -> CPUEVENT_W<'_>

Bits 0:31 - HW configuration CPU event generation

impl W<u32, Reg<u32, _HWCFGR4>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _HWCFGR3>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn event_trg(&mut self) -> EVENT_TRG_W<'_>

Bits 0:31 - HW configuration event trigger type

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - selects input

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - DEDT

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>

Bit 0 - Synchronous Slave mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&mut self) -> BRR_4_15_W<'_>

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&mut self) -> BRR_0_3_W<'_>

Bits 0:3 - BRR_0_3

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn udrcf(&mut self) -> UDRCF_W<'_>

Bit 13 - SPI slave underrun clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>

Bit 7 - Transmission complete before Guard time clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn txfecf(&mut self) -> TXFECF_W<'_>

Bit 5 - TXFIFO empty clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - standard selection

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn se2(&mut self) -> SE2_W<'_>

Bit 10 - I2S enable

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

impl W<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - linear prescaler

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts_4(&mut self) -> TS_4_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn ts(&mut self) -> TS_W<'_>

Bits 20:21 - Trigger selection

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&mut self) -> SBIF_W<'_>

Bit 13 - System Break interrupt flag

pub fn cc5if(&mut self) -> CC5IF_W<'_>

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&mut self) -> CC6IF_W<'_>

Bit 17 - Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3(&mut self) -> CCR3_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4(&mut self) -> CCR4_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

pub fn bkdsrm(&mut self) -> BKDSRM_W<'_>

Bit 26 - Break Disarm

pub fn bk2dsrm(&mut self) -> BK2DSRM_W<'_>

Bit 27 - Break2 Disarm

pub fn bkbid(&mut self) -> BKBID_W<'_>

Bit 28 - Break Bidirectional

pub fn bk2id(&mut self) -> BK2ID_W<'_>

Bit 29 - Break2 bidirectional

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&mut self) -> OCREF_CLR_W<'_>

Bit 0 - Ocref_clr source selection

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr5(&mut self) -> CCR5_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr6(&mut self) -> CCR6_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _AF2>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _ISR>>

pub fn ccrdy(&mut self) -> CCRDY_W<'_>

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&mut self) -> EOCAL_W<'_>

Bit 11 - End Of Calibration flag

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - ADC group regular overrun flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADC ready flag

impl W<u32, Reg<u32, _IER>>

pub fn ccrdyie(&mut self) -> CCRDYIE_W<'_>

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADC ready interrupt

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADC calibration

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADC voltage regulator enable

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADC group regular conversion stop

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADC group regular conversion start

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADC disable

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADC enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&mut self) -> CHSELRMOD_W<'_>

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - Auto-off mode

pub fn wait(&mut self) -> WAIT_W<'_>

Bit 14 - Wait conversion mode

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - ADC group regular overrun configuration

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:8 - ADC group regular external trigger source

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ADC data alignement

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - ADC data resolution

pub fn scandir(&mut self) -> SCANDIR_W<'_>

Bit 2 - Scan sequence direction

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - ADC DMA transfer enable

impl W<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 30:31 - ADC clock mode

pub fn lftrig(&mut self) -> LFTRIG_W<'_>

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&mut self) -> OVSE_W<'_>

Bit 0 - ADC oversampler enable on scope ADC group regular

impl W<u32, Reg<u32, _SMPR>>

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 0:2 - Sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 4:6 - Sampling time selection

pub fn smpsel(&mut self) -> SMPSEL_W<'_>

Bits 8:26 - Channel sampling time selection

impl W<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - ADC analog watchdog 1 threshold low

impl W<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:11 - ADC analog watchdog 2 threshold low

impl W<u32, Reg<u32, _CHSELR>>

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 0:18 - Channel-x selection

impl W<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:3 - conversion of the sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 4:7 - conversion of the sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 8:11 - conversion of the sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 12:15 - conversion of the sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 16:19 - conversion of the sequence

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 20:23 - conversion of the sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 24:27 - conversion of the sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 28:31 - conversion of the sequence

impl W<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:11 - ADC analog watchdog 3 threshold high

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact(&mut self) -> CALFACT_W<'_>

Bits 0:6 - ADC calibration factor in single-ended mode

impl W<u32, Reg<u32, _CCR>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _HWCFGR6>>

pub fn chmap20(&mut self) -> CHMAP20_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap21(&mut self) -> CHMAP21_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap22(&mut self) -> CHMAP22_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap23(&mut self) -> CHMAP23_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR5>>

pub fn chmap19(&mut self) -> CHMAP19_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap18(&mut self) -> CHMAP18_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap17(&mut self) -> CHMAP17_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap16(&mut self) -> CHMAP16_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR4>>

pub fn chmap15(&mut self) -> CHMAP15_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap14(&mut self) -> CHMAP14_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap13(&mut self) -> CHMAP13_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap12(&mut self) -> CHMAP12_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR3>>

pub fn chmap11(&mut self) -> CHMAP11_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap10(&mut self) -> CHMAP10_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap9(&mut self) -> CHMAP9_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap8(&mut self) -> CHMAP8_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn chmap7(&mut self) -> CHMAP7_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap6(&mut self) -> CHMAP6_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap5(&mut self) -> CHMAP5_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap4(&mut self) -> CHMAP4_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _HWCFGR1>>

pub fn chmap3(&mut self) -> CHMAP3_W<'_>

Bits 0:4 - Input channel mapping

pub fn chmap2(&mut self) -> CHMAP2_W<'_>

Bits 8:12 - Input channel mapping

pub fn chmap1(&mut self) -> CHMAP1_W<'_>

Bits 16:20 - Input channel mapping

pub fn chmap0(&mut self) -> CHMAP0_W<'_>

Bits 24:28 - Input channel mapping

impl W<u32, Reg<u32, _COMP1_CSR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&mut self) -> INMSEL_W<'_>

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&mut self) -> INPSEL_W<'_>

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&mut self) -> WINMODE_W<'_>

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&mut self) -> WINOUT_W<'_>

Bit 14 - Comparator 2 output selector

pub fn polarity(&mut self) -> POLARITY_W<'_>

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&mut self) -> PWRMODE_W<'_>

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&mut self) -> BLANKSEL_W<'_>

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&mut self) -> VALUE_W<'_>

Bit 30 - Comparator 2 output status

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - COMP2_CSR register lock

impl W<u32, Reg<u32, _COMP2_CSR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&mut self) -> INMSEL_W<'_>

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&mut self) -> INPSEL_W<'_>

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&mut self) -> WINMODE_W<'_>

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&mut self) -> WINOUT_W<'_>

Bit 14 - Comparator 2 output selector

pub fn polarity(&mut self) -> POLARITY_W<'_>

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&mut self) -> PWRMODE_W<'_>

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&mut self) -> BLANKSEL_W<'_>

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&mut self) -> VALUE_W<'_>

Bit 30 - Comparator 2 output status

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - COMP2_CSR register lock

impl W<u32, Reg<u32, _VREFBUF_CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrs(&mut self) -> VRS_W<'_>

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl W<u32, Reg<u32, _VREFBUF_CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl W<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&mut self) -> I2C_PAX_FMP_W<'_>

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&mut self) -> I2C_PBX_FMP_W<'_>

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn ucpd2_strobe(&mut self) -> UCPD2_STROBE_W<'_>

Bit 10 - Strobe signal bit for UCPD2

pub fn ucpd1_strobe(&mut self) -> UCPD1_STROBE_W<'_>

Bit 9 - Strobe signal bit for UCPD1

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&mut self) -> IR_MOD_W<'_>

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&mut self) -> IR_POL_W<'_>

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - Memory mapping selection bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&mut self) -> ECC_LOCK_W<'_>

Bit 3 - ECC error lock bit

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity error flag

impl W<u32, Reg<u32, _CR1>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - TAMP1E

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 1 - TAMP2E

pub fn itamp1e(&mut self) -> ITAMP1E_W<'_>

Bit 16 - ITAMP1E

pub fn itamp3e(&mut self) -> ITAMP3E_W<'_>

Bit 18 - ITAMP3E

pub fn itamp4e(&mut self) -> ITAMP4E_W<'_>

Bit 19 - ITAMP4E

pub fn itamp5e(&mut self) -> ITAMP5E_W<'_>

Bit 20 - ITAMP5E

pub fn itamp6e(&mut self) -> ITAMP6E_W<'_>

Bit 21 - ITAMP6E

impl W<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&mut self) -> TAMP1NOER_W<'_>

Bit 0 - TAMP1NOER

pub fn tamp2noer(&mut self) -> TAMP2NOER_W<'_>

Bit 1 - TAMP2NOER

pub fn tamp1msk(&mut self) -> TAMP1MSK_W<'_>

Bit 16 - TAMP1MSK

pub fn tamp2msk(&mut self) -> TAMP2MSK_W<'_>

Bit 17 - TAMP2MSK

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 24 - TAMP1TRG

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 25 - TAMP2TRG

impl W<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 0:2 - TAMPFREQ

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 3:4 - TAMPFLT

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 7 - TAMPPUDIS

impl W<u32, Reg<u32, _IER>>

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 0 - TAMP1IE

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 1 - TAMP2IE

pub fn itamp1ie(&mut self) -> ITAMP1IE_W<'_>

Bit 16 - ITAMP1IE

pub fn itamp3ie(&mut self) -> ITAMP3IE_W<'_>

Bit 18 - ITAMP3IE

pub fn itamp4ie(&mut self) -> ITAMP4IE_W<'_>

Bit 19 - ITAMP4IE

pub fn itamp5ie(&mut self) -> ITAMP5IE_W<'_>

Bit 20 - ITAMP5IE

pub fn itamp6ie(&mut self) -> ITAMP6IE_W<'_>

Bit 21 - ITAMP6IE

impl W<u32, Reg<u32, _SCR>>

pub fn ctamp1f(&mut self) -> CTAMP1F_W<'_>

Bit 0 - CTAMP1F

pub fn ctamp2f(&mut self) -> CTAMP2F_W<'_>

Bit 1 - CTAMP2F

pub fn citamp1f(&mut self) -> CITAMP1F_W<'_>

Bit 16 - CITAMP1F

pub fn citamp3f(&mut self) -> CITAMP3F_W<'_>

Bit 18 - CITAMP3F

pub fn citamp4f(&mut self) -> CITAMP4F_W<'_>

Bit 19 - CITAMP4F

pub fn citamp5f(&mut self) -> CITAMP5F_W<'_>

Bit 20 - CITAMP5F

pub fn citamp6f(&mut self) -> CITAMP6F_W<'_>

Bit 21 - CITAMP6F

pub fn citamp7f(&mut self) -> CITAMP7F_W<'_>

Bit 22 - CITAMP7F

impl W<u32, Reg<u32, _BKP0R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP1R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP2R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP3R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP4R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CFG1>>

pub fn hbitclkdiv(&mut self) -> HBITCLKDIV_W<'_>

Bits 0:5 - HBITCLKDIV

pub fn ifrgap(&mut self) -> IFRGAP_W<'_>

Bits 6:10 - IFRGAP

pub fn transwin(&mut self) -> TRANSWIN_W<'_>

Bits 11:15 - TRANSWIN

pub fn psc_usbpdclk(&mut self) -> PSC_USBPDCLK_W<'_>

Bits 17:19 - PSC_USBPDCLK

pub fn rxordseten(&mut self) -> RXORDSETEN_W<'_>

Bits 20:28 - RXORDSETEN

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 29 - TXDMAEN

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 30 - RXDMAEN:

pub fn ucpden(&mut self) -> UCPDEN_W<'_>

Bit 31 - UCPDEN

impl W<u32, Reg<u32, _CFG2>>

pub fn rxfiltdis(&mut self) -> RXFILTDIS_W<'_>

Bit 0 - RXFILTDIS

pub fn rxfilt2n3(&mut self) -> RXFILT2N3_W<'_>

Bit 1 - RXFILT2N3

pub fn forceclk(&mut self) -> FORCECLK_W<'_>

Bit 2 - FORCECLK

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 3 - WUPEN

impl W<u32, Reg<u32, _CFG3>>

pub fn trim1_ng_ccrpd(&mut self) -> TRIM1_NG_CCRPD_W<'_>

Bits 0:3 - TRIM1_NG_CCRPD

pub fn trim1_ng_cc1a5(&mut self) -> TRIM1_NG_CC1A5_W<'_>

Bits 4:8 - TRIM1_NG_CC1A5

pub fn trim1_ng_cc3a0(&mut self) -> TRIM1_NG_CC3A0_W<'_>

Bits 9:12 - TRIM1_NG_CC3A0

pub fn trim2_ng_ccrpd(&mut self) -> TRIM2_NG_CCRPD_W<'_>

Bits 16:19 - TRIM2_NG_CCRPD

pub fn trim2_ng_cc1a5(&mut self) -> TRIM2_NG_CC1A5_W<'_>

Bits 20:24 - TRIM2_NG_CC1A5

pub fn trim2_ng_cc3a0(&mut self) -> TRIM2_NG_CC3A0_W<'_>

Bits 25:28 - TRIM2_NG_CC3A0

impl W<u32, Reg<u32, _CR>>

pub fn txmode(&mut self) -> TXMODE_W<'_>

Bits 0:1 - TXMODE

pub fn txsend(&mut self) -> TXSEND_W<'_>

Bit 2 - TXSEND

pub fn txhrst(&mut self) -> TXHRST_W<'_>

Bit 3 - TXHRST

pub fn rxmode(&mut self) -> RXMODE_W<'_>

Bit 4 - RXMODE

pub fn phyrxen(&mut self) -> PHYRXEN_W<'_>

Bit 5 - PHYRXEN

pub fn phyccsel(&mut self) -> PHYCCSEL_W<'_>

Bit 6 - PHYCCSEL

pub fn anasubmode(&mut self) -> ANASUBMODE_W<'_>

Bits 7:8 - ANASUBMODE

pub fn anamode(&mut self) -> ANAMODE_W<'_>

Bit 9 - ANAMODE

pub fn ccenable(&mut self) -> CCENABLE_W<'_>

Bits 10:11 - CCENABLE

pub fn dbatten(&mut self) -> DBATTEN_W<'_>

Bit 15 - DBATTEN

pub fn frsrxen(&mut self) -> FRSRXEN_W<'_>

Bit 16 - FRSRXEN

pub fn frstx(&mut self) -> FRSTX_W<'_>

Bit 17 - FRSTX

pub fn rdch(&mut self) -> RDCH_W<'_>

Bit 18 - RDCH

pub fn cc1tcdis(&mut self) -> CC1TCDIS_W<'_>

Bit 20 - CC1TCDIS

pub fn cc2tcdis(&mut self) -> CC2TCDIS_W<'_>

Bit 21 - CC2TCDIS

impl W<u32, Reg<u32, _IMR>>

pub fn txisie(&mut self) -> TXISIE_W<'_>

Bit 0 - TXISIE

pub fn txmsgdiscie(&mut self) -> TXMSGDISCIE_W<'_>

Bit 1 - TXMSGDISCIE

pub fn txmsgsentie(&mut self) -> TXMSGSENTIE_W<'_>

Bit 2 - TXMSGSENTIE

pub fn txmsgabtie(&mut self) -> TXMSGABTIE_W<'_>

Bit 3 - TXMSGABTIE

pub fn hrstdiscie(&mut self) -> HRSTDISCIE_W<'_>

Bit 4 - HRSTDISCIE

pub fn hrstsentie(&mut self) -> HRSTSENTIE_W<'_>

Bit 5 - HRSTSENTIE

pub fn txundie(&mut self) -> TXUNDIE_W<'_>

Bit 6 - TXUNDIE

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 8 - RXNEIE

pub fn rxorddetie(&mut self) -> RXORDDETIE_W<'_>

Bit 9 - RXORDDETIE

pub fn rxhrstdetie(&mut self) -> RXHRSTDETIE_W<'_>

Bit 10 - RXHRSTDETIE

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>

Bit 11 - RXOVRIE

pub fn rxmsgendie(&mut self) -> RXMSGENDIE_W<'_>

Bit 12 - RXMSGENDIE

pub fn typecevt1ie(&mut self) -> TYPECEVT1IE_W<'_>

Bit 14 - TYPECEVT1IE

pub fn typecevt2ie(&mut self) -> TYPECEVT2IE_W<'_>

Bit 15 - TYPECEVT2IE

pub fn frsevtie(&mut self) -> FRSEVTIE_W<'_>

Bit 20 - FRSEVTIE

impl W<u32, Reg<u32, _ICR>>

pub fn txmsgdisccf(&mut self) -> TXMSGDISCCF_W<'_>

Bit 1 - TXMSGDISCCF

pub fn txmsgsentcf(&mut self) -> TXMSGSENTCF_W<'_>

Bit 2 - TXMSGSENTCF

pub fn txmsgabtcf(&mut self) -> TXMSGABTCF_W<'_>

Bit 3 - TXMSGABTCF

pub fn hrstdisccf(&mut self) -> HRSTDISCCF_W<'_>

Bit 4 - HRSTDISCCF

pub fn hrstsentcf(&mut self) -> HRSTSENTCF_W<'_>

Bit 5 - HRSTSENTCF

pub fn txundcf(&mut self) -> TXUNDCF_W<'_>

Bit 6 - TXUNDCF

pub fn rxorddetcf(&mut self) -> RXORDDETCF_W<'_>

Bit 9 - RXORDDETCF

pub fn rxhrstdetcf(&mut self) -> RXHRSTDETCF_W<'_>

Bit 10 - RXHRSTDETCF

pub fn rxovrcf(&mut self) -> RXOVRCF_W<'_>

Bit 11 - RXOVRCF

pub fn rxmsgendcf(&mut self) -> RXMSGENDCF_W<'_>

Bit 12 - RXMSGENDCF

pub fn typecevt1cf(&mut self) -> TYPECEVT1CF_W<'_>

Bit 14 - TYPECEVT1CF

pub fn typecevt2cf(&mut self) -> TYPECEVT2CF_W<'_>

Bit 15 - TYPECEVT2CF

pub fn frsevtcf(&mut self) -> FRSEVTCF_W<'_>

Bit 20 - FRSEVTCF

impl W<u32, Reg<u32, _TX_ORDSET>>

pub fn txordset(&mut self) -> TXORDSET_W<'_>

Bits 0:19 - TXORDSET

impl W<u32, Reg<u32, _TX_PAYSZ>>

pub fn txpaysz(&mut self) -> TXPAYSZ_W<'_>

Bits 0:9 - TXPAYSZ

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TXDATA

impl W<u32, Reg<u32, _RX_PAYSZ>>

pub fn rxpaysz(&mut self) -> RXPAYSZ_W<'_>

Bits 0:9 - RXPAYSZ

impl W<u32, Reg<u32, _RX_ORDEXT1>>

pub fn rxsopx1(&mut self) -> RXSOPX1_W<'_>

Bits 0:19 - RXSOPX1

impl W<u32, Reg<u32, _RX_ORDEXT2>>

pub fn rxsopx2(&mut self) -> RXSOPX2_W<'_>

Bits 0:19 - RXSOPX2

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn rstare(&mut self) -> RSTARE_W<'_>

Bit 4 - Reset after read enable

pub fn countrst(&mut self) -> COUNTRST_W<'_>

Bit 3 - Counter reset

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&mut self) -> IN2SEL_W<'_>

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&mut self) -> IN1SEL_W<'_>

Bits 0:1 - LPTIMx Input 1 selection

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - DEAT0

pub fn dedt0(&mut self) -> DEDT0_W<'_>

Bits 16:20 - DEDT0

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:19 - BRR

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _HWCFGR2>>

pub fn cfg1(&mut self) -> CFG1_W<'_>

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&mut self) -> CFG2_W<'_>

Bits 4:7 - LUART hardware configuration 2

impl W<u32, Reg<u32, _HWCFGR1>>

pub fn cfg1(&mut self) -> CFG1_W<'_>

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&mut self) -> CFG2_W<'_>

Bits 4:7 - LUART hardware configuration 2

pub fn cfg3(&mut self) -> CFG3_W<'_>

Bits 8:11 - LUART hardware configuration 1

pub fn cfg4(&mut self) -> CFG4_W<'_>

Bits 12:15 - LUART hardware configuration 2

pub fn cfg5(&mut self) -> CFG5_W<'_>

Bits 16:19 - LUART hardware configuration 2

pub fn cfg6(&mut self) -> CFG6_W<'_>

Bits 20:23 - LUART hardware configuration 2

pub fn cfg7(&mut self) -> CFG7_W<'_>

Bits 24:27 - LUART hardware configuration 2

pub fn cfg8(&mut self) -> CFG8_W<'_>

Bits 28:31 - LUART hardware configuration 2

impl W<u32, Reg<u32, _CEC_CR>>

pub fn cecen(&mut self) -> CECEN_W<'_>

Bit 0 - CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.

pub fn txsom(&mut self) -> TXSOM_W<'_>

Bit 1 - Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception

pub fn txeom(&mut self) -> TXEOM_W<'_>

Bit 2 - Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message)

impl W<u32, Reg<u32, _CEC_CFGR>>

pub fn sft(&mut self) -> SFT_W<'_>

Bits 0:2 - Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods

pub fn rxtol(&mut self) -> RXTOL_W<'_>

Bit 3 - Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall

pub fn brestp(&mut self) -> BRESTP_W<'_>

Bit 4 - Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software.

pub fn bregen(&mut self) -> BREGEN_W<'_>

Bit 5 - Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0

pub fn lbpegen(&mut self) -> LBPEGEN_W<'_>

Bit 6 - Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0

pub fn brdnogen(&mut self) -> BRDNOGEN_W<'_>

Bit 7 - Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software.

pub fn sftopt(&mut self) -> SFTOPT_W<'_>

Bit 8 - SFT Option Bit The SFTOPT bit is set and cleared by software.

pub fn oar(&mut self) -> OAR_W<'_>

Bits 16:30 - Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.

pub fn lstn(&mut self) -> LSTN_W<'_>

Bit 31 - Listen mode LSTN bit is set and cleared by software.

impl W<u32, Reg<u32, _CEC_TXDR>>

pub fn txd(&mut self) -> TXD_W<'_>

Bits 0:7 - Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1

impl W<u32, Reg<u32, _CEC_ISR>>

pub fn rxbr(&mut self) -> RXBR_W<'_>

Bit 0 - Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1.

pub fn rxend(&mut self) -> RXEND_W<'_>

Bit 1 - End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1.

pub fn rxovr(&mut self) -> RXOVR_W<'_>

Bit 2 - Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1.

pub fn bre(&mut self) -> BRE_W<'_>

Bit 3 - Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1.

pub fn sbpe(&mut self) -> SBPE_W<'_>

Bit 4 - Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1.

pub fn lbpe(&mut self) -> LBPE_W<'_>

Bit 5 - Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1.

pub fn rxacke(&mut self) -> RXACKE_W<'_>

Bit 6 - Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1.

pub fn arblst(&mut self) -> ARBLST_W<'_>

Bit 7 - Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1.

pub fn txbr(&mut self) -> TXBR_W<'_>

Bit 8 - Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1.

pub fn txend(&mut self) -> TXEND_W<'_>

Bit 9 - End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1.

pub fn txudr(&mut self) -> TXUDR_W<'_>

Bit 10 - Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 11 - Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1.

pub fn txacke(&mut self) -> TXACKE_W<'_>

Bit 12 - Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1.

impl W<u32, Reg<u32, _CEC_IER>>

pub fn rxbrie(&mut self) -> RXBRIE_W<'_>

Bit 0 - Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software.

pub fn rxendie(&mut self) -> RXENDIE_W<'_>

Bit 1 - End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software.

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>

Bit 2 - Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software.

pub fn breie(&mut self) -> BREIE_W<'_>

Bit 3 - Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software.

pub fn sbpeie(&mut self) -> SBPEIE_W<'_>

Bit 4 - Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software.

pub fn lbpeie(&mut self) -> LBPEIE_W<'_>

Bit 5 - Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software.

pub fn rxackie(&mut self) -> RXACKIE_W<'_>

Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software.

pub fn arblstie(&mut self) -> ARBLSTIE_W<'_>

Bit 7 - Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software.

pub fn txbrie(&mut self) -> TXBRIE_W<'_>

Bit 8 - Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software.

pub fn txendie(&mut self) -> TXENDIE_W<'_>

Bit 9 - Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software.

pub fn txudrie(&mut self) -> TXUDRIE_W<'_>

Bit 10 - Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software.

pub fn txerrie(&mut self) -> TXERRIE_W<'_>

Bit 11 - Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software.

pub fn txackie(&mut self) -> TXACKIE_W<'_>

Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software.

impl W<u32, Reg<u32, _DAC_CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 1 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 2:5 - DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable This bit is set and cleared by software.

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.

pub fn cen1(&mut self) -> CEN1_W<'_>

Bit 14 - DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 17 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 18:21 - DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable This bit is set and cleared by software.

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.

pub fn cen2(&mut self) -> CEN2_W<'_>

Bit 30 - DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

impl W<u32, Reg<u32, _DAC_SWTRGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.

impl W<u32, Reg<u32, _DAC_DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl W<u32, Reg<u32, _DAC_DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl W<u32, Reg<u32, _DAC_DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

impl W<u32, Reg<u32, _DAC_DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl W<u32, Reg<u32, _DAC_SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

impl W<u32, Reg<u32, _DAC_CCR>>

pub fn otrim1(&mut self) -> OTRIM1_W<'_>

Bits 0:4 - DAC Channel 1 offset trimming value

pub fn otrim2(&mut self) -> OTRIM2_W<'_>

Bits 16:20 - DAC Channel 2 offset trimming value

impl W<u32, Reg<u32, _DAC_MCR>>

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 0:2 - DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 16:18 - DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode

impl W<u32, Reg<u32, _DAC_SHSR1>>

pub fn tsample1(&mut self) -> TSAMPLE1_W<'_>

Bits 0:9 - DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.

impl W<u32, Reg<u32, _DAC_SHSR2>>

pub fn tsample2(&mut self) -> TSAMPLE2_W<'_>

Bits 0:9 - DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.

impl W<u32, Reg<u32, _DAC_SHHR>>

pub fn thold1(&mut self) -> THOLD1_W<'_>

Bits 0:9 - DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI

pub fn thold2(&mut self) -> THOLD2_W<'_>

Bits 16:25 - DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI

impl W<u32, Reg<u32, _DAC_SHRR>>

pub fn trefresh1(&mut self) -> TREFRESH1_W<'_>

Bits 0:7 - DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

pub fn trefresh2(&mut self) -> TREFRESH2_W<'_>

Bits 16:23 - DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

impl W<u32, Reg<u32, _IP_HWCFGR0>>

pub fn dual(&mut self) -> DUAL_W<'_>

Bits 0:3 - Dual DAC capability

pub fn lfsr(&mut self) -> LFSR_W<'_>

Bits 4:7 - Pseudonoise wave generation capability

pub fn triangle(&mut self) -> TRIANGLE_W<'_>

Bits 8:11 - Triangle wave generation capability

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:15 - Sample and hold mode capability

pub fn or_cfg(&mut self) -> OR_CFG_W<'_>

Bits 16:23 - option register bit width

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&mut self) -> OA1_0_W<'_>

Bit 0 - Interface address

pub fn oa1_7_1(&mut self) -> OA1_7_1_W<'_>

Bits 1:7 - Interface address

pub fn oa1_8_9(&mut self) -> OA1_8_9_W<'_>

Bits 8:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _ICSR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - WUCKSEL

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - TSEDGE

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - REFCKON

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - BYPSHAD

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - FMT

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - ALRAE

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - ALRBE

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - WUTE

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - TSE

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - ALRAIE

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - ALRBIE

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - WUTIE

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - TSIE

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - ADD1H

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - SUB1H

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - BKP

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - COSEL

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - POL

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - OSEL

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - COE

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - ITSE

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 25 - TAMPTS

pub fn tampoe(&mut self) -> TAMPOE_W<'_>

Bit 26 - TAMPOE

pub fn tampalrm_pu(&mut self) -> TAMPALRM_PU_W<'_>

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&mut self) -> TAMPALRM_TYPE_W<'_>

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&mut self) -> OUT2EN_W<'_>

Bit 31 - OUT2EN

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _SCR>>

pub fn calraf(&mut self) -> CALRAF_W<'_>

Bit 0 - CALRAF

pub fn calrbf(&mut self) -> CALRBF_W<'_>

Bit 1 - CALRBF

pub fn cwutf(&mut self) -> CWUTF_W<'_>

Bit 2 - CWUTF

pub fn ctsf(&mut self) -> CTSF_W<'_>

Bit 3 - CTSF

pub fn ctsovf(&mut self) -> CTSOVF_W<'_>

Bit 4 - CTSOVF

pub fn citsf(&mut self) -> CITSF_W<'_>

Bit 5 - CITSF

impl W<u32, Reg<u32, _HWCFGR>>

pub fn alarmb(&mut self) -> ALARMB_W<'_>

Bits 0:3 - ALARMB

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bits 4:7 - WAKEUP

pub fn smooth_calib(&mut self) -> SMOOTH_CALIB_W<'_>

Bits 8:11 - SMOOTH_CALIB

pub fn timestamp(&mut self) -> TIMESTAMP_W<'_>

Bits 12:15 - TIMESTAMP

pub fn optionreg_out(&mut self) -> OPTIONREG_OUT_W<'_>

Bits 16:23 - OPTIONREG_OUT

pub fn trust_zone(&mut self) -> TRUST_ZONE_W<'_>

Bits 24:27 - TRUST_ZONE

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - CC1S

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - OC1FE

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - OC1PE

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - OC1M

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - OC1CE

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&mut self) -> ICPCS_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _TISEL>>

pub fn tisel(&mut self) -> TISEL_W<'_>

Bits 0:3 - TI1[0] to TI1[15] input selection

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

pub fn uifcpy(&mut self) -> UIFCPY_W<'_>

Bit 31 - UIF Copy

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&mut self) -> TS_4_3_W<'_>

Bits 20:21 - Trigger selection

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&mut self) -> CNT_L_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&mut self) -> ARR_L_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&mut self) -> CCR1_L_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&mut self) -> CCR2_H_W<'_>

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&mut self) -> CCR2_L_W<'_>

Bits 0:15 - Low Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&mut self) -> CCR3_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&mut self) -> CCR3_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&mut self) -> CCR4_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&mut self) -> CCR4_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&mut self) -> IOCREF_CLR_W<'_>

Bit 0 - IOCREF_CLR

impl W<u32, Reg<u32, _AF1>>

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:17 - External trigger source selection

impl W<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&mut self) -> TI1SEL_W<'_>

Bits 0:3 - TI1SEL

pub fn ti2sel(&mut self) -> TI2SEL_W<'_>

Bits 8:11 - TI2SEL

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero