1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299
#[doc = "Reader of register EXTICR4"] pub type R = crate::R<u32, super::EXTICR4>; #[doc = "Writer for register EXTICR4"] pub type W = crate::W<u32, super::EXTICR4>; #[doc = "Register EXTICR4 `reset()`'s with value 0"] impl crate::ResetValue for super::EXTICR4 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "GPIO port selection\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum EXTI0_7_A { #[doc = "0: GPIO port A selected"] PA = 0, #[doc = "1: GPIO port B selected"] PB = 1, #[doc = "2: GPIO port C selected"] PC = 2, #[doc = "3: GPIO port D selected"] PD = 3, #[doc = "5: GPIO port F selected"] PF = 5, } impl From<EXTI0_7_A> for u8 { #[inline(always)] fn from(variant: EXTI0_7_A) -> Self { variant as _ } } #[doc = "Reader of field `EXTI0_7`"] pub type EXTI0_7_R = crate::R<u8, EXTI0_7_A>; impl EXTI0_7_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, EXTI0_7_A> { use crate::Variant::*; match self.bits { 0 => Val(EXTI0_7_A::PA), 1 => Val(EXTI0_7_A::PB), 2 => Val(EXTI0_7_A::PC), 3 => Val(EXTI0_7_A::PD), 5 => Val(EXTI0_7_A::PF), i => Res(i), } } #[doc = "Checks if the value of the field is `PA`"] #[inline(always)] pub fn is_pa(&self) -> bool { *self == EXTI0_7_A::PA } #[doc = "Checks if the value of the field is `PB`"] #[inline(always)] pub fn is_pb(&self) -> bool { *self == EXTI0_7_A::PB } #[doc = "Checks if the value of the field is `PC`"] #[inline(always)] pub fn is_pc(&self) -> bool { *self == EXTI0_7_A::PC } #[doc = "Checks if the value of the field is `PD`"] #[inline(always)] pub fn is_pd(&self) -> bool { *self == EXTI0_7_A::PD } #[doc = "Checks if the value of the field is `PF`"] #[inline(always)] pub fn is_pf(&self) -> bool { *self == EXTI0_7_A::PF } } #[doc = "Write proxy for field `EXTI0_7`"] pub struct EXTI0_7_W<'a> { w: &'a mut W, } impl<'a> EXTI0_7_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: EXTI0_7_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "GPIO port A selected"] #[inline(always)] pub fn pa(self) -> &'a mut W { self.variant(EXTI0_7_A::PA) } #[doc = "GPIO port B selected"] #[inline(always)] pub fn pb(self) -> &'a mut W { self.variant(EXTI0_7_A::PB) } #[doc = "GPIO port C selected"] #[inline(always)] pub fn pc(self) -> &'a mut W { self.variant(EXTI0_7_A::PC) } #[doc = "GPIO port D selected"] #[inline(always)] pub fn pd(self) -> &'a mut W { self.variant(EXTI0_7_A::PD) } #[doc = "GPIO port F selected"] #[inline(always)] pub fn pf(self) -> &'a mut W { self.variant(EXTI0_7_A::PF) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); self.w } } #[doc = "GPIO port selection"] pub type EXTI8_15_A = EXTI0_7_A; #[doc = "Reader of field `EXTI8_15`"] pub type EXTI8_15_R = crate::R<u8, EXTI0_7_A>; #[doc = "Write proxy for field `EXTI8_15`"] pub struct EXTI8_15_W<'a> { w: &'a mut W, } impl<'a> EXTI8_15_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: EXTI8_15_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "GPIO port A selected"] #[inline(always)] pub fn pa(self) -> &'a mut W { self.variant(EXTI0_7_A::PA) } #[doc = "GPIO port B selected"] #[inline(always)] pub fn pb(self) -> &'a mut W { self.variant(EXTI0_7_A::PB) } #[doc = "GPIO port C selected"] #[inline(always)] pub fn pc(self) -> &'a mut W { self.variant(EXTI0_7_A::PC) } #[doc = "GPIO port D selected"] #[inline(always)] pub fn pd(self) -> &'a mut W { self.variant(EXTI0_7_A::PD) } #[doc = "GPIO port F selected"] #[inline(always)] pub fn pf(self) -> &'a mut W { self.variant(EXTI0_7_A::PF) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); self.w } } #[doc = "GPIO port selection"] pub type EXTI16_23_A = EXTI0_7_A; #[doc = "Reader of field `EXTI16_23`"] pub type EXTI16_23_R = crate::R<u8, EXTI0_7_A>; #[doc = "Write proxy for field `EXTI16_23`"] pub struct EXTI16_23_W<'a> { w: &'a mut W, } impl<'a> EXTI16_23_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: EXTI16_23_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "GPIO port A selected"] #[inline(always)] pub fn pa(self) -> &'a mut W { self.variant(EXTI0_7_A::PA) } #[doc = "GPIO port B selected"] #[inline(always)] pub fn pb(self) -> &'a mut W { self.variant(EXTI0_7_A::PB) } #[doc = "GPIO port C selected"] #[inline(always)] pub fn pc(self) -> &'a mut W { self.variant(EXTI0_7_A::PC) } #[doc = "GPIO port D selected"] #[inline(always)] pub fn pd(self) -> &'a mut W { self.variant(EXTI0_7_A::PD) } #[doc = "GPIO port F selected"] #[inline(always)] pub fn pf(self) -> &'a mut W { self.variant(EXTI0_7_A::PF) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); self.w } } #[doc = "GPIO port selection"] pub type EXTI24_31_A = EXTI0_7_A; #[doc = "Reader of field `EXTI24_31`"] pub type EXTI24_31_R = crate::R<u8, EXTI0_7_A>; #[doc = "Write proxy for field `EXTI24_31`"] pub struct EXTI24_31_W<'a> { w: &'a mut W, } impl<'a> EXTI24_31_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: EXTI24_31_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "GPIO port A selected"] #[inline(always)] pub fn pa(self) -> &'a mut W { self.variant(EXTI0_7_A::PA) } #[doc = "GPIO port B selected"] #[inline(always)] pub fn pb(self) -> &'a mut W { self.variant(EXTI0_7_A::PB) } #[doc = "GPIO port C selected"] #[inline(always)] pub fn pc(self) -> &'a mut W { self.variant(EXTI0_7_A::PC) } #[doc = "GPIO port D selected"] #[inline(always)] pub fn pd(self) -> &'a mut W { self.variant(EXTI0_7_A::PD) } #[doc = "GPIO port F selected"] #[inline(always)] pub fn pf(self) -> &'a mut W { self.variant(EXTI0_7_A::PF) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); self.w } } impl R { #[doc = "Bits 0:7 - GPIO port selection"] #[inline(always)] pub fn exti0_7(&self) -> EXTI0_7_R { EXTI0_7_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:15 - GPIO port selection"] #[inline(always)] pub fn exti8_15(&self) -> EXTI8_15_R { EXTI8_15_R::new(((self.bits >> 8) & 0xff) as u8) } #[doc = "Bits 16:23 - GPIO port selection"] #[inline(always)] pub fn exti16_23(&self) -> EXTI16_23_R { EXTI16_23_R::new(((self.bits >> 16) & 0xff) as u8) } #[doc = "Bits 24:31 - GPIO port selection"] #[inline(always)] pub fn exti24_31(&self) -> EXTI24_31_R { EXTI24_31_R::new(((self.bits >> 24) & 0xff) as u8) } } impl W { #[doc = "Bits 0:7 - GPIO port selection"] #[inline(always)] pub fn exti0_7(&mut self) -> EXTI0_7_W { EXTI0_7_W { w: self } } #[doc = "Bits 8:15 - GPIO port selection"] #[inline(always)] pub fn exti8_15(&mut self) -> EXTI8_15_W { EXTI8_15_W { w: self } } #[doc = "Bits 16:23 - GPIO port selection"] #[inline(always)] pub fn exti16_23(&mut self) -> EXTI16_23_W { EXTI16_23_W { w: self } } #[doc = "Bits 24:31 - GPIO port selection"] #[inline(always)] pub fn exti24_31(&mut self) -> EXTI24_31_W { EXTI24_31_W { w: self } } }