Struct stm32g0::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Implementations

impl<U, T> R<U, T> where
    U: Copy, 

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<u32, Reg<u32, _PR>>

pub fn pr(&self) -> PR_R

Bits 0:2 - Prescaler divider

impl R<u32, Reg<u32, _RLR>>

pub fn rl(&self) -> RL_R

Bits 0:11 - Watchdog counter reload value

impl R<u32, Reg<u32, _SR>>

pub fn wvu(&self) -> WVU_R

Bit 2 - Watchdog counter window value update

pub fn rvu(&self) -> RVU_R

Bit 1 - Watchdog counter reload value update

pub fn pvu(&self) -> PVU_R

Bit 0 - Watchdog prescaler value update

impl R<u32, Reg<u32, _WINR>>

pub fn win(&self) -> WIN_R

Bits 0:11 - Watchdog counter window value

impl R<u32, Reg<u32, _CR>>

pub fn wdga(&self) -> WDGA_R

Bit 7 - Activation bit

pub fn t(&self) -> T_R

Bits 0:6 - 7-bit counter (MSB to LSB)

impl R<u32, Reg<u32, _CFR>>

pub fn wdgtb(&self) -> WDGTB_R

Bits 11:13 - Timer base

pub fn ewi(&self) -> EWI_R

Bit 9 - Early wakeup interrupt

pub fn w(&self) -> W_R

Bits 0:6 - 7-bit window value

impl R<u32, Reg<u32, _SR>>

pub fn ewif(&self) -> EWIF_R

Bit 0 - Early wakeup interrupt flag

impl R<u32, Reg<u32, _ACR>>

pub fn latency(&self) -> LATENCY_R

Bits 0:2 - Latency

pub fn prften(&self) -> PRFTEN_R

Bit 8 - Prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - Instruction cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - Instruction cache reset

pub fn empty(&self) -> EMPTY_R

Bit 16 - Flash User area empty

pub fn dbg_swen(&self) -> DBG_SWEN_R

Bit 18 - Debug access software enable

impl R<u32, Reg<u32, _SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - Write protected error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn miserr(&self) -> MISERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn optverr(&self) -> OPTVERR_R

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy.

impl R<u32, Reg<u32, _CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - Mass erase

pub fn pnb(&self) -> PNB_R

Bits 3:8 - Page number

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn optstrt(&self) -> OPTSTRT_R

Bit 17 - Options modification start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&self) -> OBL_LAUNCH_R

Bit 27 - Force the option byte loading

pub fn sec_prot(&self) -> SEC_PROT_R

Bit 28 - Securable memory area protection enable

pub fn optlock(&self) -> OPTLOCK_R

Bit 30 - Options Lock

pub fn lock(&self) -> LOCK_R

Bit 31 - FLASH_CR Lock

impl R<u32, Reg<u32, _ECCR>>

pub fn addr_ecc(&self) -> ADDR_ECC_R

Bits 0:13 - ECC fail address

pub fn sysf_ecc(&self) -> SYSF_ECC_R

Bit 20 - ECC fail for Corrected ECC Error or Double ECC Error in info block

pub fn eccie(&self) -> ECCIE_R

Bit 24 - ECC correction interrupt enable

pub fn eccc(&self) -> ECCC_R

Bit 30 - ECC correction

pub fn eccd(&self) -> ECCD_R

Bit 31 - ECC detection

impl R<u32, Reg<u32, _OPTR>>

pub fn rdp(&self) -> RDP_R

Bits 0:7 - Read protection level

pub fn boren(&self) -> BOREN_R

Bit 8 - BOR reset Level

pub fn borf_lev(&self) -> BORF_LEV_R

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&self) -> BORR_LEV_R

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&self) -> NRST_STOP_R

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&self) -> NRST_STDBY_R

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&self) -> NRSTS_HDW_R

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&self) -> IDWG_SW_R

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&self) -> IWDG_STOP_R

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&self) -> IWDG_STDBY_R

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&self) -> WWDG_SW_R

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&self) -> RAM_PARITY_CHECK_R

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&self) -> NBOOT_SEL_R

Bit 24 - nBOOT_SEL

pub fn n_boot1(&self) -> NBOOT1_R

Bit 25 - Boot configuration

pub fn n_boot0(&self) -> NBOOT0_R

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&self) -> NRST_MODE_R

Bits 27:28 - NRST_MODE

pub fn irhen(&self) -> IRHEN_R

Bit 29 - Internal reset holder enable bit

impl R<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R

Bits 0:7 - PCROP1A area start offset

impl R<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&self) -> PCROP1A_END_R

Bits 0:7 - PCROP1A area end offset

pub fn pcrop_rdp(&self) -> PCROP_RDP_R

Bit 31 - PCROP area preserved when RDP level decreased

impl R<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&self) -> WRP1A_STRT_R

Bits 0:5 - WRP area A start offset

pub fn wrp1a_end(&self) -> WRP1A_END_R

Bits 16:21 - WRP area A end offset

impl R<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&self) -> WRP1B_STRT_R

Bits 0:5 - WRP area B start offset

pub fn wrp1b_end(&self) -> WRP1B_END_R

Bits 16:21 - WRP area B end offset

impl R<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R

Bits 0:7 - PCROP1B area start offset

impl R<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&self) -> PCROP1B_END_R

Bits 0:7 - PCROP1B area end offset

impl R<u32, Reg<u32, _SECR>>

pub fn sec_size(&self) -> SEC_SIZE_R

Bits 0:6 - Securable memory area size

pub fn boot_lock(&self) -> BOOT_LOCK_R

Bit 16 - used to force boot from user area

impl R<u32, Reg<u32, _CR>>

pub fn hsion(&self) -> HSION_R

Bit 8 - HSI16 clock enable

pub fn hsikeron(&self) -> HSIKERON_R

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&self) -> HSIRDY_R

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&self) -> HSIDIV_R

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&self) -> HSEON_R

Bit 16 - HSE clock enable

pub fn hserdy(&self) -> HSERDY_R

Bit 17 - HSE clock ready flag

pub fn hsebyp(&self) -> HSEBYP_R

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&self) -> CSSON_R

Bit 19 - Clock security system enable

pub fn pllon(&self) -> PLLON_R

Bit 24 - PLL enable

pub fn pllrdy(&self) -> PLLRDY_R

Bit 25 - PLL clock ready flag

impl R<u32, Reg<u32, _ICSCR>>

pub fn hsical(&self) -> HSICAL_R

Bits 0:7 - HSI16 clock calibration

pub fn hsitrim(&self) -> HSITRIM_R

Bits 8:14 - HSI16 clock trimming

impl R<u32, Reg<u32, _CFGR>>

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&self) -> MCOSEL_R

Bits 24:26 - Microcontroller clock output

pub fn ppre(&self) -> PPRE_R

Bits 12:14 - APB prescaler

pub fn hpre(&self) -> HPRE_R

Bits 8:11 - AHB prescaler

pub fn sws(&self) -> SWS_R

Bits 3:5 - System clock switch status

pub fn sw(&self) -> SW_R

Bits 0:2 - System clock switch

impl R<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - PLL input clock source

pub fn pllm(&self) -> PLLM_R

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&self) -> PLLN_R

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&self) -> PLLREN_R

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl R<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&self) -> LSIRDYIE_R

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&self) -> LSERDYIE_R

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&self) -> HSIRDYIE_R

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&self) -> HSERDYIE_R

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&self) -> PLLSYSRDYIE_R

Bit 5 - PLL ready interrupt enable

impl R<u32, Reg<u32, _CIFR>>

pub fn lsirdyf(&self) -> LSIRDYF_R

Bit 0 - LSI ready interrupt flag

pub fn lserdyf(&self) -> LSERDYF_R

Bit 1 - LSE ready interrupt flag

pub fn hsirdyf(&self) -> HSIRDYF_R

Bit 3 - HSI ready interrupt flag

pub fn hserdyf(&self) -> HSERDYF_R

Bit 4 - HSE ready interrupt flag

pub fn pllsysrdyf(&self) -> PLLSYSRDYF_R

Bit 5 - PLL ready interrupt flag

pub fn cssf(&self) -> CSSF_R

Bit 8 - Clock security system interrupt flag

pub fn lsecssf(&self) -> LSECSSF_R

Bit 9 - LSE Clock security system interrupt flag

impl R<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&self) -> DMARST_R

Bit 0 - DMA1 reset

pub fn flashrst(&self) -> FLASHRST_R

Bit 8 - FLITF reset

pub fn crcrst(&self) -> CRCRST_R

Bit 12 - CRC reset

impl R<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&self) -> IOPARST_R

Bit 0 - I/O port A reset

pub fn iopbrst(&self) -> IOPBRST_R

Bit 1 - I/O port B reset

pub fn iopcrst(&self) -> IOPCRST_R

Bit 2 - I/O port C reset

pub fn iopdrst(&self) -> IOPDRST_R

Bit 3 - I/O port D reset

pub fn iopfrst(&self) -> IOPFRST_R

Bit 5 - I/O port F reset

impl R<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&self) -> TIM2RST_R

Bit 0 - TIM2 timer reset

pub fn tim3rst(&self) -> TIM3RST_R

Bit 1 - TIM3 timer reset

pub fn spi2rst(&self) -> SPI2RST_R

Bit 14 - SPI2 reset

pub fn usart2rst(&self) -> USART2RST_R

Bit 17 - USART2 reset

pub fn i2c1rst(&self) -> I2C1RST_R

Bit 21 - I2C1 reset

pub fn i2c2rst(&self) -> I2C2RST_R

Bit 22 - I2C2 reset

pub fn dbgrst(&self) -> DBGRST_R

Bit 27 - Debug support reset

pub fn pwrrst(&self) -> PWRRST_R

Bit 28 - Power interface reset

impl R<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&self) -> SYSCFGRST_R

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&self) -> TIM1RST_R

Bit 11 - TIM1 timer reset

pub fn spi1rst(&self) -> SPI1RST_R

Bit 12 - SPI1 reset

pub fn usart1rst(&self) -> USART1RST_R

Bit 14 - USART1 reset

pub fn tim14rst(&self) -> TIM14RST_R

Bit 15 - TIM14 timer reset

pub fn tim16rst(&self) -> TIM16RST_R

Bit 17 - TIM16 timer reset

pub fn tim17rst(&self) -> TIM17RST_R

Bit 18 - TIM17 timer reset

pub fn adcrst(&self) -> ADCRST_R

Bit 20 - ADC reset

impl R<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&self) -> IOPAEN_R

Bit 0 - I/O port A clock enable

pub fn iopben(&self) -> IOPBEN_R

Bit 1 - I/O port B clock enable

pub fn iopcen(&self) -> IOPCEN_R

Bit 2 - I/O port C clock enable

pub fn iopden(&self) -> IOPDEN_R

Bit 3 - I/O port D clock enable

pub fn iopfen(&self) -> IOPFEN_R

Bit 5 - I/O port F clock enable

impl R<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - DMA clock enable

pub fn flashen(&self) -> FLASHEN_R

Bit 8 - Flash memory interface clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CRC clock enable

impl R<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&self) -> TIM2EN_R

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&self) -> TIM3EN_R

Bit 1 - TIM3 timer clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - RTC APB clock enable

pub fn wwdgen(&self) -> WWDGEN_R

Bit 11 - WWDG clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - SPI2 clock enable

pub fn usart2en(&self) -> USART2EN_R

Bit 17 - USART2 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - I2C1 clock enable

pub fn i2c2en(&self) -> I2C2EN_R

Bit 22 - I2C2 clock enable

pub fn dbgen(&self) -> DBGEN_R

Bit 27 - Debug support clock enable

pub fn pwren(&self) -> PWREN_R

Bit 28 - Power interface clock enable

impl R<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&self) -> SYSCFGEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - SPI1 clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - USART1 clock enable

pub fn tim14en(&self) -> TIM14EN_R

Bit 15 - TIM14 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - TIM16 timer clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 20 - ADC clock enable

impl R<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&self) -> IOPASMEN_R

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&self) -> IOPBSMEN_R

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&self) -> IOPCSMEN_R

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&self) -> IOPDSMEN_R

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&self) -> IOPFSMEN_R

Bit 5 - I/O port F clock enable during Sleep mode

impl R<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&self) -> DMASMEN_R

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&self) -> SRAMSMEN_R

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CRC clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&self) -> TIM2SMEN_R

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&self) -> TIM3SMEN_R

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&self) -> WWDGSMEN_R

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&self) -> USART2SMEN_R

Bit 17 - USART2 clock enable during Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&self) -> I2C2SMEN_R

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&self) -> DBGSMEN_R

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&self) -> PWRSMEN_R

Bit 28 - Power interface clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&self) -> SYSCFGSMEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&self) -> TIM14SMEN_R

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&self) -> ADCSMEN_R

Bit 20 - ADC clock enable during Sleep mode

impl R<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&self) -> USART1SEL_R

Bits 0:1 - USART1 clock source selection

pub fn i2c1sel(&self) -> I2C1SEL_R

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&self) -> I2S2SEL_R

Bits 14:15 - I2S1 clock source selection

pub fn tim1sel(&self) -> TIM1SEL_R

Bit 22 - TIM1 clock source selection

pub fn rngsel(&self) -> RNGSEL_R

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&self) -> RNGDIV_R

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&self) -> ADCSEL_R

Bits 30:31 - ADCs clock source selection

impl R<u32, Reg<u32, _BDCR>>

pub fn lseon(&self) -> LSEON_R

Bit 0 - LSE oscillator enable

pub fn lserdy(&self) -> LSERDY_R

Bit 1 - LSE oscillator ready

pub fn lsebyp(&self) -> LSEBYP_R

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&self) -> LSEDRV_R

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&self) -> LSECSSON_R

Bit 5 - CSS on LSE enable

pub fn lsecssd(&self) -> LSECSSD_R

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&self) -> RTCSEL_R

Bits 8:9 - RTC clock source selection

pub fn rtcen(&self) -> RTCEN_R

Bit 15 - RTC clock enable

pub fn bdrst(&self) -> BDRST_R

Bit 16 - RTC domain software reset

pub fn lscoen(&self) -> LSCOEN_R

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&self) -> LSCOSEL_R

Bit 25 - Low-speed clock output selection

impl R<u32, Reg<u32, _CSR>>

pub fn lsion(&self) -> LSION_R

Bit 0 - LSI oscillator enable

pub fn lsirdy(&self) -> LSIRDY_R

Bit 1 - LSI oscillator ready

pub fn rmvf(&self) -> RMVF_R

Bit 23 - Remove reset flags

pub fn oblrstf(&self) -> OBLRSTF_R

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&self) -> PINRSTF_R

Bit 26 - Pin reset flag

pub fn pwrrstf(&self) -> PWRRSTF_R

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&self) -> SFTRSTF_R

Bit 28 - Software reset flag

pub fn iwdgrstf(&self) -> IWDGRSTF_R

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&self) -> WWDGRSTF_R

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&self) -> LPWRRSTF_R

Bit 31 - Low-power reset flag

impl R<u32, Reg<u32, _CR1>>

pub fn lpr(&self) -> LPR_R

Bit 14 - Low-power run

pub fn vos(&self) -> VOS_R

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&self) -> DBP_R

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&self) -> FPD_LPSLP_R

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&self) -> FPD_LPRUN_R

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&self) -> FPD_STOP_R

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection

impl R<u32, Reg<u32, _CR2>>

pub fn pvde(&self) -> PVDE_R

Bit 0 - Power voltage detector enable

pub fn pvdft(&self) -> PVDFT_R

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&self) -> PVDRT_R

Bits 4:6 - Power voltage detector rising threshold selection

impl R<u32, Reg<u32, _CR3>>

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&self) -> EWUP6_R

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&self) -> RRS_R

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&self) -> ULPEN_R

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&self) -> APC_R

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line

impl R<u32, Reg<u32, _CR4>>

pub fn wp1(&self) -> WP1_R

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&self) -> WP2_R

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&self) -> WP4_R

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&self) -> WP5_R

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&self) -> WP6_R

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&self) -> VBE_R

Bit 8 - VBAT battery charging enable

pub fn vbrs(&self) -> VBRS_R

Bit 9 - VBAT battery charging resistor selection

impl R<u32, Reg<u32, _SR1>>

pub fn wuf1(&self) -> WUF1_R

Bit 0 - Wakeup flag 1

pub fn wuf2(&self) -> WUF2_R

Bit 1 - Wakeup flag 2

pub fn wuf4(&self) -> WUF4_R

Bit 3 - Wakeup flag 4

pub fn wuf5(&self) -> WUF5_R

Bit 4 - Wakeup flag 5

pub fn wuf6(&self) -> WUF6_R

Bit 5 - Wakeup flag 6

pub fn sbf(&self) -> SBF_R

Bit 8 - Standby flag

pub fn wufi(&self) -> WUFI_R

Bit 15 - Wakeup flag internal

impl R<u32, Reg<u32, _SR2>>

pub fn pvdo(&self) -> PVDO_R

Bit 11 - Power voltage detector output

pub fn vosf(&self) -> VOSF_R

Bit 10 - Voltage scaling flag

pub fn reglpf(&self) -> REGLPF_R

Bit 9 - Low-power regulator flag

pub fn reglps(&self) -> REGLPS_R

Bit 8 - Low-power regulator started

pub fn flash_rdy(&self) -> FLASH_RDY_R

Bit 7 - Flash ready flag

impl R<u32, Reg<u32, _PUCRA>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port A pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRA>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port A pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRB>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port B pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRB>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port B pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRC>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port C pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRC>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port C pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRD>>

pub fn pu3(&self) -> PU3_R

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port D pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRD>>

pub fn pd9(&self) -> PD9_R

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port D pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRF>>

pub fn pu2(&self) -> PU2_R

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port F pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRF>>

pub fn pd2(&self) -> PD2_R

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port F pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _CR>>

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

impl R<u32, Reg<u32, _NDTR>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _PAR>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _MAR>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _ISR>>

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel 1 global interrupt flag

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel 1 transfer complete flag

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel 1 half transfer flag

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel 1 transfer error flag

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel 2 global interrupt flag

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel 2 transfer complete flag

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel 2 half transfer flag

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel 2 transfer error flag

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel 3 global interrupt flag

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel 3 transfer complete flag

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel 3 half transfer flag

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel 3 transfer error flag

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel 4 global interrupt flag

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel 4 transfer complete flag

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel 4 half transfer flag

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel 4 transfer error flag

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel 5 global interrupt flag

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel 5 transfer complete flag

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel 5 half transfer flag

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel 5 transfer error flag

impl R<u32, Reg<u32, _C0CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C1CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C2CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C3CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C4CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C5CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C6CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _RG0CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG1CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG2CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG3CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RGSR>>

pub fn of(&self) -> OF_R

Bits 0:3 - Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:31 - Data register bits

impl R<u32, Reg<u32, _IDR>>

pub fn idr(&self) -> IDR_R

Bits 0:31 - General-purpose 32-bit data register bits

impl R<u32, Reg<u32, _CR>>

pub fn rev_out(&self) -> REV_OUT_R

Bit 7 - Reverse output data

pub fn rev_in(&self) -> REV_IN_R

Bits 5:6 - Reverse input data

pub fn polysize(&self) -> POLYSIZE_R

Bits 3:4 - Polynomial size

impl R<u32, Reg<u32, _INIT>>

pub fn crc_init(&self) -> CRC_INIT_R

Bits 0:31 - Programmable initial CRC value

impl R<u32, Reg<u32, _POL>>

pub fn pol(&self) -> POL_R

Bits 0:31 - Programmable polynomial

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _RTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _FTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, SWIER0_A>

pub fn variant(&self) -> Variant<bool, SWIER0_A>

Get enumerated values variant

pub fn is_pend(&self) -> bool

Checks if the value of the field is PEND

impl R<u32, Reg<u32, _SWIER1>>

pub fn swier0(&self) -> SWIER0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&self) -> SWIER1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&self) -> SWIER2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&self) -> SWIER3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&self) -> SWIER4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&self) -> SWIER5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&self) -> SWIER6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&self) -> SWIER7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&self) -> SWIER8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&self) -> SWIER9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&self) -> SWIER10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&self) -> SWIER11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&self) -> SWIER12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&self) -> SWIER13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&self) -> SWIER14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&self) -> SWIER15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&self) -> SWIER16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, RPIF0_A>

pub fn variant(&self) -> RPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _RPR1>>

pub fn rpif0(&self) -> RPIF0_R

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&self) -> RPIF1_R

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&self) -> RPIF2_R

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&self) -> RPIF3_R

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&self) -> RPIF4_R

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&self) -> RPIF5_R

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&self) -> RPIF6_R

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&self) -> RPIF7_R

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&self) -> RPIF8_R

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&self) -> RPIF9_R

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&self) -> RPIF10_R

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&self) -> RPIF11_R

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&self) -> RPIF12_R

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&self) -> RPIF13_R

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&self) -> RPIF14_R

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&self) -> RPIF15_R

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&self) -> RPIF16_R

Bit 16 - configurable event inputs x rising edge Pending bit.

impl R<bool, FPIF0_A>

pub fn variant(&self) -> FPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _FPR1>>

pub fn fpif0(&self) -> FPIF0_R

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&self) -> FPIF1_R

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&self) -> FPIF2_R

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&self) -> FPIF3_R

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&self) -> FPIF4_R

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&self) -> FPIF5_R

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&self) -> FPIF6_R

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&self) -> FPIF7_R

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&self) -> FPIF8_R

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&self) -> FPIF9_R

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&self) -> FPIF10_R

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&self) -> FPIF11_R

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&self) -> FPIF12_R

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&self) -> FPIF13_R

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&self) -> FPIF14_R

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&self) -> FPIF15_R

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&self) -> FPIF16_R

Bit 16 - configurable event inputs x falling edge pending bit.

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<bool, IM0_A>

pub fn variant(&self) -> IM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR1>>

pub fn im0(&self) -> IM0_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&self) -> IM1_R

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&self) -> IM2_R

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&self) -> IM3_R

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&self) -> IM4_R

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&self) -> IM5_R

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&self) -> IM6_R

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&self) -> IM7_R

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&self) -> IM8_R

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&self) -> IM9_R

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&self) -> IM10_R

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&self) -> IM11_R

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&self) -> IM12_R

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&self) -> IM13_R

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&self) -> IM14_R

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&self) -> IM15_R

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&self) -> IM16_R

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im19(&self) -> IM19_R

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&self) -> IM20_R

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&self) -> IM21_R

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&self) -> IM22_R

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&self) -> IM23_R

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&self) -> IM24_R

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&self) -> IM25_R

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&self) -> IM26_R

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im28(&self) -> IM28_R

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&self) -> IM29_R

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&self) -> IM30_R

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&self) -> IM31_R

Bit 31 - CPU wakeup with interrupt mask on event input

impl R<bool, EM0_A>

pub fn variant(&self) -> EM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR1>>

pub fn em0(&self) -> EM0_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&self) -> EM1_R

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&self) -> EM2_R

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&self) -> EM3_R

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&self) -> EM4_R

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&self) -> EM5_R

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&self) -> EM6_R

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&self) -> EM7_R

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&self) -> EM8_R

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&self) -> EM9_R

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&self) -> EM10_R

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&self) -> EM11_R

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&self) -> EM12_R

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&self) -> EM13_R

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&self) -> EM14_R

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&self) -> EM15_R

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&self) -> EM16_R

Bit 16 - CPU wakeup with event mask on event input

pub fn em19(&self) -> EM19_R

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&self) -> EM21_R

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&self) -> EM23_R

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&self) -> EM25_R

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&self) -> EM26_R

Bit 26 - CPU wakeup with event mask on event input

pub fn em28(&self) -> EM28_R

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&self) -> EM29_R

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&self) -> EM30_R

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&self) -> EM31_R

Bit 31 - CPU wakeup with event mask on event input

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&self) -> BKDFBK1E_R

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - selects input

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT

pub fn dedt(&self) -> DEDT_R

Bits 16:20 - DEDT

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn rtoen(&self) -> RTOEN_R

Bit 23 - Receiver timeout enable

pub fn abrmod(&self) -> ABRMOD_R

Bits 21:22 - Auto baud rate mode

pub fn abren(&self) -> ABREN_R

Bit 20 - Auto baud rate enable

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn linen(&self) -> LINEN_R

Bit 14 - LIN mode enable

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn clken(&self) -> CLKEN_R

Bit 11 - Clock enable

pub fn cpol(&self) -> CPOL_R

Bit 10 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 9 - Clock phase

pub fn lbcl(&self) -> LBCL_R

Bit 8 - Last bit clock pulse

pub fn lbdie(&self) -> LBDIE_R

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&self) -> LBDL_R

Bit 5 - LIN break detection length

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&self) -> DIS_NSS_R

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&self) -> SLVEN_R

Bit 0 - Synchronous Slave mode enable

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&self) -> TCBGTIE_R

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&self) -> SCARCNT_R

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn onebit(&self) -> ONEBIT_R

Bit 11 - One sample bit method enable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn scen(&self) -> SCEN_R

Bit 5 - Smartcard mode enable

pub fn nack(&self) -> NACK_R

Bit 4 - Smartcard NACK enable

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn irlp(&self) -> IRLP_R

Bit 2 - Ir low-power

pub fn iren(&self) -> IREN_R

Bit 1 - Ir mode enable

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&self) -> BRR_4_15_R

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&self) -> BRR_0_3_R

Bits 0:3 - BRR_0_3

impl R<u32, Reg<u32, _GTPR>>

pub fn gt(&self) -> GT_R

Bits 8:15 - Guard time value

pub fn psc(&self) -> PSC_R

Bits 0:7 - Prescaler value

impl R<u32, Reg<u32, _RTOR>>

pub fn blen(&self) -> BLEN_R

Bits 24:31 - Block Length

pub fn rto(&self) -> RTO_R

Bits 0:23 - Receiver timeout value

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn tcbgt(&self) -> TCBGT_R

Bit 25 - Transmission complete before guard time flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn abrf(&self) -> ABRF_R

Bit 15 - ABRF

pub fn abre(&self) -> ABRE_R

Bit 14 - ABRE

pub fn udr(&self) -> UDR_R

Bit 13 - SPI slave underrun error flag

pub fn eobf(&self) -> EOBF_R

Bit 12 - EOBF

pub fn rtof(&self) -> RTOF_R

Bit 11 - RTOF

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn lbdf(&self) -> LBDF_R

Bit 8 - LBDF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn bidimode(&self) -> BIDIMODE_R

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&self) -> BIDIOE_R

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&self) -> CRCEN_R

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&self) -> CRCNEXT_R

Bit 12 - CRC transfer next

pub fn dff(&self) -> DFF_R

Bit 11 - Data frame format

pub fn rxonly(&self) -> RXONLY_R

Bit 10 - Receive only

pub fn ssm(&self) -> SSM_R

Bit 9 - Software slave management

pub fn ssi(&self) -> SSI_R

Bit 8 - Internal slave select

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 7 - Frame format

pub fn spe(&self) -> SPE_R

Bit 6 - SPI enable

pub fn br(&self) -> BR_R

Bits 3:5 - Baud rate control

pub fn mstr(&self) -> MSTR_R

Bit 2 - Master selection

pub fn cpol(&self) -> CPOL_R

Bit 1 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 0 - Clock phase

impl R<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&self) -> SSOE_R

Bit 2 - SS output enable

pub fn nssp(&self) -> NSSP_R

Bit 3 - NSS pulse management

pub fn frf(&self) -> FRF_R

Bit 4 - Frame format

pub fn errie(&self) -> ERRIE_R

Bit 5 - Error interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&self) -> DS_R

Bits 8:11 - Data size

pub fn frxth(&self) -> FRXTH_R

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&self) -> LDMA_RX_R

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&self) -> LDMA_TX_R

Bit 14 - Last DMA transfer for transmission

impl R<u32, Reg<u32, _SR>>

pub fn rxne(&self) -> RXNE_R

Bit 0 - Receive buffer not empty

pub fn txe(&self) -> TXE_R

Bit 1 - Transmit buffer empty

pub fn chside(&self) -> CHSIDE_R

Bit 2 - Channel side

pub fn udr(&self) -> UDR_R

Bit 3 - Underrun flag

pub fn crcerr(&self) -> CRCERR_R

Bit 4 - CRC error flag

pub fn modf(&self) -> MODF_R

Bit 5 - Mode fault

pub fn ovr(&self) -> OVR_R

Bit 6 - Overrun flag

pub fn bsy(&self) -> BSY_R

Bit 7 - Busy flag

pub fn tifrfe(&self) -> TIFRFE_R

Bit 8 - TI frame format error

pub fn frlvl(&self) -> FRLVL_R

Bits 9:10 - FIFO reception level

pub fn ftlvl(&self) -> FTLVL_R

Bits 11:12 - FIFO transmission level

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:15 - Data register

impl R<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&self) -> CRCPOLY_R

Bits 0:15 - CRC polynomial register

impl R<u32, Reg<u32, _RXCRCR>>

pub fn rx_crc(&self) -> RXCRC_R

Bits 0:15 - Rx CRC register

impl R<u32, Reg<u32, _TXCRCR>>

pub fn tx_crc(&self) -> TXCRC_R

Bits 0:15 - Tx CRC register

impl R<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&self) -> CHLEN_R

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&self) -> DATLEN_R

Bits 1:2 - Data length to be transferred

pub fn ckpol(&self) -> CKPOL_R

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&self) -> I2SSTD_R

Bits 4:5 - standard selection

pub fn pcmsync(&self) -> PCMSYNC_R

Bit 7 - PCM frame synchronization

pub fn i2scfg(&self) -> I2SCFG_R

Bits 8:9 - I2S configuration mode

pub fn se2(&self) -> SE2_R

Bit 10 - I2S enable

pub fn i2smod(&self) -> I2SMOD_R

Bit 11 - I2S mode selection

impl R<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&self) -> I2SDIV_R

Bits 0:7 - linear prescaler

pub fn odd(&self) -> ODD_R

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&self) -> MCKOE_R

Bit 9 - Master clock output enable

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn ts_4(&self) -> TS_4_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn ts(&self) -> TS_R

Bits 20:21 - Trigger selection

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag

pub fn cc5if(&self) -> CC5IF_R

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&self) -> CC6IF_R

Bit 17 - Compare 6 interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

impl R<u32, Reg<u32, _CCER>>

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&self) -> CC2NE_R

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&self) -> CC3NE_R

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&self) -> CC5E_R

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&self) -> CC5P_R

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&self) -> CC6E_R

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&self) -> CC6P_R

Bit 21 - Capture/Compare 6 output polarity

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:15 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3(&self) -> CCR3_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4(&self) -> CCR4_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bk2f(&self) -> BK2F_R

Bits 20:23 - Break 2 filter

pub fn bk2e(&self) -> BK2E_R

Bit 24 - Break 2 enable

pub fn bk2p(&self) -> BK2P_R

Bit 25 - Break 2 polarity

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bk2dsrm(&self) -> BK2DSRM_R

Bit 27 - Break2 Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

pub fn bk2id(&self) -> BK2ID_R

Bit 29 - Break2 bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&self) -> OCREF_CLR_R

Bit 0 - Ocref_clr source selection

impl R<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&self) -> OC6M_BIT3_R

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&self) -> OC5M_BIT3_R

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&self) -> OC6CE_R

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&self) -> OC6M_R

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&self) -> OC6PE_R

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&self) -> OC6FE_R

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&self) -> OC5CE_R

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&self) -> OC5M_R

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&self) -> OC5PE_R

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&self) -> OC5FE_R

Bit 2 - Output compare 5 fast enable

impl R<u32, Reg<u32, _CCR5>>

pub fn ccr5(&self) -> CCR5_R

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&self) -> GC5C1_R

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&self) -> GC5C2_R

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&self) -> GC5C3_R

Bit 31 - Group Channel 5 and Channel 3

impl R<u32, Reg<u32, _CCR6>>

pub fn ccr6(&self) -> CCR6_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - ETR source selection

impl R<u32, Reg<u32, _AF2>>

pub fn bk2ine(&self) -> BK2INE_R

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&self) -> BK2CMP1E_R

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&self) -> BK2CMP2E_R

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&self) -> BK2INP_R

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&self) -> BK2CMP1P_R

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&self) -> BK2CMP2P_R

Bit 11 - BRK2 COMP2 input polarity

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel3_0(&self) -> TI1SEL3_0_R

Bits 0:3 - selects TI1[0] to TI1[15] input

pub fn ti2sel3_0(&self) -> TI2SEL3_0_R

Bits 8:11 - selects TI2[0] to TI2[15] input

pub fn ti3sel3_0(&self) -> TI3SEL3_0_R

Bits 16:19 - selects TI3[0] to TI3[15] input

pub fn ti4sel3_0(&self) -> TI4SEL3_0_R

Bits 24:27 - selects TI4[0] to TI4[15] input

impl R<u32, Reg<u32, _ISR>>

pub fn ccrdy(&self) -> CCRDY_R

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&self) -> EOCAL_R

Bit 11 - End Of Calibration flag

pub fn awd3(&self) -> AWD3_R

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&self) -> AWD2_R

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&self) -> AWD1_R

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&self) -> OVR_R

Bit 4 - ADC group regular overrun flag

pub fn eos(&self) -> EOS_R

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&self) -> EOC_R

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&self) -> EOSMP_R

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&self) -> ADRDY_R

Bit 0 - ADC ready flag

impl R<u32, Reg<u32, _IER>>

pub fn ccrdyie(&self) -> CCRDYIE_R

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&self) -> EOCALIE_R

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&self) -> AWD3IE_R

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&self) -> AWD2IE_R

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&self) -> AWD1IE_R

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&self) -> OVRIE_R

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&self) -> EOSIE_R

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&self) -> EOCIE_R

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&self) -> EOSMPIE_R

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&self) -> ADRDYIE_R

Bit 0 - ADC ready interrupt

impl R<u32, Reg<u32, _CR>>

pub fn adcal(&self) -> ADCAL_R

Bit 31 - ADC calibration

pub fn advregen(&self) -> ADVREGEN_R

Bit 28 - ADC voltage regulator enable

pub fn adstp(&self) -> ADSTP_R

Bit 4 - ADC group regular conversion stop

pub fn adstart(&self) -> ADSTART_R

Bit 2 - ADC group regular conversion start

pub fn addis(&self) -> ADDIS_R

Bit 1 - ADC disable

pub fn aden(&self) -> ADEN_R

Bit 0 - ADC enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&self) -> AWDCH1CH_R

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&self) -> AWD1EN_R

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGL_R

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&self) -> CHSELRMOD_R

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&self) -> DISCEN_R

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&self) -> AUTOFF_R

Bit 15 - Auto-off mode

pub fn wait(&self) -> WAIT_R

Bit 14 - Wait conversion mode

pub fn cont(&self) -> CONT_R

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMOD_R

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTEN_R

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSEL_R

Bits 6:8 - ADC group regular external trigger source

pub fn align(&self) -> ALIGN_R

Bit 5 - ADC data alignement

pub fn res(&self) -> RES_R

Bits 3:4 - ADC data resolution

pub fn scandir(&self) -> SCANDIR_R

Bit 2 - Scan sequence direction

pub fn dmacfg(&self) -> DMACFG_R

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - ADC DMA transfer enable

impl R<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&self) -> CKMODE_R

Bits 30:31 - ADC clock mode

pub fn lftrig(&self) -> LFTRIG_R

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&self) -> TOVS_R

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&self) -> OVSS_R

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&self) -> OVSR_R

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&self) -> OVSE_R

Bit 0 - ADC oversampler enable on scope ADC group regular

impl R<u32, Reg<u32, _SMPR>>

pub fn smp1(&self) -> SMP1_R

Bits 0:2 - Sampling time selection

pub fn smp2(&self) -> SMP2_R

Bits 4:6 - Sampling time selection

pub fn smpsel(&self) -> SMPSEL_R

Bits 8:26 - Channel sampling time selection

impl R<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&self) -> HT1_R

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&self) -> LT1_R

Bits 0:11 - ADC analog watchdog 1 threshold low

impl R<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&self) -> HT2_R

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&self) -> LT2_R

Bits 0:11 - ADC analog watchdog 2 threshold low

impl R<u32, Reg<u32, _CHSELR>>

pub fn chsel(&self) -> CHSEL_R

Bits 0:18 - Channel-x selection

impl R<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&self) -> SQ1_R

Bits 0:3 - conversion of the sequence

pub fn sq2(&self) -> SQ2_R

Bits 4:7 - conversion of the sequence

pub fn sq3(&self) -> SQ3_R

Bits 8:11 - conversion of the sequence

pub fn sq4(&self) -> SQ4_R

Bits 12:15 - conversion of the sequence

pub fn sq5(&self) -> SQ5_R

Bits 16:19 - conversion of the sequence

pub fn sq6(&self) -> SQ6_R

Bits 20:23 - conversion of the sequence

pub fn sq7(&self) -> SQ7_R

Bits 24:27 - conversion of the sequence

pub fn sq8(&self) -> SQ8_R

Bits 28:31 - conversion of the sequence

impl R<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&self) -> HT3_R

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&self) -> LT3_R

Bits 0:11 - ADC analog watchdog 3 threshold high

impl R<u32, Reg<u32, _DR>>

pub fn regular_data(&self) -> REGULARDATA_R

Bits 0:15 - ADC group regular conversion data

impl R<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&self) -> AWD2CH_R

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl R<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&self) -> AWD3CH_R

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl R<u32, Reg<u32, _CALFACT>>

pub fn calfact(&self) -> CALFACT_R

Bits 0:6 - ADC calibration factor in single-ended mode

impl R<u32, Reg<u32, _CCR>>

pub fn presc(&self) -> PRESC_R

Bits 18:21 - ADC prescaler

pub fn vrefen(&self) -> VREFEN_R

Bit 22 - VREFINT enable

pub fn tsen(&self) -> TSEN_R

Bit 23 - Temperature sensor enable

pub fn vbaten(&self) -> VBATEN_R

Bit 24 - VBAT enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&self) -> I2C_PAX_FMP_R

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&self) -> I2C2_FMP_R

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&self) -> I2C1_FMP_R

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&self) -> I2C_PBX_FMP_R

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn boosten(&self) -> BOOSTEN_R

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&self) -> IR_MOD_R

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&self) -> IR_POL_R

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&self) -> PA11_PA12_RMP_R

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&self) -> MEM_MODE_R

Bits 0:1 - Memory mapping selection bits

impl R<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&self) -> LOCKUP_LOCK_R

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&self) -> SRAM_PARITY_LOCK_R

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&self) -> PVD_LOCK_R

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&self) -> ECC_LOCK_R

Bit 3 - ECC error lock bit

pub fn sram_pef(&self) -> SRAM_PEF_R

Bit 8 - SRAM parity error flag

pub fn pa1_cden(&self) -> PA1_CDEN_R

Bit 16 - PA1_CDEN

pub fn pa3_cden(&self) -> PA3_CDEN_R

Bit 17 - PA3_CDEN

pub fn pa5_cden(&self) -> PA5_CDEN_R

Bit 18 - PA5_CDEN

pub fn pa6_cden(&self) -> PA6_CDEN_R

Bit 19 - PA6_CDEN

pub fn pa13_cden(&self) -> PA13_CDEN_R

Bit 20 - PA13_CDEN

pub fn pb0_cden(&self) -> PB0_CDEN_R

Bit 21 - PB0_CDEN

pub fn pb1_cden(&self) -> PB1_CDEN_R

Bit 22 - PB1_CDEN

pub fn pb2_cden(&self) -> PB2_CDEN_R

Bit 23 - PB2_CDEN

impl R<u32, Reg<u32, _CR1>>

pub fn tamp1e(&self) -> TAMP1E_R

Bit 0 - TAMP1E

pub fn tamp2e(&self) -> TAMP2E_R

Bit 1 - TAMP2E

pub fn itamp1e(&self) -> ITAMP1E_R

Bit 16 - ITAMP1E

pub fn itamp3e(&self) -> ITAMP3E_R

Bit 18 - ITAMP3E

pub fn itamp4e(&self) -> ITAMP4E_R

Bit 19 - ITAMP4E

pub fn itamp5e(&self) -> ITAMP5E_R

Bit 20 - ITAMP5E

pub fn itamp6e(&self) -> ITAMP6E_R

Bit 21 - ITAMP6E

impl R<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&self) -> TAMP1NOER_R

Bit 0 - TAMP1NOER

pub fn tamp2noer(&self) -> TAMP2NOER_R

Bit 1 - TAMP2NOER

pub fn tamp1msk(&self) -> TAMP1MSK_R

Bit 16 - TAMP1MSK

pub fn tamp2msk(&self) -> TAMP2MSK_R

Bit 17 - TAMP2MSK

pub fn tamp1trg(&self) -> TAMP1TRG_R

Bit 24 - TAMP1TRG

pub fn tamp2trg(&self) -> TAMP2TRG_R

Bit 25 - TAMP2TRG

impl R<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&self) -> TAMPFREQ_R

Bits 0:2 - TAMPFREQ

pub fn tampflt(&self) -> TAMPFLT_R

Bits 3:4 - TAMPFLT

pub fn tampprch(&self) -> TAMPPRCH_R

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&self) -> TAMPPUDIS_R

Bit 7 - TAMPPUDIS

impl R<u32, Reg<u32, _IER>>

pub fn tamp1ie(&self) -> TAMP1IE_R

Bit 0 - TAMP1IE

pub fn tamp2ie(&self) -> TAMP2IE_R

Bit 1 - TAMP2IE

pub fn itamp1ie(&self) -> ITAMP1IE_R

Bit 16 - ITAMP1IE

pub fn itamp3ie(&self) -> ITAMP3IE_R

Bit 18 - ITAMP3IE

pub fn itamp4ie(&self) -> ITAMP4IE_R

Bit 19 - ITAMP4IE

pub fn itamp5ie(&self) -> ITAMP5IE_R

Bit 20 - ITAMP5IE

pub fn itamp6ie(&self) -> ITAMP6IE_R

Bit 21 - ITAMP6IE

impl R<u32, Reg<u32, _SR>>

pub fn tamp1f(&self) -> TAMP1F_R

Bit 0 - TAMP1F

pub fn tamp2f(&self) -> TAMP2F_R

Bit 1 - TAMP2F

pub fn itamp1f(&self) -> ITAMP1F_R

Bit 16 - ITAMP1F

pub fn itamp3f(&self) -> ITAMP3F_R

Bit 18 - ITAMP3F

pub fn itamp4f(&self) -> ITAMP4F_R

Bit 19 - ITAMP4F

pub fn itamp5f(&self) -> ITAMP5F_R

Bit 20 - ITAMP5F

pub fn itamp6f(&self) -> ITAMP6F_R

Bit 21 - ITAMP6F

pub fn itamp7f(&self) -> ITAMP7F_R

Bit 22 - ITAMP7F

impl R<u32, Reg<u32, _MISR>>

pub fn tamp1mf(&self) -> TAMP1MF_R

Bit 0 - TAMP1MF:

pub fn tamp2mf(&self) -> TAMP2MF_R

Bit 1 - TAMP2MF

pub fn itamp1mf(&self) -> ITAMP1MF_R

Bit 16 - ITAMP1MF

pub fn itamp3mf(&self) -> ITAMP3MF_R

Bit 18 - ITAMP3MF

pub fn itamp4mf(&self) -> ITAMP4MF_R

Bit 19 - ITAMP4MF

pub fn itamp5mf(&self) -> ITAMP5MF_R

Bit 20 - ITAMP5MF

pub fn itamp6mf(&self) -> ITAMP6MF_R

Bit 21 - ITAMP6MF

impl R<u32, Reg<u32, _BKP0R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP1R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP2R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP3R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP4R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _CR1>>

pub fn pe(&self) -> PE_R

Bit 0 - Peripheral enable

pub fn txie(&self) -> TXIE_R

Bit 1 - TX Interrupt enable

pub fn rxie(&self) -> RXIE_R

Bit 2 - RX Interrupt enable

pub fn addrie(&self) -> ADDRIE_R

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&self) -> NACKIE_R

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&self) -> STOPIE_R

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 7 - Error interrupts enable

pub fn dnf(&self) -> DNF_R

Bits 8:11 - Digital noise filter

pub fn anfoff(&self) -> ANFOFF_R

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 15 - DMA reception requests enable

pub fn sbc(&self) -> SBC_R

Bit 16 - Slave byte control

pub fn nostretch(&self) -> NOSTRETCH_R

Bit 17 - Clock stretching disable

pub fn wupen(&self) -> WUPEN_R

Bit 18 - Wakeup from STOP enable

pub fn gcen(&self) -> GCEN_R

Bit 19 - General call enable

pub fn smbhen(&self) -> SMBHEN_R

Bit 20 - SMBus Host address enable

pub fn smbden(&self) -> SMBDEN_R

Bit 21 - SMBus Device Default address enable

pub fn alerten(&self) -> ALERTEN_R

Bit 22 - SMBUS alert enable

pub fn pecen(&self) -> PECEN_R

Bit 23 - PEC enable

impl R<u32, Reg<u32, _CR2>>

pub fn pecbyte(&self) -> PECBYTE_R

Bit 26 - Packet error checking byte

pub fn autoend(&self) -> AUTOEND_R

Bit 25 - Automatic end mode (master mode)

pub fn reload(&self) -> RELOAD_R

Bit 24 - NBYTES reload mode

pub fn nbytes(&self) -> NBYTES_R

Bits 16:23 - Number of bytes

pub fn nack(&self) -> NACK_R

Bit 15 - NACK generation (slave mode)

pub fn stop(&self) -> STOP_R

Bit 14 - Stop generation (master mode)

pub fn start(&self) -> START_R

Bit 13 - Start generation

pub fn head10r(&self) -> HEAD10R_R

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&self) -> ADD10_R

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&self) -> RD_WRN_R

Bit 10 - Transfer direction (master mode)

pub fn sadd(&self) -> SADD_R

Bits 0:9 - Slave address bit (master mode)

impl R<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&self) -> OA1_0_R

Bit 0 - Interface address

pub fn oa1_7_1(&self) -> OA1_7_1_R

Bits 1:7 - Interface address

pub fn oa1_8_9(&self) -> OA1_8_9_R

Bits 8:9 - Interface address

pub fn oa1mode(&self) -> OA1MODE_R

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&self) -> OA1EN_R

Bit 15 - Own Address 1 enable

impl R<u32, Reg<u32, _OAR2>>

pub fn oa2(&self) -> OA2_R

Bits 1:7 - Interface address

pub fn oa2msk(&self) -> OA2MSK_R

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&self) -> OA2EN_R

Bit 15 - Own Address 2 enable

impl R<u32, Reg<u32, _TIMINGR>>

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler

impl R<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&self) -> TIMEOUTA_R

Bits 0:11 - Bus timeout A

pub fn tidle(&self) -> TIDLE_R

Bit 12 - Idle clock timeout detection

pub fn timouten(&self) -> TIMOUTEN_R

Bit 15 - Clock timeout enable

pub fn timeoutb(&self) -> TIMEOUTB_R

Bits 16:27 - Bus timeout B

pub fn texten(&self) -> TEXTEN_R

Bit 31 - Extended clock timeout enable

impl R<u32, Reg<u32, _ISR>>

pub fn addcode(&self) -> ADDCODE_R

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R

Bit 0 - Transmit data register empty (transmitters)

impl R<u32, Reg<u32, _PECR>>

pub fn pec(&self) -> PEC_R

Bits 0:7 - Packet error checking register

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - 8-bit receive data

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - 8-bit transmit data

impl R<u32, Reg<u32, _TR>>

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _DR>>

pub fn yt(&self) -> YT_R

Bits 20:23 - Year tens in BCD format

pub fn yu(&self) -> YU_R

Bits 16:19 - Year units in BCD format

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _SSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ICSR>>

pub fn alrawf(&self) -> ALRAWF_R

Bit 0 - Alarm A write flag

pub fn alrbwf(&self) -> ALRBWF_R

Bit 1 - Alarm B write flag

pub fn wutwf(&self) -> WUTWF_R

Bit 2 - Wakeup timer write flag

pub fn shpf(&self) -> SHPF_R

Bit 3 - Shift operation pending

pub fn inits(&self) -> INITS_R

Bit 4 - Initialization status flag

pub fn rsf(&self) -> RSF_R

Bit 5 - Registers synchronization flag

pub fn initf(&self) -> INITF_R

Bit 6 - Initialization flag

pub fn init(&self) -> INIT_R

Bit 7 - Initialization mode

pub fn recalpf(&self) -> RECALPF_R

Bit 16 - Recalibration pending Flag

impl R<u32, Reg<u32, _PRER>>

pub fn prediv_a(&self) -> PREDIV_A_R

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&self) -> PREDIV_S_R

Bits 0:14 - Synchronous prescaler factor

impl R<u32, Reg<u32, _WUTR>>

pub fn wut(&self) -> WUT_R

Bits 0:15 - Wakeup auto-reload value bits

impl R<u32, Reg<u32, _CR>>

pub fn wucksel(&self) -> WUCKSEL_R

Bits 0:2 - WUCKSEL

pub fn tsedge(&self) -> TSEDGE_R

Bit 3 - TSEDGE

pub fn refckon(&self) -> REFCKON_R

Bit 4 - REFCKON

pub fn bypshad(&self) -> BYPSHAD_R

Bit 5 - BYPSHAD

pub fn fmt(&self) -> FMT_R

Bit 6 - FMT

pub fn alrae(&self) -> ALRAE_R

Bit 8 - ALRAE

pub fn alrbe(&self) -> ALRBE_R

Bit 9 - ALRBE

pub fn wute(&self) -> WUTE_R

Bit 10 - WUTE

pub fn tse(&self) -> TSE_R

Bit 11 - TSE

pub fn alraie(&self) -> ALRAIE_R

Bit 12 - ALRAIE

pub fn alrbie(&self) -> ALRBIE_R

Bit 13 - ALRBIE

pub fn wutie(&self) -> WUTIE_R

Bit 14 - WUTIE

pub fn tsie(&self) -> TSIE_R

Bit 15 - TSIE

pub fn add1h(&self) -> ADD1H_R

Bit 16 - ADD1H

pub fn sub1h(&self) -> SUB1H_R

Bit 17 - SUB1H

pub fn bkp(&self) -> BKP_R

Bit 18 - BKP

pub fn cosel(&self) -> COSEL_R

Bit 19 - COSEL

pub fn pol(&self) -> POL_R

Bit 20 - POL

pub fn osel(&self) -> OSEL_R

Bits 21:22 - OSEL

pub fn coe(&self) -> COE_R

Bit 23 - COE

pub fn itse(&self) -> ITSE_R

Bit 24 - ITSE

pub fn tampts(&self) -> TAMPTS_R

Bit 25 - TAMPTS

pub fn tampoe(&self) -> TAMPOE_R

Bit 26 - TAMPOE

pub fn tampalrm_pu(&self) -> TAMPALRM_PU_R

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&self) -> TAMPALRM_TYPE_R

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&self) -> OUT2EN_R

Bit 31 - OUT2EN

impl R<u32, Reg<u32, _CALR>>

pub fn calp(&self) -> CALP_R

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&self) -> CALW8_R

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&self) -> CALW16_R

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&self) -> CALM_R

Bits 0:8 - Calibration minus

impl R<u32, Reg<u32, _TSTR>>

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

impl R<u32, Reg<u32, _TSDR>>

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _TSSSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm A date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm A hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm A minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm A seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm B date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm B hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm B minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm B seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _SR>>

pub fn alraf(&self) -> ALRAF_R

Bit 0 - ALRAF

pub fn alrbf(&self) -> ALRBF_R

Bit 1 - ALRBF

pub fn wutf(&self) -> WUTF_R

Bit 2 - WUTF

pub fn tsf(&self) -> TSF_R

Bit 3 - TSF

pub fn tsovf(&self) -> TSOVF_R

Bit 4 - TSOVF

pub fn itsf(&self) -> ITSF_R

Bit 5 - ITSF

impl R<u32, Reg<u32, _MISR>>

pub fn alramf(&self) -> ALRAMF_R

Bit 0 - ALRAMF

pub fn alrbmf(&self) -> ALRBMF_R

Bit 1 - ALRBMF

pub fn wutmf(&self) -> WUTMF_R

Bit 2 - WUTMF

pub fn tsmf(&self) -> TSMF_R

Bit 3 - TSMF

pub fn tsovmf(&self) -> TSOVMF_R

Bit 4 - TSOVMF

pub fn itsmf(&self) -> ITSMF_R

Bit 5 - ITSMF

impl R<u32, Reg<u32, _SCR>>

pub fn calraf(&self) -> CALRAF_R

Bit 0 - CALRAF

pub fn calrbf(&self) -> CALRBF_R

Bit 1 - CALRBF

pub fn cwutf(&self) -> CWUTF_R

Bit 2 - CWUTF

pub fn ctsf(&self) -> CTSF_R

Bit 3 - CTSF

pub fn ctsovf(&self) -> CTSOVF_R

Bit 4 - CTSOVF

pub fn citsf(&self) -> CITSF_R

Bit 5 - CITSF

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _DIER>>

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - CC1S

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - OC1FE

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - OC1PE

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - OC1M

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - OC1CE

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&self) -> ICPCS_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _TISEL>>

pub fn tisel(&self) -> TISEL_R

Bits 0:3 - TI1[0] to TI1[15] input selection

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

impl R<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&self) -> TS_4_3_R

Bits 20:21 - Trigger selection

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&self) -> IC3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt_h(&self) -> CNT_H_R

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&self) -> CNT_L_R

Bits 0:15 - Low counter value

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr_h(&self) -> ARR_H_R

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&self) -> ARR_L_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&self) -> CCR1_H_R

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&self) -> CCR1_L_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&self) -> CCR2_H_R

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&self) -> CCR2_L_R

Bits 0:15 - Low Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&self) -> CCR3_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&self) -> CCR3_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&self) -> CCR4_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&self) -> CCR4_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&self) -> IOCREF_CLR_R

Bit 0 - IOCREF_CLR

impl R<u32, Reg<u32, _AF1>>

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:17 - External trigger source selection

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - TI1SEL

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - TI2SEL

impl R<u32, Reg<u32, _CSR>>

pub fn enable(&self) -> ENABLE_R

Bit 0 - Counter enable

pub fn tickint(&self) -> TICKINT_R

Bit 1 - SysTick exception request enable

pub fn clksource(&self) -> CLKSOURCE_R

Bit 2 - Clock source selection

pub fn countflag(&self) -> COUNTFLAG_R

Bit 16 - COUNTFLAG

impl R<u32, Reg<u32, _RVR>>

pub fn reload(&self) -> RELOAD_R

Bits 0:23 - RELOAD value

impl R<u32, Reg<u32, _CVR>>

pub fn current(&self) -> CURRENT_R

Bits 0:23 - Current counter value

impl R<u32, Reg<u32, _CALIB>>

pub fn tenms(&self) -> TENMS_R

Bits 0:23 - Calibration value

pub fn skew(&self) -> SKEW_R

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&self) -> NOREF_R

Bit 31 - NOREF flag. Reads as zero

impl R<u32, Reg<u32, _CSR>>

pub fn envr(&self) -> ENVR_R

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&self) -> HIZ_R

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrr(&self) -> VRR_R

Bit 3 - Voltage reference buffer ready

pub fn vrs(&self) -> VRS_R

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl R<u32, Reg<u32, _CCR>>

pub fn trim(&self) -> TRIM_R

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl R<u32, Reg<u32, _IDCODE>>

pub fn dev_id(&self) -> DEV_ID_R

Bits 0:11 - Device identifier

pub fn rev_id(&self) -> REV_ID_R

Bits 16:31 - Revision identifie

impl R<u32, Reg<u32, _CR>>

pub fn dbg_stop(&self) -> DBG_STOP_R

Bit 1 - Debug Stop mode

pub fn dbg_standby(&self) -> DBG_STANDBY_R

Bit 2 - Debug Standby mode

impl R<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R

Bit 0 - TIM2 counter stopped when core is halted

pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R

Bit 11 - Window watchdog counter stopped when core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - Independent watchdog counter stopped when core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted

impl R<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - DBG_TIM17_STOP

impl R<u32, Reg<u32, _STIR>>

pub fn intid(&self) -> INTID_R

Bits 0:8 - Software generated interrupt ID

impl R<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&self) -> DISMCYCINT_R

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&self) -> DISDEFWBUF_R

Bit 1 - DISDEFWBUF

pub fn disfold(&self) -> DISFOLD_R

Bit 2 - DISFOLD

pub fn disfpca(&self) -> DISFPCA_R

Bit 8 - DISFPCA

pub fn disoofp(&self) -> DISOOFP_R

Bit 9 - DISOOFP

impl R<u32, Reg<u32, _CPACR>>

pub fn cp(&self) -> CP_R

Bits 20:23 - CP

impl R<u32, Reg<u32, _FPCCR>>

pub fn lspact(&self) -> LSPACT_R

Bit 0 - LSPACT

pub fn user(&self) -> USER_R

Bit 1 - USER

pub fn thread(&self) -> THREAD_R

Bit 3 - THREAD

pub fn hfrdy(&self) -> HFRDY_R

Bit 4 - HFRDY

pub fn mmrdy(&self) -> MMRDY_R

Bit 5 - MMRDY

pub fn bfrdy(&self) -> BFRDY_R

Bit 6 - BFRDY

pub fn monrdy(&self) -> MONRDY_R

Bit 8 - MONRDY

pub fn lspen(&self) -> LSPEN_R

Bit 30 - LSPEN

pub fn aspen(&self) -> ASPEN_R

Bit 31 - ASPEN

impl R<u32, Reg<u32, _FPCAR>>

pub fn address(&self) -> ADDRESS_R

Bits 3:31 - Location of unpopulated floating-point

impl R<u32, Reg<u32, _FPSCR>>

pub fn ioc(&self) -> IOC_R

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&self) -> DZC_R

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&self) -> OFC_R

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&self) -> UFC_R

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&self) -> IXC_R

Bit 4 - Inexact cumulative exception bit

pub fn idc(&self) -> IDC_R

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&self) -> RMODE_R

Bits 22:23 - Rounding Mode control field

pub fn fz(&self) -> FZ_R

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&self) -> DN_R

Bit 25 - Default NaN mode control bit

pub fn ahp(&self) -> AHP_R

Bit 26 - Alternative half-precision control bit

pub fn v(&self) -> V_R

Bit 28 - Overflow condition code flag

pub fn c(&self) -> C_R

Bit 29 - Carry condition code flag

pub fn z(&self) -> Z_R

Bit 30 - Zero condition code flag

pub fn n(&self) -> N_R

Bit 31 - Negative condition code flag

impl R<u32, Reg<u32, _ITLINE0>>

pub fn wwdg(&self) -> WWDG_R

Bit 0 - Window watchdog interrupt pending flag

impl R<u32, Reg<u32, _ITLINE1>>

pub fn pvdout(&self) -> PVDOUT_R

Bit 0 - PVD supply monitoring interrupt request pending (EXTI line 16).

impl R<u32, Reg<u32, _ITLINE2>>

pub fn tamp(&self) -> TAMP_R

Bit 0 - TAMP

pub fn rtc(&self) -> RTC_R

Bit 1 - RTC

impl R<u32, Reg<u32, _ITLINE3>>

pub fn flash_itf(&self) -> FLASH_ITF_R

Bit 0 - FLASH_ITF

pub fn flash_ecc(&self) -> FLASH_ECC_R

Bit 1 - FLASH_ECC

impl R<u32, Reg<u32, _ITLINE4>>

pub fn rcc(&self) -> RCC_R

Bit 0 - RCC

impl R<u32, Reg<u32, _ITLINE5>>

pub fn exti0(&self) -> EXTI0_R

Bit 0 - EXTI0

pub fn exti1(&self) -> EXTI1_R

Bit 1 - EXTI1

impl R<u32, Reg<u32, _ITLINE6>>

pub fn exti2(&self) -> EXTI2_R

Bit 0 - EXTI2

pub fn exti3(&self) -> EXTI3_R

Bit 1 - EXTI3

impl R<u32, Reg<u32, _ITLINE7>>

pub fn exti4(&self) -> EXTI4_R

Bit 0 - EXTI4

pub fn exti5(&self) -> EXTI5_R

Bit 1 - EXTI5

pub fn exti6(&self) -> EXTI6_R

Bit 2 - EXTI6

pub fn exti7(&self) -> EXTI7_R

Bit 3 - EXTI7

pub fn exti8(&self) -> EXTI8_R

Bit 4 - EXTI8

pub fn exti9(&self) -> EXTI9_R

Bit 5 - EXTI9

pub fn exti10(&self) -> EXTI10_R

Bit 6 - EXTI10

pub fn exti11(&self) -> EXTI11_R

Bit 7 - EXTI11

pub fn exti12(&self) -> EXTI12_R

Bit 8 - EXTI12

pub fn exti13(&self) -> EXTI13_R

Bit 9 - EXTI13

pub fn exti14(&self) -> EXTI14_R

Bit 10 - EXTI14

pub fn exti15(&self) -> EXTI15_R

Bit 11 - EXTI15

impl R<u32, Reg<u32, _ITLINE9>>

pub fn dma1_ch1(&self) -> DMA1_CH1_R

Bit 0 - DMA1_CH1

impl R<u32, Reg<u32, _ITLINE10>>

pub fn dma1_ch2(&self) -> DMA1_CH2_R

Bit 0 - DMA1_CH1

pub fn dma1_ch3(&self) -> DMA1_CH3_R

Bit 1 - DMA1_CH3

impl R<u32, Reg<u32, _ITLINE11>>

pub fn dmamux(&self) -> DMAMUX_R

Bit 0 - DMAMUX

pub fn dma1_ch4(&self) -> DMA1_CH4_R

Bit 1 - DMA1_CH4

pub fn dma1_ch5(&self) -> DMA1_CH5_R

Bit 2 - DMA1_CH5

impl R<u32, Reg<u32, _ITLINE12>>

pub fn adc(&self) -> ADC_R

Bit 0 - ADC

impl R<u32, Reg<u32, _ITLINE13>>

pub fn tim1_ccu(&self) -> TIM1_CCU_R

Bit 0 - TIM1_CCU

pub fn tim1_trg(&self) -> TIM1_TRG_R

Bit 1 - TIM1_TRG

pub fn tim1_upd(&self) -> TIM1_UPD_R

Bit 2 - TIM1_UPD

pub fn tim1_brk(&self) -> TIM1_BRK_R

Bit 3 - TIM1_BRK

impl R<u32, Reg<u32, _ITLINE14>>

pub fn tim1_cc(&self) -> TIM1_CC_R

Bit 0 - TIM1_CC

impl R<u32, Reg<u32, _ITLINE15>>

pub fn tim2(&self) -> TIM2_R

Bit 0 - TIM2

impl R<u32, Reg<u32, _ITLINE16>>

pub fn tim3(&self) -> TIM3_R

Bit 0 - TIM3

impl R<u32, Reg<u32, _ITLINE19>>

pub fn tim14(&self) -> TIM14_R

Bit 0 - TIM14

impl R<u32, Reg<u32, _ITLINE21>>

pub fn tim16(&self) -> TIM16_R

Bit 0 - TIM16

impl R<u32, Reg<u32, _ITLINE22>>

pub fn tim17(&self) -> TIM17_R

Bit 0 - TIM17

impl R<u32, Reg<u32, _ITLINE23>>

pub fn i2c1(&self) -> I2C1_R

Bit 0 - I2C1

impl R<u32, Reg<u32, _ITLINE24>>

pub fn i2c2(&self) -> I2C2_R

Bit 0 - I2C2

impl R<u32, Reg<u32, _ITLINE25>>

pub fn spi1(&self) -> SPI1_R

Bit 0 - SPI1

impl R<u32, Reg<u32, _ITLINE26>>

pub fn spi2(&self) -> SPI2_R

Bit 0 - SPI2

impl R<u32, Reg<u32, _ITLINE27>>

pub fn usart1(&self) -> USART1_R

Bit 0 - USART1

impl R<u32, Reg<u32, _ITLINE28>>

pub fn usart2(&self) -> USART2_R

Bit 0 - USART2

impl R<u32, Reg<u32, _ITLINE29>>

pub fn usart5(&self) -> USART5_R

Bit 2 - USART5

impl R<u32, Reg<u32, _PR>>

pub fn pr(&self) -> PR_R

Bits 0:2 - Prescaler divider

impl R<u32, Reg<u32, _RLR>>

pub fn rl(&self) -> RL_R

Bits 0:11 - Watchdog counter reload value

impl R<u32, Reg<u32, _SR>>

pub fn wvu(&self) -> WVU_R

Bit 2 - Watchdog counter window value update

pub fn rvu(&self) -> RVU_R

Bit 1 - Watchdog counter reload value update

pub fn pvu(&self) -> PVU_R

Bit 0 - Watchdog prescaler value update

impl R<u32, Reg<u32, _WINR>>

pub fn win(&self) -> WIN_R

Bits 0:11 - Watchdog counter window value

impl R<u32, Reg<u32, _CR>>

pub fn wdga(&self) -> WDGA_R

Bit 7 - Activation bit

pub fn t(&self) -> T_R

Bits 0:6 - 7-bit counter (MSB to LSB)

impl R<u32, Reg<u32, _CFR>>

pub fn wdgtb(&self) -> WDGTB_R

Bits 11:13 - Timer base

pub fn ewi(&self) -> EWI_R

Bit 9 - Early wakeup interrupt

pub fn w(&self) -> W_R

Bits 0:6 - 7-bit window value

impl R<u32, Reg<u32, _SR>>

pub fn ewif(&self) -> EWIF_R

Bit 0 - Early wakeup interrupt flag

impl R<u32, Reg<u32, _ACR>>

pub fn latency(&self) -> LATENCY_R

Bits 0:2 - Latency

pub fn prften(&self) -> PRFTEN_R

Bit 8 - Prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - Instruction cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - Instruction cache reset

pub fn empty(&self) -> EMPTY_R

Bit 16 - Flash User area empty

pub fn dbg_swen(&self) -> DBG_SWEN_R

Bit 18 - Debug access software enable

impl R<u32, Reg<u32, _SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - Write protected error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn miserr(&self) -> MISERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn optverr(&self) -> OPTVERR_R

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy.

impl R<u32, Reg<u32, _CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - Mass erase

pub fn pnb(&self) -> PNB_R

Bits 3:8 - Page number

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn optstrt(&self) -> OPTSTRT_R

Bit 17 - Options modification start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&self) -> OBL_LAUNCH_R

Bit 27 - Force the option byte loading

pub fn sec_prot(&self) -> SEC_PROT_R

Bit 28 - Securable memory area protection enable

pub fn optlock(&self) -> OPTLOCK_R

Bit 30 - Options Lock

pub fn lock(&self) -> LOCK_R

Bit 31 - FLASH_CR Lock

impl R<u32, Reg<u32, _ECCR>>

pub fn addr_ecc(&self) -> ADDR_ECC_R

Bits 0:13 - ECC fail address

pub fn sysf_ecc(&self) -> SYSF_ECC_R

Bit 20 - ECC fail for Corrected ECC Error or Double ECC Error in info block

pub fn eccie(&self) -> ECCIE_R

Bit 24 - ECC correction interrupt enable

pub fn eccc(&self) -> ECCC_R

Bit 30 - ECC correction

pub fn eccd(&self) -> ECCD_R

Bit 31 - ECC detection

impl R<u32, Reg<u32, _OPTR>>

pub fn rdp(&self) -> RDP_R

Bits 0:7 - Read protection level

pub fn boren(&self) -> BOREN_R

Bit 8 - BOR reset Level

pub fn borf_lev(&self) -> BORF_LEV_R

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&self) -> BORR_LEV_R

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&self) -> NRST_STOP_R

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&self) -> NRST_STDBY_R

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&self) -> NRSTS_HDW_R

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&self) -> IDWG_SW_R

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&self) -> IWDG_STOP_R

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&self) -> IWDG_STDBY_R

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&self) -> WWDG_SW_R

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&self) -> RAM_PARITY_CHECK_R

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&self) -> NBOOT_SEL_R

Bit 24 - nBOOT_SEL

pub fn n_boot1(&self) -> NBOOT1_R

Bit 25 - Boot configuration

pub fn n_boot0(&self) -> NBOOT0_R

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&self) -> NRST_MODE_R

Bits 27:28 - NRST_MODE

pub fn irhen(&self) -> IRHEN_R

Bit 29 - Internal reset holder enable bit

impl R<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R

Bits 0:7 - PCROP1A area start offset

impl R<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&self) -> PCROP1A_END_R

Bits 0:7 - PCROP1A area end offset

pub fn pcrop_rdp(&self) -> PCROP_RDP_R

Bit 31 - PCROP area preserved when RDP level decreased

impl R<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&self) -> WRP1A_STRT_R

Bits 0:5 - WRP area A start offset

pub fn wrp1a_end(&self) -> WRP1A_END_R

Bits 16:21 - WRP area A end offset

impl R<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&self) -> WRP1B_STRT_R

Bits 0:5 - WRP area B start offset

pub fn wrp1b_end(&self) -> WRP1B_END_R

Bits 16:21 - WRP area B end offset

impl R<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R

Bits 0:7 - PCROP1B area start offset

impl R<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&self) -> PCROP1B_END_R

Bits 0:7 - PCROP1B area end offset

impl R<u32, Reg<u32, _SECR>>

pub fn sec_size(&self) -> SEC_SIZE_R

Bits 0:6 - Securable memory area size

pub fn boot_lock(&self) -> BOOT_LOCK_R

Bit 16 - used to force boot from user area

impl R<u32, Reg<u32, _CR>>

pub fn hsion(&self) -> HSION_R

Bit 8 - HSI16 clock enable

pub fn hsikeron(&self) -> HSIKERON_R

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&self) -> HSIRDY_R

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&self) -> HSIDIV_R

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&self) -> HSEON_R

Bit 16 - HSE clock enable

pub fn hserdy(&self) -> HSERDY_R

Bit 17 - HSE clock ready flag

pub fn hsebyp(&self) -> HSEBYP_R

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&self) -> CSSON_R

Bit 19 - Clock security system enable

pub fn pllon(&self) -> PLLON_R

Bit 24 - PLL enable

pub fn pllrdy(&self) -> PLLRDY_R

Bit 25 - PLL clock ready flag

impl R<u32, Reg<u32, _ICSCR>>

pub fn hsical(&self) -> HSICAL_R

Bits 0:7 - HSI16 clock calibration

pub fn hsitrim(&self) -> HSITRIM_R

Bits 8:14 - HSI16 clock trimming

impl R<u32, Reg<u32, _CFGR>>

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&self) -> MCOSEL_R

Bits 24:26 - Microcontroller clock output

pub fn ppre(&self) -> PPRE_R

Bits 12:14 - APB prescaler

pub fn hpre(&self) -> HPRE_R

Bits 8:11 - AHB prescaler

pub fn sws(&self) -> SWS_R

Bits 3:5 - System clock switch status

pub fn sw(&self) -> SW_R

Bits 0:2 - System clock switch

impl R<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - PLL input clock source

pub fn pllm(&self) -> PLLM_R

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&self) -> PLLN_R

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&self) -> PLLREN_R

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl R<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&self) -> LSIRDYIE_R

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&self) -> LSERDYIE_R

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&self) -> HSIRDYIE_R

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&self) -> HSERDYIE_R

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&self) -> PLLSYSRDYIE_R

Bit 5 - PLL ready interrupt enable

impl R<u32, Reg<u32, _CIFR>>

pub fn lsirdyf(&self) -> LSIRDYF_R

Bit 0 - LSI ready interrupt flag

pub fn lserdyf(&self) -> LSERDYF_R

Bit 1 - LSE ready interrupt flag

pub fn hsirdyf(&self) -> HSIRDYF_R

Bit 3 - HSI ready interrupt flag

pub fn hserdyf(&self) -> HSERDYF_R

Bit 4 - HSE ready interrupt flag

pub fn pllsysrdyf(&self) -> PLLSYSRDYF_R

Bit 5 - PLL ready interrupt flag

pub fn cssf(&self) -> CSSF_R

Bit 8 - Clock security system interrupt flag

pub fn lsecssf(&self) -> LSECSSF_R

Bit 9 - LSE Clock security system interrupt flag

impl R<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&self) -> DMARST_R

Bit 0 - DMA1 reset

pub fn flashrst(&self) -> FLASHRST_R

Bit 8 - FLITF reset

pub fn crcrst(&self) -> CRCRST_R

Bit 12 - CRC reset

impl R<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&self) -> IOPARST_R

Bit 0 - I/O port A reset

pub fn iopbrst(&self) -> IOPBRST_R

Bit 1 - I/O port B reset

pub fn iopcrst(&self) -> IOPCRST_R

Bit 2 - I/O port C reset

pub fn iopdrst(&self) -> IOPDRST_R

Bit 3 - I/O port D reset

pub fn iopfrst(&self) -> IOPFRST_R

Bit 5 - I/O port F reset

impl R<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&self) -> TIM2RST_R

Bit 0 - TIM2 timer reset

pub fn tim3rst(&self) -> TIM3RST_R

Bit 1 - TIM3 timer reset

pub fn spi2rst(&self) -> SPI2RST_R

Bit 14 - SPI2 reset

pub fn usart2rst(&self) -> USART2RST_R

Bit 17 - USART2 reset

pub fn lpuart1rst(&self) -> LPUART1RST_R

Bit 20 - LPUART1 reset

pub fn i2c1rst(&self) -> I2C1RST_R

Bit 21 - I2C1 reset

pub fn i2c2rst(&self) -> I2C2RST_R

Bit 22 - I2C2 reset

pub fn dbgrst(&self) -> DBGRST_R

Bit 27 - Debug support reset

pub fn pwrrst(&self) -> PWRRST_R

Bit 28 - Power interface reset

pub fn lptim2rst(&self) -> LPTIM2RST_R

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&self) -> LPTIM1RST_R

Bit 31 - Low Power Timer 1 reset

impl R<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&self) -> SYSCFGRST_R

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&self) -> TIM1RST_R

Bit 11 - TIM1 timer reset

pub fn spi1rst(&self) -> SPI1RST_R

Bit 12 - SPI1 reset

pub fn usart1rst(&self) -> USART1RST_R

Bit 14 - USART1 reset

pub fn tim14rst(&self) -> TIM14RST_R

Bit 15 - TIM14 timer reset

pub fn tim16rst(&self) -> TIM16RST_R

Bit 17 - TIM16 timer reset

pub fn tim17rst(&self) -> TIM17RST_R

Bit 18 - TIM17 timer reset

pub fn adcrst(&self) -> ADCRST_R

Bit 20 - ADC reset

impl R<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&self) -> IOPAEN_R

Bit 0 - I/O port A clock enable

pub fn iopben(&self) -> IOPBEN_R

Bit 1 - I/O port B clock enable

pub fn iopcen(&self) -> IOPCEN_R

Bit 2 - I/O port C clock enable

pub fn iopden(&self) -> IOPDEN_R

Bit 3 - I/O port D clock enable

pub fn iopfen(&self) -> IOPFEN_R

Bit 5 - I/O port F clock enable

impl R<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - DMA clock enable

pub fn flashen(&self) -> FLASHEN_R

Bit 8 - Flash memory interface clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CRC clock enable

impl R<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&self) -> TIM2EN_R

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&self) -> TIM3EN_R

Bit 1 - TIM3 timer clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - RTC APB clock enable

pub fn wwdgen(&self) -> WWDGEN_R

Bit 11 - WWDG clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - SPI2 clock enable

pub fn usart2en(&self) -> USART2EN_R

Bit 17 - USART2 clock enable

pub fn lpuart1en(&self) -> LPUART1EN_R

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - I2C1 clock enable

pub fn i2c2en(&self) -> I2C2EN_R

Bit 22 - I2C2 clock enable

pub fn dbgen(&self) -> DBGEN_R

Bit 27 - Debug support clock enable

pub fn pwren(&self) -> PWREN_R

Bit 28 - Power interface clock enable

pub fn lptim2en(&self) -> LPTIM2EN_R

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&self) -> LPTIM1EN_R

Bit 31 - LPTIM1 clock enable

impl R<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&self) -> SYSCFGEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - SPI1 clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - USART1 clock enable

pub fn tim14en(&self) -> TIM14EN_R

Bit 15 - TIM14 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - TIM16 timer clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 20 - ADC clock enable

impl R<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&self) -> IOPASMEN_R

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&self) -> IOPBSMEN_R

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&self) -> IOPCSMEN_R

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&self) -> IOPDSMEN_R

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&self) -> IOPFSMEN_R

Bit 5 - I/O port F clock enable during Sleep mode

impl R<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&self) -> DMASMEN_R

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&self) -> SRAMSMEN_R

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CRC clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&self) -> TIM2SMEN_R

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&self) -> TIM3SMEN_R

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&self) -> WWDGSMEN_R

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&self) -> USART2SMEN_R

Bit 17 - USART2 clock enable during Sleep mode

pub fn lpuart1smen(&self) -> LPUART1SMEN_R

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&self) -> I2C2SMEN_R

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&self) -> DBGSMEN_R

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&self) -> PWRSMEN_R

Bit 28 - Power interface clock enable during Sleep mode

pub fn lptim2smen(&self) -> LPTIM2SMEN_R

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&self) -> LPTIM1SMEN_R

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&self) -> SYSCFGSMEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&self) -> TIM14SMEN_R

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&self) -> ADCSMEN_R

Bit 20 - ADC clock enable during Sleep mode

impl R<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&self) -> USART1SEL_R

Bits 0:1 - USART1 clock source selection

pub fn lpuart1sel(&self) -> LPUART1SEL_R

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&self) -> I2C1SEL_R

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&self) -> I2S2SEL_R

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&self) -> LPTIM1SEL_R

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&self) -> LPTIM2SEL_R

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&self) -> TIM1SEL_R

Bit 22 - TIM1 clock source selection

pub fn rngsel(&self) -> RNGSEL_R

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&self) -> RNGDIV_R

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&self) -> ADCSEL_R

Bits 30:31 - ADCs clock source selection

impl R<u32, Reg<u32, _BDCR>>

pub fn lseon(&self) -> LSEON_R

Bit 0 - LSE oscillator enable

pub fn lserdy(&self) -> LSERDY_R

Bit 1 - LSE oscillator ready

pub fn lsebyp(&self) -> LSEBYP_R

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&self) -> LSEDRV_R

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&self) -> LSECSSON_R

Bit 5 - CSS on LSE enable

pub fn lsecssd(&self) -> LSECSSD_R

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&self) -> RTCSEL_R

Bits 8:9 - RTC clock source selection

pub fn rtcen(&self) -> RTCEN_R

Bit 15 - RTC clock enable

pub fn bdrst(&self) -> BDRST_R

Bit 16 - RTC domain software reset

pub fn lscoen(&self) -> LSCOEN_R

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&self) -> LSCOSEL_R

Bit 25 - Low-speed clock output selection

impl R<u32, Reg<u32, _CSR>>

pub fn lsion(&self) -> LSION_R

Bit 0 - LSI oscillator enable

pub fn lsirdy(&self) -> LSIRDY_R

Bit 1 - LSI oscillator ready

pub fn rmvf(&self) -> RMVF_R

Bit 23 - Remove reset flags

pub fn oblrstf(&self) -> OBLRSTF_R

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&self) -> PINRSTF_R

Bit 26 - Pin reset flag

pub fn pwrrstf(&self) -> PWRRSTF_R

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&self) -> SFTRSTF_R

Bit 28 - Software reset flag

pub fn iwdgrstf(&self) -> IWDGRSTF_R

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&self) -> WWDGRSTF_R

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&self) -> LPWRRSTF_R

Bit 31 - Low-power reset flag

impl R<u32, Reg<u32, _CR1>>

pub fn lpr(&self) -> LPR_R

Bit 14 - Low-power run

pub fn vos(&self) -> VOS_R

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&self) -> DBP_R

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&self) -> FPD_LPSLP_R

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&self) -> FPD_LPRUN_R

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&self) -> FPD_STOP_R

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection

impl R<u32, Reg<u32, _CR2>>

pub fn pvde(&self) -> PVDE_R

Bit 0 - Power voltage detector enable

pub fn pvdft(&self) -> PVDFT_R

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&self) -> PVDRT_R

Bits 4:6 - Power voltage detector rising threshold selection

impl R<u32, Reg<u32, _CR3>>

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&self) -> EWUP6_R

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&self) -> RRS_R

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&self) -> ULPEN_R

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&self) -> APC_R

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line

impl R<u32, Reg<u32, _CR4>>

pub fn wp1(&self) -> WP1_R

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&self) -> WP2_R

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&self) -> WP4_R

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&self) -> WP5_R

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&self) -> WP6_R

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&self) -> VBE_R

Bit 8 - VBAT battery charging enable

pub fn vbrs(&self) -> VBRS_R

Bit 9 - VBAT battery charging resistor selection

impl R<u32, Reg<u32, _SR1>>

pub fn wuf1(&self) -> WUF1_R

Bit 0 - Wakeup flag 1

pub fn wuf2(&self) -> WUF2_R

Bit 1 - Wakeup flag 2

pub fn wuf4(&self) -> WUF4_R

Bit 3 - Wakeup flag 4

pub fn wuf5(&self) -> WUF5_R

Bit 4 - Wakeup flag 5

pub fn wuf6(&self) -> WUF6_R

Bit 5 - Wakeup flag 6

pub fn sbf(&self) -> SBF_R

Bit 8 - Standby flag

pub fn wufi(&self) -> WUFI_R

Bit 15 - Wakeup flag internal

impl R<u32, Reg<u32, _SR2>>

pub fn pvdo(&self) -> PVDO_R

Bit 11 - Power voltage detector output

pub fn vosf(&self) -> VOSF_R

Bit 10 - Voltage scaling flag

pub fn reglpf(&self) -> REGLPF_R

Bit 9 - Low-power regulator flag

pub fn reglps(&self) -> REGLPS_R

Bit 8 - Low-power regulator started

pub fn flash_rdy(&self) -> FLASH_RDY_R

Bit 7 - Flash ready flag

impl R<u32, Reg<u32, _PUCRA>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port A pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRA>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port A pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRB>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port B pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRB>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port B pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRC>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port C pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRC>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port C pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRD>>

pub fn pu3(&self) -> PU3_R

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port D pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRD>>

pub fn pd9(&self) -> PD9_R

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port D pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRF>>

pub fn pu2(&self) -> PU2_R

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port F pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRF>>

pub fn pd2(&self) -> PD2_R

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port F pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _CR>>

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

impl R<u32, Reg<u32, _NDTR>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _PAR>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _MAR>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _ISR>>

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel 1 global interrupt flag

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel 1 transfer complete flag

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel 1 half transfer flag

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel 1 transfer error flag

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel 2 global interrupt flag

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel 2 transfer complete flag

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel 2 half transfer flag

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel 2 transfer error flag

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel 3 global interrupt flag

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel 3 transfer complete flag

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel 3 half transfer flag

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel 3 transfer error flag

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel 4 global interrupt flag

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel 4 transfer complete flag

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel 4 half transfer flag

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel 4 transfer error flag

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel 5 global interrupt flag

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel 5 transfer complete flag

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel 5 half transfer flag

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel 5 transfer error flag

impl R<u32, Reg<u32, _C0CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C1CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C2CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C3CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C4CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C5CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C6CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _RG0CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG1CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG2CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG3CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RGSR>>

pub fn of(&self) -> OF_R

Bits 0:3 - Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:31 - Data register bits

impl R<u32, Reg<u32, _IDR>>

pub fn idr(&self) -> IDR_R

Bits 0:31 - General-purpose 32-bit data register bits

impl R<u32, Reg<u32, _CR>>

pub fn rev_out(&self) -> REV_OUT_R

Bit 7 - Reverse output data

pub fn rev_in(&self) -> REV_IN_R

Bits 5:6 - Reverse input data

pub fn polysize(&self) -> POLYSIZE_R

Bits 3:4 - Polynomial size

impl R<u32, Reg<u32, _INIT>>

pub fn crc_init(&self) -> CRC_INIT_R

Bits 0:31 - Programmable initial CRC value

impl R<u32, Reg<u32, _POL>>

pub fn pol(&self) -> POL_R

Bits 0:31 - Programmable polynomial

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _RTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _FTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, SWIER0_A>

pub fn variant(&self) -> Variant<bool, SWIER0_A>

Get enumerated values variant

pub fn is_pend(&self) -> bool

Checks if the value of the field is PEND

impl R<u32, Reg<u32, _SWIER1>>

pub fn swier0(&self) -> SWIER0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&self) -> SWIER1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&self) -> SWIER2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&self) -> SWIER3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&self) -> SWIER4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&self) -> SWIER5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&self) -> SWIER6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&self) -> SWIER7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&self) -> SWIER8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&self) -> SWIER9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&self) -> SWIER10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&self) -> SWIER11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&self) -> SWIER12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&self) -> SWIER13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&self) -> SWIER14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&self) -> SWIER15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&self) -> SWIER16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, RPIF0_A>

pub fn variant(&self) -> RPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _RPR1>>

pub fn rpif0(&self) -> RPIF0_R

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&self) -> RPIF1_R

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&self) -> RPIF2_R

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&self) -> RPIF3_R

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&self) -> RPIF4_R

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&self) -> RPIF5_R

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&self) -> RPIF6_R

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&self) -> RPIF7_R

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&self) -> RPIF8_R

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&self) -> RPIF9_R

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&self) -> RPIF10_R

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&self) -> RPIF11_R

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&self) -> RPIF12_R

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&self) -> RPIF13_R

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&self) -> RPIF14_R

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&self) -> RPIF15_R

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&self) -> RPIF16_R

Bit 16 - configurable event inputs x rising edge Pending bit.

impl R<bool, FPIF0_A>

pub fn variant(&self) -> FPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _FPR1>>

pub fn fpif0(&self) -> FPIF0_R

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&self) -> FPIF1_R

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&self) -> FPIF2_R

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&self) -> FPIF3_R

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&self) -> FPIF4_R

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&self) -> FPIF5_R

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&self) -> FPIF6_R

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&self) -> FPIF7_R

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&self) -> FPIF8_R

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&self) -> FPIF9_R

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&self) -> FPIF10_R

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&self) -> FPIF11_R

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&self) -> FPIF12_R

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&self) -> FPIF13_R

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&self) -> FPIF14_R

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&self) -> FPIF15_R

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&self) -> FPIF16_R

Bit 16 - configurable event inputs x falling edge pending bit.

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<bool, IM0_A>

pub fn variant(&self) -> IM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR1>>

pub fn im0(&self) -> IM0_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&self) -> IM1_R

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&self) -> IM2_R

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&self) -> IM3_R

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&self) -> IM4_R

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&self) -> IM5_R

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&self) -> IM6_R

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&self) -> IM7_R

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&self) -> IM8_R

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&self) -> IM9_R

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&self) -> IM10_R

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&self) -> IM11_R

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&self) -> IM12_R

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&self) -> IM13_R

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&self) -> IM14_R

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&self) -> IM15_R

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&self) -> IM16_R

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im19(&self) -> IM19_R

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&self) -> IM20_R

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&self) -> IM21_R

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&self) -> IM22_R

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&self) -> IM23_R

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&self) -> IM24_R

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&self) -> IM25_R

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&self) -> IM26_R

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im28(&self) -> IM28_R

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&self) -> IM29_R

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&self) -> IM30_R

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&self) -> IM31_R

Bit 31 - CPU wakeup with interrupt mask on event input

impl R<bool, EM0_A>

pub fn variant(&self) -> EM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR1>>

pub fn em0(&self) -> EM0_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&self) -> EM1_R

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&self) -> EM2_R

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&self) -> EM3_R

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&self) -> EM4_R

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&self) -> EM5_R

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&self) -> EM6_R

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&self) -> EM7_R

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&self) -> EM8_R

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&self) -> EM9_R

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&self) -> EM10_R

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&self) -> EM11_R

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&self) -> EM12_R

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&self) -> EM13_R

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&self) -> EM14_R

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&self) -> EM15_R

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&self) -> EM16_R

Bit 16 - CPU wakeup with event mask on event input

pub fn em19(&self) -> EM19_R

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&self) -> EM21_R

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&self) -> EM23_R

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&self) -> EM25_R

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&self) -> EM26_R

Bit 26 - CPU wakeup with event mask on event input

pub fn em28(&self) -> EM28_R

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&self) -> EM29_R

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&self) -> EM30_R

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&self) -> EM31_R

Bit 31 - CPU wakeup with event mask on event input

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&self) -> BKDFBK1E_R

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - selects input

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT

pub fn dedt(&self) -> DEDT_R

Bits 16:20 - DEDT

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn rtoen(&self) -> RTOEN_R

Bit 23 - Receiver timeout enable

pub fn abrmod(&self) -> ABRMOD_R

Bits 21:22 - Auto baud rate mode

pub fn abren(&self) -> ABREN_R

Bit 20 - Auto baud rate enable

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn linen(&self) -> LINEN_R

Bit 14 - LIN mode enable

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn clken(&self) -> CLKEN_R

Bit 11 - Clock enable

pub fn cpol(&self) -> CPOL_R

Bit 10 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 9 - Clock phase

pub fn lbcl(&self) -> LBCL_R

Bit 8 - Last bit clock pulse

pub fn lbdie(&self) -> LBDIE_R

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&self) -> LBDL_R

Bit 5 - LIN break detection length

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&self) -> DIS_NSS_R

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&self) -> SLVEN_R

Bit 0 - Synchronous Slave mode enable

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&self) -> TCBGTIE_R

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&self) -> SCARCNT_R

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn onebit(&self) -> ONEBIT_R

Bit 11 - One sample bit method enable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn scen(&self) -> SCEN_R

Bit 5 - Smartcard mode enable

pub fn nack(&self) -> NACK_R

Bit 4 - Smartcard NACK enable

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn irlp(&self) -> IRLP_R

Bit 2 - Ir low-power

pub fn iren(&self) -> IREN_R

Bit 1 - Ir mode enable

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&self) -> BRR_4_15_R

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&self) -> BRR_0_3_R

Bits 0:3 - BRR_0_3

impl R<u32, Reg<u32, _GTPR>>

pub fn gt(&self) -> GT_R

Bits 8:15 - Guard time value

pub fn psc(&self) -> PSC_R

Bits 0:7 - Prescaler value

impl R<u32, Reg<u32, _RTOR>>

pub fn blen(&self) -> BLEN_R

Bits 24:31 - Block Length

pub fn rto(&self) -> RTO_R

Bits 0:23 - Receiver timeout value

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn tcbgt(&self) -> TCBGT_R

Bit 25 - Transmission complete before guard time flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn abrf(&self) -> ABRF_R

Bit 15 - ABRF

pub fn abre(&self) -> ABRE_R

Bit 14 - ABRE

pub fn udr(&self) -> UDR_R

Bit 13 - SPI slave underrun error flag

pub fn eobf(&self) -> EOBF_R

Bit 12 - EOBF

pub fn rtof(&self) -> RTOF_R

Bit 11 - RTOF

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn lbdf(&self) -> LBDF_R

Bit 8 - LBDF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn bidimode(&self) -> BIDIMODE_R

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&self) -> BIDIOE_R

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&self) -> CRCEN_R

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&self) -> CRCNEXT_R

Bit 12 - CRC transfer next

pub fn dff(&self) -> DFF_R

Bit 11 - Data frame format

pub fn rxonly(&self) -> RXONLY_R

Bit 10 - Receive only

pub fn ssm(&self) -> SSM_R

Bit 9 - Software slave management

pub fn ssi(&self) -> SSI_R

Bit 8 - Internal slave select

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 7 - Frame format

pub fn spe(&self) -> SPE_R

Bit 6 - SPI enable

pub fn br(&self) -> BR_R

Bits 3:5 - Baud rate control

pub fn mstr(&self) -> MSTR_R

Bit 2 - Master selection

pub fn cpol(&self) -> CPOL_R

Bit 1 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 0 - Clock phase

impl R<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&self) -> SSOE_R

Bit 2 - SS output enable

pub fn nssp(&self) -> NSSP_R

Bit 3 - NSS pulse management

pub fn frf(&self) -> FRF_R

Bit 4 - Frame format

pub fn errie(&self) -> ERRIE_R

Bit 5 - Error interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&self) -> DS_R

Bits 8:11 - Data size

pub fn frxth(&self) -> FRXTH_R

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&self) -> LDMA_RX_R

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&self) -> LDMA_TX_R

Bit 14 - Last DMA transfer for transmission

impl R<u32, Reg<u32, _SR>>

pub fn rxne(&self) -> RXNE_R

Bit 0 - Receive buffer not empty

pub fn txe(&self) -> TXE_R

Bit 1 - Transmit buffer empty

pub fn chside(&self) -> CHSIDE_R

Bit 2 - Channel side

pub fn udr(&self) -> UDR_R

Bit 3 - Underrun flag

pub fn crcerr(&self) -> CRCERR_R

Bit 4 - CRC error flag

pub fn modf(&self) -> MODF_R

Bit 5 - Mode fault

pub fn ovr(&self) -> OVR_R

Bit 6 - Overrun flag

pub fn bsy(&self) -> BSY_R

Bit 7 - Busy flag

pub fn tifrfe(&self) -> TIFRFE_R

Bit 8 - TI frame format error

pub fn frlvl(&self) -> FRLVL_R

Bits 9:10 - FIFO reception level

pub fn ftlvl(&self) -> FTLVL_R

Bits 11:12 - FIFO transmission level

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:15 - Data register

impl R<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&self) -> CRCPOLY_R

Bits 0:15 - CRC polynomial register

impl R<u32, Reg<u32, _RXCRCR>>

pub fn rx_crc(&self) -> RXCRC_R

Bits 0:15 - Rx CRC register

impl R<u32, Reg<u32, _TXCRCR>>

pub fn tx_crc(&self) -> TXCRC_R

Bits 0:15 - Tx CRC register

impl R<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&self) -> CHLEN_R

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&self) -> DATLEN_R

Bits 1:2 - Data length to be transferred

pub fn ckpol(&self) -> CKPOL_R

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&self) -> I2SSTD_R

Bits 4:5 - standard selection

pub fn pcmsync(&self) -> PCMSYNC_R

Bit 7 - PCM frame synchronization

pub fn i2scfg(&self) -> I2SCFG_R

Bits 8:9 - I2S configuration mode

pub fn se2(&self) -> SE2_R

Bit 10 - I2S enable

pub fn i2smod(&self) -> I2SMOD_R

Bit 11 - I2S mode selection

impl R<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&self) -> I2SDIV_R

Bits 0:7 - linear prescaler

pub fn odd(&self) -> ODD_R

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&self) -> MCKOE_R

Bit 9 - Master clock output enable

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn ts_4(&self) -> TS_4_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn ts(&self) -> TS_R

Bits 20:21 - Trigger selection

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag

pub fn cc5if(&self) -> CC5IF_R

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&self) -> CC6IF_R

Bit 17 - Compare 6 interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

impl R<u32, Reg<u32, _CCER>>

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&self) -> CC2NE_R

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&self) -> CC3NE_R

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&self) -> CC5E_R

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&self) -> CC5P_R

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&self) -> CC6E_R

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&self) -> CC6P_R

Bit 21 - Capture/Compare 6 output polarity

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:15 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3(&self) -> CCR3_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4(&self) -> CCR4_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bk2f(&self) -> BK2F_R

Bits 20:23 - Break 2 filter

pub fn bk2e(&self) -> BK2E_R

Bit 24 - Break 2 enable

pub fn bk2p(&self) -> BK2P_R

Bit 25 - Break 2 polarity

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bk2dsrm(&self) -> BK2DSRM_R

Bit 27 - Break2 Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

pub fn bk2id(&self) -> BK2ID_R

Bit 29 - Break2 bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&self) -> OCREF_CLR_R

Bit 0 - Ocref_clr source selection

impl R<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&self) -> OC6M_BIT3_R

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&self) -> OC5M_BIT3_R

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&self) -> OC6CE_R

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&self) -> OC6M_R

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&self) -> OC6PE_R

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&self) -> OC6FE_R

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&self) -> OC5CE_R

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&self) -> OC5M_R

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&self) -> OC5PE_R

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&self) -> OC5FE_R

Bit 2 - Output compare 5 fast enable

impl R<u32, Reg<u32, _CCR5>>

pub fn ccr5(&self) -> CCR5_R

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&self) -> GC5C1_R

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&self) -> GC5C2_R

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&self) -> GC5C3_R

Bit 31 - Group Channel 5 and Channel 3

impl R<u32, Reg<u32, _CCR6>>

pub fn ccr6(&self) -> CCR6_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - ETR source selection

impl R<u32, Reg<u32, _AF2>>

pub fn bk2ine(&self) -> BK2INE_R

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&self) -> BK2CMP1E_R

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&self) -> BK2CMP2E_R

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&self) -> BK2INP_R

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&self) -> BK2CMP1P_R

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&self) -> BK2CMP2P_R

Bit 11 - BRK2 COMP2 input polarity

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel3_0(&self) -> TI1SEL3_0_R

Bits 0:3 - selects TI1[0] to TI1[15] input

pub fn ti2sel3_0(&self) -> TI2SEL3_0_R

Bits 8:11 - selects TI2[0] to TI2[15] input

pub fn ti3sel3_0(&self) -> TI3SEL3_0_R

Bits 16:19 - selects TI3[0] to TI3[15] input

pub fn ti4sel3_0(&self) -> TI4SEL3_0_R

Bits 24:27 - selects TI4[0] to TI4[15] input

impl R<u32, Reg<u32, _ISR>>

pub fn ccrdy(&self) -> CCRDY_R

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&self) -> EOCAL_R

Bit 11 - End Of Calibration flag

pub fn awd3(&self) -> AWD3_R

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&self) -> AWD2_R

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&self) -> AWD1_R

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&self) -> OVR_R

Bit 4 - ADC group regular overrun flag

pub fn eos(&self) -> EOS_R

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&self) -> EOC_R

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&self) -> EOSMP_R

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&self) -> ADRDY_R

Bit 0 - ADC ready flag

impl R<u32, Reg<u32, _IER>>

pub fn ccrdyie(&self) -> CCRDYIE_R

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&self) -> EOCALIE_R

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&self) -> AWD3IE_R

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&self) -> AWD2IE_R

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&self) -> AWD1IE_R

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&self) -> OVRIE_R

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&self) -> EOSIE_R

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&self) -> EOCIE_R

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&self) -> EOSMPIE_R

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&self) -> ADRDYIE_R

Bit 0 - ADC ready interrupt

impl R<u32, Reg<u32, _CR>>

pub fn adcal(&self) -> ADCAL_R

Bit 31 - ADC calibration

pub fn advregen(&self) -> ADVREGEN_R

Bit 28 - ADC voltage regulator enable

pub fn adstp(&self) -> ADSTP_R

Bit 4 - ADC group regular conversion stop

pub fn adstart(&self) -> ADSTART_R

Bit 2 - ADC group regular conversion start

pub fn addis(&self) -> ADDIS_R

Bit 1 - ADC disable

pub fn aden(&self) -> ADEN_R

Bit 0 - ADC enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&self) -> AWDCH1CH_R

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&self) -> AWD1EN_R

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGL_R

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&self) -> CHSELRMOD_R

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&self) -> DISCEN_R

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&self) -> AUTOFF_R

Bit 15 - Auto-off mode

pub fn wait(&self) -> WAIT_R

Bit 14 - Wait conversion mode

pub fn cont(&self) -> CONT_R

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMOD_R

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTEN_R

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSEL_R

Bits 6:8 - ADC group regular external trigger source

pub fn align(&self) -> ALIGN_R

Bit 5 - ADC data alignement

pub fn res(&self) -> RES_R

Bits 3:4 - ADC data resolution

pub fn scandir(&self) -> SCANDIR_R

Bit 2 - Scan sequence direction

pub fn dmacfg(&self) -> DMACFG_R

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - ADC DMA transfer enable

impl R<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&self) -> CKMODE_R

Bits 30:31 - ADC clock mode

pub fn lftrig(&self) -> LFTRIG_R

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&self) -> TOVS_R

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&self) -> OVSS_R

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&self) -> OVSR_R

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&self) -> OVSE_R

Bit 0 - ADC oversampler enable on scope ADC group regular

impl R<u32, Reg<u32, _SMPR>>

pub fn smp1(&self) -> SMP1_R

Bits 0:2 - Sampling time selection

pub fn smp2(&self) -> SMP2_R

Bits 4:6 - Sampling time selection

pub fn smpsel(&self) -> SMPSEL_R

Bits 8:26 - Channel sampling time selection

impl R<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&self) -> HT1_R

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&self) -> LT1_R

Bits 0:11 - ADC analog watchdog 1 threshold low

impl R<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&self) -> HT2_R

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&self) -> LT2_R

Bits 0:11 - ADC analog watchdog 2 threshold low

impl R<u32, Reg<u32, _CHSELR>>

pub fn chsel(&self) -> CHSEL_R

Bits 0:18 - Channel-x selection

impl R<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&self) -> SQ1_R

Bits 0:3 - conversion of the sequence

pub fn sq2(&self) -> SQ2_R

Bits 4:7 - conversion of the sequence

pub fn sq3(&self) -> SQ3_R

Bits 8:11 - conversion of the sequence

pub fn sq4(&self) -> SQ4_R

Bits 12:15 - conversion of the sequence

pub fn sq5(&self) -> SQ5_R

Bits 16:19 - conversion of the sequence

pub fn sq6(&self) -> SQ6_R

Bits 20:23 - conversion of the sequence

pub fn sq7(&self) -> SQ7_R

Bits 24:27 - conversion of the sequence

pub fn sq8(&self) -> SQ8_R

Bits 28:31 - conversion of the sequence

impl R<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&self) -> HT3_R

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&self) -> LT3_R

Bits 0:11 - ADC analog watchdog 3 threshold high

impl R<u32, Reg<u32, _DR>>

pub fn regular_data(&self) -> REGULARDATA_R

Bits 0:15 - ADC group regular conversion data

impl R<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&self) -> AWD2CH_R

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl R<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&self) -> AWD3CH_R

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl R<u32, Reg<u32, _CALFACT>>

pub fn calfact(&self) -> CALFACT_R

Bits 0:6 - ADC calibration factor in single-ended mode

impl R<u32, Reg<u32, _CCR>>

pub fn presc(&self) -> PRESC_R

Bits 18:21 - ADC prescaler

pub fn vrefen(&self) -> VREFEN_R

Bit 22 - VREFINT enable

pub fn tsen(&self) -> TSEN_R

Bit 23 - Temperature sensor enable

pub fn vbaten(&self) -> VBATEN_R

Bit 24 - VBAT enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&self) -> I2C_PAX_FMP_R

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&self) -> I2C2_FMP_R

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&self) -> I2C1_FMP_R

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&self) -> I2C_PBX_FMP_R

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn boosten(&self) -> BOOSTEN_R

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&self) -> IR_MOD_R

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&self) -> IR_POL_R

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&self) -> PA11_PA12_RMP_R

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&self) -> MEM_MODE_R

Bits 0:1 - Memory mapping selection bits

impl R<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&self) -> LOCKUP_LOCK_R

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&self) -> SRAM_PARITY_LOCK_R

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&self) -> PVD_LOCK_R

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&self) -> ECC_LOCK_R

Bit 3 - ECC error lock bit

pub fn sram_pef(&self) -> SRAM_PEF_R

Bit 8 - SRAM parity error flag

pub fn pa1_cden(&self) -> PA1_CDEN_R

Bit 16 - PA1_CDEN

pub fn pa3_cden(&self) -> PA3_CDEN_R

Bit 17 - PA3_CDEN

pub fn pa5_cden(&self) -> PA5_CDEN_R

Bit 18 - PA5_CDEN

pub fn pa6_cden(&self) -> PA6_CDEN_R

Bit 19 - PA6_CDEN

pub fn pa13_cden(&self) -> PA13_CDEN_R

Bit 20 - PA13_CDEN

pub fn pb0_cden(&self) -> PB0_CDEN_R

Bit 21 - PB0_CDEN

pub fn pb1_cden(&self) -> PB1_CDEN_R

Bit 22 - PB1_CDEN

pub fn pb2_cden(&self) -> PB2_CDEN_R

Bit 23 - PB2_CDEN

impl R<u32, Reg<u32, _CR1>>

pub fn tamp1e(&self) -> TAMP1E_R

Bit 0 - TAMP1E

pub fn tamp2e(&self) -> TAMP2E_R

Bit 1 - TAMP2E

pub fn itamp1e(&self) -> ITAMP1E_R

Bit 16 - ITAMP1E

pub fn itamp3e(&self) -> ITAMP3E_R

Bit 18 - ITAMP3E

pub fn itamp4e(&self) -> ITAMP4E_R

Bit 19 - ITAMP4E

pub fn itamp5e(&self) -> ITAMP5E_R

Bit 20 - ITAMP5E

pub fn itamp6e(&self) -> ITAMP6E_R

Bit 21 - ITAMP6E

impl R<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&self) -> TAMP1NOER_R

Bit 0 - TAMP1NOER

pub fn tamp2noer(&self) -> TAMP2NOER_R

Bit 1 - TAMP2NOER

pub fn tamp1msk(&self) -> TAMP1MSK_R

Bit 16 - TAMP1MSK

pub fn tamp2msk(&self) -> TAMP2MSK_R

Bit 17 - TAMP2MSK

pub fn tamp1trg(&self) -> TAMP1TRG_R

Bit 24 - TAMP1TRG

pub fn tamp2trg(&self) -> TAMP2TRG_R

Bit 25 - TAMP2TRG

impl R<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&self) -> TAMPFREQ_R

Bits 0:2 - TAMPFREQ

pub fn tampflt(&self) -> TAMPFLT_R

Bits 3:4 - TAMPFLT

pub fn tampprch(&self) -> TAMPPRCH_R

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&self) -> TAMPPUDIS_R

Bit 7 - TAMPPUDIS

impl R<u32, Reg<u32, _IER>>

pub fn tamp1ie(&self) -> TAMP1IE_R

Bit 0 - TAMP1IE

pub fn tamp2ie(&self) -> TAMP2IE_R

Bit 1 - TAMP2IE

pub fn itamp1ie(&self) -> ITAMP1IE_R

Bit 16 - ITAMP1IE

pub fn itamp3ie(&self) -> ITAMP3IE_R

Bit 18 - ITAMP3IE

pub fn itamp4ie(&self) -> ITAMP4IE_R

Bit 19 - ITAMP4IE

pub fn itamp5ie(&self) -> ITAMP5IE_R

Bit 20 - ITAMP5IE

pub fn itamp6ie(&self) -> ITAMP6IE_R

Bit 21 - ITAMP6IE

impl R<u32, Reg<u32, _SR>>

pub fn tamp1f(&self) -> TAMP1F_R

Bit 0 - TAMP1F

pub fn tamp2f(&self) -> TAMP2F_R

Bit 1 - TAMP2F

pub fn itamp1f(&self) -> ITAMP1F_R

Bit 16 - ITAMP1F

pub fn itamp3f(&self) -> ITAMP3F_R

Bit 18 - ITAMP3F

pub fn itamp4f(&self) -> ITAMP4F_R

Bit 19 - ITAMP4F

pub fn itamp5f(&self) -> ITAMP5F_R

Bit 20 - ITAMP5F

pub fn itamp6f(&self) -> ITAMP6F_R

Bit 21 - ITAMP6F

pub fn itamp7f(&self) -> ITAMP7F_R

Bit 22 - ITAMP7F

impl R<u32, Reg<u32, _MISR>>

pub fn tamp1mf(&self) -> TAMP1MF_R

Bit 0 - TAMP1MF:

pub fn tamp2mf(&self) -> TAMP2MF_R

Bit 1 - TAMP2MF

pub fn itamp1mf(&self) -> ITAMP1MF_R

Bit 16 - ITAMP1MF

pub fn itamp3mf(&self) -> ITAMP3MF_R

Bit 18 - ITAMP3MF

pub fn itamp4mf(&self) -> ITAMP4MF_R

Bit 19 - ITAMP4MF

pub fn itamp5mf(&self) -> ITAMP5MF_R

Bit 20 - ITAMP5MF

pub fn itamp6mf(&self) -> ITAMP6MF_R

Bit 21 - ITAMP6MF

impl R<u32, Reg<u32, _BKP0R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP1R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP2R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP3R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP4R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _ISR>>

pub fn down(&self) -> DOWN_R

Bit 6 - Counter direction change up to down

pub fn up(&self) -> UP_R

Bit 5 - Counter direction change down to up

pub fn arrok(&self) -> ARROK_R

Bit 4 - Autoreload register update OK

pub fn cmpok(&self) -> CMPOK_R

Bit 3 - Compare register update OK

pub fn exttrig(&self) -> EXTTRIG_R

Bit 2 - External trigger edge event

pub fn arrm(&self) -> ARRM_R

Bit 1 - Autoreload match

pub fn cmpm(&self) -> CMPM_R

Bit 0 - Compare match

impl R<u32, Reg<u32, _IER>>

pub fn downie(&self) -> DOWNIE_R

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&self) -> UPIE_R

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&self) -> ARROKIE_R

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&self) -> CMPOKIE_R

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&self) -> EXTTRIGIE_R

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&self) -> ARRMIE_R

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&self) -> CMPMIE_R

Bit 0 - Compare match Interrupt Enable

impl R<u32, Reg<u32, _CFGR>>

pub fn enc(&self) -> ENC_R

Bit 24 - Encoder mode enable

pub fn countmode(&self) -> COUNTMODE_R

Bit 23 - counter mode enabled

pub fn preload(&self) -> PRELOAD_R

Bit 22 - Registers update mode

pub fn wavpol(&self) -> WAVPOL_R

Bit 21 - Waveform shape polarity

pub fn wave(&self) -> WAVE_R

Bit 20 - Waveform shape

pub fn timout(&self) -> TIMOUT_R

Bit 19 - Timeout enable

pub fn trigen(&self) -> TRIGEN_R

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&self) -> TRIGSEL_R

Bits 13:15 - Trigger selector

pub fn presc(&self) -> PRESC_R

Bits 9:11 - Clock prescaler

pub fn trgflt(&self) -> TRGFLT_R

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&self) -> CKFLT_R

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&self) -> CKPOL_R

Bits 1:2 - Clock Polarity

pub fn cksel(&self) -> CKSEL_R

Bit 0 - Clock selector

impl R<u32, Reg<u32, _CR>>

pub fn rstare(&self) -> RSTARE_R

Bit 4 - Reset after read enable

pub fn countrst(&self) -> COUNTRST_R

Bit 3 - Counter reset

pub fn cntstrt(&self) -> CNTSTRT_R

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&self) -> SNGSTRT_R

Bit 1 - LPTIM start in single mode

pub fn enable(&self) -> ENABLE_R

Bit 0 - LPTIM Enable

impl R<u32, Reg<u32, _CMP>>

pub fn cmp(&self) -> CMP_R

Bits 0:15 - Compare value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto reload value

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Counter value

impl R<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&self) -> IN2SEL_R

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&self) -> IN1SEL_R

Bits 0:1 - LPTIMx Input 1 selection

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT0

pub fn dedt0(&self) -> DEDT0_R

Bits 16:20 - DEDT0

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr(&self) -> BRR_R

Bits 0:19 - BRR

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn pe(&self) -> PE_R

Bit 0 - Peripheral enable

pub fn txie(&self) -> TXIE_R

Bit 1 - TX Interrupt enable

pub fn rxie(&self) -> RXIE_R

Bit 2 - RX Interrupt enable

pub fn addrie(&self) -> ADDRIE_R

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&self) -> NACKIE_R

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&self) -> STOPIE_R

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 7 - Error interrupts enable

pub fn dnf(&self) -> DNF_R

Bits 8:11 - Digital noise filter

pub fn anfoff(&self) -> ANFOFF_R

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 15 - DMA reception requests enable

pub fn sbc(&self) -> SBC_R

Bit 16 - Slave byte control

pub fn nostretch(&self) -> NOSTRETCH_R

Bit 17 - Clock stretching disable

pub fn wupen(&self) -> WUPEN_R

Bit 18 - Wakeup from STOP enable

pub fn gcen(&self) -> GCEN_R

Bit 19 - General call enable

pub fn smbhen(&self) -> SMBHEN_R

Bit 20 - SMBus Host address enable

pub fn smbden(&self) -> SMBDEN_R

Bit 21 - SMBus Device Default address enable

pub fn alerten(&self) -> ALERTEN_R

Bit 22 - SMBUS alert enable

pub fn pecen(&self) -> PECEN_R

Bit 23 - PEC enable

impl R<u32, Reg<u32, _CR2>>

pub fn pecbyte(&self) -> PECBYTE_R

Bit 26 - Packet error checking byte

pub fn autoend(&self) -> AUTOEND_R

Bit 25 - Automatic end mode (master mode)

pub fn reload(&self) -> RELOAD_R

Bit 24 - NBYTES reload mode

pub fn nbytes(&self) -> NBYTES_R

Bits 16:23 - Number of bytes

pub fn nack(&self) -> NACK_R

Bit 15 - NACK generation (slave mode)

pub fn stop(&self) -> STOP_R

Bit 14 - Stop generation (master mode)

pub fn start(&self) -> START_R

Bit 13 - Start generation

pub fn head10r(&self) -> HEAD10R_R

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&self) -> ADD10_R

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&self) -> RD_WRN_R

Bit 10 - Transfer direction (master mode)

pub fn sadd(&self) -> SADD_R

Bits 0:9 - Slave address bit (master mode)

impl R<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&self) -> OA1_0_R

Bit 0 - Interface address

pub fn oa1_7_1(&self) -> OA1_7_1_R

Bits 1:7 - Interface address

pub fn oa1_8_9(&self) -> OA1_8_9_R

Bits 8:9 - Interface address

pub fn oa1mode(&self) -> OA1MODE_R

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&self) -> OA1EN_R

Bit 15 - Own Address 1 enable

impl R<u32, Reg<u32, _OAR2>>

pub fn oa2(&self) -> OA2_R

Bits 1:7 - Interface address

pub fn oa2msk(&self) -> OA2MSK_R

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&self) -> OA2EN_R

Bit 15 - Own Address 2 enable

impl R<u32, Reg<u32, _TIMINGR>>

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler

impl R<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&self) -> TIMEOUTA_R

Bits 0:11 - Bus timeout A

pub fn tidle(&self) -> TIDLE_R

Bit 12 - Idle clock timeout detection

pub fn timouten(&self) -> TIMOUTEN_R

Bit 15 - Clock timeout enable

pub fn timeoutb(&self) -> TIMEOUTB_R

Bits 16:27 - Bus timeout B

pub fn texten(&self) -> TEXTEN_R

Bit 31 - Extended clock timeout enable

impl R<u32, Reg<u32, _ISR>>

pub fn addcode(&self) -> ADDCODE_R

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R

Bit 0 - Transmit data register empty (transmitters)

impl R<u32, Reg<u32, _PECR>>

pub fn pec(&self) -> PEC_R

Bits 0:7 - Packet error checking register

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - 8-bit receive data

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - 8-bit transmit data

impl R<u32, Reg<u32, _TR>>

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _DR>>

pub fn yt(&self) -> YT_R

Bits 20:23 - Year tens in BCD format

pub fn yu(&self) -> YU_R

Bits 16:19 - Year units in BCD format

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _SSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ICSR>>

pub fn alrawf(&self) -> ALRAWF_R

Bit 0 - Alarm A write flag

pub fn alrbwf(&self) -> ALRBWF_R

Bit 1 - Alarm B write flag

pub fn wutwf(&self) -> WUTWF_R

Bit 2 - Wakeup timer write flag

pub fn shpf(&self) -> SHPF_R

Bit 3 - Shift operation pending

pub fn inits(&self) -> INITS_R

Bit 4 - Initialization status flag

pub fn rsf(&self) -> RSF_R

Bit 5 - Registers synchronization flag

pub fn initf(&self) -> INITF_R

Bit 6 - Initialization flag

pub fn init(&self) -> INIT_R

Bit 7 - Initialization mode

pub fn recalpf(&self) -> RECALPF_R

Bit 16 - Recalibration pending Flag

impl R<u32, Reg<u32, _PRER>>

pub fn prediv_a(&self) -> PREDIV_A_R

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&self) -> PREDIV_S_R

Bits 0:14 - Synchronous prescaler factor

impl R<u32, Reg<u32, _WUTR>>

pub fn wut(&self) -> WUT_R

Bits 0:15 - Wakeup auto-reload value bits

impl R<u32, Reg<u32, _CR>>

pub fn wucksel(&self) -> WUCKSEL_R

Bits 0:2 - WUCKSEL

pub fn tsedge(&self) -> TSEDGE_R

Bit 3 - TSEDGE

pub fn refckon(&self) -> REFCKON_R

Bit 4 - REFCKON

pub fn bypshad(&self) -> BYPSHAD_R

Bit 5 - BYPSHAD

pub fn fmt(&self) -> FMT_R

Bit 6 - FMT

pub fn alrae(&self) -> ALRAE_R

Bit 8 - ALRAE

pub fn alrbe(&self) -> ALRBE_R

Bit 9 - ALRBE

pub fn wute(&self) -> WUTE_R

Bit 10 - WUTE

pub fn tse(&self) -> TSE_R

Bit 11 - TSE

pub fn alraie(&self) -> ALRAIE_R

Bit 12 - ALRAIE

pub fn alrbie(&self) -> ALRBIE_R

Bit 13 - ALRBIE

pub fn wutie(&self) -> WUTIE_R

Bit 14 - WUTIE

pub fn tsie(&self) -> TSIE_R

Bit 15 - TSIE

pub fn add1h(&self) -> ADD1H_R

Bit 16 - ADD1H

pub fn sub1h(&self) -> SUB1H_R

Bit 17 - SUB1H

pub fn bkp(&self) -> BKP_R

Bit 18 - BKP

pub fn cosel(&self) -> COSEL_R

Bit 19 - COSEL

pub fn pol(&self) -> POL_R

Bit 20 - POL

pub fn osel(&self) -> OSEL_R

Bits 21:22 - OSEL

pub fn coe(&self) -> COE_R

Bit 23 - COE

pub fn itse(&self) -> ITSE_R

Bit 24 - ITSE

pub fn tampts(&self) -> TAMPTS_R

Bit 25 - TAMPTS

pub fn tampoe(&self) -> TAMPOE_R

Bit 26 - TAMPOE

pub fn tampalrm_pu(&self) -> TAMPALRM_PU_R

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&self) -> TAMPALRM_TYPE_R

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&self) -> OUT2EN_R

Bit 31 - OUT2EN

impl R<u32, Reg<u32, _CALR>>

pub fn calp(&self) -> CALP_R

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&self) -> CALW8_R

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&self) -> CALW16_R

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&self) -> CALM_R

Bits 0:8 - Calibration minus

impl R<u32, Reg<u32, _TSTR>>

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

impl R<u32, Reg<u32, _TSDR>>

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _TSSSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm A date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm A hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm A minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm A seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm B date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm B hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm B minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm B seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _SR>>

pub fn alraf(&self) -> ALRAF_R

Bit 0 - ALRAF

pub fn alrbf(&self) -> ALRBF_R

Bit 1 - ALRBF

pub fn wutf(&self) -> WUTF_R

Bit 2 - WUTF

pub fn tsf(&self) -> TSF_R

Bit 3 - TSF

pub fn tsovf(&self) -> TSOVF_R

Bit 4 - TSOVF

pub fn itsf(&self) -> ITSF_R

Bit 5 - ITSF

impl R<u32, Reg<u32, _MISR>>

pub fn alramf(&self) -> ALRAMF_R

Bit 0 - ALRAMF

pub fn alrbmf(&self) -> ALRBMF_R

Bit 1 - ALRBMF

pub fn wutmf(&self) -> WUTMF_R

Bit 2 - WUTMF

pub fn tsmf(&self) -> TSMF_R

Bit 3 - TSMF

pub fn tsovmf(&self) -> TSOVMF_R

Bit 4 - TSOVMF

pub fn itsmf(&self) -> ITSMF_R

Bit 5 - ITSMF

impl R<u32, Reg<u32, _SCR>>

pub fn calraf(&self) -> CALRAF_R

Bit 0 - CALRAF

pub fn calrbf(&self) -> CALRBF_R

Bit 1 - CALRBF

pub fn cwutf(&self) -> CWUTF_R

Bit 2 - CWUTF

pub fn ctsf(&self) -> CTSF_R

Bit 3 - CTSF

pub fn ctsovf(&self) -> CTSOVF_R

Bit 4 - CTSOVF

pub fn citsf(&self) -> CITSF_R

Bit 5 - CITSF

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _DIER>>

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - CC1S

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - OC1FE

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - OC1PE

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - OC1M

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - OC1CE

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&self) -> ICPCS_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _TISEL>>

pub fn tisel(&self) -> TISEL_R

Bits 0:3 - TI1[0] to TI1[15] input selection

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

impl R<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&self) -> TS_4_3_R

Bits 20:21 - Trigger selection

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&self) -> IC3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt_h(&self) -> CNT_H_R

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&self) -> CNT_L_R

Bits 0:15 - Low counter value

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr_h(&self) -> ARR_H_R

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&self) -> ARR_L_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&self) -> CCR1_H_R

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&self) -> CCR1_L_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&self) -> CCR2_H_R

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&self) -> CCR2_L_R

Bits 0:15 - Low Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&self) -> CCR3_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&self) -> CCR3_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&self) -> CCR4_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&self) -> CCR4_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&self) -> IOCREF_CLR_R

Bit 0 - IOCREF_CLR

impl R<u32, Reg<u32, _AF1>>

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:17 - External trigger source selection

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - TI1SEL

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - TI2SEL

impl R<u32, Reg<u32, _CSR>>

pub fn enable(&self) -> ENABLE_R

Bit 0 - Counter enable

pub fn tickint(&self) -> TICKINT_R

Bit 1 - SysTick exception request enable

pub fn clksource(&self) -> CLKSOURCE_R

Bit 2 - Clock source selection

pub fn countflag(&self) -> COUNTFLAG_R

Bit 16 - COUNTFLAG

impl R<u32, Reg<u32, _RVR>>

pub fn reload(&self) -> RELOAD_R

Bits 0:23 - RELOAD value

impl R<u32, Reg<u32, _CVR>>

pub fn current(&self) -> CURRENT_R

Bits 0:23 - Current counter value

impl R<u32, Reg<u32, _CALIB>>

pub fn tenms(&self) -> TENMS_R

Bits 0:23 - Calibration value

pub fn skew(&self) -> SKEW_R

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&self) -> NOREF_R

Bit 31 - NOREF flag. Reads as zero

impl R<u32, Reg<u32, _CSR>>

pub fn envr(&self) -> ENVR_R

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&self) -> HIZ_R

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrr(&self) -> VRR_R

Bit 3 - Voltage reference buffer ready

pub fn vrs(&self) -> VRS_R

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl R<u32, Reg<u32, _CCR>>

pub fn trim(&self) -> TRIM_R

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl R<u32, Reg<u32, _IDCODE>>

pub fn dev_id(&self) -> DEV_ID_R

Bits 0:11 - Device identifier

pub fn rev_id(&self) -> REV_ID_R

Bits 16:31 - Revision identifie

impl R<u32, Reg<u32, _CR>>

pub fn dbg_stop(&self) -> DBG_STOP_R

Bit 1 - Debug Stop mode

pub fn dbg_standby(&self) -> DBG_STANDBY_R

Bit 2 - Debug Standby mode

impl R<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R

Bit 0 - TIM2 counter stopped when core is halted

pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R

Bit 11 - Window watchdog counter stopped when core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - Independent watchdog counter stopped when core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 30 - LPTIM2 counter stopped when core is halted

pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R

Bit 31 - LPTIM1 counter stopped when core is halted

impl R<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - DBG_TIM17_STOP

impl R<u32, Reg<u32, _STIR>>

pub fn intid(&self) -> INTID_R

Bits 0:8 - Software generated interrupt ID

impl R<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&self) -> DISMCYCINT_R

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&self) -> DISDEFWBUF_R

Bit 1 - DISDEFWBUF

pub fn disfold(&self) -> DISFOLD_R

Bit 2 - DISFOLD

pub fn disfpca(&self) -> DISFPCA_R

Bit 8 - DISFPCA

pub fn disoofp(&self) -> DISOOFP_R

Bit 9 - DISOOFP

impl R<u32, Reg<u32, _CPACR>>

pub fn cp(&self) -> CP_R

Bits 20:23 - CP

impl R<u32, Reg<u32, _FPCCR>>

pub fn lspact(&self) -> LSPACT_R

Bit 0 - LSPACT

pub fn user(&self) -> USER_R

Bit 1 - USER

pub fn thread(&self) -> THREAD_R

Bit 3 - THREAD

pub fn hfrdy(&self) -> HFRDY_R

Bit 4 - HFRDY

pub fn mmrdy(&self) -> MMRDY_R

Bit 5 - MMRDY

pub fn bfrdy(&self) -> BFRDY_R

Bit 6 - BFRDY

pub fn monrdy(&self) -> MONRDY_R

Bit 8 - MONRDY

pub fn lspen(&self) -> LSPEN_R

Bit 30 - LSPEN

pub fn aspen(&self) -> ASPEN_R

Bit 31 - ASPEN

impl R<u32, Reg<u32, _FPCAR>>

pub fn address(&self) -> ADDRESS_R

Bits 3:31 - Location of unpopulated floating-point

impl R<u32, Reg<u32, _FPSCR>>

pub fn ioc(&self) -> IOC_R

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&self) -> DZC_R

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&self) -> OFC_R

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&self) -> UFC_R

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&self) -> IXC_R

Bit 4 - Inexact cumulative exception bit

pub fn idc(&self) -> IDC_R

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&self) -> RMODE_R

Bits 22:23 - Rounding Mode control field

pub fn fz(&self) -> FZ_R

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&self) -> DN_R

Bit 25 - Default NaN mode control bit

pub fn ahp(&self) -> AHP_R

Bit 26 - Alternative half-precision control bit

pub fn v(&self) -> V_R

Bit 28 - Overflow condition code flag

pub fn c(&self) -> C_R

Bit 29 - Carry condition code flag

pub fn z(&self) -> Z_R

Bit 30 - Zero condition code flag

pub fn n(&self) -> N_R

Bit 31 - Negative condition code flag

impl R<u32, Reg<u32, _ITLINE0>>

pub fn wwdg(&self) -> WWDG_R

Bit 0 - Window watchdog interrupt pending flag

impl R<u32, Reg<u32, _ITLINE1>>

pub fn pvdout(&self) -> PVDOUT_R

Bit 0 - PVD supply monitoring interrupt request pending (EXTI line 16).

impl R<u32, Reg<u32, _ITLINE2>>

pub fn tamp(&self) -> TAMP_R

Bit 0 - TAMP

pub fn rtc(&self) -> RTC_R

Bit 1 - RTC

impl R<u32, Reg<u32, _ITLINE3>>

pub fn flash_itf(&self) -> FLASH_ITF_R

Bit 0 - FLASH_ITF

pub fn flash_ecc(&self) -> FLASH_ECC_R

Bit 1 - FLASH_ECC

impl R<u32, Reg<u32, _ITLINE4>>

pub fn rcc(&self) -> RCC_R

Bit 0 - RCC

impl R<u32, Reg<u32, _ITLINE5>>

pub fn exti0(&self) -> EXTI0_R

Bit 0 - EXTI0

pub fn exti1(&self) -> EXTI1_R

Bit 1 - EXTI1

impl R<u32, Reg<u32, _ITLINE6>>

pub fn exti2(&self) -> EXTI2_R

Bit 0 - EXTI2

pub fn exti3(&self) -> EXTI3_R

Bit 1 - EXTI3

impl R<u32, Reg<u32, _ITLINE7>>

pub fn exti4(&self) -> EXTI4_R

Bit 0 - EXTI4

pub fn exti5(&self) -> EXTI5_R

Bit 1 - EXTI5

pub fn exti6(&self) -> EXTI6_R

Bit 2 - EXTI6

pub fn exti7(&self) -> EXTI7_R

Bit 3 - EXTI7

pub fn exti8(&self) -> EXTI8_R

Bit 4 - EXTI8

pub fn exti9(&self) -> EXTI9_R

Bit 5 - EXTI9

pub fn exti10(&self) -> EXTI10_R

Bit 6 - EXTI10

pub fn exti11(&self) -> EXTI11_R

Bit 7 - EXTI11

pub fn exti12(&self) -> EXTI12_R

Bit 8 - EXTI12

pub fn exti13(&self) -> EXTI13_R

Bit 9 - EXTI13

pub fn exti14(&self) -> EXTI14_R

Bit 10 - EXTI14

pub fn exti15(&self) -> EXTI15_R

Bit 11 - EXTI15

impl R<u32, Reg<u32, _ITLINE9>>

pub fn dma1_ch1(&self) -> DMA1_CH1_R

Bit 0 - DMA1_CH1

impl R<u32, Reg<u32, _ITLINE10>>

pub fn dma1_ch2(&self) -> DMA1_CH2_R

Bit 0 - DMA1_CH1

pub fn dma1_ch3(&self) -> DMA1_CH3_R

Bit 1 - DMA1_CH3

impl R<u32, Reg<u32, _ITLINE11>>

pub fn dmamux(&self) -> DMAMUX_R

Bit 0 - DMAMUX

pub fn dma1_ch4(&self) -> DMA1_CH4_R

Bit 1 - DMA1_CH4

pub fn dma1_ch5(&self) -> DMA1_CH5_R

Bit 2 - DMA1_CH5

impl R<u32, Reg<u32, _ITLINE12>>

pub fn adc(&self) -> ADC_R

Bit 0 - ADC

impl R<u32, Reg<u32, _ITLINE13>>

pub fn tim1_ccu(&self) -> TIM1_CCU_R

Bit 0 - TIM1_CCU

pub fn tim1_trg(&self) -> TIM1_TRG_R

Bit 1 - TIM1_TRG

pub fn tim1_upd(&self) -> TIM1_UPD_R

Bit 2 - TIM1_UPD

pub fn tim1_brk(&self) -> TIM1_BRK_R

Bit 3 - TIM1_BRK

impl R<u32, Reg<u32, _ITLINE14>>

pub fn tim1_cc(&self) -> TIM1_CC_R

Bit 0 - TIM1_CC

impl R<u32, Reg<u32, _ITLINE15>>

pub fn tim2(&self) -> TIM2_R

Bit 0 - TIM2

impl R<u32, Reg<u32, _ITLINE16>>

pub fn tim3(&self) -> TIM3_R

Bit 0 - TIM3

impl R<u32, Reg<u32, _ITLINE17>>

pub fn lptim1(&self) -> LPTIM1_R

Bit 2 - LPTIM1

impl R<u32, Reg<u32, _ITLINE18>>

pub fn lptim2(&self) -> LPTIM2_R

Bit 1 - LPTIM2

impl R<u32, Reg<u32, _ITLINE19>>

pub fn tim14(&self) -> TIM14_R

Bit 0 - TIM14

impl R<u32, Reg<u32, _ITLINE21>>

pub fn tim16(&self) -> TIM16_R

Bit 0 - TIM16

impl R<u32, Reg<u32, _ITLINE22>>

pub fn tim17(&self) -> TIM17_R

Bit 0 - TIM17

impl R<u32, Reg<u32, _ITLINE23>>

pub fn i2c1(&self) -> I2C1_R

Bit 0 - I2C1

impl R<u32, Reg<u32, _ITLINE24>>

pub fn i2c2(&self) -> I2C2_R

Bit 0 - I2C2

impl R<u32, Reg<u32, _ITLINE25>>

pub fn spi1(&self) -> SPI1_R

Bit 0 - SPI1

impl R<u32, Reg<u32, _ITLINE26>>

pub fn spi2(&self) -> SPI2_R

Bit 0 - SPI2

impl R<u32, Reg<u32, _ITLINE27>>

pub fn usart1(&self) -> USART1_R

Bit 0 - USART1

impl R<u32, Reg<u32, _ITLINE28>>

pub fn usart2(&self) -> USART2_R

Bit 0 - USART2

impl R<u32, Reg<u32, _ITLINE29>>

pub fn usart5(&self) -> USART5_R

Bit 2 - USART5

impl R<u32, Reg<u32, _PR>>

pub fn pr(&self) -> PR_R

Bits 0:2 - Prescaler divider

impl R<u32, Reg<u32, _RLR>>

pub fn rl(&self) -> RL_R

Bits 0:11 - Watchdog counter reload value

impl R<u32, Reg<u32, _SR>>

pub fn wvu(&self) -> WVU_R

Bit 2 - Watchdog counter window value update

pub fn rvu(&self) -> RVU_R

Bit 1 - Watchdog counter reload value update

pub fn pvu(&self) -> PVU_R

Bit 0 - Watchdog prescaler value update

impl R<u32, Reg<u32, _WINR>>

pub fn win(&self) -> WIN_R

Bits 0:11 - Watchdog counter window value

impl R<u32, Reg<u32, _CR>>

pub fn wdga(&self) -> WDGA_R

Bit 7 - Activation bit

pub fn t(&self) -> T_R

Bits 0:6 - 7-bit counter (MSB to LSB)

impl R<u32, Reg<u32, _CFR>>

pub fn wdgtb(&self) -> WDGTB_R

Bits 11:13 - Timer base

pub fn ewi(&self) -> EWI_R

Bit 9 - Early wakeup interrupt

pub fn w(&self) -> W_R

Bits 0:6 - 7-bit window value

impl R<u32, Reg<u32, _SR>>

pub fn ewif(&self) -> EWIF_R

Bit 0 - Early wakeup interrupt flag

impl R<u32, Reg<u32, _ACR>>

pub fn latency(&self) -> LATENCY_R

Bits 0:2 - Latency

pub fn prften(&self) -> PRFTEN_R

Bit 8 - Prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - Instruction cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - Instruction cache reset

pub fn empty(&self) -> EMPTY_R

Bit 16 - Flash User area empty

pub fn dbg_swen(&self) -> DBG_SWEN_R

Bit 18 - Debug access software enable

impl R<u32, Reg<u32, _SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - Write protected error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn miserr(&self) -> MISERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn optverr(&self) -> OPTVERR_R

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy.

impl R<u32, Reg<u32, _CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - Mass erase

pub fn pnb(&self) -> PNB_R

Bits 3:8 - Page number

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn optstrt(&self) -> OPTSTRT_R

Bit 17 - Options modification start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&self) -> OBL_LAUNCH_R

Bit 27 - Force the option byte loading

pub fn sec_prot(&self) -> SEC_PROT_R

Bit 28 - Securable memory area protection enable

pub fn optlock(&self) -> OPTLOCK_R

Bit 30 - Options Lock

pub fn lock(&self) -> LOCK_R

Bit 31 - FLASH_CR Lock

impl R<u32, Reg<u32, _ECCR>>

pub fn addr_ecc(&self) -> ADDR_ECC_R

Bits 0:13 - ECC fail address

pub fn sysf_ecc(&self) -> SYSF_ECC_R

Bit 20 - ECC fail for Corrected ECC Error or Double ECC Error in info block

pub fn eccie(&self) -> ECCIE_R

Bit 24 - ECC correction interrupt enable

pub fn eccc(&self) -> ECCC_R

Bit 30 - ECC correction

pub fn eccd(&self) -> ECCD_R

Bit 31 - ECC detection

impl R<u32, Reg<u32, _OPTR>>

pub fn rdp(&self) -> RDP_R

Bits 0:7 - Read protection level

pub fn boren(&self) -> BOREN_R

Bit 8 - BOR reset Level

pub fn borf_lev(&self) -> BORF_LEV_R

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&self) -> BORR_LEV_R

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&self) -> NRST_STOP_R

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&self) -> NRST_STDBY_R

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&self) -> NRSTS_HDW_R

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&self) -> IDWG_SW_R

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&self) -> IWDG_STOP_R

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&self) -> IWDG_STDBY_R

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&self) -> WWDG_SW_R

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&self) -> RAM_PARITY_CHECK_R

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&self) -> NBOOT_SEL_R

Bit 24 - nBOOT_SEL

pub fn n_boot1(&self) -> NBOOT1_R

Bit 25 - Boot configuration

pub fn n_boot0(&self) -> NBOOT0_R

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&self) -> NRST_MODE_R

Bits 27:28 - NRST_MODE

pub fn irhen(&self) -> IRHEN_R

Bit 29 - Internal reset holder enable bit

impl R<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R

Bits 0:7 - PCROP1A area start offset

impl R<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&self) -> PCROP1A_END_R

Bits 0:7 - PCROP1A area end offset

pub fn pcrop_rdp(&self) -> PCROP_RDP_R

Bit 31 - PCROP area preserved when RDP level decreased

impl R<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&self) -> WRP1A_STRT_R

Bits 0:5 - WRP area A start offset

pub fn wrp1a_end(&self) -> WRP1A_END_R

Bits 16:21 - WRP area A end offset

impl R<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&self) -> WRP1B_STRT_R

Bits 0:5 - WRP area B start offset

pub fn wrp1b_end(&self) -> WRP1B_END_R

Bits 16:21 - WRP area B end offset

impl R<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R

Bits 0:7 - PCROP1B area start offset

impl R<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&self) -> PCROP1B_END_R

Bits 0:7 - PCROP1B area end offset

impl R<u32, Reg<u32, _SECR>>

pub fn sec_size(&self) -> SEC_SIZE_R

Bits 0:6 - Securable memory area size

pub fn boot_lock(&self) -> BOOT_LOCK_R

Bit 16 - used to force boot from user area

impl R<u32, Reg<u32, _CR>>

pub fn hsion(&self) -> HSION_R

Bit 8 - HSI16 clock enable

pub fn hsikeron(&self) -> HSIKERON_R

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&self) -> HSIRDY_R

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&self) -> HSIDIV_R

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&self) -> HSEON_R

Bit 16 - HSE clock enable

pub fn hserdy(&self) -> HSERDY_R

Bit 17 - HSE clock ready flag

pub fn hsebyp(&self) -> HSEBYP_R

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&self) -> CSSON_R

Bit 19 - Clock security system enable

pub fn pllon(&self) -> PLLON_R

Bit 24 - PLL enable

pub fn pllrdy(&self) -> PLLRDY_R

Bit 25 - PLL clock ready flag

impl R<u32, Reg<u32, _ICSCR>>

pub fn hsical(&self) -> HSICAL_R

Bits 0:7 - HSI16 clock calibration

pub fn hsitrim(&self) -> HSITRIM_R

Bits 8:14 - HSI16 clock trimming

impl R<u32, Reg<u32, _CFGR>>

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&self) -> MCOSEL_R

Bits 24:26 - Microcontroller clock output

pub fn ppre(&self) -> PPRE_R

Bits 12:14 - APB prescaler

pub fn hpre(&self) -> HPRE_R

Bits 8:11 - AHB prescaler

pub fn sws(&self) -> SWS_R

Bits 3:5 - System clock switch status

pub fn sw(&self) -> SW_R

Bits 0:2 - System clock switch

impl R<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - PLL input clock source

pub fn pllm(&self) -> PLLM_R

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&self) -> PLLN_R

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&self) -> PLLREN_R

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl R<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&self) -> LSIRDYIE_R

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&self) -> LSERDYIE_R

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&self) -> HSIRDYIE_R

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&self) -> HSERDYIE_R

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&self) -> PLLSYSRDYIE_R

Bit 5 - PLL ready interrupt enable

impl R<u32, Reg<u32, _CIFR>>

pub fn lsirdyf(&self) -> LSIRDYF_R

Bit 0 - LSI ready interrupt flag

pub fn lserdyf(&self) -> LSERDYF_R

Bit 1 - LSE ready interrupt flag

pub fn hsirdyf(&self) -> HSIRDYF_R

Bit 3 - HSI ready interrupt flag

pub fn hserdyf(&self) -> HSERDYF_R

Bit 4 - HSE ready interrupt flag

pub fn pllsysrdyf(&self) -> PLLSYSRDYF_R

Bit 5 - PLL ready interrupt flag

pub fn cssf(&self) -> CSSF_R

Bit 8 - Clock security system interrupt flag

pub fn lsecssf(&self) -> LSECSSF_R

Bit 9 - LSE Clock security system interrupt flag

impl R<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&self) -> DMARST_R

Bit 0 - DMA1 reset

pub fn flashrst(&self) -> FLASHRST_R

Bit 8 - FLITF reset

pub fn crcrst(&self) -> CRCRST_R

Bit 12 - CRC reset

pub fn aesrst(&self) -> AESRST_R

Bit 16 - AES hardware accelerator reset

pub fn rngrst(&self) -> RNGRST_R

Bit 18 - Random number generator reset

impl R<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&self) -> IOPARST_R

Bit 0 - I/O port A reset

pub fn iopbrst(&self) -> IOPBRST_R

Bit 1 - I/O port B reset

pub fn iopcrst(&self) -> IOPCRST_R

Bit 2 - I/O port C reset

pub fn iopdrst(&self) -> IOPDRST_R

Bit 3 - I/O port D reset

pub fn iopfrst(&self) -> IOPFRST_R

Bit 5 - I/O port F reset

impl R<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&self) -> TIM2RST_R

Bit 0 - TIM2 timer reset

pub fn tim3rst(&self) -> TIM3RST_R

Bit 1 - TIM3 timer reset

pub fn spi2rst(&self) -> SPI2RST_R

Bit 14 - SPI2 reset

pub fn usart2rst(&self) -> USART2RST_R

Bit 17 - USART2 reset

pub fn lpuart1rst(&self) -> LPUART1RST_R

Bit 20 - LPUART1 reset

pub fn i2c1rst(&self) -> I2C1RST_R

Bit 21 - I2C1 reset

pub fn i2c2rst(&self) -> I2C2RST_R

Bit 22 - I2C2 reset

pub fn dbgrst(&self) -> DBGRST_R

Bit 27 - Debug support reset

pub fn pwrrst(&self) -> PWRRST_R

Bit 28 - Power interface reset

pub fn lptim2rst(&self) -> LPTIM2RST_R

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&self) -> LPTIM1RST_R

Bit 31 - Low Power Timer 1 reset

impl R<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&self) -> SYSCFGRST_R

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&self) -> TIM1RST_R

Bit 11 - TIM1 timer reset

pub fn spi1rst(&self) -> SPI1RST_R

Bit 12 - SPI1 reset

pub fn usart1rst(&self) -> USART1RST_R

Bit 14 - USART1 reset

pub fn tim14rst(&self) -> TIM14RST_R

Bit 15 - TIM14 timer reset

pub fn tim16rst(&self) -> TIM16RST_R

Bit 17 - TIM16 timer reset

pub fn tim17rst(&self) -> TIM17RST_R

Bit 18 - TIM17 timer reset

pub fn adcrst(&self) -> ADCRST_R

Bit 20 - ADC reset

impl R<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&self) -> IOPAEN_R

Bit 0 - I/O port A clock enable

pub fn iopben(&self) -> IOPBEN_R

Bit 1 - I/O port B clock enable

pub fn iopcen(&self) -> IOPCEN_R

Bit 2 - I/O port C clock enable

pub fn iopden(&self) -> IOPDEN_R

Bit 3 - I/O port D clock enable

pub fn iopfen(&self) -> IOPFEN_R

Bit 5 - I/O port F clock enable

impl R<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - DMA clock enable

pub fn flashen(&self) -> FLASHEN_R

Bit 8 - Flash memory interface clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CRC clock enable

pub fn aesen(&self) -> AESEN_R

Bit 16 - AES hardware accelerator

pub fn rngen(&self) -> RNGEN_R

Bit 18 - Random number generator clock enable

impl R<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&self) -> TIM2EN_R

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&self) -> TIM3EN_R

Bit 1 - TIM3 timer clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - RTC APB clock enable

pub fn wwdgen(&self) -> WWDGEN_R

Bit 11 - WWDG clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - SPI2 clock enable

pub fn usart2en(&self) -> USART2EN_R

Bit 17 - USART2 clock enable

pub fn lpuart1en(&self) -> LPUART1EN_R

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - I2C1 clock enable

pub fn i2c2en(&self) -> I2C2EN_R

Bit 22 - I2C2 clock enable

pub fn dbgen(&self) -> DBGEN_R

Bit 27 - Debug support clock enable

pub fn pwren(&self) -> PWREN_R

Bit 28 - Power interface clock enable

pub fn lptim2en(&self) -> LPTIM2EN_R

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&self) -> LPTIM1EN_R

Bit 31 - LPTIM1 clock enable

impl R<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&self) -> SYSCFGEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - SPI1 clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - USART1 clock enable

pub fn tim14en(&self) -> TIM14EN_R

Bit 15 - TIM14 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - TIM16 timer clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 20 - ADC clock enable

impl R<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&self) -> IOPASMEN_R

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&self) -> IOPBSMEN_R

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&self) -> IOPCSMEN_R

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&self) -> IOPDSMEN_R

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&self) -> IOPFSMEN_R

Bit 5 - I/O port F clock enable during Sleep mode

impl R<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&self) -> DMASMEN_R

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&self) -> SRAMSMEN_R

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CRC clock enable during Sleep mode

pub fn aessmen(&self) -> AESSMEN_R

Bit 16 - AES hardware accelerator clock enable during Sleep mode

pub fn rngsmen(&self) -> RNGSMEN_R

Bit 18 - Random number generator clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&self) -> TIM2SMEN_R

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&self) -> TIM3SMEN_R

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&self) -> WWDGSMEN_R

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&self) -> USART2SMEN_R

Bit 17 - USART2 clock enable during Sleep mode

pub fn lpuart1smen(&self) -> LPUART1SMEN_R

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&self) -> I2C2SMEN_R

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&self) -> DBGSMEN_R

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&self) -> PWRSMEN_R

Bit 28 - Power interface clock enable during Sleep mode

pub fn lptim2smen(&self) -> LPTIM2SMEN_R

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&self) -> LPTIM1SMEN_R

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&self) -> SYSCFGSMEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&self) -> TIM14SMEN_R

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&self) -> ADCSMEN_R

Bit 20 - ADC clock enable during Sleep mode

impl R<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&self) -> USART1SEL_R

Bits 0:1 - USART1 clock source selection

pub fn lpuart1sel(&self) -> LPUART1SEL_R

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&self) -> I2C1SEL_R

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&self) -> I2S2SEL_R

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&self) -> LPTIM1SEL_R

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&self) -> LPTIM2SEL_R

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&self) -> TIM1SEL_R

Bit 22 - TIM1 clock source selection

pub fn rngsel(&self) -> RNGSEL_R

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&self) -> RNGDIV_R

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&self) -> ADCSEL_R

Bits 30:31 - ADCs clock source selection

impl R<u32, Reg<u32, _BDCR>>

pub fn lseon(&self) -> LSEON_R

Bit 0 - LSE oscillator enable

pub fn lserdy(&self) -> LSERDY_R

Bit 1 - LSE oscillator ready

pub fn lsebyp(&self) -> LSEBYP_R

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&self) -> LSEDRV_R

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&self) -> LSECSSON_R

Bit 5 - CSS on LSE enable

pub fn lsecssd(&self) -> LSECSSD_R

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&self) -> RTCSEL_R

Bits 8:9 - RTC clock source selection

pub fn rtcen(&self) -> RTCEN_R

Bit 15 - RTC clock enable

pub fn bdrst(&self) -> BDRST_R

Bit 16 - RTC domain software reset

pub fn lscoen(&self) -> LSCOEN_R

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&self) -> LSCOSEL_R

Bit 25 - Low-speed clock output selection

impl R<u32, Reg<u32, _CSR>>

pub fn lsion(&self) -> LSION_R

Bit 0 - LSI oscillator enable

pub fn lsirdy(&self) -> LSIRDY_R

Bit 1 - LSI oscillator ready

pub fn rmvf(&self) -> RMVF_R

Bit 23 - Remove reset flags

pub fn oblrstf(&self) -> OBLRSTF_R

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&self) -> PINRSTF_R

Bit 26 - Pin reset flag

pub fn pwrrstf(&self) -> PWRRSTF_R

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&self) -> SFTRSTF_R

Bit 28 - Software reset flag

pub fn iwdgrstf(&self) -> IWDGRSTF_R

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&self) -> WWDGRSTF_R

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&self) -> LPWRRSTF_R

Bit 31 - Low-power reset flag

impl R<u32, Reg<u32, _CR1>>

pub fn lpr(&self) -> LPR_R

Bit 14 - Low-power run

pub fn vos(&self) -> VOS_R

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&self) -> DBP_R

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&self) -> FPD_LPSLP_R

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&self) -> FPD_LPRUN_R

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&self) -> FPD_STOP_R

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection

impl R<u32, Reg<u32, _CR2>>

pub fn pvde(&self) -> PVDE_R

Bit 0 - Power voltage detector enable

pub fn pvdft(&self) -> PVDFT_R

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&self) -> PVDRT_R

Bits 4:6 - Power voltage detector rising threshold selection

impl R<u32, Reg<u32, _CR3>>

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&self) -> EWUP6_R

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&self) -> RRS_R

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&self) -> ULPEN_R

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&self) -> APC_R

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line

impl R<u32, Reg<u32, _CR4>>

pub fn wp1(&self) -> WP1_R

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&self) -> WP2_R

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&self) -> WP4_R

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&self) -> WP5_R

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&self) -> WP6_R

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&self) -> VBE_R

Bit 8 - VBAT battery charging enable

pub fn vbrs(&self) -> VBRS_R

Bit 9 - VBAT battery charging resistor selection

impl R<u32, Reg<u32, _SR1>>

pub fn wuf1(&self) -> WUF1_R

Bit 0 - Wakeup flag 1

pub fn wuf2(&self) -> WUF2_R

Bit 1 - Wakeup flag 2

pub fn wuf4(&self) -> WUF4_R

Bit 3 - Wakeup flag 4

pub fn wuf5(&self) -> WUF5_R

Bit 4 - Wakeup flag 5

pub fn wuf6(&self) -> WUF6_R

Bit 5 - Wakeup flag 6

pub fn sbf(&self) -> SBF_R

Bit 8 - Standby flag

pub fn wufi(&self) -> WUFI_R

Bit 15 - Wakeup flag internal

impl R<u32, Reg<u32, _SR2>>

pub fn pvdo(&self) -> PVDO_R

Bit 11 - Power voltage detector output

pub fn vosf(&self) -> VOSF_R

Bit 10 - Voltage scaling flag

pub fn reglpf(&self) -> REGLPF_R

Bit 9 - Low-power regulator flag

pub fn reglps(&self) -> REGLPS_R

Bit 8 - Low-power regulator started

pub fn flash_rdy(&self) -> FLASH_RDY_R

Bit 7 - Flash ready flag

impl R<u32, Reg<u32, _PUCRA>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port A pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRA>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port A pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRB>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port B pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRB>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port B pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRC>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port C pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRC>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port C pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRD>>

pub fn pu3(&self) -> PU3_R

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port D pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRD>>

pub fn pd9(&self) -> PD9_R

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port D pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRF>>

pub fn pu2(&self) -> PU2_R

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port F pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRF>>

pub fn pd2(&self) -> PD2_R

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port F pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _CR>>

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

impl R<u32, Reg<u32, _NDTR>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _PAR>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _MAR>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _ISR>>

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel 1 global interrupt flag

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel 1 transfer complete flag

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel 1 half transfer flag

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel 1 transfer error flag

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel 2 global interrupt flag

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel 2 transfer complete flag

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel 2 half transfer flag

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel 2 transfer error flag

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel 3 global interrupt flag

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel 3 transfer complete flag

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel 3 half transfer flag

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel 3 transfer error flag

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel 4 global interrupt flag

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel 4 transfer complete flag

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel 4 half transfer flag

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel 4 transfer error flag

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel 5 global interrupt flag

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel 5 transfer complete flag

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel 5 half transfer flag

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel 5 transfer error flag

impl R<u32, Reg<u32, _C0CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C1CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C2CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C3CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C4CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C5CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _C6CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _RG0CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG1CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG2CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RG3CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _RGSR>>

pub fn of(&self) -> OF_R

Bits 0:3 - Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _CR>>

pub fn npblb(&self) -> NPBLB_R

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&self) -> KEYSIZE_R

Bit 18 - Key size selection

pub fn chmod2(&self) -> CHMOD2_R

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&self) -> GCMPH_R

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&self) -> DMAOUTEN_R

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&self) -> DMAINEN_R

Bit 11 - Enable DMA management of data input phase

pub fn errie(&self) -> ERRIE_R

Bit 10 - Error interrupt enable

pub fn ccfie(&self) -> CCFIE_R

Bit 9 - CCF flag interrupt enable

pub fn errc(&self) -> ERRC_R

Bit 8 - Error clear

pub fn ccfc(&self) -> CCFC_R

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&self) -> CHMOD10_R

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&self) -> MODE_R

Bits 3:4 - AES operating mode

pub fn datatype(&self) -> DATATYPE_R

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&self) -> EN_R

Bit 0 - AES enable

impl R<u32, Reg<u32, _SR>>

pub fn busy(&self) -> BUSY_R

Bit 3 - Busy flag

pub fn wrerr(&self) -> WRERR_R

Bit 2 - Write error flag

pub fn rderr(&self) -> RDERR_R

Bit 1 - Read error flag

pub fn ccf(&self) -> CCF_R

Bit 0 - Computation complete flag

impl R<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&self) -> AES_DINR_R

Bits 0:31 - Data Input Register

impl R<u32, Reg<u32, _DOUTR>>

pub fn aes_doutr(&self) -> AES_DOUTR_R

Bits 0:31 - Data output register

impl R<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&self) -> AES_KEYR0_R

Bits 0:31 - Data Output Register (LSB key [31:0])

impl R<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&self) -> AES_KEYR1_R

Bits 0:31 - AES key register (key [63:32])

impl R<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&self) -> AES_KEYR2_R

Bits 0:31 - AES key register (key [95:64])

impl R<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&self) -> AES_KEYR3_R

Bits 0:31 - AES key register (MSB key [127:96])

impl R<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&self) -> AES_IVR0_R

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl R<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&self) -> AES_IVR1_R

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl R<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&self) -> AES_IVR2_R

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl R<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&self) -> AES_IVR3_R

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl R<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&self) -> AES_KEYR4_R

Bits 0:31 - AES key register (MSB key [159:128])

impl R<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&self) -> AES_KEYR5_R

Bits 0:31 - AES key register (MSB key [191:160])

impl R<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&self) -> AES_KEYR6_R

Bits 0:31 - AES key register (MSB key [223:192])

impl R<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&self) -> AES_KEYR7_R

Bits 0:31 - AES key register (MSB key [255:224])

impl R<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&self) -> AES_SUSP0R_R

Bits 0:31 - AES suspend register 0

impl R<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&self) -> AES_SUSP1R_R

Bits 0:31 - AES suspend register 1

impl R<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&self) -> AES_SUSP2R_R

Bits 0:31 - AES suspend register 2

impl R<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&self) -> AES_SUSP3R_R

Bits 0:31 - AES suspend register 3

impl R<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&self) -> AES_SUSP4R_R

Bits 0:31 - AES suspend register 4

impl R<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&self) -> AES_SUSP5R_R

Bits 0:31 - AES suspend register 5

impl R<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&self) -> AES_SUSP6R_R

Bits 0:31 - AES suspend register 6

impl R<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&self) -> AES_SUSP7R_R

Bits 0:31 - AES suspend register 7

impl R<u32, Reg<u32, _CR>>

pub fn rngen(&self) -> RNGEN_R

Bit 2 - Random number generator enable

pub fn ie(&self) -> IE_R

Bit 3 - Interrupt enable

pub fn ced(&self) -> CED_R

Bit 5 - Clock error detection

pub fn byp(&self) -> BYP_R

Bit 6 - Bypass mode enable

impl R<u32, Reg<u32, _SR>>

pub fn seis(&self) -> SEIS_R

Bit 6 - Seed error interrupt status

pub fn ceis(&self) -> CEIS_R

Bit 5 - Clock error interrupt status

pub fn secs(&self) -> SECS_R

Bit 2 - Seed error current status

pub fn cecs(&self) -> CECS_R

Bit 1 - Clock error current status

pub fn drdy(&self) -> DRDY_R

Bit 0 - Data ready

impl R<u32, Reg<u32, _DR>>

pub fn rndata(&self) -> RNDATA_R

Bits 0:31 - Random data

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:31 - Data register bits

impl R<u32, Reg<u32, _IDR>>

pub fn idr(&self) -> IDR_R

Bits 0:31 - General-purpose 32-bit data register bits

impl R<u32, Reg<u32, _CR>>

pub fn rev_out(&self) -> REV_OUT_R

Bit 7 - Reverse output data

pub fn rev_in(&self) -> REV_IN_R

Bits 5:6 - Reverse input data

pub fn polysize(&self) -> POLYSIZE_R

Bits 3:4 - Polynomial size

impl R<u32, Reg<u32, _INIT>>

pub fn crc_init(&self) -> CRC_INIT_R

Bits 0:31 - Programmable initial CRC value

impl R<u32, Reg<u32, _POL>>

pub fn pol(&self) -> POL_R

Bits 0:31 - Programmable polynomial

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _RTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _FTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, SWIER0_A>

pub fn variant(&self) -> Variant<bool, SWIER0_A>

Get enumerated values variant

pub fn is_pend(&self) -> bool

Checks if the value of the field is PEND

impl R<u32, Reg<u32, _SWIER1>>

pub fn swier0(&self) -> SWIER0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&self) -> SWIER1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&self) -> SWIER2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&self) -> SWIER3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&self) -> SWIER4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&self) -> SWIER5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&self) -> SWIER6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&self) -> SWIER7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&self) -> SWIER8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&self) -> SWIER9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&self) -> SWIER10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&self) -> SWIER11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&self) -> SWIER12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&self) -> SWIER13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&self) -> SWIER14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&self) -> SWIER15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&self) -> SWIER16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, RPIF0_A>

pub fn variant(&self) -> RPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _RPR1>>

pub fn rpif0(&self) -> RPIF0_R

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&self) -> RPIF1_R

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&self) -> RPIF2_R

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&self) -> RPIF3_R

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&self) -> RPIF4_R

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&self) -> RPIF5_R

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&self) -> RPIF6_R

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&self) -> RPIF7_R

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&self) -> RPIF8_R

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&self) -> RPIF9_R

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&self) -> RPIF10_R

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&self) -> RPIF11_R

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&self) -> RPIF12_R

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&self) -> RPIF13_R

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&self) -> RPIF14_R

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&self) -> RPIF15_R

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&self) -> RPIF16_R

Bit 16 - configurable event inputs x rising edge Pending bit.

impl R<bool, FPIF0_A>

pub fn variant(&self) -> FPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _FPR1>>

pub fn fpif0(&self) -> FPIF0_R

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&self) -> FPIF1_R

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&self) -> FPIF2_R

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&self) -> FPIF3_R

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&self) -> FPIF4_R

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&self) -> FPIF5_R

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&self) -> FPIF6_R

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&self) -> FPIF7_R

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&self) -> FPIF8_R

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&self) -> FPIF9_R

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&self) -> FPIF10_R

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&self) -> FPIF11_R

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&self) -> FPIF12_R

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&self) -> FPIF13_R

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&self) -> FPIF14_R

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&self) -> FPIF15_R

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&self) -> FPIF16_R

Bit 16 - configurable event inputs x falling edge pending bit.

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<bool, IM0_A>

pub fn variant(&self) -> IM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR1>>

pub fn im0(&self) -> IM0_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&self) -> IM1_R

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&self) -> IM2_R

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&self) -> IM3_R

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&self) -> IM4_R

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&self) -> IM5_R

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&self) -> IM6_R

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&self) -> IM7_R

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&self) -> IM8_R

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&self) -> IM9_R

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&self) -> IM10_R

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&self) -> IM11_R

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&self) -> IM12_R

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&self) -> IM13_R

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&self) -> IM14_R

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&self) -> IM15_R

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&self) -> IM16_R

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im19(&self) -> IM19_R

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&self) -> IM20_R

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&self) -> IM21_R

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&self) -> IM22_R

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&self) -> IM23_R

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&self) -> IM24_R

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&self) -> IM25_R

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&self) -> IM26_R

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im28(&self) -> IM28_R

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&self) -> IM29_R

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&self) -> IM30_R

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&self) -> IM31_R

Bit 31 - CPU wakeup with interrupt mask on event input

impl R<bool, EM0_A>

pub fn variant(&self) -> EM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR1>>

pub fn em0(&self) -> EM0_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&self) -> EM1_R

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&self) -> EM2_R

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&self) -> EM3_R

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&self) -> EM4_R

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&self) -> EM5_R

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&self) -> EM6_R

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&self) -> EM7_R

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&self) -> EM8_R

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&self) -> EM9_R

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&self) -> EM10_R

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&self) -> EM11_R

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&self) -> EM12_R

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&self) -> EM13_R

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&self) -> EM14_R

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&self) -> EM15_R

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&self) -> EM16_R

Bit 16 - CPU wakeup with event mask on event input

pub fn em19(&self) -> EM19_R

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&self) -> EM21_R

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&self) -> EM23_R

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&self) -> EM25_R

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&self) -> EM26_R

Bit 26 - CPU wakeup with event mask on event input

pub fn em28(&self) -> EM28_R

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&self) -> EM29_R

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&self) -> EM30_R

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&self) -> EM31_R

Bit 31 - CPU wakeup with event mask on event input

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&self) -> BKDFBK1E_R

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - selects input

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT

pub fn dedt(&self) -> DEDT_R

Bits 16:20 - DEDT

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn rtoen(&self) -> RTOEN_R

Bit 23 - Receiver timeout enable

pub fn abrmod(&self) -> ABRMOD_R

Bits 21:22 - Auto baud rate mode

pub fn abren(&self) -> ABREN_R

Bit 20 - Auto baud rate enable

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn linen(&self) -> LINEN_R

Bit 14 - LIN mode enable

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn clken(&self) -> CLKEN_R

Bit 11 - Clock enable

pub fn cpol(&self) -> CPOL_R

Bit 10 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 9 - Clock phase

pub fn lbcl(&self) -> LBCL_R

Bit 8 - Last bit clock pulse

pub fn lbdie(&self) -> LBDIE_R

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&self) -> LBDL_R

Bit 5 - LIN break detection length

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&self) -> DIS_NSS_R

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&self) -> SLVEN_R

Bit 0 - Synchronous Slave mode enable

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&self) -> TCBGTIE_R

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&self) -> SCARCNT_R

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn onebit(&self) -> ONEBIT_R

Bit 11 - One sample bit method enable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn scen(&self) -> SCEN_R

Bit 5 - Smartcard mode enable

pub fn nack(&self) -> NACK_R

Bit 4 - Smartcard NACK enable

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn irlp(&self) -> IRLP_R

Bit 2 - Ir low-power

pub fn iren(&self) -> IREN_R

Bit 1 - Ir mode enable

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&self) -> BRR_4_15_R

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&self) -> BRR_0_3_R

Bits 0:3 - BRR_0_3

impl R<u32, Reg<u32, _GTPR>>

pub fn gt(&self) -> GT_R

Bits 8:15 - Guard time value

pub fn psc(&self) -> PSC_R

Bits 0:7 - Prescaler value

impl R<u32, Reg<u32, _RTOR>>

pub fn blen(&self) -> BLEN_R

Bits 24:31 - Block Length

pub fn rto(&self) -> RTO_R

Bits 0:23 - Receiver timeout value

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn tcbgt(&self) -> TCBGT_R

Bit 25 - Transmission complete before guard time flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn abrf(&self) -> ABRF_R

Bit 15 - ABRF

pub fn abre(&self) -> ABRE_R

Bit 14 - ABRE

pub fn udr(&self) -> UDR_R

Bit 13 - SPI slave underrun error flag

pub fn eobf(&self) -> EOBF_R

Bit 12 - EOBF

pub fn rtof(&self) -> RTOF_R

Bit 11 - RTOF

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn lbdf(&self) -> LBDF_R

Bit 8 - LBDF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn bidimode(&self) -> BIDIMODE_R

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&self) -> BIDIOE_R

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&self) -> CRCEN_R

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&self) -> CRCNEXT_R

Bit 12 - CRC transfer next

pub fn dff(&self) -> DFF_R

Bit 11 - Data frame format

pub fn rxonly(&self) -> RXONLY_R

Bit 10 - Receive only

pub fn ssm(&self) -> SSM_R

Bit 9 - Software slave management

pub fn ssi(&self) -> SSI_R

Bit 8 - Internal slave select

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 7 - Frame format

pub fn spe(&self) -> SPE_R

Bit 6 - SPI enable

pub fn br(&self) -> BR_R

Bits 3:5 - Baud rate control

pub fn mstr(&self) -> MSTR_R

Bit 2 - Master selection

pub fn cpol(&self) -> CPOL_R

Bit 1 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 0 - Clock phase

impl R<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&self) -> SSOE_R

Bit 2 - SS output enable

pub fn nssp(&self) -> NSSP_R

Bit 3 - NSS pulse management

pub fn frf(&self) -> FRF_R

Bit 4 - Frame format

pub fn errie(&self) -> ERRIE_R

Bit 5 - Error interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&self) -> DS_R

Bits 8:11 - Data size

pub fn frxth(&self) -> FRXTH_R

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&self) -> LDMA_RX_R

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&self) -> LDMA_TX_R

Bit 14 - Last DMA transfer for transmission

impl R<u32, Reg<u32, _SR>>

pub fn rxne(&self) -> RXNE_R

Bit 0 - Receive buffer not empty

pub fn txe(&self) -> TXE_R

Bit 1 - Transmit buffer empty

pub fn chside(&self) -> CHSIDE_R

Bit 2 - Channel side

pub fn udr(&self) -> UDR_R

Bit 3 - Underrun flag

pub fn crcerr(&self) -> CRCERR_R

Bit 4 - CRC error flag

pub fn modf(&self) -> MODF_R

Bit 5 - Mode fault

pub fn ovr(&self) -> OVR_R

Bit 6 - Overrun flag

pub fn bsy(&self) -> BSY_R

Bit 7 - Busy flag

pub fn tifrfe(&self) -> TIFRFE_R

Bit 8 - TI frame format error

pub fn frlvl(&self) -> FRLVL_R

Bits 9:10 - FIFO reception level

pub fn ftlvl(&self) -> FTLVL_R

Bits 11:12 - FIFO transmission level

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:15 - Data register

impl R<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&self) -> CRCPOLY_R

Bits 0:15 - CRC polynomial register

impl R<u32, Reg<u32, _RXCRCR>>

pub fn rx_crc(&self) -> RXCRC_R

Bits 0:15 - Rx CRC register

impl R<u32, Reg<u32, _TXCRCR>>

pub fn tx_crc(&self) -> TXCRC_R

Bits 0:15 - Tx CRC register

impl R<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&self) -> CHLEN_R

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&self) -> DATLEN_R

Bits 1:2 - Data length to be transferred

pub fn ckpol(&self) -> CKPOL_R

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&self) -> I2SSTD_R

Bits 4:5 - standard selection

pub fn pcmsync(&self) -> PCMSYNC_R

Bit 7 - PCM frame synchronization

pub fn i2scfg(&self) -> I2SCFG_R

Bits 8:9 - I2S configuration mode

pub fn se2(&self) -> SE2_R

Bit 10 - I2S enable

pub fn i2smod(&self) -> I2SMOD_R

Bit 11 - I2S mode selection

impl R<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&self) -> I2SDIV_R

Bits 0:7 - linear prescaler

pub fn odd(&self) -> ODD_R

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&self) -> MCKOE_R

Bit 9 - Master clock output enable

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn ts_4(&self) -> TS_4_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn ts(&self) -> TS_R

Bits 20:21 - Trigger selection

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag

pub fn cc5if(&self) -> CC5IF_R

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&self) -> CC6IF_R

Bit 17 - Compare 6 interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

impl R<u32, Reg<u32, _CCER>>

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&self) -> CC2NE_R

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&self) -> CC3NE_R

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&self) -> CC5E_R

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&self) -> CC5P_R

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&self) -> CC6E_R

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&self) -> CC6P_R

Bit 21 - Capture/Compare 6 output polarity

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:15 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3(&self) -> CCR3_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4(&self) -> CCR4_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bk2f(&self) -> BK2F_R

Bits 20:23 - Break 2 filter

pub fn bk2e(&self) -> BK2E_R

Bit 24 - Break 2 enable

pub fn bk2p(&self) -> BK2P_R

Bit 25 - Break 2 polarity

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bk2dsrm(&self) -> BK2DSRM_R

Bit 27 - Break2 Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

pub fn bk2id(&self) -> BK2ID_R

Bit 29 - Break2 bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&self) -> OCREF_CLR_R

Bit 0 - Ocref_clr source selection

impl R<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&self) -> OC6M_BIT3_R

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&self) -> OC5M_BIT3_R

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&self) -> OC6CE_R

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&self) -> OC6M_R

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&self) -> OC6PE_R

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&self) -> OC6FE_R

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&self) -> OC5CE_R

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&self) -> OC5M_R

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&self) -> OC5PE_R

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&self) -> OC5FE_R

Bit 2 - Output compare 5 fast enable

impl R<u32, Reg<u32, _CCR5>>

pub fn ccr5(&self) -> CCR5_R

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&self) -> GC5C1_R

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&self) -> GC5C2_R

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&self) -> GC5C3_R

Bit 31 - Group Channel 5 and Channel 3

impl R<u32, Reg<u32, _CCR6>>

pub fn ccr6(&self) -> CCR6_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - ETR source selection

impl R<u32, Reg<u32, _AF2>>

pub fn bk2ine(&self) -> BK2INE_R

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&self) -> BK2CMP1E_R

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&self) -> BK2CMP2E_R

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&self) -> BK2INP_R

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&self) -> BK2CMP1P_R

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&self) -> BK2CMP2P_R

Bit 11 - BRK2 COMP2 input polarity

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel3_0(&self) -> TI1SEL3_0_R

Bits 0:3 - selects TI1[0] to TI1[15] input

pub fn ti2sel3_0(&self) -> TI2SEL3_0_R

Bits 8:11 - selects TI2[0] to TI2[15] input

pub fn ti3sel3_0(&self) -> TI3SEL3_0_R

Bits 16:19 - selects TI3[0] to TI3[15] input

pub fn ti4sel3_0(&self) -> TI4SEL3_0_R

Bits 24:27 - selects TI4[0] to TI4[15] input

impl R<u32, Reg<u32, _ISR>>

pub fn ccrdy(&self) -> CCRDY_R

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&self) -> EOCAL_R

Bit 11 - End Of Calibration flag

pub fn awd3(&self) -> AWD3_R

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&self) -> AWD2_R

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&self) -> AWD1_R

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&self) -> OVR_R

Bit 4 - ADC group regular overrun flag

pub fn eos(&self) -> EOS_R

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&self) -> EOC_R

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&self) -> EOSMP_R

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&self) -> ADRDY_R

Bit 0 - ADC ready flag

impl R<u32, Reg<u32, _IER>>

pub fn ccrdyie(&self) -> CCRDYIE_R

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&self) -> EOCALIE_R

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&self) -> AWD3IE_R

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&self) -> AWD2IE_R

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&self) -> AWD1IE_R

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&self) -> OVRIE_R

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&self) -> EOSIE_R

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&self) -> EOCIE_R

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&self) -> EOSMPIE_R

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&self) -> ADRDYIE_R

Bit 0 - ADC ready interrupt

impl R<u32, Reg<u32, _CR>>

pub fn adcal(&self) -> ADCAL_R

Bit 31 - ADC calibration

pub fn advregen(&self) -> ADVREGEN_R

Bit 28 - ADC voltage regulator enable

pub fn adstp(&self) -> ADSTP_R

Bit 4 - ADC group regular conversion stop

pub fn adstart(&self) -> ADSTART_R

Bit 2 - ADC group regular conversion start

pub fn addis(&self) -> ADDIS_R

Bit 1 - ADC disable

pub fn aden(&self) -> ADEN_R

Bit 0 - ADC enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&self) -> AWDCH1CH_R

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&self) -> AWD1EN_R

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGL_R

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&self) -> CHSELRMOD_R

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&self) -> DISCEN_R

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&self) -> AUTOFF_R

Bit 15 - Auto-off mode

pub fn wait(&self) -> WAIT_R

Bit 14 - Wait conversion mode

pub fn cont(&self) -> CONT_R

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMOD_R

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTEN_R

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSEL_R

Bits 6:8 - ADC group regular external trigger source

pub fn align(&self) -> ALIGN_R

Bit 5 - ADC data alignement

pub fn res(&self) -> RES_R

Bits 3:4 - ADC data resolution

pub fn scandir(&self) -> SCANDIR_R

Bit 2 - Scan sequence direction

pub fn dmacfg(&self) -> DMACFG_R

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - ADC DMA transfer enable

impl R<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&self) -> CKMODE_R

Bits 30:31 - ADC clock mode

pub fn lftrig(&self) -> LFTRIG_R

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&self) -> TOVS_R

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&self) -> OVSS_R

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&self) -> OVSR_R

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&self) -> OVSE_R

Bit 0 - ADC oversampler enable on scope ADC group regular

impl R<u32, Reg<u32, _SMPR>>

pub fn smp1(&self) -> SMP1_R

Bits 0:2 - Sampling time selection

pub fn smp2(&self) -> SMP2_R

Bits 4:6 - Sampling time selection

pub fn smpsel(&self) -> SMPSEL_R

Bits 8:26 - Channel sampling time selection

impl R<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&self) -> HT1_R

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&self) -> LT1_R

Bits 0:11 - ADC analog watchdog 1 threshold low

impl R<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&self) -> HT2_R

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&self) -> LT2_R

Bits 0:11 - ADC analog watchdog 2 threshold low

impl R<u32, Reg<u32, _CHSELR>>

pub fn chsel(&self) -> CHSEL_R

Bits 0:18 - Channel-x selection

impl R<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&self) -> SQ1_R

Bits 0:3 - conversion of the sequence

pub fn sq2(&self) -> SQ2_R

Bits 4:7 - conversion of the sequence

pub fn sq3(&self) -> SQ3_R

Bits 8:11 - conversion of the sequence

pub fn sq4(&self) -> SQ4_R

Bits 12:15 - conversion of the sequence

pub fn sq5(&self) -> SQ5_R

Bits 16:19 - conversion of the sequence

pub fn sq6(&self) -> SQ6_R

Bits 20:23 - conversion of the sequence

pub fn sq7(&self) -> SQ7_R

Bits 24:27 - conversion of the sequence

pub fn sq8(&self) -> SQ8_R

Bits 28:31 - conversion of the sequence

impl R<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&self) -> HT3_R

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&self) -> LT3_R

Bits 0:11 - ADC analog watchdog 3 threshold high

impl R<u32, Reg<u32, _DR>>

pub fn regular_data(&self) -> REGULARDATA_R

Bits 0:15 - ADC group regular conversion data

impl R<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&self) -> AWD2CH_R

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl R<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&self) -> AWD3CH_R

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl R<u32, Reg<u32, _CALFACT>>

pub fn calfact(&self) -> CALFACT_R

Bits 0:6 - ADC calibration factor in single-ended mode

impl R<u32, Reg<u32, _CCR>>

pub fn presc(&self) -> PRESC_R

Bits 18:21 - ADC prescaler

pub fn vrefen(&self) -> VREFEN_R

Bit 22 - VREFINT enable

pub fn tsen(&self) -> TSEN_R

Bit 23 - Temperature sensor enable

pub fn vbaten(&self) -> VBATEN_R

Bit 24 - VBAT enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&self) -> I2C_PAX_FMP_R

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&self) -> I2C2_FMP_R

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&self) -> I2C1_FMP_R

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&self) -> I2C_PBX_FMP_R

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn boosten(&self) -> BOOSTEN_R

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&self) -> IR_MOD_R

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&self) -> IR_POL_R

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&self) -> PA11_PA12_RMP_R

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&self) -> MEM_MODE_R

Bits 0:1 - Memory mapping selection bits

impl R<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&self) -> LOCKUP_LOCK_R

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&self) -> SRAM_PARITY_LOCK_R

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&self) -> PVD_LOCK_R

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&self) -> ECC_LOCK_R

Bit 3 - ECC error lock bit

pub fn sram_pef(&self) -> SRAM_PEF_R

Bit 8 - SRAM parity error flag

pub fn pa1_cden(&self) -> PA1_CDEN_R

Bit 16 - PA1_CDEN

pub fn pa3_cden(&self) -> PA3_CDEN_R

Bit 17 - PA3_CDEN

pub fn pa5_cden(&self) -> PA5_CDEN_R

Bit 18 - PA5_CDEN

pub fn pa6_cden(&self) -> PA6_CDEN_R

Bit 19 - PA6_CDEN

pub fn pa13_cden(&self) -> PA13_CDEN_R

Bit 20 - PA13_CDEN

pub fn pb0_cden(&self) -> PB0_CDEN_R

Bit 21 - PB0_CDEN

pub fn pb1_cden(&self) -> PB1_CDEN_R

Bit 22 - PB1_CDEN

pub fn pb2_cden(&self) -> PB2_CDEN_R

Bit 23 - PB2_CDEN

impl R<u32, Reg<u32, _CR1>>

pub fn tamp1e(&self) -> TAMP1E_R

Bit 0 - TAMP1E

pub fn tamp2e(&self) -> TAMP2E_R

Bit 1 - TAMP2E

pub fn itamp1e(&self) -> ITAMP1E_R

Bit 16 - ITAMP1E

pub fn itamp3e(&self) -> ITAMP3E_R

Bit 18 - ITAMP3E

pub fn itamp4e(&self) -> ITAMP4E_R

Bit 19 - ITAMP4E

pub fn itamp5e(&self) -> ITAMP5E_R

Bit 20 - ITAMP5E

pub fn itamp6e(&self) -> ITAMP6E_R

Bit 21 - ITAMP6E

impl R<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&self) -> TAMP1NOER_R

Bit 0 - TAMP1NOER

pub fn tamp2noer(&self) -> TAMP2NOER_R

Bit 1 - TAMP2NOER

pub fn tamp1msk(&self) -> TAMP1MSK_R

Bit 16 - TAMP1MSK

pub fn tamp2msk(&self) -> TAMP2MSK_R

Bit 17 - TAMP2MSK

pub fn tamp1trg(&self) -> TAMP1TRG_R

Bit 24 - TAMP1TRG

pub fn tamp2trg(&self) -> TAMP2TRG_R

Bit 25 - TAMP2TRG

impl R<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&self) -> TAMPFREQ_R

Bits 0:2 - TAMPFREQ

pub fn tampflt(&self) -> TAMPFLT_R

Bits 3:4 - TAMPFLT

pub fn tampprch(&self) -> TAMPPRCH_R

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&self) -> TAMPPUDIS_R

Bit 7 - TAMPPUDIS

impl R<u32, Reg<u32, _IER>>

pub fn tamp1ie(&self) -> TAMP1IE_R

Bit 0 - TAMP1IE

pub fn tamp2ie(&self) -> TAMP2IE_R

Bit 1 - TAMP2IE

pub fn itamp1ie(&self) -> ITAMP1IE_R

Bit 16 - ITAMP1IE

pub fn itamp3ie(&self) -> ITAMP3IE_R

Bit 18 - ITAMP3IE

pub fn itamp4ie(&self) -> ITAMP4IE_R

Bit 19 - ITAMP4IE

pub fn itamp5ie(&self) -> ITAMP5IE_R

Bit 20 - ITAMP5IE

pub fn itamp6ie(&self) -> ITAMP6IE_R

Bit 21 - ITAMP6IE

impl R<u32, Reg<u32, _SR>>

pub fn tamp1f(&self) -> TAMP1F_R

Bit 0 - TAMP1F

pub fn tamp2f(&self) -> TAMP2F_R

Bit 1 - TAMP2F

pub fn itamp1f(&self) -> ITAMP1F_R

Bit 16 - ITAMP1F

pub fn itamp3f(&self) -> ITAMP3F_R

Bit 18 - ITAMP3F

pub fn itamp4f(&self) -> ITAMP4F_R

Bit 19 - ITAMP4F

pub fn itamp5f(&self) -> ITAMP5F_R

Bit 20 - ITAMP5F

pub fn itamp6f(&self) -> ITAMP6F_R

Bit 21 - ITAMP6F

pub fn itamp7f(&self) -> ITAMP7F_R

Bit 22 - ITAMP7F

impl R<u32, Reg<u32, _MISR>>

pub fn tamp1mf(&self) -> TAMP1MF_R

Bit 0 - TAMP1MF:

pub fn tamp2mf(&self) -> TAMP2MF_R

Bit 1 - TAMP2MF

pub fn itamp1mf(&self) -> ITAMP1MF_R

Bit 16 - ITAMP1MF

pub fn itamp3mf(&self) -> ITAMP3MF_R

Bit 18 - ITAMP3MF

pub fn itamp4mf(&self) -> ITAMP4MF_R

Bit 19 - ITAMP4MF

pub fn itamp5mf(&self) -> ITAMP5MF_R

Bit 20 - ITAMP5MF

pub fn itamp6mf(&self) -> ITAMP6MF_R

Bit 21 - ITAMP6MF

impl R<u32, Reg<u32, _BKP0R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP1R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP2R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP3R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP4R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _ISR>>

pub fn down(&self) -> DOWN_R

Bit 6 - Counter direction change up to down

pub fn up(&self) -> UP_R

Bit 5 - Counter direction change down to up

pub fn arrok(&self) -> ARROK_R

Bit 4 - Autoreload register update OK

pub fn cmpok(&self) -> CMPOK_R

Bit 3 - Compare register update OK

pub fn exttrig(&self) -> EXTTRIG_R

Bit 2 - External trigger edge event

pub fn arrm(&self) -> ARRM_R

Bit 1 - Autoreload match

pub fn cmpm(&self) -> CMPM_R

Bit 0 - Compare match

impl R<u32, Reg<u32, _IER>>

pub fn downie(&self) -> DOWNIE_R

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&self) -> UPIE_R

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&self) -> ARROKIE_R

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&self) -> CMPOKIE_R

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&self) -> EXTTRIGIE_R

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&self) -> ARRMIE_R

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&self) -> CMPMIE_R

Bit 0 - Compare match Interrupt Enable

impl R<u32, Reg<u32, _CFGR>>

pub fn enc(&self) -> ENC_R

Bit 24 - Encoder mode enable

pub fn countmode(&self) -> COUNTMODE_R

Bit 23 - counter mode enabled

pub fn preload(&self) -> PRELOAD_R

Bit 22 - Registers update mode

pub fn wavpol(&self) -> WAVPOL_R

Bit 21 - Waveform shape polarity

pub fn wave(&self) -> WAVE_R

Bit 20 - Waveform shape

pub fn timout(&self) -> TIMOUT_R

Bit 19 - Timeout enable

pub fn trigen(&self) -> TRIGEN_R

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&self) -> TRIGSEL_R

Bits 13:15 - Trigger selector

pub fn presc(&self) -> PRESC_R

Bits 9:11 - Clock prescaler

pub fn trgflt(&self) -> TRGFLT_R

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&self) -> CKFLT_R

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&self) -> CKPOL_R

Bits 1:2 - Clock Polarity

pub fn cksel(&self) -> CKSEL_R

Bit 0 - Clock selector

impl R<u32, Reg<u32, _CR>>

pub fn rstare(&self) -> RSTARE_R

Bit 4 - Reset after read enable

pub fn countrst(&self) -> COUNTRST_R

Bit 3 - Counter reset

pub fn cntstrt(&self) -> CNTSTRT_R

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&self) -> SNGSTRT_R

Bit 1 - LPTIM start in single mode

pub fn enable(&self) -> ENABLE_R

Bit 0 - LPTIM Enable

impl R<u32, Reg<u32, _CMP>>

pub fn cmp(&self) -> CMP_R

Bits 0:15 - Compare value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto reload value

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Counter value

impl R<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&self) -> IN2SEL_R

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&self) -> IN1SEL_R

Bits 0:1 - LPTIMx Input 1 selection

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT0

pub fn dedt0(&self) -> DEDT0_R

Bits 16:20 - DEDT0

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr(&self) -> BRR_R

Bits 0:19 - BRR

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn pe(&self) -> PE_R

Bit 0 - Peripheral enable

pub fn txie(&self) -> TXIE_R

Bit 1 - TX Interrupt enable

pub fn rxie(&self) -> RXIE_R

Bit 2 - RX Interrupt enable

pub fn addrie(&self) -> ADDRIE_R

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&self) -> NACKIE_R

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&self) -> STOPIE_R

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 7 - Error interrupts enable

pub fn dnf(&self) -> DNF_R

Bits 8:11 - Digital noise filter

pub fn anfoff(&self) -> ANFOFF_R

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 15 - DMA reception requests enable

pub fn sbc(&self) -> SBC_R

Bit 16 - Slave byte control

pub fn nostretch(&self) -> NOSTRETCH_R

Bit 17 - Clock stretching disable

pub fn wupen(&self) -> WUPEN_R

Bit 18 - Wakeup from STOP enable

pub fn gcen(&self) -> GCEN_R

Bit 19 - General call enable

pub fn smbhen(&self) -> SMBHEN_R

Bit 20 - SMBus Host address enable

pub fn smbden(&self) -> SMBDEN_R

Bit 21 - SMBus Device Default address enable

pub fn alerten(&self) -> ALERTEN_R

Bit 22 - SMBUS alert enable

pub fn pecen(&self) -> PECEN_R

Bit 23 - PEC enable

impl R<u32, Reg<u32, _CR2>>

pub fn pecbyte(&self) -> PECBYTE_R

Bit 26 - Packet error checking byte

pub fn autoend(&self) -> AUTOEND_R

Bit 25 - Automatic end mode (master mode)

pub fn reload(&self) -> RELOAD_R

Bit 24 - NBYTES reload mode

pub fn nbytes(&self) -> NBYTES_R

Bits 16:23 - Number of bytes

pub fn nack(&self) -> NACK_R

Bit 15 - NACK generation (slave mode)

pub fn stop(&self) -> STOP_R

Bit 14 - Stop generation (master mode)

pub fn start(&self) -> START_R

Bit 13 - Start generation

pub fn head10r(&self) -> HEAD10R_R

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&self) -> ADD10_R

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&self) -> RD_WRN_R

Bit 10 - Transfer direction (master mode)

pub fn sadd(&self) -> SADD_R

Bits 0:9 - Slave address bit (master mode)

impl R<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&self) -> OA1_0_R

Bit 0 - Interface address

pub fn oa1_7_1(&self) -> OA1_7_1_R

Bits 1:7 - Interface address

pub fn oa1_8_9(&self) -> OA1_8_9_R

Bits 8:9 - Interface address

pub fn oa1mode(&self) -> OA1MODE_R

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&self) -> OA1EN_R

Bit 15 - Own Address 1 enable

impl R<u32, Reg<u32, _OAR2>>

pub fn oa2(&self) -> OA2_R

Bits 1:7 - Interface address

pub fn oa2msk(&self) -> OA2MSK_R

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&self) -> OA2EN_R

Bit 15 - Own Address 2 enable

impl R<u32, Reg<u32, _TIMINGR>>

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler

impl R<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&self) -> TIMEOUTA_R

Bits 0:11 - Bus timeout A

pub fn tidle(&self) -> TIDLE_R

Bit 12 - Idle clock timeout detection

pub fn timouten(&self) -> TIMOUTEN_R

Bit 15 - Clock timeout enable

pub fn timeoutb(&self) -> TIMEOUTB_R

Bits 16:27 - Bus timeout B

pub fn texten(&self) -> TEXTEN_R

Bit 31 - Extended clock timeout enable

impl R<u32, Reg<u32, _ISR>>

pub fn addcode(&self) -> ADDCODE_R

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R

Bit 0 - Transmit data register empty (transmitters)

impl R<u32, Reg<u32, _PECR>>

pub fn pec(&self) -> PEC_R

Bits 0:7 - Packet error checking register

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - 8-bit receive data

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - 8-bit transmit data

impl R<u32, Reg<u32, _TR>>

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _DR>>

pub fn yt(&self) -> YT_R

Bits 20:23 - Year tens in BCD format

pub fn yu(&self) -> YU_R

Bits 16:19 - Year units in BCD format

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _SSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ICSR>>

pub fn alrawf(&self) -> ALRAWF_R

Bit 0 - Alarm A write flag

pub fn alrbwf(&self) -> ALRBWF_R

Bit 1 - Alarm B write flag

pub fn wutwf(&self) -> WUTWF_R

Bit 2 - Wakeup timer write flag

pub fn shpf(&self) -> SHPF_R

Bit 3 - Shift operation pending

pub fn inits(&self) -> INITS_R

Bit 4 - Initialization status flag

pub fn rsf(&self) -> RSF_R

Bit 5 - Registers synchronization flag

pub fn initf(&self) -> INITF_R

Bit 6 - Initialization flag

pub fn init(&self) -> INIT_R

Bit 7 - Initialization mode

pub fn recalpf(&self) -> RECALPF_R

Bit 16 - Recalibration pending Flag

impl R<u32, Reg<u32, _PRER>>

pub fn prediv_a(&self) -> PREDIV_A_R

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&self) -> PREDIV_S_R

Bits 0:14 - Synchronous prescaler factor

impl R<u32, Reg<u32, _WUTR>>

pub fn wut(&self) -> WUT_R

Bits 0:15 - Wakeup auto-reload value bits

impl R<u32, Reg<u32, _CR>>

pub fn wucksel(&self) -> WUCKSEL_R

Bits 0:2 - WUCKSEL

pub fn tsedge(&self) -> TSEDGE_R

Bit 3 - TSEDGE

pub fn refckon(&self) -> REFCKON_R

Bit 4 - REFCKON

pub fn bypshad(&self) -> BYPSHAD_R

Bit 5 - BYPSHAD

pub fn fmt(&self) -> FMT_R

Bit 6 - FMT

pub fn alrae(&self) -> ALRAE_R

Bit 8 - ALRAE

pub fn alrbe(&self) -> ALRBE_R

Bit 9 - ALRBE

pub fn wute(&self) -> WUTE_R

Bit 10 - WUTE

pub fn tse(&self) -> TSE_R

Bit 11 - TSE

pub fn alraie(&self) -> ALRAIE_R

Bit 12 - ALRAIE

pub fn alrbie(&self) -> ALRBIE_R

Bit 13 - ALRBIE

pub fn wutie(&self) -> WUTIE_R

Bit 14 - WUTIE

pub fn tsie(&self) -> TSIE_R

Bit 15 - TSIE

pub fn add1h(&self) -> ADD1H_R

Bit 16 - ADD1H

pub fn sub1h(&self) -> SUB1H_R

Bit 17 - SUB1H

pub fn bkp(&self) -> BKP_R

Bit 18 - BKP

pub fn cosel(&self) -> COSEL_R

Bit 19 - COSEL

pub fn pol(&self) -> POL_R

Bit 20 - POL

pub fn osel(&self) -> OSEL_R

Bits 21:22 - OSEL

pub fn coe(&self) -> COE_R

Bit 23 - COE

pub fn itse(&self) -> ITSE_R

Bit 24 - ITSE

pub fn tampts(&self) -> TAMPTS_R

Bit 25 - TAMPTS

pub fn tampoe(&self) -> TAMPOE_R

Bit 26 - TAMPOE

pub fn tampalrm_pu(&self) -> TAMPALRM_PU_R

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&self) -> TAMPALRM_TYPE_R

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&self) -> OUT2EN_R

Bit 31 - OUT2EN

impl R<u32, Reg<u32, _CALR>>

pub fn calp(&self) -> CALP_R

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&self) -> CALW8_R

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&self) -> CALW16_R

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&self) -> CALM_R

Bits 0:8 - Calibration minus

impl R<u32, Reg<u32, _TSTR>>

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

impl R<u32, Reg<u32, _TSDR>>

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _TSSSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm A date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm A hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm A minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm A seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm B date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm B hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm B minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm B seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _SR>>

pub fn alraf(&self) -> ALRAF_R

Bit 0 - ALRAF

pub fn alrbf(&self) -> ALRBF_R

Bit 1 - ALRBF

pub fn wutf(&self) -> WUTF_R

Bit 2 - WUTF

pub fn tsf(&self) -> TSF_R

Bit 3 - TSF

pub fn tsovf(&self) -> TSOVF_R

Bit 4 - TSOVF

pub fn itsf(&self) -> ITSF_R

Bit 5 - ITSF

impl R<u32, Reg<u32, _MISR>>

pub fn alramf(&self) -> ALRAMF_R

Bit 0 - ALRAMF

pub fn alrbmf(&self) -> ALRBMF_R

Bit 1 - ALRBMF

pub fn wutmf(&self) -> WUTMF_R

Bit 2 - WUTMF

pub fn tsmf(&self) -> TSMF_R

Bit 3 - TSMF

pub fn tsovmf(&self) -> TSOVMF_R

Bit 4 - TSOVMF

pub fn itsmf(&self) -> ITSMF_R

Bit 5 - ITSMF

impl R<u32, Reg<u32, _SCR>>

pub fn calraf(&self) -> CALRAF_R

Bit 0 - CALRAF

pub fn calrbf(&self) -> CALRBF_R

Bit 1 - CALRBF

pub fn cwutf(&self) -> CWUTF_R

Bit 2 - CWUTF

pub fn ctsf(&self) -> CTSF_R

Bit 3 - CTSF

pub fn ctsovf(&self) -> CTSOVF_R

Bit 4 - CTSOVF

pub fn citsf(&self) -> CITSF_R

Bit 5 - CITSF

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _DIER>>

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - CC1S

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - OC1FE

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - OC1PE

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - OC1M

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - OC1CE

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&self) -> ICPCS_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _TISEL>>

pub fn tisel(&self) -> TISEL_R

Bits 0:3 - TI1[0] to TI1[15] input selection

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

impl R<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&self) -> TS_4_3_R

Bits 20:21 - Trigger selection

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&self) -> IC3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt_h(&self) -> CNT_H_R

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&self) -> CNT_L_R

Bits 0:15 - Low counter value

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr_h(&self) -> ARR_H_R

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&self) -> ARR_L_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&self) -> CCR1_H_R

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&self) -> CCR1_L_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&self) -> CCR2_H_R

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&self) -> CCR2_L_R

Bits 0:15 - Low Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&self) -> CCR3_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&self) -> CCR3_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&self) -> CCR4_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&self) -> CCR4_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&self) -> IOCREF_CLR_R

Bit 0 - IOCREF_CLR

impl R<u32, Reg<u32, _AF1>>

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:17 - External trigger source selection

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - TI1SEL

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - TI2SEL

impl R<u32, Reg<u32, _CSR>>

pub fn enable(&self) -> ENABLE_R

Bit 0 - Counter enable

pub fn tickint(&self) -> TICKINT_R

Bit 1 - SysTick exception request enable

pub fn clksource(&self) -> CLKSOURCE_R

Bit 2 - Clock source selection

pub fn countflag(&self) -> COUNTFLAG_R

Bit 16 - COUNTFLAG

impl R<u32, Reg<u32, _RVR>>

pub fn reload(&self) -> RELOAD_R

Bits 0:23 - RELOAD value

impl R<u32, Reg<u32, _CVR>>

pub fn current(&self) -> CURRENT_R

Bits 0:23 - Current counter value

impl R<u32, Reg<u32, _CALIB>>

pub fn tenms(&self) -> TENMS_R

Bits 0:23 - Calibration value

pub fn skew(&self) -> SKEW_R

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&self) -> NOREF_R

Bit 31 - NOREF flag. Reads as zero

impl R<u32, Reg<u32, _CSR>>

pub fn envr(&self) -> ENVR_R

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&self) -> HIZ_R

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrr(&self) -> VRR_R

Bit 3 - Voltage reference buffer ready

pub fn vrs(&self) -> VRS_R

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl R<u32, Reg<u32, _CCR>>

pub fn trim(&self) -> TRIM_R

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl R<u32, Reg<u32, _IDCODE>>

pub fn dev_id(&self) -> DEV_ID_R

Bits 0:11 - Device identifier

pub fn rev_id(&self) -> REV_ID_R

Bits 16:31 - Revision identifie

impl R<u32, Reg<u32, _CR>>

pub fn dbg_stop(&self) -> DBG_STOP_R

Bit 1 - Debug Stop mode

pub fn dbg_standby(&self) -> DBG_STANDBY_R

Bit 2 - Debug Standby mode

impl R<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R

Bit 0 - TIM2 counter stopped when core is halted

pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R

Bit 11 - Window watchdog counter stopped when core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - Independent watchdog counter stopped when core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 30 - LPTIM2 counter stopped when core is halted

pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R

Bit 31 - LPTIM1 counter stopped when core is halted

impl R<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - DBG_TIM17_STOP

impl R<u32, Reg<u32, _STIR>>

pub fn intid(&self) -> INTID_R

Bits 0:8 - Software generated interrupt ID

impl R<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&self) -> DISMCYCINT_R

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&self) -> DISDEFWBUF_R

Bit 1 - DISDEFWBUF

pub fn disfold(&self) -> DISFOLD_R

Bit 2 - DISFOLD

pub fn disfpca(&self) -> DISFPCA_R

Bit 8 - DISFPCA

pub fn disoofp(&self) -> DISOOFP_R

Bit 9 - DISOOFP

impl R<u32, Reg<u32, _CPACR>>

pub fn cp(&self) -> CP_R

Bits 20:23 - CP

impl R<u32, Reg<u32, _FPCCR>>

pub fn lspact(&self) -> LSPACT_R

Bit 0 - LSPACT

pub fn user(&self) -> USER_R

Bit 1 - USER

pub fn thread(&self) -> THREAD_R

Bit 3 - THREAD

pub fn hfrdy(&self) -> HFRDY_R

Bit 4 - HFRDY

pub fn mmrdy(&self) -> MMRDY_R

Bit 5 - MMRDY

pub fn bfrdy(&self) -> BFRDY_R

Bit 6 - BFRDY

pub fn monrdy(&self) -> MONRDY_R

Bit 8 - MONRDY

pub fn lspen(&self) -> LSPEN_R

Bit 30 - LSPEN

pub fn aspen(&self) -> ASPEN_R

Bit 31 - ASPEN

impl R<u32, Reg<u32, _FPCAR>>

pub fn address(&self) -> ADDRESS_R

Bits 3:31 - Location of unpopulated floating-point

impl R<u32, Reg<u32, _FPSCR>>

pub fn ioc(&self) -> IOC_R

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&self) -> DZC_R

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&self) -> OFC_R

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&self) -> UFC_R

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&self) -> IXC_R

Bit 4 - Inexact cumulative exception bit

pub fn idc(&self) -> IDC_R

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&self) -> RMODE_R

Bits 22:23 - Rounding Mode control field

pub fn fz(&self) -> FZ_R

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&self) -> DN_R

Bit 25 - Default NaN mode control bit

pub fn ahp(&self) -> AHP_R

Bit 26 - Alternative half-precision control bit

pub fn v(&self) -> V_R

Bit 28 - Overflow condition code flag

pub fn c(&self) -> C_R

Bit 29 - Carry condition code flag

pub fn z(&self) -> Z_R

Bit 30 - Zero condition code flag

pub fn n(&self) -> N_R

Bit 31 - Negative condition code flag

impl R<u32, Reg<u32, _ITLINE0>>

pub fn wwdg(&self) -> WWDG_R

Bit 0 - Window watchdog interrupt pending flag

impl R<u32, Reg<u32, _ITLINE1>>

pub fn pvdout(&self) -> PVDOUT_R

Bit 0 - PVD supply monitoring interrupt request pending (EXTI line 16).

impl R<u32, Reg<u32, _ITLINE2>>

pub fn tamp(&self) -> TAMP_R

Bit 0 - TAMP

pub fn rtc(&self) -> RTC_R

Bit 1 - RTC

impl R<u32, Reg<u32, _ITLINE3>>

pub fn flash_itf(&self) -> FLASH_ITF_R

Bit 0 - FLASH_ITF

pub fn flash_ecc(&self) -> FLASH_ECC_R

Bit 1 - FLASH_ECC

impl R<u32, Reg<u32, _ITLINE4>>

pub fn rcc(&self) -> RCC_R

Bit 0 - RCC

impl R<u32, Reg<u32, _ITLINE5>>

pub fn exti0(&self) -> EXTI0_R

Bit 0 - EXTI0

pub fn exti1(&self) -> EXTI1_R

Bit 1 - EXTI1

impl R<u32, Reg<u32, _ITLINE6>>

pub fn exti2(&self) -> EXTI2_R

Bit 0 - EXTI2

pub fn exti3(&self) -> EXTI3_R

Bit 1 - EXTI3

impl R<u32, Reg<u32, _ITLINE7>>

pub fn exti4(&self) -> EXTI4_R

Bit 0 - EXTI4

pub fn exti5(&self) -> EXTI5_R

Bit 1 - EXTI5

pub fn exti6(&self) -> EXTI6_R

Bit 2 - EXTI6

pub fn exti7(&self) -> EXTI7_R

Bit 3 - EXTI7

pub fn exti8(&self) -> EXTI8_R

Bit 4 - EXTI8

pub fn exti9(&self) -> EXTI9_R

Bit 5 - EXTI9

pub fn exti10(&self) -> EXTI10_R

Bit 6 - EXTI10

pub fn exti11(&self) -> EXTI11_R

Bit 7 - EXTI11

pub fn exti12(&self) -> EXTI12_R

Bit 8 - EXTI12

pub fn exti13(&self) -> EXTI13_R

Bit 9 - EXTI13

pub fn exti14(&self) -> EXTI14_R

Bit 10 - EXTI14

pub fn exti15(&self) -> EXTI15_R

Bit 11 - EXTI15

impl R<u32, Reg<u32, _ITLINE9>>

pub fn dma1_ch1(&self) -> DMA1_CH1_R

Bit 0 - DMA1_CH1

impl R<u32, Reg<u32, _ITLINE10>>

pub fn dma1_ch2(&self) -> DMA1_CH2_R

Bit 0 - DMA1_CH1

pub fn dma1_ch3(&self) -> DMA1_CH3_R

Bit 1 - DMA1_CH3

impl R<u32, Reg<u32, _ITLINE11>>

pub fn dmamux(&self) -> DMAMUX_R

Bit 0 - DMAMUX

pub fn dma1_ch4(&self) -> DMA1_CH4_R

Bit 1 - DMA1_CH4

pub fn dma1_ch5(&self) -> DMA1_CH5_R

Bit 2 - DMA1_CH5

impl R<u32, Reg<u32, _ITLINE12>>

pub fn adc(&self) -> ADC_R

Bit 0 - ADC

impl R<u32, Reg<u32, _ITLINE13>>

pub fn tim1_ccu(&self) -> TIM1_CCU_R

Bit 0 - TIM1_CCU

pub fn tim1_trg(&self) -> TIM1_TRG_R

Bit 1 - TIM1_TRG

pub fn tim1_upd(&self) -> TIM1_UPD_R

Bit 2 - TIM1_UPD

pub fn tim1_brk(&self) -> TIM1_BRK_R

Bit 3 - TIM1_BRK

impl R<u32, Reg<u32, _ITLINE14>>

pub fn tim1_cc(&self) -> TIM1_CC_R

Bit 0 - TIM1_CC

impl R<u32, Reg<u32, _ITLINE15>>

pub fn tim2(&self) -> TIM2_R

Bit 0 - TIM2

impl R<u32, Reg<u32, _ITLINE16>>

pub fn tim3(&self) -> TIM3_R

Bit 0 - TIM3

impl R<u32, Reg<u32, _ITLINE17>>

pub fn lptim1(&self) -> LPTIM1_R

Bit 2 - LPTIM1

impl R<u32, Reg<u32, _ITLINE18>>

pub fn lptim2(&self) -> LPTIM2_R

Bit 1 - LPTIM2

impl R<u32, Reg<u32, _ITLINE19>>

pub fn tim14(&self) -> TIM14_R

Bit 0 - TIM14

impl R<u32, Reg<u32, _ITLINE21>>

pub fn tim16(&self) -> TIM16_R

Bit 0 - TIM16

impl R<u32, Reg<u32, _ITLINE22>>

pub fn tim17(&self) -> TIM17_R

Bit 0 - TIM17

impl R<u32, Reg<u32, _ITLINE23>>

pub fn i2c1(&self) -> I2C1_R

Bit 0 - I2C1

impl R<u32, Reg<u32, _ITLINE24>>

pub fn i2c2(&self) -> I2C2_R

Bit 0 - I2C2

impl R<u32, Reg<u32, _ITLINE25>>

pub fn spi1(&self) -> SPI1_R

Bit 0 - SPI1

impl R<u32, Reg<u32, _ITLINE26>>

pub fn spi2(&self) -> SPI2_R

Bit 0 - SPI2

impl R<u32, Reg<u32, _ITLINE27>>

pub fn usart1(&self) -> USART1_R

Bit 0 - USART1

impl R<u32, Reg<u32, _ITLINE28>>

pub fn usart2(&self) -> USART2_R

Bit 0 - USART2

impl R<u32, Reg<u32, _ITLINE29>>

pub fn usart5(&self) -> USART5_R

Bit 2 - USART5

impl R<u32, Reg<u32, _ITLINE31>>

pub fn rng(&self) -> RNG_R

Bit 0 - RNG

pub fn aes(&self) -> AES_R

Bit 1 - AES

impl R<u32, Reg<u32, _PR>>

pub fn pr(&self) -> PR_R

Bits 0:2 - Prescaler divider

impl R<u32, Reg<u32, _RLR>>

pub fn rl(&self) -> RL_R

Bits 0:11 - Watchdog counter reload value

impl R<u32, Reg<u32, _SR>>

pub fn wvu(&self) -> WVU_R

Bit 2 - Watchdog counter window value update

pub fn rvu(&self) -> RVU_R

Bit 1 - Watchdog counter reload value update

pub fn pvu(&self) -> PVU_R

Bit 0 - Watchdog prescaler value update

impl R<u32, Reg<u32, _WINR>>

pub fn win(&self) -> WIN_R

Bits 0:11 - Watchdog counter window value

impl R<u32, Reg<u32, _HWCFGR>>

pub fn window(&self) -> WINDOW_R

Bits 0:3 - Support of Window function

pub fn pr_default(&self) -> PR_DEFAULT_R

Bits 4:7 - Prescaler default value

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR>>

pub fn wdga(&self) -> WDGA_R

Bit 7 - Activation bit

pub fn t(&self) -> T_R

Bits 0:6 - 7-bit counter (MSB to LSB)

impl R<u32, Reg<u32, _CFR>>

pub fn wdgtb(&self) -> WDGTB_R

Bits 11:13 - Timer base

pub fn ewi(&self) -> EWI_R

Bit 9 - Early wakeup interrupt

pub fn w(&self) -> W_R

Bits 0:6 - 7-bit window value

impl R<u32, Reg<u32, _SR>>

pub fn ewif(&self) -> EWIF_R

Bit 0 - Early wakeup interrupt flag

impl R<u32, Reg<u32, _ACR>>

pub fn latency(&self) -> LATENCY_R

Bits 0:2 - Latency

pub fn prften(&self) -> PRFTEN_R

Bit 8 - Prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - Instruction cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - Instruction cache reset

pub fn empty(&self) -> EMPTY_R

Bit 16 - Flash User area empty

pub fn dbg_swen(&self) -> DBG_SWEN_R

Bit 18 - Debug access software enable

impl R<u32, Reg<u32, _SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - Write protected error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn miserr(&self) -> MISERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn optverr(&self) -> OPTVERR_R

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy.

impl R<u32, Reg<u32, _CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - Mass erase

pub fn pnb(&self) -> PNB_R

Bits 3:8 - Page number

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn optstrt(&self) -> OPTSTRT_R

Bit 17 - Options modification start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&self) -> OBL_LAUNCH_R

Bit 27 - Force the option byte loading

pub fn sec_prot(&self) -> SEC_PROT_R

Bit 28 - Securable memory area protection enable

pub fn optlock(&self) -> OPTLOCK_R

Bit 30 - Options Lock

pub fn lock(&self) -> LOCK_R

Bit 31 - FLASH_CR Lock

impl R<u32, Reg<u32, _ECCR>>

pub fn addr_ecc(&self) -> ADDR_ECC_R

Bits 0:13 - ECC fail address

pub fn sysf_ecc(&self) -> SYSF_ECC_R

Bit 20 - ECC fail for Corrected ECC Error or Double ECC Error in info block

pub fn eccie(&self) -> ECCIE_R

Bit 24 - ECC correction interrupt enable

pub fn eccc(&self) -> ECCC_R

Bit 30 - ECC correction

pub fn eccd(&self) -> ECCD_R

Bit 31 - ECC detection

impl R<u32, Reg<u32, _OPTR>>

pub fn rdp(&self) -> RDP_R

Bits 0:7 - Read protection level

pub fn boren(&self) -> BOREN_R

Bit 8 - BOR reset Level

pub fn borf_lev(&self) -> BORF_LEV_R

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&self) -> BORR_LEV_R

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&self) -> NRST_STOP_R

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&self) -> NRST_STDBY_R

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&self) -> NRSTS_HDW_R

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&self) -> IDWG_SW_R

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&self) -> IWDG_STOP_R

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&self) -> IWDG_STDBY_R

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&self) -> WWDG_SW_R

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&self) -> RAM_PARITY_CHECK_R

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&self) -> NBOOT_SEL_R

Bit 24 - nBOOT_SEL

pub fn n_boot1(&self) -> NBOOT1_R

Bit 25 - Boot configuration

pub fn n_boot0(&self) -> NBOOT0_R

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&self) -> NRST_MODE_R

Bits 27:28 - NRST_MODE

pub fn irhen(&self) -> IRHEN_R

Bit 29 - Internal reset holder enable bit

impl R<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R

Bits 0:7 - PCROP1A area start offset

impl R<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&self) -> PCROP1A_END_R

Bits 0:7 - PCROP1A area end offset

pub fn pcrop_rdp(&self) -> PCROP_RDP_R

Bit 31 - PCROP area preserved when RDP level decreased

impl R<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&self) -> WRP1A_STRT_R

Bits 0:5 - WRP area A start offset

pub fn wrp1a_end(&self) -> WRP1A_END_R

Bits 16:21 - WRP area A end offset

impl R<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&self) -> WRP1B_STRT_R

Bits 0:5 - WRP area B start offset

pub fn wrp1b_end(&self) -> WRP1B_END_R

Bits 16:21 - WRP area B end offset

impl R<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R

Bits 0:7 - PCROP1B area start offset

impl R<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&self) -> PCROP1B_END_R

Bits 0:7 - PCROP1B area end offset

impl R<u32, Reg<u32, _SECR>>

pub fn sec_size(&self) -> SEC_SIZE_R

Bits 0:6 - Securable memory area size

pub fn boot_lock(&self) -> BOOT_LOCK_R

Bit 16 - used to force boot from user area

impl R<u32, Reg<u32, _IDCODE>>

pub fn dev_id(&self) -> DEV_ID_R

Bits 0:15 - Device Identifier

pub fn rev_id(&self) -> REV_ID_R

Bits 16:31 - Revision Identifier

impl R<u32, Reg<u32, _CR>>

pub fn dbg_stop(&self) -> DBG_STOP_R

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&self) -> DBG_STANDBY_R

Bit 2 - Debug Standby Mode

impl R<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_timer2_stop(&self) -> DBG_TIMER2_STOP_R

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_timer6_stop(&self) -> DBG_TIMER6_STOP_R

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 30 - Clocking of LPTIMER2 counter when the core is halted

pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R

Bit 31 - Clocking of LPTIMER1 counter when the core is halted

impl R<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - DBG_TIM1_STOP

pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim15_stop(&self) -> DBG_TIM15_STOP_R

Bit 16 - DBG_TIM15_STOP

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - DBG_TIM17_STOP

impl R<u32, Reg<u32, _CR>>

pub fn hsion(&self) -> HSION_R

Bit 8 - HSI16 clock enable

pub fn hsikeron(&self) -> HSIKERON_R

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&self) -> HSIRDY_R

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&self) -> HSIDIV_R

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&self) -> HSEON_R

Bit 16 - HSE clock enable

pub fn hserdy(&self) -> HSERDY_R

Bit 17 - HSE clock ready flag

pub fn hsebyp(&self) -> HSEBYP_R

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&self) -> CSSON_R

Bit 19 - Clock security system enable

pub fn pllon(&self) -> PLLON_R

Bit 24 - PLL enable

pub fn pllrdy(&self) -> PLLRDY_R

Bit 25 - PLL clock ready flag

impl R<u32, Reg<u32, _ICSCR>>

pub fn hsical(&self) -> HSICAL_R

Bits 0:7 - HSI16 clock calibration

pub fn hsitrim(&self) -> HSITRIM_R

Bits 8:14 - HSI16 clock trimming

impl R<u32, Reg<u32, _CFGR>>

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&self) -> MCOSEL_R

Bits 24:26 - Microcontroller clock output

pub fn ppre(&self) -> PPRE_R

Bits 12:14 - APB prescaler

pub fn hpre(&self) -> HPRE_R

Bits 8:11 - AHB prescaler

pub fn sws(&self) -> SWS_R

Bits 3:5 - System clock switch status

pub fn sw(&self) -> SW_R

Bits 0:2 - System clock switch

impl R<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - PLL input clock source

pub fn pllm(&self) -> PLLM_R

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&self) -> PLLN_R

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&self) -> PLLREN_R

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl R<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&self) -> LSIRDYIE_R

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&self) -> LSERDYIE_R

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&self) -> HSIRDYIE_R

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&self) -> HSERDYIE_R

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&self) -> PLLSYSRDYIE_R

Bit 5 - PLL ready interrupt enable

impl R<u32, Reg<u32, _CIFR>>

pub fn lsirdyf(&self) -> LSIRDYF_R

Bit 0 - LSI ready interrupt flag

pub fn lserdyf(&self) -> LSERDYF_R

Bit 1 - LSE ready interrupt flag

pub fn hsirdyf(&self) -> HSIRDYF_R

Bit 3 - HSI ready interrupt flag

pub fn hserdyf(&self) -> HSERDYF_R

Bit 4 - HSE ready interrupt flag

pub fn pllsysrdyf(&self) -> PLLSYSRDYF_R

Bit 5 - PLL ready interrupt flag

pub fn cssf(&self) -> CSSF_R

Bit 8 - Clock security system interrupt flag

pub fn lsecssf(&self) -> LSECSSF_R

Bit 9 - LSE Clock security system interrupt flag

impl R<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&self) -> DMARST_R

Bit 0 - DMA1 reset

pub fn flashrst(&self) -> FLASHRST_R

Bit 8 - FLITF reset

pub fn crcrst(&self) -> CRCRST_R

Bit 12 - CRC reset

impl R<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&self) -> IOPARST_R

Bit 0 - I/O port A reset

pub fn iopbrst(&self) -> IOPBRST_R

Bit 1 - I/O port B reset

pub fn iopcrst(&self) -> IOPCRST_R

Bit 2 - I/O port C reset

pub fn iopdrst(&self) -> IOPDRST_R

Bit 3 - I/O port D reset

pub fn iopfrst(&self) -> IOPFRST_R

Bit 5 - I/O port F reset

impl R<u32, Reg<u32, _APBRSTR1>>

pub fn tim3rst(&self) -> TIM3RST_R

Bit 1 - TIM3 timer reset

pub fn tim6rst(&self) -> TIM6RST_R

Bit 4 - TIM6 timer reset

pub fn tim7rst(&self) -> TIM7RST_R

Bit 5 - TIM7 timer reset

pub fn spi2rst(&self) -> SPI2RST_R

Bit 14 - SPI2 reset

pub fn usart2rst(&self) -> USART2RST_R

Bit 17 - USART2 reset

pub fn usart3rst(&self) -> USART3RST_R

Bit 18 - USART3 reset

pub fn usart4rst(&self) -> USART4RST_R

Bit 19 - USART4 reset

pub fn i2c1rst(&self) -> I2C1RST_R

Bit 21 - I2C1 reset

pub fn i2c2rst(&self) -> I2C2RST_R

Bit 22 - I2C2 reset

pub fn dbgrst(&self) -> DBGRST_R

Bit 27 - Debug support reset

pub fn pwrrst(&self) -> PWRRST_R

Bit 28 - Power interface reset

impl R<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&self) -> SYSCFGRST_R

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&self) -> TIM1RST_R

Bit 11 - TIM1 timer reset

pub fn spi1rst(&self) -> SPI1RST_R

Bit 12 - SPI1 reset

pub fn usart1rst(&self) -> USART1RST_R

Bit 14 - USART1 reset

pub fn tim14rst(&self) -> TIM14RST_R

Bit 15 - TIM14 timer reset

pub fn tim15rst(&self) -> TIM15RST_R

Bit 16 - TIM15 timer reset

pub fn tim16rst(&self) -> TIM16RST_R

Bit 17 - TIM16 timer reset

pub fn tim17rst(&self) -> TIM17RST_R

Bit 18 - TIM17 timer reset

pub fn adcrst(&self) -> ADCRST_R

Bit 20 - ADC reset

impl R<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&self) -> IOPAEN_R

Bit 0 - I/O port A clock enable

pub fn iopben(&self) -> IOPBEN_R

Bit 1 - I/O port B clock enable

pub fn iopcen(&self) -> IOPCEN_R

Bit 2 - I/O port C clock enable

pub fn iopden(&self) -> IOPDEN_R

Bit 3 - I/O port D clock enable

pub fn iopfen(&self) -> IOPFEN_R

Bit 5 - I/O port F clock enable

impl R<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - DMA clock enable

pub fn flashen(&self) -> FLASHEN_R

Bit 8 - Flash memory interface clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CRC clock enable

impl R<u32, Reg<u32, _APBENR1>>

pub fn tim3en(&self) -> TIM3EN_R

Bit 1 - TIM3 timer clock enable

pub fn tim6en(&self) -> TIM6EN_R

Bit 4 - TIM6 timer clock enable

pub fn tim7en(&self) -> TIM7EN_R

Bit 5 - TIM7 timer clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - RTC APB clock enable

pub fn wwdgen(&self) -> WWDGEN_R

Bit 11 - WWDG clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - SPI2 clock enable

pub fn usart2en(&self) -> USART2EN_R

Bit 17 - USART2 clock enable

pub fn usart3en(&self) -> USART3EN_R

Bit 18 - USART3 clock enable

pub fn usart4en(&self) -> USART4EN_R

Bit 19 - USART4 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - I2C1 clock enable

pub fn i2c2en(&self) -> I2C2EN_R

Bit 22 - I2C2 clock enable

pub fn dbgen(&self) -> DBGEN_R

Bit 27 - Debug support clock enable

pub fn pwren(&self) -> PWREN_R

Bit 28 - Power interface clock enable

impl R<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&self) -> SYSCFGEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - SPI1 clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - USART1 clock enable

pub fn tim14en(&self) -> TIM14EN_R

Bit 15 - TIM14 timer clock enable

pub fn tim15en(&self) -> TIM15EN_R

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - TIM16 timer clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 20 - ADC clock enable

impl R<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&self) -> IOPASMEN_R

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&self) -> IOPBSMEN_R

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&self) -> IOPCSMEN_R

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&self) -> IOPDSMEN_R

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&self) -> IOPFSMEN_R

Bit 5 - I/O port F clock enable during Sleep mode

impl R<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&self) -> DMASMEN_R

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&self) -> SRAMSMEN_R

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CRC clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR1>>

pub fn tim3smen(&self) -> TIM3SMEN_R

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn tim6smen(&self) -> TIM6SMEN_R

Bit 4 - TIM6 timer clock enable during Sleep mode

pub fn tim7smen(&self) -> TIM7SMEN_R

Bit 5 - TIM7 timer clock enable during Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&self) -> WWDGSMEN_R

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&self) -> USART2SMEN_R

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3smen(&self) -> USART3SMEN_R

Bit 18 - USART3 clock enable during Sleep mode

pub fn usart4smen(&self) -> USART4SMEN_R

Bit 19 - USART4 clock enable during Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&self) -> I2C2SMEN_R

Bit 22 - I2C2 clock enable during Sleep mode

pub fn dbgsmen(&self) -> DBGSMEN_R

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&self) -> PWRSMEN_R

Bit 28 - Power interface clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&self) -> SYSCFGSMEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&self) -> TIM14SMEN_R

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim15smen(&self) -> TIM15SMEN_R

Bit 16 - TIM15 timer clock enable during Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&self) -> ADCSMEN_R

Bit 20 - ADC clock enable during Sleep mode

impl R<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&self) -> USART1SEL_R

Bits 0:1 - USART1 clock source selection

pub fn usart2sel(&self) -> USART2SEL_R

Bits 2:3 - USART2 clock source selection

pub fn i2c1sel(&self) -> I2C1SEL_R

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&self) -> I2S2SEL_R

Bits 14:15 - I2S1 clock source selection

pub fn tim1sel(&self) -> TIM1SEL_R

Bit 22 - TIM1 clock source selection

pub fn tim15sel(&self) -> TIM15SEL_R

Bit 24 - TIM15 clock source selection

pub fn adcsel(&self) -> ADCSEL_R

Bits 30:31 - ADCs clock source selection

impl R<u32, Reg<u32, _BDCR>>

pub fn lseon(&self) -> LSEON_R

Bit 0 - LSE oscillator enable

pub fn lserdy(&self) -> LSERDY_R

Bit 1 - LSE oscillator ready

pub fn lsebyp(&self) -> LSEBYP_R

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&self) -> LSEDRV_R

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&self) -> LSECSSON_R

Bit 5 - CSS on LSE enable

pub fn lsecssd(&self) -> LSECSSD_R

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&self) -> RTCSEL_R

Bits 8:9 - RTC clock source selection

pub fn rtcen(&self) -> RTCEN_R

Bit 15 - RTC clock enable

pub fn bdrst(&self) -> BDRST_R

Bit 16 - RTC domain software reset

pub fn lscoen(&self) -> LSCOEN_R

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&self) -> LSCOSEL_R

Bit 25 - Low-speed clock output selection

impl R<u32, Reg<u32, _CSR>>

pub fn lsion(&self) -> LSION_R

Bit 0 - LSI oscillator enable

pub fn lsirdy(&self) -> LSIRDY_R

Bit 1 - LSI oscillator ready

pub fn rmvf(&self) -> RMVF_R

Bit 23 - Remove reset flags

pub fn oblrstf(&self) -> OBLRSTF_R

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&self) -> PINRSTF_R

Bit 26 - Pin reset flag

pub fn pwrrstf(&self) -> PWRRSTF_R

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&self) -> SFTRSTF_R

Bit 28 - Software reset flag

pub fn iwdgrstf(&self) -> IWDGRSTF_R

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&self) -> WWDGRSTF_R

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&self) -> LPWRRSTF_R

Bit 31 - Low-power reset flag

impl R<u32, Reg<u32, _CR1>>

pub fn lpr(&self) -> LPR_R

Bit 14 - Low-power run

pub fn vos(&self) -> VOS_R

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&self) -> DBP_R

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&self) -> FPD_LPSLP_R

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&self) -> FPD_LPRUN_R

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&self) -> FPD_STOP_R

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection

impl R<u32, Reg<u32, _CR2>>

pub fn pvde(&self) -> PVDE_R

Bit 0 - Power voltage detector enable

pub fn pvdft(&self) -> PVDFT_R

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&self) -> PVDRT_R

Bits 4:6 - Power voltage detector rising threshold selection

impl R<u32, Reg<u32, _CR3>>

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&self) -> EWUP6_R

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&self) -> RRS_R

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&self) -> ULPEN_R

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&self) -> APC_R

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line

impl R<u32, Reg<u32, _CR4>>

pub fn wp1(&self) -> WP1_R

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&self) -> WP2_R

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&self) -> WP4_R

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&self) -> WP5_R

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&self) -> WP6_R

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&self) -> VBE_R

Bit 8 - VBAT battery charging enable

pub fn vbrs(&self) -> VBRS_R

Bit 9 - VBAT battery charging resistor selection

impl R<u32, Reg<u32, _SR1>>

pub fn wuf1(&self) -> WUF1_R

Bit 0 - Wakeup flag 1

pub fn wuf2(&self) -> WUF2_R

Bit 1 - Wakeup flag 2

pub fn wuf4(&self) -> WUF4_R

Bit 3 - Wakeup flag 4

pub fn wuf5(&self) -> WUF5_R

Bit 4 - Wakeup flag 5

pub fn wuf6(&self) -> WUF6_R

Bit 5 - Wakeup flag 6

pub fn sbf(&self) -> SBF_R

Bit 8 - Standby flag

pub fn wufi(&self) -> WUFI_R

Bit 15 - Wakeup flag internal

impl R<u32, Reg<u32, _SR2>>

pub fn pvdo(&self) -> PVDO_R

Bit 11 - Power voltage detector output

pub fn vosf(&self) -> VOSF_R

Bit 10 - Voltage scaling flag

pub fn reglpf(&self) -> REGLPF_R

Bit 9 - Low-power regulator flag

pub fn reglps(&self) -> REGLPS_R

Bit 8 - Low-power regulator started

pub fn flash_rdy(&self) -> FLASH_RDY_R

Bit 7 - Flash ready flag

impl R<u32, Reg<u32, _PUCRA>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port A pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRA>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port A pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRB>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port B pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRB>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port B pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRC>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port C pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRC>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port C pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRD>>

pub fn pu9(&self) -> PU9_R

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port D pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRD>>

pub fn pd9(&self) -> PD9_R

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port D pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRF>>

pub fn pu2(&self) -> PU2_R

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port F pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRF>>

pub fn pd2(&self) -> PD2_R

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port F pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _CR>>

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

impl R<u32, Reg<u32, _NDTR>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _PAR>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _MAR>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _ISR>>

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel 1 global interrupt flag

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel 1 transfer complete flag

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel 1 half transfer flag

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel 1 transfer error flag

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel 2 global interrupt flag

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel 2 transfer complete flag

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel 2 half transfer flag

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel 2 transfer error flag

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel 3 global interrupt flag

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel 3 transfer complete flag

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel 3 half transfer flag

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel 3 transfer error flag

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel 4 global interrupt flag

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel 4 transfer complete flag

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel 4 half transfer flag

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel 4 transfer error flag

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel 5 global interrupt flag

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel 5 transfer complete flag

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel 5 half transfer flag

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel 5 transfer error flag

pub fn gif6(&self) -> GIF6_R

Bit 20 - Channel 6 global interrupt flag

pub fn tcif6(&self) -> TCIF6_R

Bit 21 - Channel 6 transfer complete flag

pub fn htif6(&self) -> HTIF6_R

Bit 22 - Channel 6 half transfer flag

pub fn teif6(&self) -> TEIF6_R

Bit 23 - Channel 6 transfer error flag

pub fn gif7(&self) -> GIF7_R

Bit 24 - Channel 7 global interrupt flag

pub fn tcif7(&self) -> TCIF7_R

Bit 25 - Channel 7 transfer complete flag

pub fn htif7(&self) -> HTIF7_R

Bit 26 - Channel 7 half transfer flag

pub fn teif7(&self) -> TEIF7_R

Bit 27 - Channel 7 transfer error flag

impl R<u32, Reg<u32, _DMAMUX_C0CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C1CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C2CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C3CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C4CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C5CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C6CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_RG0CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG1CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG2CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG3CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RGSR>>

pub fn of(&self) -> OF_R

Bits 0:3 - Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.

impl R<u32, Reg<u32, _DMAMUX_CSR>>

pub fn sof(&self) -> SOF_R

Bits 0:6 - Synchronization overrun event flag

impl R<u32, Reg<u32, _DMAMUX_SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size identification

impl R<u32, Reg<u32, _DMAMUX_IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - IP identification

impl R<u32, Reg<u32, _DMAMUX_VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor IP revision

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major IP revision

impl R<u32, Reg<u32, _DMAMUX_HWCFGR1>>

pub fn num_dma_streams(&self) -> NUM_DMA_STREAMS_R

Bits 0:7 - number of DMA request line multiplexer (output) channels

pub fn num_dma_periph_req(&self) -> NUM_DMA_PERIPH_REQ_R

Bits 8:15 - number of DMA request lines from peripherals

pub fn num_dma_trig(&self) -> NUM_DMA_TRIG_R

Bits 16:23 - number of synchronization inputs

pub fn num_dma_reqgen(&self) -> NUM_DMA_REQGEN_R

Bits 24:31 - number of DMA request generator channels

impl R<u32, Reg<u32, _DMAMUX_HWCFGR2>>

pub fn num_dma_ext_req(&self) -> NUM_DMA_EXT_REQ_R

Bits 0:7 - Number of DMA request trigger inputs

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:31 - Data register bits

impl R<u32, Reg<u32, _IDR>>

pub fn idr(&self) -> IDR_R

Bits 0:31 - General-purpose 32-bit data register bits

impl R<u32, Reg<u32, _CR>>

pub fn rev_out(&self) -> REV_OUT_R

Bit 7 - Reverse output data

pub fn rev_in(&self) -> REV_IN_R

Bits 5:6 - Reverse input data

pub fn polysize(&self) -> POLYSIZE_R

Bits 3:4 - Polynomial size

impl R<u32, Reg<u32, _INIT>>

pub fn crc_init(&self) -> CRC_INIT_R

Bits 0:31 - Programmable initial CRC value

impl R<u32, Reg<u32, _POL>>

pub fn pol(&self) -> POL_R

Bits 0:31 - Programmable polynomial

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _RTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&self) -> TR17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&self) -> TR18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _FTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&self) -> TR17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&self) -> TR18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, SWIER0_A>

pub fn variant(&self) -> Variant<bool, SWIER0_A>

Get enumerated values variant

pub fn is_pend(&self) -> bool

Checks if the value of the field is PEND

impl R<u32, Reg<u32, _SWIER1>>

pub fn swier0(&self) -> SWIER0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&self) -> SWIER1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&self) -> SWIER2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&self) -> SWIER3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&self) -> SWIER4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&self) -> SWIER5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&self) -> SWIER6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&self) -> SWIER7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&self) -> SWIER8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&self) -> SWIER9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&self) -> SWIER10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&self) -> SWIER11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&self) -> SWIER12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&self) -> SWIER13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&self) -> SWIER14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&self) -> SWIER15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&self) -> SWIER16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn swier17(&self) -> SWIER17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn swier18(&self) -> SWIER18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, RPIF0_A>

pub fn variant(&self) -> RPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _RPR1>>

pub fn rpif0(&self) -> RPIF0_R

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&self) -> RPIF1_R

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&self) -> RPIF2_R

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&self) -> RPIF3_R

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&self) -> RPIF4_R

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&self) -> RPIF5_R

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&self) -> RPIF6_R

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&self) -> RPIF7_R

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&self) -> RPIF8_R

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&self) -> RPIF9_R

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&self) -> RPIF10_R

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&self) -> RPIF11_R

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&self) -> RPIF12_R

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&self) -> RPIF13_R

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&self) -> RPIF14_R

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&self) -> RPIF15_R

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&self) -> RPIF16_R

Bit 16 - configurable event inputs x rising edge Pending bit.

pub fn rpif17(&self) -> RPIF17_R

Bit 17 - configurable event inputs x rising edge Pending bit.

pub fn rpif18(&self) -> RPIF18_R

Bit 18 - configurable event inputs x rising edge Pending bit.

impl R<bool, FPIF0_A>

pub fn variant(&self) -> FPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _FPR1>>

pub fn fpif0(&self) -> FPIF0_R

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&self) -> FPIF1_R

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&self) -> FPIF2_R

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&self) -> FPIF3_R

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&self) -> FPIF4_R

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&self) -> FPIF5_R

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&self) -> FPIF6_R

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&self) -> FPIF7_R

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&self) -> FPIF8_R

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&self) -> FPIF9_R

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&self) -> FPIF10_R

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&self) -> FPIF11_R

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&self) -> FPIF12_R

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&self) -> FPIF13_R

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&self) -> FPIF14_R

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&self) -> FPIF15_R

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&self) -> FPIF16_R

Bit 16 - configurable event inputs x falling edge pending bit.

pub fn fpif17(&self) -> FPIF17_R

Bit 17 - configurable event inputs x falling edge pending bit.

pub fn fpif18(&self) -> FPIF18_R

Bit 18 - configurable event inputs x falling edge pending bit.

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<bool, IM0_A>

pub fn variant(&self) -> IM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR1>>

pub fn im0(&self) -> IM0_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&self) -> IM1_R

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&self) -> IM2_R

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&self) -> IM3_R

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&self) -> IM4_R

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&self) -> IM5_R

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&self) -> IM6_R

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&self) -> IM7_R

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&self) -> IM8_R

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&self) -> IM9_R

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&self) -> IM10_R

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&self) -> IM11_R

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&self) -> IM12_R

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&self) -> IM13_R

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&self) -> IM14_R

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&self) -> IM15_R

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&self) -> IM16_R

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im17(&self) -> IM17_R

Bit 17 - CPU wakeup with interrupt mask on event input

pub fn im18(&self) -> IM18_R

Bit 18 - CPU wakeup with interrupt mask on event input

pub fn im19(&self) -> IM19_R

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&self) -> IM20_R

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&self) -> IM21_R

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&self) -> IM22_R

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&self) -> IM23_R

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&self) -> IM24_R

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&self) -> IM25_R

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&self) -> IM26_R

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im27(&self) -> IM27_R

Bit 27 - CPU wakeup with interrupt mask on event input

pub fn im28(&self) -> IM28_R

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&self) -> IM29_R

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&self) -> IM30_R

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&self) -> IM31_R

Bit 31 - CPU wakeup with interrupt mask on event input

impl R<bool, EM0_A>

pub fn variant(&self) -> EM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR1>>

pub fn em0(&self) -> EM0_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&self) -> EM1_R

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&self) -> EM2_R

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&self) -> EM3_R

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&self) -> EM4_R

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&self) -> EM5_R

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&self) -> EM6_R

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&self) -> EM7_R

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&self) -> EM8_R

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&self) -> EM9_R

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&self) -> EM10_R

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&self) -> EM11_R

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&self) -> EM12_R

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&self) -> EM13_R

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&self) -> EM14_R

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&self) -> EM15_R

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&self) -> EM16_R

Bit 16 - CPU wakeup with event mask on event input

pub fn em17(&self) -> EM17_R

Bit 17 - CPU wakeup with event mask on event input

pub fn em18(&self) -> EM18_R

Bit 18 - CPU wakeup with event mask on event input

pub fn em19(&self) -> EM19_R

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&self) -> EM21_R

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&self) -> EM23_R

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&self) -> EM25_R

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&self) -> EM26_R

Bit 26 - CPU wakeup with event mask on event input

pub fn em27(&self) -> EM27_R

Bit 27 - CPU wakeup with event mask on event input

pub fn em28(&self) -> EM28_R

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&self) -> EM29_R

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&self) -> EM30_R

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&self) -> EM31_R

Bit 31 - CPU wakeup with event mask on event input

impl R<bool, IM32_A>

pub fn variant(&self) -> IM32_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR2>>

pub fn im32(&self) -> IM32_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im33(&self) -> IM33_R

Bit 1 - CPU wakeup with interrupt mask on event input

impl R<bool, EM32_A>

pub fn variant(&self) -> EM32_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR2>>

pub fn em32(&self) -> EM32_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em33(&self) -> EM33_R

Bit 1 - CPU wakeup with event mask on event input

impl R<u32, Reg<u32, _HWCFGR7>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR6>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR5>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR4>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR3>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn nbioport(&self) -> NBIOPORT_R

Bits 16:23 - HW configuration of number of IO ports

pub fn cpuevten(&self) -> CPUEVTEN_R

Bits 12:15 - HW configuration of CPU event output enable

pub fn nbcpus(&self) -> NBCPUS_R

Bits 8:11 - configuration number of CPUs

pub fn nbevents(&self) -> NBEVENTS_R

Bits 0:7 - configuration number of event

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&self) -> BKDFBK1E_R

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - selects input

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT

pub fn dedt(&self) -> DEDT_R

Bits 16:20 - DEDT

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn rtoen(&self) -> RTOEN_R

Bit 23 - Receiver timeout enable

pub fn abrmod(&self) -> ABRMOD_R

Bits 21:22 - Auto baud rate mode

pub fn abren(&self) -> ABREN_R

Bit 20 - Auto baud rate enable

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn linen(&self) -> LINEN_R

Bit 14 - LIN mode enable

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn clken(&self) -> CLKEN_R

Bit 11 - Clock enable

pub fn cpol(&self) -> CPOL_R

Bit 10 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 9 - Clock phase

pub fn lbcl(&self) -> LBCL_R

Bit 8 - Last bit clock pulse

pub fn lbdie(&self) -> LBDIE_R

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&self) -> LBDL_R

Bit 5 - LIN break detection length

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&self) -> DIS_NSS_R

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&self) -> SLVEN_R

Bit 0 - Synchronous Slave mode enable

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&self) -> TCBGTIE_R

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&self) -> SCARCNT_R

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn onebit(&self) -> ONEBIT_R

Bit 11 - One sample bit method enable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn scen(&self) -> SCEN_R

Bit 5 - Smartcard mode enable

pub fn nack(&self) -> NACK_R

Bit 4 - Smartcard NACK enable

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn irlp(&self) -> IRLP_R

Bit 2 - Ir low-power

pub fn iren(&self) -> IREN_R

Bit 1 - Ir mode enable

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&self) -> BRR_4_15_R

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&self) -> BRR_0_3_R

Bits 0:3 - BRR_0_3

impl R<u32, Reg<u32, _GTPR>>

pub fn gt(&self) -> GT_R

Bits 8:15 - Guard time value

pub fn psc(&self) -> PSC_R

Bits 0:7 - Prescaler value

impl R<u32, Reg<u32, _RTOR>>

pub fn blen(&self) -> BLEN_R

Bits 24:31 - Block Length

pub fn rto(&self) -> RTO_R

Bits 0:23 - Receiver timeout value

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn tcbgt(&self) -> TCBGT_R

Bit 25 - Transmission complete before guard time flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn abrf(&self) -> ABRF_R

Bit 15 - ABRF

pub fn abre(&self) -> ABRE_R

Bit 14 - ABRE

pub fn udr(&self) -> UDR_R

Bit 13 - SPI slave underrun error flag

pub fn eobf(&self) -> EOBF_R

Bit 12 - EOBF

pub fn rtof(&self) -> RTOF_R

Bit 11 - RTOF

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn lbdf(&self) -> LBDF_R

Bit 8 - LBDF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn bidimode(&self) -> BIDIMODE_R

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&self) -> BIDIOE_R

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&self) -> CRCEN_R

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&self) -> CRCNEXT_R

Bit 12 - CRC transfer next

pub fn dff(&self) -> DFF_R

Bit 11 - Data frame format

pub fn rxonly(&self) -> RXONLY_R

Bit 10 - Receive only

pub fn ssm(&self) -> SSM_R

Bit 9 - Software slave management

pub fn ssi(&self) -> SSI_R

Bit 8 - Internal slave select

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 7 - Frame format

pub fn spe(&self) -> SPE_R

Bit 6 - SPI enable

pub fn br(&self) -> BR_R

Bits 3:5 - Baud rate control

pub fn mstr(&self) -> MSTR_R

Bit 2 - Master selection

pub fn cpol(&self) -> CPOL_R

Bit 1 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 0 - Clock phase

impl R<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&self) -> SSOE_R

Bit 2 - SS output enable

pub fn nssp(&self) -> NSSP_R

Bit 3 - NSS pulse management

pub fn frf(&self) -> FRF_R

Bit 4 - Frame format

pub fn errie(&self) -> ERRIE_R

Bit 5 - Error interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&self) -> DS_R

Bits 8:11 - Data size

pub fn frxth(&self) -> FRXTH_R

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&self) -> LDMA_RX_R

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&self) -> LDMA_TX_R

Bit 14 - Last DMA transfer for transmission

impl R<u32, Reg<u32, _SR>>

pub fn rxne(&self) -> RXNE_R

Bit 0 - Receive buffer not empty

pub fn txe(&self) -> TXE_R

Bit 1 - Transmit buffer empty

pub fn chside(&self) -> CHSIDE_R

Bit 2 - Channel side

pub fn udr(&self) -> UDR_R

Bit 3 - Underrun flag

pub fn crcerr(&self) -> CRCERR_R

Bit 4 - CRC error flag

pub fn modf(&self) -> MODF_R

Bit 5 - Mode fault

pub fn ovr(&self) -> OVR_R

Bit 6 - Overrun flag

pub fn bsy(&self) -> BSY_R

Bit 7 - Busy flag

pub fn tifrfe(&self) -> TIFRFE_R

Bit 8 - TI frame format error

pub fn frlvl(&self) -> FRLVL_R

Bits 9:10 - FIFO reception level

pub fn ftlvl(&self) -> FTLVL_R

Bits 11:12 - FIFO transmission level

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:15 - Data register

impl R<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&self) -> CRCPOLY_R

Bits 0:15 - CRC polynomial register

impl R<u32, Reg<u32, _RXCRCR>>

pub fn rx_crc(&self) -> RXCRC_R

Bits 0:15 - Rx CRC register

impl R<u32, Reg<u32, _TXCRCR>>

pub fn tx_crc(&self) -> TXCRC_R

Bits 0:15 - Tx CRC register

impl R<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&self) -> CHLEN_R

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&self) -> DATLEN_R

Bits 1:2 - Data length to be transferred

pub fn ckpol(&self) -> CKPOL_R

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&self) -> I2SSTD_R

Bits 4:5 - standard selection

pub fn pcmsync(&self) -> PCMSYNC_R

Bit 7 - PCM frame synchronization

pub fn i2scfg(&self) -> I2SCFG_R

Bits 8:9 - I2S configuration mode

pub fn se2(&self) -> SE2_R

Bit 10 - I2S enable

pub fn i2smod(&self) -> I2SMOD_R

Bit 11 - I2S mode selection

impl R<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&self) -> I2SDIV_R

Bits 0:7 - linear prescaler

pub fn odd(&self) -> ODD_R

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&self) -> MCKOE_R

Bit 9 - Master clock output enable

impl R<u32, Reg<u32, _HWCFGR>>

pub fn crccfg(&self) -> CRCCFG_R

Bits 0:3 - CRC capable at SPI mode

pub fn i2scfg(&self) -> I2SCFG_R

Bits 4:7 - I2S mode implementation

pub fn i2sckcfg(&self) -> I2SCKCFG_R

Bits 8:11 - I2S master clock generator at I2S mode

pub fn dscfg(&self) -> DSCFG_R

Bits 12:15 - SPI data size configuration

pub fn nsscfg(&self) -> NSSCFG_R

Bits 16:19 - NSS pulse feature enhancement at SPI master

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn ts_4(&self) -> TS_4_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn ts(&self) -> TS_R

Bits 20:21 - Trigger selection

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag

pub fn cc5if(&self) -> CC5IF_R

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&self) -> CC6IF_R

Bit 17 - Compare 6 interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

impl R<u32, Reg<u32, _CCER>>

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&self) -> CC2NE_R

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&self) -> CC3NE_R

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&self) -> CC5E_R

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&self) -> CC5P_R

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&self) -> CC6E_R

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&self) -> CC6P_R

Bit 21 - Capture/Compare 6 output polarity

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:15 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3(&self) -> CCR3_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4(&self) -> CCR4_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bk2f(&self) -> BK2F_R

Bits 20:23 - Break 2 filter

pub fn bk2e(&self) -> BK2E_R

Bit 24 - Break 2 enable

pub fn bk2p(&self) -> BK2P_R

Bit 25 - Break 2 polarity

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bk2dsrm(&self) -> BK2DSRM_R

Bit 27 - Break2 Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

pub fn bk2id(&self) -> BK2ID_R

Bit 29 - Break2 bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&self) -> OCREF_CLR_R

Bit 0 - Ocref_clr source selection

impl R<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&self) -> OC6M_BIT3_R

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&self) -> OC5M_BIT3_R

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&self) -> OC6CE_R

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&self) -> OC6M_R

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&self) -> OC6PE_R

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&self) -> OC6FE_R

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&self) -> OC5CE_R

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&self) -> OC5M_R

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&self) -> OC5PE_R

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&self) -> OC5FE_R

Bit 2 - Output compare 5 fast enable

impl R<u32, Reg<u32, _CCR5>>

pub fn ccr5(&self) -> CCR5_R

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&self) -> GC5C1_R

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&self) -> GC5C2_R

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&self) -> GC5C3_R

Bit 31 - Group Channel 5 and Channel 3

impl R<u32, Reg<u32, _CCR6>>

pub fn ccr6(&self) -> CCR6_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - ETR source selection

impl R<u32, Reg<u32, _AF2>>

pub fn bk2ine(&self) -> BK2INE_R

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&self) -> BK2CMP1E_R

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&self) -> BK2CMP2E_R

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&self) -> BK2INP_R

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&self) -> BK2CMP1P_R

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&self) -> BK2CMP2P_R

Bit 11 - BRK2 COMP2 input polarity

impl R<u32, Reg<u32, _ISR>>

pub fn ccrdy(&self) -> CCRDY_R

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&self) -> EOCAL_R

Bit 11 - End Of Calibration flag

pub fn awd3(&self) -> AWD3_R

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&self) -> AWD2_R

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&self) -> AWD1_R

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&self) -> OVR_R

Bit 4 - ADC group regular overrun flag

pub fn eos(&self) -> EOS_R

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&self) -> EOC_R

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&self) -> EOSMP_R

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&self) -> ADRDY_R

Bit 0 - ADC ready flag

impl R<u32, Reg<u32, _IER>>

pub fn ccrdyie(&self) -> CCRDYIE_R

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&self) -> EOCALIE_R

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&self) -> AWD3IE_R

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&self) -> AWD2IE_R

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&self) -> AWD1IE_R

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&self) -> OVRIE_R

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&self) -> EOSIE_R

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&self) -> EOCIE_R

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&self) -> EOSMPIE_R

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&self) -> ADRDYIE_R

Bit 0 - ADC ready interrupt

impl R<u32, Reg<u32, _CR>>

pub fn adcal(&self) -> ADCAL_R

Bit 31 - ADC calibration

pub fn advregen(&self) -> ADVREGEN_R

Bit 28 - ADC voltage regulator enable

pub fn adstp(&self) -> ADSTP_R

Bit 4 - ADC group regular conversion stop

pub fn adstart(&self) -> ADSTART_R

Bit 2 - ADC group regular conversion start

pub fn addis(&self) -> ADDIS_R

Bit 1 - ADC disable

pub fn aden(&self) -> ADEN_R

Bit 0 - ADC enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&self) -> AWDCH1CH_R

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&self) -> AWD1EN_R

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGL_R

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&self) -> CHSELRMOD_R

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&self) -> DISCEN_R

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&self) -> AUTOFF_R

Bit 15 - Auto-off mode

pub fn wait(&self) -> WAIT_R

Bit 14 - Wait conversion mode

pub fn cont(&self) -> CONT_R

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMOD_R

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTEN_R

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSEL_R

Bits 6:8 - ADC group regular external trigger source

pub fn align(&self) -> ALIGN_R

Bit 5 - ADC data alignement

pub fn res(&self) -> RES_R

Bits 3:4 - ADC data resolution

pub fn scandir(&self) -> SCANDIR_R

Bit 2 - Scan sequence direction

pub fn dmacfg(&self) -> DMACFG_R

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - ADC DMA transfer enable

impl R<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&self) -> CKMODE_R

Bits 30:31 - ADC clock mode

pub fn lftrig(&self) -> LFTRIG_R

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&self) -> TOVS_R

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&self) -> OVSS_R

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&self) -> OVSR_R

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&self) -> OVSE_R

Bit 0 - ADC oversampler enable on scope ADC group regular

impl R<u32, Reg<u32, _SMPR>>

pub fn smp1(&self) -> SMP1_R

Bits 0:2 - Sampling time selection

pub fn smp2(&self) -> SMP2_R

Bits 4:6 - Sampling time selection

pub fn smpsel(&self) -> SMPSEL_R

Bits 8:26 - Channel sampling time selection

impl R<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&self) -> HT1_R

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&self) -> LT1_R

Bits 0:11 - ADC analog watchdog 1 threshold low

impl R<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&self) -> HT2_R

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&self) -> LT2_R

Bits 0:11 - ADC analog watchdog 2 threshold low

impl R<u32, Reg<u32, _CHSELR>>

pub fn chsel(&self) -> CHSEL_R

Bits 0:18 - Channel-x selection

impl R<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&self) -> SQ1_R

Bits 0:3 - conversion of the sequence

pub fn sq2(&self) -> SQ2_R

Bits 4:7 - conversion of the sequence

pub fn sq3(&self) -> SQ3_R

Bits 8:11 - conversion of the sequence

pub fn sq4(&self) -> SQ4_R

Bits 12:15 - conversion of the sequence

pub fn sq5(&self) -> SQ5_R

Bits 16:19 - conversion of the sequence

pub fn sq6(&self) -> SQ6_R

Bits 20:23 - conversion of the sequence

pub fn sq7(&self) -> SQ7_R

Bits 24:27 - conversion of the sequence

pub fn sq8(&self) -> SQ8_R

Bits 28:31 - conversion of the sequence

impl R<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&self) -> HT3_R

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&self) -> LT3_R

Bits 0:11 - ADC analog watchdog 3 threshold high

impl R<u32, Reg<u32, _DR>>

pub fn regular_data(&self) -> REGULARDATA_R

Bits 0:15 - ADC group regular conversion data

impl R<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&self) -> AWD2CH_R

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl R<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&self) -> AWD3CH_R

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl R<u32, Reg<u32, _CALFACT>>

pub fn calfact(&self) -> CALFACT_R

Bits 0:6 - ADC calibration factor in single-ended mode

impl R<u32, Reg<u32, _CCR>>

pub fn presc(&self) -> PRESC_R

Bits 18:21 - ADC prescaler

pub fn vrefen(&self) -> VREFEN_R

Bit 22 - VREFINT enable

pub fn tsen(&self) -> TSEN_R

Bit 23 - Temperature sensor enable

pub fn vbaten(&self) -> VBATEN_R

Bit 24 - VBAT enable

impl R<u32, Reg<u32, _HWCFGR6>>

pub fn chmap20(&self) -> CHMAP20_R

Bits 0:4 - Input channel mapping

pub fn chmap21(&self) -> CHMAP21_R

Bits 8:12 - Input channel mapping

pub fn chmap22(&self) -> CHMAP22_R

Bits 16:20 - Input channel mapping

pub fn chmap23(&self) -> CHMAP23_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR5>>

pub fn chmap19(&self) -> CHMAP19_R

Bits 0:4 - Input channel mapping

pub fn chmap18(&self) -> CHMAP18_R

Bits 8:12 - Input channel mapping

pub fn chmap17(&self) -> CHMAP17_R

Bits 16:20 - Input channel mapping

pub fn chmap16(&self) -> CHMAP16_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR4>>

pub fn chmap15(&self) -> CHMAP15_R

Bits 0:4 - Input channel mapping

pub fn chmap14(&self) -> CHMAP14_R

Bits 8:12 - Input channel mapping

pub fn chmap13(&self) -> CHMAP13_R

Bits 16:20 - Input channel mapping

pub fn chmap12(&self) -> CHMAP12_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR3>>

pub fn chmap11(&self) -> CHMAP11_R

Bits 0:4 - Input channel mapping

pub fn chmap10(&self) -> CHMAP10_R

Bits 8:12 - Input channel mapping

pub fn chmap9(&self) -> CHMAP9_R

Bits 16:20 - Input channel mapping

pub fn chmap8(&self) -> CHMAP8_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn chmap7(&self) -> CHMAP7_R

Bits 0:4 - Input channel mapping

pub fn chmap6(&self) -> CHMAP6_R

Bits 8:12 - Input channel mapping

pub fn chmap5(&self) -> CHMAP5_R

Bits 16:20 - Input channel mapping

pub fn chmap4(&self) -> CHMAP4_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn chmap3(&self) -> CHMAP3_R

Bits 0:4 - Input channel mapping

pub fn chmap2(&self) -> CHMAP2_R

Bits 8:12 - Input channel mapping

pub fn chmap1(&self) -> CHMAP1_R

Bits 16:20 - Input channel mapping

pub fn chmap0(&self) -> CHMAP0_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR0>>

pub fn num_chan_24(&self) -> NUM_CHAN_24_R

Bits 0:3 - NUM_CHAN_24

pub fn extra_awds(&self) -> EXTRA_AWDS_R

Bits 4:7 - Extra analog watchdog

pub fn ovs(&self) -> OVS_R

Bits 8:11 - Oversampling

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn tamp1e(&self) -> TAMP1E_R

Bit 0 - TAMP1E

pub fn tamp2e(&self) -> TAMP2E_R

Bit 1 - TAMP2E

pub fn itamp1e(&self) -> ITAMP1E_R

Bit 16 - ITAMP1E

pub fn itamp3e(&self) -> ITAMP3E_R

Bit 18 - ITAMP3E

pub fn itamp4e(&self) -> ITAMP4E_R

Bit 19 - ITAMP4E

pub fn itamp5e(&self) -> ITAMP5E_R

Bit 20 - ITAMP5E

pub fn itamp6e(&self) -> ITAMP6E_R

Bit 21 - ITAMP6E

impl R<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&self) -> TAMP1NOER_R

Bit 0 - TAMP1NOER

pub fn tamp2noer(&self) -> TAMP2NOER_R

Bit 1 - TAMP2NOER

pub fn tamp1msk(&self) -> TAMP1MSK_R

Bit 16 - TAMP1MSK

pub fn tamp2msk(&self) -> TAMP2MSK_R

Bit 17 - TAMP2MSK

pub fn tamp1trg(&self) -> TAMP1TRG_R

Bit 24 - TAMP1TRG

pub fn tamp2trg(&self) -> TAMP2TRG_R

Bit 25 - TAMP2TRG

impl R<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&self) -> TAMPFREQ_R

Bits 0:2 - TAMPFREQ

pub fn tampflt(&self) -> TAMPFLT_R

Bits 3:4 - TAMPFLT

pub fn tampprch(&self) -> TAMPPRCH_R

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&self) -> TAMPPUDIS_R

Bit 7 - TAMPPUDIS

impl R<u32, Reg<u32, _IER>>

pub fn tamp1ie(&self) -> TAMP1IE_R

Bit 0 - TAMP1IE

pub fn tamp2ie(&self) -> TAMP2IE_R

Bit 1 - TAMP2IE

pub fn itamp1ie(&self) -> ITAMP1IE_R

Bit 16 - ITAMP1IE

pub fn itamp3ie(&self) -> ITAMP3IE_R

Bit 18 - ITAMP3IE

pub fn itamp4ie(&self) -> ITAMP4IE_R

Bit 19 - ITAMP4IE

pub fn itamp5ie(&self) -> ITAMP5IE_R

Bit 20 - ITAMP5IE

pub fn itamp6ie(&self) -> ITAMP6IE_R

Bit 21 - ITAMP6IE

impl R<u32, Reg<u32, _SR>>

pub fn tamp1f(&self) -> TAMP1F_R

Bit 0 - TAMP1F

pub fn tamp2f(&self) -> TAMP2F_R

Bit 1 - TAMP2F

pub fn itamp1f(&self) -> ITAMP1F_R

Bit 16 - ITAMP1F

pub fn itamp3f(&self) -> ITAMP3F_R

Bit 18 - ITAMP3F

pub fn itamp4f(&self) -> ITAMP4F_R

Bit 19 - ITAMP4F

pub fn itamp5f(&self) -> ITAMP5F_R

Bit 20 - ITAMP5F

pub fn itamp6f(&self) -> ITAMP6F_R

Bit 21 - ITAMP6F

pub fn itamp7f(&self) -> ITAMP7F_R

Bit 22 - ITAMP7F

impl R<u32, Reg<u32, _MISR>>

pub fn tamp1mf(&self) -> TAMP1MF_R

Bit 0 - TAMP1MF:

pub fn tamp2mf(&self) -> TAMP2MF_R

Bit 1 - TAMP2MF

pub fn itamp1mf(&self) -> ITAMP1MF_R

Bit 16 - ITAMP1MF

pub fn itamp3mf(&self) -> ITAMP3MF_R

Bit 18 - ITAMP3MF

pub fn itamp4mf(&self) -> ITAMP4MF_R

Bit 19 - ITAMP4MF

pub fn itamp5mf(&self) -> ITAMP5MF_R

Bit 20 - ITAMP5MF

pub fn itamp6mf(&self) -> ITAMP6MF_R

Bit 21 - ITAMP6MF

impl R<u32, Reg<u32, _BKP0R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP1R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP2R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP3R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP4R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn ptionreg_out(&self) -> PTIONREG_OUT_R

Bits 0:7 - PTIONREG_OUT

pub fn trust_zone(&self) -> TRUST_ZONE_R

Bits 8:11 - TRUST_ZONE

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn backup_regs(&self) -> BACKUP_REGS_R

Bits 0:7 - BACKUP_REGS

pub fn tamper(&self) -> TAMPER_R

Bits 8:11 - TAMPER

pub fn active_tamper(&self) -> ACTIVE_TAMPER_R

Bits 12:15 - ACTIVE_TAMPER

pub fn int_tamper(&self) -> INT_TAMPER_R

Bits 16:31 - INT_TAMPER

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn pe(&self) -> PE_R

Bit 0 - Peripheral enable

pub fn txie(&self) -> TXIE_R

Bit 1 - TX Interrupt enable

pub fn rxie(&self) -> RXIE_R

Bit 2 - RX Interrupt enable

pub fn addrie(&self) -> ADDRIE_R

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&self) -> NACKIE_R

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&self) -> STOPIE_R

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 7 - Error interrupts enable

pub fn dnf(&self) -> DNF_R

Bits 8:11 - Digital noise filter

pub fn anfoff(&self) -> ANFOFF_R

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 15 - DMA reception requests enable

pub fn sbc(&self) -> SBC_R

Bit 16 - Slave byte control

pub fn nostretch(&self) -> NOSTRETCH_R

Bit 17 - Clock stretching disable

pub fn wupen(&self) -> WUPEN_R

Bit 18 - Wakeup from STOP enable

pub fn gcen(&self) -> GCEN_R

Bit 19 - General call enable

pub fn smbhen(&self) -> SMBHEN_R

Bit 20 - SMBus Host address enable

pub fn smbden(&self) -> SMBDEN_R

Bit 21 - SMBus Device Default address enable

pub fn alerten(&self) -> ALERTEN_R

Bit 22 - SMBUS alert enable

pub fn pecen(&self) -> PECEN_R

Bit 23 - PEC enable

impl R<u32, Reg<u32, _CR2>>

pub fn pecbyte(&self) -> PECBYTE_R

Bit 26 - Packet error checking byte

pub fn autoend(&self) -> AUTOEND_R

Bit 25 - Automatic end mode (master mode)

pub fn reload(&self) -> RELOAD_R

Bit 24 - NBYTES reload mode

pub fn nbytes(&self) -> NBYTES_R

Bits 16:23 - Number of bytes

pub fn nack(&self) -> NACK_R

Bit 15 - NACK generation (slave mode)

pub fn stop(&self) -> STOP_R

Bit 14 - Stop generation (master mode)

pub fn start(&self) -> START_R

Bit 13 - Start generation

pub fn head10r(&self) -> HEAD10R_R

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&self) -> ADD10_R

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&self) -> RD_WRN_R

Bit 10 - Transfer direction (master mode)

pub fn sadd(&self) -> SADD_R

Bits 0:9 - Slave address bit (master mode)

impl R<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&self) -> OA1_0_R

Bit 0 - Interface address

pub fn oa1_7_1(&self) -> OA1_7_1_R

Bits 1:7 - Interface address

pub fn oa1_8_9(&self) -> OA1_8_9_R

Bits 8:9 - Interface address

pub fn oa1mode(&self) -> OA1MODE_R

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&self) -> OA1EN_R

Bit 15 - Own Address 1 enable

impl R<u32, Reg<u32, _OAR2>>

pub fn oa2(&self) -> OA2_R

Bits 1:7 - Interface address

pub fn oa2msk(&self) -> OA2MSK_R

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&self) -> OA2EN_R

Bit 15 - Own Address 2 enable

impl R<u32, Reg<u32, _TIMINGR>>

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler

impl R<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&self) -> TIMEOUTA_R

Bits 0:11 - Bus timeout A

pub fn tidle(&self) -> TIDLE_R

Bit 12 - Idle clock timeout detection

pub fn timouten(&self) -> TIMOUTEN_R

Bit 15 - Clock timeout enable

pub fn timeoutb(&self) -> TIMEOUTB_R

Bits 16:27 - Bus timeout B

pub fn texten(&self) -> TEXTEN_R

Bit 31 - Extended clock timeout enable

impl R<u32, Reg<u32, _ISR>>

pub fn addcode(&self) -> ADDCODE_R

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R

Bit 0 - Transmit data register empty (transmitters)

impl R<u32, Reg<u32, _PECR>>

pub fn pec(&self) -> PEC_R

Bits 0:7 - Packet error checking register

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - 8-bit receive data

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - 8-bit transmit data

impl R<u32, Reg<u32, _TR>>

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _DR>>

pub fn yt(&self) -> YT_R

Bits 20:23 - Year tens in BCD format

pub fn yu(&self) -> YU_R

Bits 16:19 - Year units in BCD format

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _SSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ICSR>>

pub fn alrawf(&self) -> ALRAWF_R

Bit 0 - Alarm A write flag

pub fn alrbwf(&self) -> ALRBWF_R

Bit 1 - Alarm B write flag

pub fn wutwf(&self) -> WUTWF_R

Bit 2 - Wakeup timer write flag

pub fn shpf(&self) -> SHPF_R

Bit 3 - Shift operation pending

pub fn inits(&self) -> INITS_R

Bit 4 - Initialization status flag

pub fn rsf(&self) -> RSF_R

Bit 5 - Registers synchronization flag

pub fn initf(&self) -> INITF_R

Bit 6 - Initialization flag

pub fn init(&self) -> INIT_R

Bit 7 - Initialization mode

pub fn recalpf(&self) -> RECALPF_R

Bit 16 - Recalibration pending Flag

impl R<u32, Reg<u32, _PRER>>

pub fn prediv_a(&self) -> PREDIV_A_R

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&self) -> PREDIV_S_R

Bits 0:14 - Synchronous prescaler factor

impl R<u32, Reg<u32, _WUTR>>

pub fn wut(&self) -> WUT_R

Bits 0:15 - Wakeup auto-reload value bits

impl R<u32, Reg<u32, _CR>>

pub fn wucksel(&self) -> WUCKSEL_R

Bits 0:2 - WUCKSEL

pub fn tsedge(&self) -> TSEDGE_R

Bit 3 - TSEDGE

pub fn refckon(&self) -> REFCKON_R

Bit 4 - REFCKON

pub fn bypshad(&self) -> BYPSHAD_R

Bit 5 - BYPSHAD

pub fn fmt(&self) -> FMT_R

Bit 6 - FMT

pub fn alrae(&self) -> ALRAE_R

Bit 8 - ALRAE

pub fn alrbe(&self) -> ALRBE_R

Bit 9 - ALRBE

pub fn wute(&self) -> WUTE_R

Bit 10 - WUTE

pub fn tse(&self) -> TSE_R

Bit 11 - TSE

pub fn alraie(&self) -> ALRAIE_R

Bit 12 - ALRAIE

pub fn alrbie(&self) -> ALRBIE_R

Bit 13 - ALRBIE

pub fn wutie(&self) -> WUTIE_R

Bit 14 - WUTIE

pub fn tsie(&self) -> TSIE_R

Bit 15 - TSIE

pub fn add1h(&self) -> ADD1H_R

Bit 16 - ADD1H

pub fn sub1h(&self) -> SUB1H_R

Bit 17 - SUB1H

pub fn bkp(&self) -> BKP_R

Bit 18 - BKP

pub fn cosel(&self) -> COSEL_R

Bit 19 - COSEL

pub fn pol(&self) -> POL_R

Bit 20 - POL

pub fn osel(&self) -> OSEL_R

Bits 21:22 - OSEL

pub fn coe(&self) -> COE_R

Bit 23 - COE

pub fn itse(&self) -> ITSE_R

Bit 24 - ITSE

pub fn tampts(&self) -> TAMPTS_R

Bit 25 - TAMPTS

pub fn tampoe(&self) -> TAMPOE_R

Bit 26 - TAMPOE

pub fn tampalrm_pu(&self) -> TAMPALRM_PU_R

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&self) -> TAMPALRM_TYPE_R

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&self) -> OUT2EN_R

Bit 31 - OUT2EN

impl R<u32, Reg<u32, _CALR>>

pub fn calp(&self) -> CALP_R

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&self) -> CALW8_R

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&self) -> CALW16_R

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&self) -> CALM_R

Bits 0:8 - Calibration minus

impl R<u32, Reg<u32, _TSTR>>

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

impl R<u32, Reg<u32, _TSDR>>

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _TSSSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm A date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm A hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm A minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm A seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm B date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm B hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm B minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm B seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _SR>>

pub fn alraf(&self) -> ALRAF_R

Bit 0 - ALRAF

pub fn alrbf(&self) -> ALRBF_R

Bit 1 - ALRBF

pub fn wutf(&self) -> WUTF_R

Bit 2 - WUTF

pub fn tsf(&self) -> TSF_R

Bit 3 - TSF

pub fn tsovf(&self) -> TSOVF_R

Bit 4 - TSOVF

pub fn itsf(&self) -> ITSF_R

Bit 5 - ITSF

impl R<u32, Reg<u32, _MISR>>

pub fn alramf(&self) -> ALRAMF_R

Bit 0 - ALRAMF

pub fn alrbmf(&self) -> ALRBMF_R

Bit 1 - ALRBMF

pub fn wutmf(&self) -> WUTMF_R

Bit 2 - WUTMF

pub fn tsmf(&self) -> TSMF_R

Bit 3 - TSMF

pub fn tsovmf(&self) -> TSOVMF_R

Bit 4 - TSOVMF

pub fn itsmf(&self) -> ITSMF_R

Bit 5 - ITSMF

impl R<u32, Reg<u32, _SCR>>

pub fn calraf(&self) -> CALRAF_R

Bit 0 - CALRAF

pub fn calrbf(&self) -> CALRBF_R

Bit 1 - CALRBF

pub fn cwutf(&self) -> CWUTF_R

Bit 2 - CWUTF

pub fn ctsf(&self) -> CTSF_R

Bit 3 - CTSF

pub fn ctsovf(&self) -> CTSOVF_R

Bit 4 - CTSOVF

pub fn citsf(&self) -> CITSF_R

Bit 5 - CITSF

impl R<u32, Reg<u32, _HWCFGR>>

pub fn alarmb(&self) -> ALARMB_R

Bits 0:3 - ALARMB

pub fn wakeup(&self) -> WAKEUP_R

Bits 4:7 - WAKEUP

pub fn smooth_calib(&self) -> SMOOTH_CALIB_R

Bits 8:11 - SMOOTH_CALIB

pub fn timestamp(&self) -> TIMESTAMP_R

Bits 12:15 - TIMESTAMP

pub fn optionreg_out(&self) -> OPTIONREG_OUT_R

Bits 16:23 - OPTIONREG_OUT

pub fn trust_zone(&self) -> TRUST_ZONE_R

Bits 24:27 - TRUST_ZONE

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _DIER>>

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - CC1S

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - OC1FE

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - OC1PE

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - OC1M

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - OC1CE

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&self) -> ICPCS_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _TISEL>>

pub fn tisel(&self) -> TISEL_R

Bits 0:3 - TI1[0] to TI1[15] input selection

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

impl R<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&self) -> TS_4_3_R

Bits 20:21 - Trigger selection

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&self) -> IC3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt_h(&self) -> CNT_H_R

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&self) -> CNT_L_R

Bits 0:15 - Low counter value

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr_h(&self) -> ARR_H_R

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&self) -> ARR_L_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&self) -> CCR1_H_R

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&self) -> CCR1_L_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&self) -> CCR2_H_R

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&self) -> CCR2_L_R

Bits 0:15 - Low Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&self) -> CCR3_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&self) -> CCR3_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&self) -> CCR4_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&self) -> CCR4_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&self) -> IOCREF_CLR_R

Bit 0 - IOCREF_CLR

impl R<u32, Reg<u32, _AF1>>

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:17 - External trigger source selection

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - TI1SEL

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - TI2SEL

impl R<u32, Reg<u32, _CSR>>

pub fn enable(&self) -> ENABLE_R

Bit 0 - Counter enable

pub fn tickint(&self) -> TICKINT_R

Bit 1 - SysTick exception request enable

pub fn clksource(&self) -> CLKSOURCE_R

Bit 2 - Clock source selection

pub fn countflag(&self) -> COUNTFLAG_R

Bit 16 - COUNTFLAG

impl R<u32, Reg<u32, _RVR>>

pub fn reload(&self) -> RELOAD_R

Bits 0:23 - RELOAD value

impl R<u32, Reg<u32, _CVR>>

pub fn current(&self) -> CURRENT_R

Bits 0:23 - Current counter value

impl R<u32, Reg<u32, _CALIB>>

pub fn tenms(&self) -> TENMS_R

Bits 0:23 - Calibration value

pub fn skew(&self) -> SKEW_R

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&self) -> NOREF_R

Bit 31 - NOREF flag. Reads as zero

impl R<u32, Reg<u32, _PR>>

pub fn pr(&self) -> PR_R

Bits 0:2 - Prescaler divider

impl R<u32, Reg<u32, _RLR>>

pub fn rl(&self) -> RL_R

Bits 0:11 - Watchdog counter reload value

impl R<u32, Reg<u32, _SR>>

pub fn wvu(&self) -> WVU_R

Bit 2 - Watchdog counter window value update

pub fn rvu(&self) -> RVU_R

Bit 1 - Watchdog counter reload value update

pub fn pvu(&self) -> PVU_R

Bit 0 - Watchdog prescaler value update

impl R<u32, Reg<u32, _WINR>>

pub fn win(&self) -> WIN_R

Bits 0:11 - Watchdog counter window value

impl R<u32, Reg<u32, _HWCFGR>>

pub fn window(&self) -> WINDOW_R

Bits 0:3 - Support of Window function

pub fn pr_default(&self) -> PR_DEFAULT_R

Bits 4:7 - Prescaler default value

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR>>

pub fn wdga(&self) -> WDGA_R

Bit 7 - Activation bit

pub fn t(&self) -> T_R

Bits 0:6 - 7-bit counter (MSB to LSB)

impl R<u32, Reg<u32, _CFR>>

pub fn wdgtb(&self) -> WDGTB_R

Bits 11:13 - Timer base

pub fn ewi(&self) -> EWI_R

Bit 9 - Early wakeup interrupt

pub fn w(&self) -> W_R

Bits 0:6 - 7-bit window value

impl R<u32, Reg<u32, _SR>>

pub fn ewif(&self) -> EWIF_R

Bit 0 - Early wakeup interrupt flag

impl R<u32, Reg<u32, _ACR>>

pub fn latency(&self) -> LATENCY_R

Bits 0:2 - Latency

pub fn prften(&self) -> PRFTEN_R

Bit 8 - Prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - Instruction cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - Instruction cache reset

pub fn empty(&self) -> EMPTY_R

Bit 16 - Flash User area empty

pub fn dbg_swen(&self) -> DBG_SWEN_R

Bit 18 - Debug access software enable

impl R<u32, Reg<u32, _SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - Write protected error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn miserr(&self) -> MISERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn optverr(&self) -> OPTVERR_R

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy.

impl R<u32, Reg<u32, _CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - Mass erase

pub fn pnb(&self) -> PNB_R

Bits 3:8 - Page number

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn optstrt(&self) -> OPTSTRT_R

Bit 17 - Options modification start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&self) -> OBL_LAUNCH_R

Bit 27 - Force the option byte loading

pub fn sec_prot(&self) -> SEC_PROT_R

Bit 28 - Securable memory area protection enable

pub fn optlock(&self) -> OPTLOCK_R

Bit 30 - Options Lock

pub fn lock(&self) -> LOCK_R

Bit 31 - FLASH_CR Lock

impl R<u32, Reg<u32, _ECCR>>

pub fn addr_ecc(&self) -> ADDR_ECC_R

Bits 0:13 - ECC fail address

pub fn sysf_ecc(&self) -> SYSF_ECC_R

Bit 20 - ECC fail for Corrected ECC Error or Double ECC Error in info block

pub fn eccie(&self) -> ECCIE_R

Bit 24 - ECC correction interrupt enable

pub fn eccc(&self) -> ECCC_R

Bit 30 - ECC correction

pub fn eccd(&self) -> ECCD_R

Bit 31 - ECC detection

impl R<u32, Reg<u32, _OPTR>>

pub fn rdp(&self) -> RDP_R

Bits 0:7 - Read protection level

pub fn boren(&self) -> BOREN_R

Bit 8 - BOR reset Level

pub fn borf_lev(&self) -> BORF_LEV_R

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&self) -> BORR_LEV_R

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&self) -> NRST_STOP_R

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&self) -> NRST_STDBY_R

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&self) -> NRSTS_HDW_R

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&self) -> IDWG_SW_R

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&self) -> IWDG_STOP_R

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&self) -> IWDG_STDBY_R

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&self) -> WWDG_SW_R

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&self) -> RAM_PARITY_CHECK_R

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&self) -> NBOOT_SEL_R

Bit 24 - nBOOT_SEL

pub fn n_boot1(&self) -> NBOOT1_R

Bit 25 - Boot configuration

pub fn n_boot0(&self) -> NBOOT0_R

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&self) -> NRST_MODE_R

Bits 27:28 - NRST_MODE

pub fn irhen(&self) -> IRHEN_R

Bit 29 - Internal reset holder enable bit

impl R<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R

Bits 0:7 - PCROP1A area start offset

impl R<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&self) -> PCROP1A_END_R

Bits 0:7 - PCROP1A area end offset

pub fn pcrop_rdp(&self) -> PCROP_RDP_R

Bit 31 - PCROP area preserved when RDP level decreased

impl R<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&self) -> WRP1A_STRT_R

Bits 0:5 - WRP area A start offset

pub fn wrp1a_end(&self) -> WRP1A_END_R

Bits 16:21 - WRP area A end offset

impl R<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&self) -> WRP1B_STRT_R

Bits 0:5 - WRP area B start offset

pub fn wrp1b_end(&self) -> WRP1B_END_R

Bits 16:21 - WRP area B end offset

impl R<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R

Bits 0:7 - PCROP1B area start offset

impl R<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&self) -> PCROP1B_END_R

Bits 0:7 - PCROP1B area end offset

impl R<u32, Reg<u32, _SECR>>

pub fn sec_size(&self) -> SEC_SIZE_R

Bits 0:6 - Securable memory area size

pub fn boot_lock(&self) -> BOOT_LOCK_R

Bit 16 - used to force boot from user area

impl R<u32, Reg<u32, _IDCODE>>

pub fn dev_id(&self) -> DEV_ID_R

Bits 0:15 - Device Identifier

pub fn rev_id(&self) -> REV_ID_R

Bits 16:31 - Revision Identifier

impl R<u32, Reg<u32, _CR>>

pub fn dbg_stop(&self) -> DBG_STOP_R

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&self) -> DBG_STANDBY_R

Bit 2 - Debug Standby Mode

impl R<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_timer2_stop(&self) -> DBG_TIMER2_STOP_R

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_timer6_stop(&self) -> DBG_TIMER6_STOP_R

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 30 - Clocking of LPTIMER2 counter when the core is halted

pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R

Bit 31 - Clocking of LPTIMER1 counter when the core is halted

impl R<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - DBG_TIM1_STOP

pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim15_stop(&self) -> DBG_TIM15_STOP_R

Bit 16 - DBG_TIM15_STOP

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - DBG_TIM17_STOP

impl R<u32, Reg<u32, _CR>>

pub fn hsion(&self) -> HSION_R

Bit 8 - HSI16 clock enable

pub fn hsikeron(&self) -> HSIKERON_R

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&self) -> HSIRDY_R

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&self) -> HSIDIV_R

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&self) -> HSEON_R

Bit 16 - HSE clock enable

pub fn hserdy(&self) -> HSERDY_R

Bit 17 - HSE clock ready flag

pub fn hsebyp(&self) -> HSEBYP_R

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&self) -> CSSON_R

Bit 19 - Clock security system enable

pub fn pllon(&self) -> PLLON_R

Bit 24 - PLL enable

pub fn pllrdy(&self) -> PLLRDY_R

Bit 25 - PLL clock ready flag

impl R<u32, Reg<u32, _ICSCR>>

pub fn hsical(&self) -> HSICAL_R

Bits 0:7 - HSI16 clock calibration

pub fn hsitrim(&self) -> HSITRIM_R

Bits 8:14 - HSI16 clock trimming

impl R<u32, Reg<u32, _CFGR>>

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&self) -> MCOSEL_R

Bits 24:26 - Microcontroller clock output

pub fn ppre(&self) -> PPRE_R

Bits 12:14 - APB prescaler

pub fn hpre(&self) -> HPRE_R

Bits 8:11 - AHB prescaler

pub fn sws(&self) -> SWS_R

Bits 3:5 - System clock switch status

pub fn sw(&self) -> SW_R

Bits 0:2 - System clock switch

impl R<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - PLL input clock source

pub fn pllm(&self) -> PLLM_R

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&self) -> PLLN_R

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&self) -> PLLREN_R

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl R<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&self) -> LSIRDYIE_R

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&self) -> LSERDYIE_R

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&self) -> HSIRDYIE_R

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&self) -> HSERDYIE_R

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&self) -> PLLSYSRDYIE_R

Bit 5 - PLL ready interrupt enable

impl R<u32, Reg<u32, _CIFR>>

pub fn lsirdyf(&self) -> LSIRDYF_R

Bit 0 - LSI ready interrupt flag

pub fn lserdyf(&self) -> LSERDYF_R

Bit 1 - LSE ready interrupt flag

pub fn hsirdyf(&self) -> HSIRDYF_R

Bit 3 - HSI ready interrupt flag

pub fn hserdyf(&self) -> HSERDYF_R

Bit 4 - HSE ready interrupt flag

pub fn pllsysrdyf(&self) -> PLLSYSRDYF_R

Bit 5 - PLL ready interrupt flag

pub fn cssf(&self) -> CSSF_R

Bit 8 - Clock security system interrupt flag

pub fn lsecssf(&self) -> LSECSSF_R

Bit 9 - LSE Clock security system interrupt flag

impl R<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&self) -> DMARST_R

Bit 0 - DMA1 reset

pub fn flashrst(&self) -> FLASHRST_R

Bit 8 - FLITF reset

pub fn crcrst(&self) -> CRCRST_R

Bit 12 - CRC reset

impl R<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&self) -> IOPARST_R

Bit 0 - I/O port A reset

pub fn iopbrst(&self) -> IOPBRST_R

Bit 1 - I/O port B reset

pub fn iopcrst(&self) -> IOPCRST_R

Bit 2 - I/O port C reset

pub fn iopdrst(&self) -> IOPDRST_R

Bit 3 - I/O port D reset

pub fn iopfrst(&self) -> IOPFRST_R

Bit 5 - I/O port F reset

impl R<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&self) -> TIM2RST_R

Bit 0 - TIM2 timer reset

pub fn tim3rst(&self) -> TIM3RST_R

Bit 1 - TIM3 timer reset

pub fn tim6rst(&self) -> TIM6RST_R

Bit 4 - TIM6 timer reset

pub fn tim7rst(&self) -> TIM7RST_R

Bit 5 - TIM7 timer reset

pub fn spi2rst(&self) -> SPI2RST_R

Bit 14 - SPI2 reset

pub fn usart2rst(&self) -> USART2RST_R

Bit 17 - USART2 reset

pub fn usart3rst(&self) -> USART3RST_R

Bit 18 - USART3 reset

pub fn usart4rst(&self) -> USART4RST_R

Bit 19 - USART4 reset

pub fn lpuart1rst(&self) -> LPUART1RST_R

Bit 20 - LPUART1 reset

pub fn i2c1rst(&self) -> I2C1RST_R

Bit 21 - I2C1 reset

pub fn i2c2rst(&self) -> I2C2RST_R

Bit 22 - I2C2 reset

pub fn cecrst(&self) -> CECRST_R

Bit 24 - HDMI CEC reset

pub fn ucpd1rst(&self) -> UCPD1RST_R

Bit 25 - UCPD1 reset

pub fn ucpd2rst(&self) -> UCPD2RST_R

Bit 26 - UCPD2 reset

pub fn dbgrst(&self) -> DBGRST_R

Bit 27 - Debug support reset

pub fn pwrrst(&self) -> PWRRST_R

Bit 28 - Power interface reset

pub fn dac1rst(&self) -> DAC1RST_R

Bit 29 - DAC1 interface reset

pub fn lptim2rst(&self) -> LPTIM2RST_R

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&self) -> LPTIM1RST_R

Bit 31 - Low Power Timer 1 reset

impl R<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&self) -> SYSCFGRST_R

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&self) -> TIM1RST_R

Bit 11 - TIM1 timer reset

pub fn spi1rst(&self) -> SPI1RST_R

Bit 12 - SPI1 reset

pub fn usart1rst(&self) -> USART1RST_R

Bit 14 - USART1 reset

pub fn tim14rst(&self) -> TIM14RST_R

Bit 15 - TIM14 timer reset

pub fn tim15rst(&self) -> TIM15RST_R

Bit 16 - TIM15 timer reset

pub fn tim16rst(&self) -> TIM16RST_R

Bit 17 - TIM16 timer reset

pub fn tim17rst(&self) -> TIM17RST_R

Bit 18 - TIM17 timer reset

pub fn adcrst(&self) -> ADCRST_R

Bit 20 - ADC reset

impl R<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&self) -> IOPAEN_R

Bit 0 - I/O port A clock enable

pub fn iopben(&self) -> IOPBEN_R

Bit 1 - I/O port B clock enable

pub fn iopcen(&self) -> IOPCEN_R

Bit 2 - I/O port C clock enable

pub fn iopden(&self) -> IOPDEN_R

Bit 3 - I/O port D clock enable

pub fn iopfen(&self) -> IOPFEN_R

Bit 5 - I/O port F clock enable

impl R<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - DMA clock enable

pub fn flashen(&self) -> FLASHEN_R

Bit 8 - Flash memory interface clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CRC clock enable

impl R<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&self) -> TIM2EN_R

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&self) -> TIM3EN_R

Bit 1 - TIM3 timer clock enable

pub fn tim6en(&self) -> TIM6EN_R

Bit 4 - TIM6 timer clock enable

pub fn tim7en(&self) -> TIM7EN_R

Bit 5 - TIM7 timer clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - RTC APB clock enable

pub fn wwdgen(&self) -> WWDGEN_R

Bit 11 - WWDG clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - SPI2 clock enable

pub fn usart2en(&self) -> USART2EN_R

Bit 17 - USART2 clock enable

pub fn usart3en(&self) -> USART3EN_R

Bit 18 - USART3 clock enable

pub fn usart4en(&self) -> USART4EN_R

Bit 19 - USART4 clock enable

pub fn lpuart1en(&self) -> LPUART1EN_R

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - I2C1 clock enable

pub fn i2c2en(&self) -> I2C2EN_R

Bit 22 - I2C2 clock enable

pub fn cecen(&self) -> CECEN_R

Bit 24 - HDMI CEC clock enable

pub fn ucpd1en(&self) -> UCPD1EN_R

Bit 25 - UCPD1 clock enable

pub fn ucpd2en(&self) -> UCPD2EN_R

Bit 26 - UCPD2 clock enable

pub fn dbgen(&self) -> DBGEN_R

Bit 27 - Debug support clock enable

pub fn pwren(&self) -> PWREN_R

Bit 28 - Power interface clock enable

pub fn dac1en(&self) -> DAC1EN_R

Bit 29 - DAC1 interface clock enable

pub fn lptim2en(&self) -> LPTIM2EN_R

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&self) -> LPTIM1EN_R

Bit 31 - LPTIM1 clock enable

impl R<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&self) -> SYSCFGEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - SPI1 clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - USART1 clock enable

pub fn tim14en(&self) -> TIM14EN_R

Bit 15 - TIM14 timer clock enable

pub fn tim15en(&self) -> TIM15EN_R

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - TIM16 timer clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 20 - ADC clock enable

impl R<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&self) -> IOPASMEN_R

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&self) -> IOPBSMEN_R

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&self) -> IOPCSMEN_R

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&self) -> IOPDSMEN_R

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&self) -> IOPFSMEN_R

Bit 5 - I/O port F clock enable during Sleep mode

impl R<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&self) -> DMASMEN_R

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&self) -> SRAMSMEN_R

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CRC clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&self) -> TIM2SMEN_R

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&self) -> TIM3SMEN_R

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn tim6smen(&self) -> TIM6SMEN_R

Bit 4 - TIM6 timer clock enable during Sleep mode

pub fn tim7smen(&self) -> TIM7SMEN_R

Bit 5 - TIM7 timer clock enable during Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&self) -> WWDGSMEN_R

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&self) -> USART2SMEN_R

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3smen(&self) -> USART3SMEN_R

Bit 18 - USART3 clock enable during Sleep mode

pub fn usart4smen(&self) -> USART4SMEN_R

Bit 19 - USART4 clock enable during Sleep mode

pub fn lpuart1smen(&self) -> LPUART1SMEN_R

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&self) -> I2C2SMEN_R

Bit 22 - I2C2 clock enable during Sleep mode

pub fn cecsmen(&self) -> CECSMEN_R

Bit 24 - HDMI CEC clock enable during Sleep mode

pub fn ucpd1smen(&self) -> UCPD1SMEN_R

Bit 25 - UCPD1 clock enable during Sleep mode

pub fn ucpd2smen(&self) -> UCPD2SMEN_R

Bit 26 - UCPD2 clock enable during Sleep mode

pub fn dbgsmen(&self) -> DBGSMEN_R

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&self) -> PWRSMEN_R

Bit 28 - Power interface clock enable during Sleep mode

pub fn dac1smen(&self) -> DAC1SMEN_R

Bit 29 - DAC1 interface clock enable during Sleep mode

pub fn lptim2smen(&self) -> LPTIM2SMEN_R

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&self) -> LPTIM1SMEN_R

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&self) -> SYSCFGSMEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&self) -> TIM14SMEN_R

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim15smen(&self) -> TIM15SMEN_R

Bit 16 - TIM15 timer clock enable during Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&self) -> ADCSMEN_R

Bit 20 - ADC clock enable during Sleep mode

impl R<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&self) -> USART1SEL_R

Bits 0:1 - USART1 clock source selection

pub fn usart2sel(&self) -> USART2SEL_R

Bits 2:3 - USART2 clock source selection

pub fn cecsel(&self) -> CECSEL_R

Bit 6 - HDMI CEC clock source selection

pub fn lpuart1sel(&self) -> LPUART1SEL_R

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&self) -> I2C1SEL_R

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&self) -> I2S2SEL_R

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&self) -> LPTIM1SEL_R

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&self) -> LPTIM2SEL_R

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&self) -> TIM1SEL_R

Bit 22 - TIM1 clock source selection

pub fn tim15sel(&self) -> TIM15SEL_R

Bit 24 - TIM15 clock source selection

pub fn adcsel(&self) -> ADCSEL_R

Bits 30:31 - ADCs clock source selection

impl R<u32, Reg<u32, _BDCR>>

pub fn lseon(&self) -> LSEON_R

Bit 0 - LSE oscillator enable

pub fn lserdy(&self) -> LSERDY_R

Bit 1 - LSE oscillator ready

pub fn lsebyp(&self) -> LSEBYP_R

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&self) -> LSEDRV_R

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&self) -> LSECSSON_R

Bit 5 - CSS on LSE enable

pub fn lsecssd(&self) -> LSECSSD_R

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&self) -> RTCSEL_R

Bits 8:9 - RTC clock source selection

pub fn rtcen(&self) -> RTCEN_R

Bit 15 - RTC clock enable

pub fn bdrst(&self) -> BDRST_R

Bit 16 - RTC domain software reset

pub fn lscoen(&self) -> LSCOEN_R

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&self) -> LSCOSEL_R

Bit 25 - Low-speed clock output selection

impl R<u32, Reg<u32, _CSR>>

pub fn lsion(&self) -> LSION_R

Bit 0 - LSI oscillator enable

pub fn lsirdy(&self) -> LSIRDY_R

Bit 1 - LSI oscillator ready

pub fn rmvf(&self) -> RMVF_R

Bit 23 - Remove reset flags

pub fn oblrstf(&self) -> OBLRSTF_R

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&self) -> PINRSTF_R

Bit 26 - Pin reset flag

pub fn pwrrstf(&self) -> PWRRSTF_R

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&self) -> SFTRSTF_R

Bit 28 - Software reset flag

pub fn iwdgrstf(&self) -> IWDGRSTF_R

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&self) -> WWDGRSTF_R

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&self) -> LPWRRSTF_R

Bit 31 - Low-power reset flag

impl R<u32, Reg<u32, _CR1>>

pub fn lpr(&self) -> LPR_R

Bit 14 - Low-power run

pub fn vos(&self) -> VOS_R

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&self) -> DBP_R

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&self) -> FPD_LPSLP_R

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&self) -> FPD_LPRUN_R

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&self) -> FPD_STOP_R

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection

impl R<u32, Reg<u32, _CR2>>

pub fn pvde(&self) -> PVDE_R

Bit 0 - Power voltage detector enable

pub fn pvdft(&self) -> PVDFT_R

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&self) -> PVDRT_R

Bits 4:6 - Power voltage detector rising threshold selection

impl R<u32, Reg<u32, _CR3>>

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&self) -> EWUP6_R

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&self) -> RRS_R

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&self) -> ULPEN_R

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&self) -> APC_R

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line

impl R<u32, Reg<u32, _CR4>>

pub fn wp1(&self) -> WP1_R

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&self) -> WP2_R

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&self) -> WP4_R

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&self) -> WP5_R

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&self) -> WP6_R

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&self) -> VBE_R

Bit 8 - VBAT battery charging enable

pub fn vbrs(&self) -> VBRS_R

Bit 9 - VBAT battery charging resistor selection

impl R<u32, Reg<u32, _SR1>>

pub fn wuf1(&self) -> WUF1_R

Bit 0 - Wakeup flag 1

pub fn wuf2(&self) -> WUF2_R

Bit 1 - Wakeup flag 2

pub fn wuf4(&self) -> WUF4_R

Bit 3 - Wakeup flag 4

pub fn wuf5(&self) -> WUF5_R

Bit 4 - Wakeup flag 5

pub fn wuf6(&self) -> WUF6_R

Bit 5 - Wakeup flag 6

pub fn sbf(&self) -> SBF_R

Bit 8 - Standby flag

pub fn wufi(&self) -> WUFI_R

Bit 15 - Wakeup flag internal

impl R<u32, Reg<u32, _SR2>>

pub fn pvdo(&self) -> PVDO_R

Bit 11 - Power voltage detector output

pub fn vosf(&self) -> VOSF_R

Bit 10 - Voltage scaling flag

pub fn reglpf(&self) -> REGLPF_R

Bit 9 - Low-power regulator flag

pub fn reglps(&self) -> REGLPS_R

Bit 8 - Low-power regulator started

pub fn flash_rdy(&self) -> FLASH_RDY_R

Bit 7 - Flash ready flag

impl R<u32, Reg<u32, _PUCRA>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port A pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRA>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port A pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRB>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port B pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRB>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port B pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRC>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port C pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRC>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port C pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRD>>

pub fn pu9(&self) -> PU9_R

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port D pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRD>>

pub fn pd9(&self) -> PD9_R

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port D pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRF>>

pub fn pu2(&self) -> PU2_R

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port F pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRF>>

pub fn pd2(&self) -> PD2_R

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port F pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _CR>>

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

impl R<u32, Reg<u32, _NDTR>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _PAR>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _MAR>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _ISR>>

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel 1 global interrupt flag

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel 1 transfer complete flag

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel 1 half transfer flag

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel 1 transfer error flag

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel 2 global interrupt flag

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel 2 transfer complete flag

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel 2 half transfer flag

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel 2 transfer error flag

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel 3 global interrupt flag

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel 3 transfer complete flag

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel 3 half transfer flag

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel 3 transfer error flag

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel 4 global interrupt flag

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel 4 transfer complete flag

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel 4 half transfer flag

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel 4 transfer error flag

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel 5 global interrupt flag

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel 5 transfer complete flag

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel 5 half transfer flag

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel 5 transfer error flag

pub fn gif6(&self) -> GIF6_R

Bit 20 - Channel 6 global interrupt flag

pub fn tcif6(&self) -> TCIF6_R

Bit 21 - Channel 6 transfer complete flag

pub fn htif6(&self) -> HTIF6_R

Bit 22 - Channel 6 half transfer flag

pub fn teif6(&self) -> TEIF6_R

Bit 23 - Channel 6 transfer error flag

pub fn gif7(&self) -> GIF7_R

Bit 24 - Channel 7 global interrupt flag

pub fn tcif7(&self) -> TCIF7_R

Bit 25 - Channel 7 transfer complete flag

pub fn htif7(&self) -> HTIF7_R

Bit 26 - Channel 7 half transfer flag

pub fn teif7(&self) -> TEIF7_R

Bit 27 - Channel 7 transfer error flag

impl R<u32, Reg<u32, _DMAMUX_C0CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C1CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C2CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C3CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C4CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C5CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C6CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_RG0CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG1CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG2CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG3CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RGSR>>

pub fn of(&self) -> OF_R

Bits 0:3 - Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.

impl R<u32, Reg<u32, _DMAMUX_CSR>>

pub fn sof(&self) -> SOF_R

Bits 0:6 - Synchronization overrun event flag

impl R<u32, Reg<u32, _DMAMUX_SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size identification

impl R<u32, Reg<u32, _DMAMUX_IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - IP identification

impl R<u32, Reg<u32, _DMAMUX_VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor IP revision

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major IP revision

impl R<u32, Reg<u32, _DMAMUX_HWCFGR1>>

pub fn num_dma_streams(&self) -> NUM_DMA_STREAMS_R

Bits 0:7 - number of DMA request line multiplexer (output) channels

pub fn num_dma_periph_req(&self) -> NUM_DMA_PERIPH_REQ_R

Bits 8:15 - number of DMA request lines from peripherals

pub fn num_dma_trig(&self) -> NUM_DMA_TRIG_R

Bits 16:23 - number of synchronization inputs

pub fn num_dma_reqgen(&self) -> NUM_DMA_REQGEN_R

Bits 24:31 - number of DMA request generator channels

impl R<u32, Reg<u32, _DMAMUX_HWCFGR2>>

pub fn num_dma_ext_req(&self) -> NUM_DMA_EXT_REQ_R

Bits 0:7 - Number of DMA request trigger inputs

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:31 - Data register bits

impl R<u32, Reg<u32, _IDR>>

pub fn idr(&self) -> IDR_R

Bits 0:31 - General-purpose 32-bit data register bits

impl R<u32, Reg<u32, _CR>>

pub fn rev_out(&self) -> REV_OUT_R

Bit 7 - Reverse output data

pub fn rev_in(&self) -> REV_IN_R

Bits 5:6 - Reverse input data

pub fn polysize(&self) -> POLYSIZE_R

Bits 3:4 - Polynomial size

impl R<u32, Reg<u32, _INIT>>

pub fn crc_init(&self) -> CRC_INIT_R

Bits 0:31 - Programmable initial CRC value

impl R<u32, Reg<u32, _POL>>

pub fn pol(&self) -> POL_R

Bits 0:31 - Programmable polynomial

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _RTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&self) -> TR17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&self) -> TR18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _FTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&self) -> TR17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&self) -> TR18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, SWIER0_A>

pub fn variant(&self) -> Variant<bool, SWIER0_A>

Get enumerated values variant

pub fn is_pend(&self) -> bool

Checks if the value of the field is PEND

impl R<u32, Reg<u32, _SWIER1>>

pub fn swier0(&self) -> SWIER0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&self) -> SWIER1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&self) -> SWIER2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&self) -> SWIER3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&self) -> SWIER4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&self) -> SWIER5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&self) -> SWIER6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&self) -> SWIER7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&self) -> SWIER8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&self) -> SWIER9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&self) -> SWIER10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&self) -> SWIER11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&self) -> SWIER12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&self) -> SWIER13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&self) -> SWIER14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&self) -> SWIER15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&self) -> SWIER16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn swier17(&self) -> SWIER17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn swier18(&self) -> SWIER18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, RPIF0_A>

pub fn variant(&self) -> RPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _RPR1>>

pub fn rpif0(&self) -> RPIF0_R

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&self) -> RPIF1_R

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&self) -> RPIF2_R

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&self) -> RPIF3_R

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&self) -> RPIF4_R

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&self) -> RPIF5_R

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&self) -> RPIF6_R

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&self) -> RPIF7_R

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&self) -> RPIF8_R

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&self) -> RPIF9_R

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&self) -> RPIF10_R

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&self) -> RPIF11_R

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&self) -> RPIF12_R

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&self) -> RPIF13_R

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&self) -> RPIF14_R

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&self) -> RPIF15_R

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&self) -> RPIF16_R

Bit 16 - configurable event inputs x rising edge Pending bit.

pub fn rpif17(&self) -> RPIF17_R

Bit 17 - configurable event inputs x rising edge Pending bit.

pub fn rpif18(&self) -> RPIF18_R

Bit 18 - configurable event inputs x rising edge Pending bit.

impl R<bool, FPIF0_A>

pub fn variant(&self) -> FPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _FPR1>>

pub fn fpif0(&self) -> FPIF0_R

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&self) -> FPIF1_R

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&self) -> FPIF2_R

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&self) -> FPIF3_R

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&self) -> FPIF4_R

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&self) -> FPIF5_R

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&self) -> FPIF6_R

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&self) -> FPIF7_R

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&self) -> FPIF8_R

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&self) -> FPIF9_R

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&self) -> FPIF10_R

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&self) -> FPIF11_R

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&self) -> FPIF12_R

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&self) -> FPIF13_R

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&self) -> FPIF14_R

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&self) -> FPIF15_R

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&self) -> FPIF16_R

Bit 16 - configurable event inputs x falling edge pending bit.

pub fn fpif17(&self) -> FPIF17_R

Bit 17 - configurable event inputs x falling edge pending bit.

pub fn fpif18(&self) -> FPIF18_R

Bit 18 - configurable event inputs x falling edge pending bit.

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<bool, IM0_A>

pub fn variant(&self) -> IM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR1>>

pub fn im0(&self) -> IM0_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&self) -> IM1_R

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&self) -> IM2_R

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&self) -> IM3_R

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&self) -> IM4_R

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&self) -> IM5_R

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&self) -> IM6_R

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&self) -> IM7_R

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&self) -> IM8_R

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&self) -> IM9_R

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&self) -> IM10_R

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&self) -> IM11_R

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&self) -> IM12_R

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&self) -> IM13_R

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&self) -> IM14_R

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&self) -> IM15_R

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&self) -> IM16_R

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im17(&self) -> IM17_R

Bit 17 - CPU wakeup with interrupt mask on event input

pub fn im18(&self) -> IM18_R

Bit 18 - CPU wakeup with interrupt mask on event input

pub fn im19(&self) -> IM19_R

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&self) -> IM20_R

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&self) -> IM21_R

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&self) -> IM22_R

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&self) -> IM23_R

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&self) -> IM24_R

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&self) -> IM25_R

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&self) -> IM26_R

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im27(&self) -> IM27_R

Bit 27 - CPU wakeup with interrupt mask on event input

pub fn im28(&self) -> IM28_R

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&self) -> IM29_R

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&self) -> IM30_R

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&self) -> IM31_R

Bit 31 - CPU wakeup with interrupt mask on event input

impl R<bool, EM0_A>

pub fn variant(&self) -> EM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR1>>

pub fn em0(&self) -> EM0_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&self) -> EM1_R

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&self) -> EM2_R

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&self) -> EM3_R

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&self) -> EM4_R

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&self) -> EM5_R

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&self) -> EM6_R

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&self) -> EM7_R

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&self) -> EM8_R

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&self) -> EM9_R

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&self) -> EM10_R

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&self) -> EM11_R

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&self) -> EM12_R

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&self) -> EM13_R

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&self) -> EM14_R

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&self) -> EM15_R

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&self) -> EM16_R

Bit 16 - CPU wakeup with event mask on event input

pub fn em17(&self) -> EM17_R

Bit 17 - CPU wakeup with event mask on event input

pub fn em18(&self) -> EM18_R

Bit 18 - CPU wakeup with event mask on event input

pub fn em19(&self) -> EM19_R

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&self) -> EM21_R

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&self) -> EM23_R

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&self) -> EM25_R

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&self) -> EM26_R

Bit 26 - CPU wakeup with event mask on event input

pub fn em27(&self) -> EM27_R

Bit 27 - CPU wakeup with event mask on event input

pub fn em28(&self) -> EM28_R

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&self) -> EM29_R

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&self) -> EM30_R

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&self) -> EM31_R

Bit 31 - CPU wakeup with event mask on event input

impl R<bool, IM32_A>

pub fn variant(&self) -> IM32_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR2>>

pub fn im32(&self) -> IM32_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im33(&self) -> IM33_R

Bit 1 - CPU wakeup with interrupt mask on event input

impl R<bool, EM32_A>

pub fn variant(&self) -> EM32_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR2>>

pub fn em32(&self) -> EM32_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em33(&self) -> EM33_R

Bit 1 - CPU wakeup with event mask on event input

impl R<u32, Reg<u32, _HWCFGR7>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR6>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR5>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR4>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR3>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn nbioport(&self) -> NBIOPORT_R

Bits 16:23 - HW configuration of number of IO ports

pub fn cpuevten(&self) -> CPUEVTEN_R

Bits 12:15 - HW configuration of CPU event output enable

pub fn nbcpus(&self) -> NBCPUS_R

Bits 8:11 - configuration number of CPUs

pub fn nbevents(&self) -> NBEVENTS_R

Bits 0:7 - configuration number of event

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&self) -> BKDFBK1E_R

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - selects input

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - selects input

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output idle state 2 (OC2 output)

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/slave mode

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

impl R<u32, Reg<u32, _DIER>>

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/Compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 complementary output polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - BKF

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - BKDSRM

pub fn bkbid(&self) -> BKBID_R

Bit 29 - BKBID

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&self) -> BKDFBK1E_R

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - selects input

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - selects input

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT

pub fn dedt(&self) -> DEDT_R

Bits 16:20 - DEDT

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn rtoen(&self) -> RTOEN_R

Bit 23 - Receiver timeout enable

pub fn abrmod(&self) -> ABRMOD_R

Bits 21:22 - Auto baud rate mode

pub fn abren(&self) -> ABREN_R

Bit 20 - Auto baud rate enable

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn linen(&self) -> LINEN_R

Bit 14 - LIN mode enable

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn clken(&self) -> CLKEN_R

Bit 11 - Clock enable

pub fn cpol(&self) -> CPOL_R

Bit 10 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 9 - Clock phase

pub fn lbcl(&self) -> LBCL_R

Bit 8 - Last bit clock pulse

pub fn lbdie(&self) -> LBDIE_R

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&self) -> LBDL_R

Bit 5 - LIN break detection length

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&self) -> DIS_NSS_R

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&self) -> SLVEN_R

Bit 0 - Synchronous Slave mode enable

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&self) -> TCBGTIE_R

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&self) -> SCARCNT_R

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn onebit(&self) -> ONEBIT_R

Bit 11 - One sample bit method enable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn scen(&self) -> SCEN_R

Bit 5 - Smartcard mode enable

pub fn nack(&self) -> NACK_R

Bit 4 - Smartcard NACK enable

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn irlp(&self) -> IRLP_R

Bit 2 - Ir low-power

pub fn iren(&self) -> IREN_R

Bit 1 - Ir mode enable

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&self) -> BRR_4_15_R

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&self) -> BRR_0_3_R

Bits 0:3 - BRR_0_3

impl R<u32, Reg<u32, _GTPR>>

pub fn gt(&self) -> GT_R

Bits 8:15 - Guard time value

pub fn psc(&self) -> PSC_R

Bits 0:7 - Prescaler value

impl R<u32, Reg<u32, _RTOR>>

pub fn blen(&self) -> BLEN_R

Bits 24:31 - Block Length

pub fn rto(&self) -> RTO_R

Bits 0:23 - Receiver timeout value

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn tcbgt(&self) -> TCBGT_R

Bit 25 - Transmission complete before guard time flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn abrf(&self) -> ABRF_R

Bit 15 - ABRF

pub fn abre(&self) -> ABRE_R

Bit 14 - ABRE

pub fn udr(&self) -> UDR_R

Bit 13 - SPI slave underrun error flag

pub fn eobf(&self) -> EOBF_R

Bit 12 - EOBF

pub fn rtof(&self) -> RTOF_R

Bit 11 - RTOF

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn lbdf(&self) -> LBDF_R

Bit 8 - LBDF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn bidimode(&self) -> BIDIMODE_R

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&self) -> BIDIOE_R

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&self) -> CRCEN_R

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&self) -> CRCNEXT_R

Bit 12 - CRC transfer next

pub fn dff(&self) -> DFF_R

Bit 11 - Data frame format

pub fn rxonly(&self) -> RXONLY_R

Bit 10 - Receive only

pub fn ssm(&self) -> SSM_R

Bit 9 - Software slave management

pub fn ssi(&self) -> SSI_R

Bit 8 - Internal slave select

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 7 - Frame format

pub fn spe(&self) -> SPE_R

Bit 6 - SPI enable

pub fn br(&self) -> BR_R

Bits 3:5 - Baud rate control

pub fn mstr(&self) -> MSTR_R

Bit 2 - Master selection

pub fn cpol(&self) -> CPOL_R

Bit 1 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 0 - Clock phase

impl R<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&self) -> SSOE_R

Bit 2 - SS output enable

pub fn nssp(&self) -> NSSP_R

Bit 3 - NSS pulse management

pub fn frf(&self) -> FRF_R

Bit 4 - Frame format

pub fn errie(&self) -> ERRIE_R

Bit 5 - Error interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&self) -> DS_R

Bits 8:11 - Data size

pub fn frxth(&self) -> FRXTH_R

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&self) -> LDMA_RX_R

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&self) -> LDMA_TX_R

Bit 14 - Last DMA transfer for transmission

impl R<u32, Reg<u32, _SR>>

pub fn rxne(&self) -> RXNE_R

Bit 0 - Receive buffer not empty

pub fn txe(&self) -> TXE_R

Bit 1 - Transmit buffer empty

pub fn chside(&self) -> CHSIDE_R

Bit 2 - Channel side

pub fn udr(&self) -> UDR_R

Bit 3 - Underrun flag

pub fn crcerr(&self) -> CRCERR_R

Bit 4 - CRC error flag

pub fn modf(&self) -> MODF_R

Bit 5 - Mode fault

pub fn ovr(&self) -> OVR_R

Bit 6 - Overrun flag

pub fn bsy(&self) -> BSY_R

Bit 7 - Busy flag

pub fn tifrfe(&self) -> TIFRFE_R

Bit 8 - TI frame format error

pub fn frlvl(&self) -> FRLVL_R

Bits 9:10 - FIFO reception level

pub fn ftlvl(&self) -> FTLVL_R

Bits 11:12 - FIFO transmission level

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:15 - Data register

impl R<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&self) -> CRCPOLY_R

Bits 0:15 - CRC polynomial register

impl R<u32, Reg<u32, _RXCRCR>>

pub fn rx_crc(&self) -> RXCRC_R

Bits 0:15 - Rx CRC register

impl R<u32, Reg<u32, _TXCRCR>>

pub fn tx_crc(&self) -> TXCRC_R

Bits 0:15 - Tx CRC register

impl R<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&self) -> CHLEN_R

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&self) -> DATLEN_R

Bits 1:2 - Data length to be transferred

pub fn ckpol(&self) -> CKPOL_R

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&self) -> I2SSTD_R

Bits 4:5 - standard selection

pub fn pcmsync(&self) -> PCMSYNC_R

Bit 7 - PCM frame synchronization

pub fn i2scfg(&self) -> I2SCFG_R

Bits 8:9 - I2S configuration mode

pub fn se2(&self) -> SE2_R

Bit 10 - I2S enable

pub fn i2smod(&self) -> I2SMOD_R

Bit 11 - I2S mode selection

impl R<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&self) -> I2SDIV_R

Bits 0:7 - linear prescaler

pub fn odd(&self) -> ODD_R

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&self) -> MCKOE_R

Bit 9 - Master clock output enable

impl R<u32, Reg<u32, _HWCFGR>>

pub fn crccfg(&self) -> CRCCFG_R

Bits 0:3 - CRC capable at SPI mode

pub fn i2scfg(&self) -> I2SCFG_R

Bits 4:7 - I2S mode implementation

pub fn i2sckcfg(&self) -> I2SCKCFG_R

Bits 8:11 - I2S master clock generator at I2S mode

pub fn dscfg(&self) -> DSCFG_R

Bits 12:15 - SPI data size configuration

pub fn nsscfg(&self) -> NSSCFG_R

Bits 16:19 - NSS pulse feature enhancement at SPI master

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn ts_4(&self) -> TS_4_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn ts(&self) -> TS_R

Bits 20:21 - Trigger selection

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag

pub fn cc5if(&self) -> CC5IF_R

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&self) -> CC6IF_R

Bit 17 - Compare 6 interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

impl R<u32, Reg<u32, _CCER>>

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&self) -> CC2NE_R

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&self) -> CC3NE_R

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&self) -> CC5E_R

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&self) -> CC5P_R

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&self) -> CC6E_R

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&self) -> CC6P_R

Bit 21 - Capture/Compare 6 output polarity

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:15 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3(&self) -> CCR3_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4(&self) -> CCR4_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bk2f(&self) -> BK2F_R

Bits 20:23 - Break 2 filter

pub fn bk2e(&self) -> BK2E_R

Bit 24 - Break 2 enable

pub fn bk2p(&self) -> BK2P_R

Bit 25 - Break 2 polarity

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bk2dsrm(&self) -> BK2DSRM_R

Bit 27 - Break2 Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

pub fn bk2id(&self) -> BK2ID_R

Bit 29 - Break2 bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&self) -> OCREF_CLR_R

Bit 0 - Ocref_clr source selection

impl R<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&self) -> OC6M_BIT3_R

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&self) -> OC5M_BIT3_R

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&self) -> OC6CE_R

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&self) -> OC6M_R

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&self) -> OC6PE_R

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&self) -> OC6FE_R

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&self) -> OC5CE_R

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&self) -> OC5M_R

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&self) -> OC5PE_R

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&self) -> OC5FE_R

Bit 2 - Output compare 5 fast enable

impl R<u32, Reg<u32, _CCR5>>

pub fn ccr5(&self) -> CCR5_R

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&self) -> GC5C1_R

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&self) -> GC5C2_R

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&self) -> GC5C3_R

Bit 31 - Group Channel 5 and Channel 3

impl R<u32, Reg<u32, _CCR6>>

pub fn ccr6(&self) -> CCR6_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - ETR source selection

impl R<u32, Reg<u32, _AF2>>

pub fn bk2ine(&self) -> BK2INE_R

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&self) -> BK2CMP1E_R

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&self) -> BK2CMP2E_R

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&self) -> BK2INP_R

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&self) -> BK2CMP1P_R

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&self) -> BK2CMP2P_R

Bit 11 - BRK2 COMP2 input polarity

impl R<u32, Reg<u32, _ISR>>

pub fn ccrdy(&self) -> CCRDY_R

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&self) -> EOCAL_R

Bit 11 - End Of Calibration flag

pub fn awd3(&self) -> AWD3_R

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&self) -> AWD2_R

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&self) -> AWD1_R

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&self) -> OVR_R

Bit 4 - ADC group regular overrun flag

pub fn eos(&self) -> EOS_R

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&self) -> EOC_R

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&self) -> EOSMP_R

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&self) -> ADRDY_R

Bit 0 - ADC ready flag

impl R<u32, Reg<u32, _IER>>

pub fn ccrdyie(&self) -> CCRDYIE_R

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&self) -> EOCALIE_R

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&self) -> AWD3IE_R

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&self) -> AWD2IE_R

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&self) -> AWD1IE_R

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&self) -> OVRIE_R

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&self) -> EOSIE_R

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&self) -> EOCIE_R

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&self) -> EOSMPIE_R

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&self) -> ADRDYIE_R

Bit 0 - ADC ready interrupt

impl R<u32, Reg<u32, _CR>>

pub fn adcal(&self) -> ADCAL_R

Bit 31 - ADC calibration

pub fn advregen(&self) -> ADVREGEN_R

Bit 28 - ADC voltage regulator enable

pub fn adstp(&self) -> ADSTP_R

Bit 4 - ADC group regular conversion stop

pub fn adstart(&self) -> ADSTART_R

Bit 2 - ADC group regular conversion start

pub fn addis(&self) -> ADDIS_R

Bit 1 - ADC disable

pub fn aden(&self) -> ADEN_R

Bit 0 - ADC enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&self) -> AWDCH1CH_R

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&self) -> AWD1EN_R

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGL_R

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&self) -> CHSELRMOD_R

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&self) -> DISCEN_R

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&self) -> AUTOFF_R

Bit 15 - Auto-off mode

pub fn wait(&self) -> WAIT_R

Bit 14 - Wait conversion mode

pub fn cont(&self) -> CONT_R

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMOD_R

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTEN_R

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSEL_R

Bits 6:8 - ADC group regular external trigger source

pub fn align(&self) -> ALIGN_R

Bit 5 - ADC data alignement

pub fn res(&self) -> RES_R

Bits 3:4 - ADC data resolution

pub fn scandir(&self) -> SCANDIR_R

Bit 2 - Scan sequence direction

pub fn dmacfg(&self) -> DMACFG_R

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - ADC DMA transfer enable

impl R<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&self) -> CKMODE_R

Bits 30:31 - ADC clock mode

pub fn lftrig(&self) -> LFTRIG_R

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&self) -> TOVS_R

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&self) -> OVSS_R

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&self) -> OVSR_R

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&self) -> OVSE_R

Bit 0 - ADC oversampler enable on scope ADC group regular

impl R<u32, Reg<u32, _SMPR>>

pub fn smp1(&self) -> SMP1_R

Bits 0:2 - Sampling time selection

pub fn smp2(&self) -> SMP2_R

Bits 4:6 - Sampling time selection

pub fn smpsel(&self) -> SMPSEL_R

Bits 8:26 - Channel sampling time selection

impl R<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&self) -> HT1_R

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&self) -> LT1_R

Bits 0:11 - ADC analog watchdog 1 threshold low

impl R<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&self) -> HT2_R

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&self) -> LT2_R

Bits 0:11 - ADC analog watchdog 2 threshold low

impl R<u32, Reg<u32, _CHSELR>>

pub fn chsel(&self) -> CHSEL_R

Bits 0:18 - Channel-x selection

impl R<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&self) -> SQ1_R

Bits 0:3 - conversion of the sequence

pub fn sq2(&self) -> SQ2_R

Bits 4:7 - conversion of the sequence

pub fn sq3(&self) -> SQ3_R

Bits 8:11 - conversion of the sequence

pub fn sq4(&self) -> SQ4_R

Bits 12:15 - conversion of the sequence

pub fn sq5(&self) -> SQ5_R

Bits 16:19 - conversion of the sequence

pub fn sq6(&self) -> SQ6_R

Bits 20:23 - conversion of the sequence

pub fn sq7(&self) -> SQ7_R

Bits 24:27 - conversion of the sequence

pub fn sq8(&self) -> SQ8_R

Bits 28:31 - conversion of the sequence

impl R<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&self) -> HT3_R

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&self) -> LT3_R

Bits 0:11 - ADC analog watchdog 3 threshold high

impl R<u32, Reg<u32, _DR>>

pub fn regular_data(&self) -> REGULARDATA_R

Bits 0:15 - ADC group regular conversion data

impl R<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&self) -> AWD2CH_R

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl R<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&self) -> AWD3CH_R

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl R<u32, Reg<u32, _CALFACT>>

pub fn calfact(&self) -> CALFACT_R

Bits 0:6 - ADC calibration factor in single-ended mode

impl R<u32, Reg<u32, _CCR>>

pub fn presc(&self) -> PRESC_R

Bits 18:21 - ADC prescaler

pub fn vrefen(&self) -> VREFEN_R

Bit 22 - VREFINT enable

pub fn tsen(&self) -> TSEN_R

Bit 23 - Temperature sensor enable

pub fn vbaten(&self) -> VBATEN_R

Bit 24 - VBAT enable

impl R<u32, Reg<u32, _HWCFGR6>>

pub fn chmap20(&self) -> CHMAP20_R

Bits 0:4 - Input channel mapping

pub fn chmap21(&self) -> CHMAP21_R

Bits 8:12 - Input channel mapping

pub fn chmap22(&self) -> CHMAP22_R

Bits 16:20 - Input channel mapping

pub fn chmap23(&self) -> CHMAP23_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR5>>

pub fn chmap19(&self) -> CHMAP19_R

Bits 0:4 - Input channel mapping

pub fn chmap18(&self) -> CHMAP18_R

Bits 8:12 - Input channel mapping

pub fn chmap17(&self) -> CHMAP17_R

Bits 16:20 - Input channel mapping

pub fn chmap16(&self) -> CHMAP16_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR4>>

pub fn chmap15(&self) -> CHMAP15_R

Bits 0:4 - Input channel mapping

pub fn chmap14(&self) -> CHMAP14_R

Bits 8:12 - Input channel mapping

pub fn chmap13(&self) -> CHMAP13_R

Bits 16:20 - Input channel mapping

pub fn chmap12(&self) -> CHMAP12_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR3>>

pub fn chmap11(&self) -> CHMAP11_R

Bits 0:4 - Input channel mapping

pub fn chmap10(&self) -> CHMAP10_R

Bits 8:12 - Input channel mapping

pub fn chmap9(&self) -> CHMAP9_R

Bits 16:20 - Input channel mapping

pub fn chmap8(&self) -> CHMAP8_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn chmap7(&self) -> CHMAP7_R

Bits 0:4 - Input channel mapping

pub fn chmap6(&self) -> CHMAP6_R

Bits 8:12 - Input channel mapping

pub fn chmap5(&self) -> CHMAP5_R

Bits 16:20 - Input channel mapping

pub fn chmap4(&self) -> CHMAP4_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn chmap3(&self) -> CHMAP3_R

Bits 0:4 - Input channel mapping

pub fn chmap2(&self) -> CHMAP2_R

Bits 8:12 - Input channel mapping

pub fn chmap1(&self) -> CHMAP1_R

Bits 16:20 - Input channel mapping

pub fn chmap0(&self) -> CHMAP0_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR0>>

pub fn num_chan_24(&self) -> NUM_CHAN_24_R

Bits 0:3 - NUM_CHAN_24

pub fn extra_awds(&self) -> EXTRA_AWDS_R

Bits 4:7 - Extra analog watchdog

pub fn ovs(&self) -> OVS_R

Bits 8:11 - Oversampling

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _COMP1_CSR>>

pub fn en(&self) -> EN_R

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&self) -> INMSEL_R

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&self) -> INPSEL_R

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&self) -> WINMODE_R

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&self) -> WINOUT_R

Bit 14 - Comparator 2 output selector

pub fn polarity(&self) -> POLARITY_R

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&self) -> HYST_R

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&self) -> PWRMODE_R

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&self) -> BLANKSEL_R

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&self) -> VALUE_R

Bit 30 - Comparator 2 output status

pub fn lock(&self) -> LOCK_R

Bit 31 - COMP2_CSR register lock

impl R<u32, Reg<u32, _COMP2_CSR>>

pub fn en(&self) -> EN_R

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&self) -> INMSEL_R

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&self) -> INPSEL_R

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&self) -> WINMODE_R

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&self) -> WINOUT_R

Bit 14 - Comparator 2 output selector

pub fn polarity(&self) -> POLARITY_R

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&self) -> HYST_R

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&self) -> PWRMODE_R

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&self) -> BLANKSEL_R

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&self) -> VALUE_R

Bit 30 - Comparator 2 output status

pub fn lock(&self) -> LOCK_R

Bit 31 - COMP2_CSR register lock

impl R<u32, Reg<u32, _VREFBUF_CSR>>

pub fn envr(&self) -> ENVR_R

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&self) -> HIZ_R

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrr(&self) -> VRR_R

Bit 3 - Voltage reference buffer ready

pub fn vrs(&self) -> VRS_R

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl R<u32, Reg<u32, _VREFBUF_CCR>>

pub fn trim(&self) -> TRIM_R

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl R<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&self) -> I2C_PAX_FMP_R

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&self) -> I2C2_FMP_R

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&self) -> I2C1_FMP_R

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&self) -> I2C_PBX_FMP_R

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn ucpd2_strobe(&self) -> UCPD2_STROBE_R

Bit 10 - Strobe signal bit for UCPD2

pub fn ucpd1_strobe(&self) -> UCPD1_STROBE_R

Bit 9 - Strobe signal bit for UCPD1

pub fn boosten(&self) -> BOOSTEN_R

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&self) -> IR_MOD_R

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&self) -> IR_POL_R

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&self) -> PA11_PA12_RMP_R

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&self) -> MEM_MODE_R

Bits 0:1 - Memory mapping selection bits

impl R<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&self) -> LOCKUP_LOCK_R

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&self) -> SRAM_PARITY_LOCK_R

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&self) -> PVD_LOCK_R

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&self) -> ECC_LOCK_R

Bit 3 - ECC error lock bit

pub fn sram_pef(&self) -> SRAM_PEF_R

Bit 8 - SRAM parity error flag

impl R<u32, Reg<u32, _ITLINE0>>

pub fn wwdg(&self) -> WWDG_R

Bit 0 - Window watchdog interrupt pending flag

impl R<u32, Reg<u32, _ITLINE1>>

pub fn pvdout(&self) -> PVDOUT_R

Bit 0 - PVD supply monitoring interrupt request pending (EXTI line 16).

impl R<u32, Reg<u32, _ITLINE2>>

pub fn tamp(&self) -> TAMP_R

Bit 0 - TAMP

pub fn rtc(&self) -> RTC_R

Bit 1 - RTC

impl R<u32, Reg<u32, _ITLINE3>>

pub fn flash_itf(&self) -> FLASH_ITF_R

Bit 0 - FLASH_ITF

pub fn flash_ecc(&self) -> FLASH_ECC_R

Bit 1 - FLASH_ECC

impl R<u32, Reg<u32, _ITLINE4>>

pub fn rcc(&self) -> RCC_R

Bit 0 - RCC

impl R<u32, Reg<u32, _ITLINE5>>

pub fn exti0(&self) -> EXTI0_R

Bit 0 - EXTI0

pub fn exti1(&self) -> EXTI1_R

Bit 1 - EXTI1

impl R<u32, Reg<u32, _ITLINE6>>

pub fn exti2(&self) -> EXTI2_R

Bit 0 - EXTI2

pub fn exti3(&self) -> EXTI3_R

Bit 1 - EXTI3

impl R<u32, Reg<u32, _ITLINE7>>

pub fn exti4(&self) -> EXTI4_R

Bit 0 - EXTI4

pub fn exti5(&self) -> EXTI5_R

Bit 1 - EXTI5

pub fn exti6(&self) -> EXTI6_R

Bit 2 - EXTI6

pub fn exti7(&self) -> EXTI7_R

Bit 3 - EXTI7

pub fn exti8(&self) -> EXTI8_R

Bit 4 - EXTI8

pub fn exti9(&self) -> EXTI9_R

Bit 5 - EXTI9

pub fn exti10(&self) -> EXTI10_R

Bit 6 - EXTI10

pub fn exti11(&self) -> EXTI11_R

Bit 7 - EXTI11

pub fn exti12(&self) -> EXTI12_R

Bit 8 - EXTI12

pub fn exti13(&self) -> EXTI13_R

Bit 9 - EXTI13

pub fn exti14(&self) -> EXTI14_R

Bit 10 - EXTI14

pub fn exti15(&self) -> EXTI15_R

Bit 11 - EXTI15

impl R<u32, Reg<u32, _ITLINE8>>

pub fn ucpd1(&self) -> UCPD1_R

Bit 0 - UCPD1

pub fn ucpd2(&self) -> UCPD2_R

Bit 1 - UCPD2

impl R<u32, Reg<u32, _ITLINE9>>

pub fn dma1_ch1(&self) -> DMA1_CH1_R

Bit 0 - DMA1_CH1

impl R<u32, Reg<u32, _ITLINE10>>

pub fn dma1_ch2(&self) -> DMA1_CH2_R

Bit 0 - DMA1_CH1

pub fn dma1_ch3(&self) -> DMA1_CH3_R

Bit 1 - DMA1_CH3

impl R<u32, Reg<u32, _ITLINE11>>

pub fn dmamux(&self) -> DMAMUX_R

Bit 0 - DMAMUX

pub fn dma1_ch4(&self) -> DMA1_CH4_R

Bit 1 - DMA1_CH4

pub fn dma1_ch5(&self) -> DMA1_CH5_R

Bit 2 - DMA1_CH5

pub fn dma1_ch6(&self) -> DMA1_CH6_R

Bit 3 - DMA1_CH6

pub fn dma1_ch7(&self) -> DMA1_CH7_R

Bit 4 - DMA1_CH7

impl R<u32, Reg<u32, _ITLINE12>>

pub fn adc(&self) -> ADC_R

Bit 0 - ADC

pub fn comp1(&self) -> COMP1_R

Bit 1 - COMP1

pub fn comp2(&self) -> COMP2_R

Bit 2 - COMP2

impl R<u32, Reg<u32, _ITLINE13>>

pub fn tim1_ccu(&self) -> TIM1_CCU_R

Bit 0 - TIM1_CCU

pub fn tim1_trg(&self) -> TIM1_TRG_R

Bit 1 - TIM1_TRG

pub fn tim1_upd(&self) -> TIM1_UPD_R

Bit 2 - TIM1_UPD

pub fn tim1_brk(&self) -> TIM1_BRK_R

Bit 3 - TIM1_BRK

impl R<u32, Reg<u32, _ITLINE14>>

pub fn tim1_cc(&self) -> TIM1_CC_R

Bit 0 - TIM1_CC

impl R<u32, Reg<u32, _ITLINE15>>

pub fn tim2(&self) -> TIM2_R

Bit 0 - TIM2

impl R<u32, Reg<u32, _ITLINE16>>

pub fn tim3(&self) -> TIM3_R

Bit 0 - TIM3

impl R<u32, Reg<u32, _ITLINE17>>

pub fn tim6(&self) -> TIM6_R

Bit 0 - TIM6

pub fn dac(&self) -> DAC_R

Bit 1 - DAC

pub fn lptim1(&self) -> LPTIM1_R

Bit 2 - LPTIM1

impl R<u32, Reg<u32, _ITLINE18>>

pub fn tim7(&self) -> TIM7_R

Bit 0 - TIM7

pub fn lptim2(&self) -> LPTIM2_R

Bit 1 - LPTIM2

impl R<u32, Reg<u32, _ITLINE19>>

pub fn tim14(&self) -> TIM14_R

Bit 0 - TIM14

impl R<u32, Reg<u32, _ITLINE20>>

pub fn tim15(&self) -> TIM15_R

Bit 0 - TIM15

impl R<u32, Reg<u32, _ITLINE21>>

pub fn tim16(&self) -> TIM16_R

Bit 0 - TIM16

impl R<u32, Reg<u32, _ITLINE22>>

pub fn tim17(&self) -> TIM17_R

Bit 0 - TIM17

impl R<u32, Reg<u32, _ITLINE23>>

pub fn i2c1(&self) -> I2C1_R

Bit 0 - I2C1

impl R<u32, Reg<u32, _ITLINE24>>

pub fn i2c2(&self) -> I2C2_R

Bit 0 - I2C2

impl R<u32, Reg<u32, _ITLINE25>>

pub fn spi1(&self) -> SPI1_R

Bit 0 - SPI1

impl R<u32, Reg<u32, _ITLINE26>>

pub fn spi2(&self) -> SPI2_R

Bit 0 - SPI2

impl R<u32, Reg<u32, _ITLINE27>>

pub fn usart1(&self) -> USART1_R

Bit 0 - USART1

impl R<u32, Reg<u32, _ITLINE28>>

pub fn usart2(&self) -> USART2_R

Bit 0 - USART2

impl R<u32, Reg<u32, _ITLINE29>>

pub fn usart3(&self) -> USART3_R

Bit 0 - USART3

pub fn usart4(&self) -> USART4_R

Bit 1 - USART4

pub fn usart5(&self) -> USART5_R

Bit 2 - USART5

impl R<u32, Reg<u32, _ITLINE30>>

pub fn usart2(&self) -> USART2_R

Bit 0 - CEC

impl R<u32, Reg<u32, _ITLINE31>>

pub fn rng(&self) -> RNG_R

Bit 0 - RNG

pub fn aes(&self) -> AES_R

Bit 1 - AES

impl R<u32, Reg<u32, _CR1>>

pub fn tamp1e(&self) -> TAMP1E_R

Bit 0 - TAMP1E

pub fn tamp2e(&self) -> TAMP2E_R

Bit 1 - TAMP2E

pub fn itamp1e(&self) -> ITAMP1E_R

Bit 16 - ITAMP1E

pub fn itamp3e(&self) -> ITAMP3E_R

Bit 18 - ITAMP3E

pub fn itamp4e(&self) -> ITAMP4E_R

Bit 19 - ITAMP4E

pub fn itamp5e(&self) -> ITAMP5E_R

Bit 20 - ITAMP5E

pub fn itamp6e(&self) -> ITAMP6E_R

Bit 21 - ITAMP6E

impl R<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&self) -> TAMP1NOER_R

Bit 0 - TAMP1NOER

pub fn tamp2noer(&self) -> TAMP2NOER_R

Bit 1 - TAMP2NOER

pub fn tamp1msk(&self) -> TAMP1MSK_R

Bit 16 - TAMP1MSK

pub fn tamp2msk(&self) -> TAMP2MSK_R

Bit 17 - TAMP2MSK

pub fn tamp1trg(&self) -> TAMP1TRG_R

Bit 24 - TAMP1TRG

pub fn tamp2trg(&self) -> TAMP2TRG_R

Bit 25 - TAMP2TRG

impl R<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&self) -> TAMPFREQ_R

Bits 0:2 - TAMPFREQ

pub fn tampflt(&self) -> TAMPFLT_R

Bits 3:4 - TAMPFLT

pub fn tampprch(&self) -> TAMPPRCH_R

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&self) -> TAMPPUDIS_R

Bit 7 - TAMPPUDIS

impl R<u32, Reg<u32, _IER>>

pub fn tamp1ie(&self) -> TAMP1IE_R

Bit 0 - TAMP1IE

pub fn tamp2ie(&self) -> TAMP2IE_R

Bit 1 - TAMP2IE

pub fn itamp1ie(&self) -> ITAMP1IE_R

Bit 16 - ITAMP1IE

pub fn itamp3ie(&self) -> ITAMP3IE_R

Bit 18 - ITAMP3IE

pub fn itamp4ie(&self) -> ITAMP4IE_R

Bit 19 - ITAMP4IE

pub fn itamp5ie(&self) -> ITAMP5IE_R

Bit 20 - ITAMP5IE

pub fn itamp6ie(&self) -> ITAMP6IE_R

Bit 21 - ITAMP6IE

impl R<u32, Reg<u32, _SR>>

pub fn tamp1f(&self) -> TAMP1F_R

Bit 0 - TAMP1F

pub fn tamp2f(&self) -> TAMP2F_R

Bit 1 - TAMP2F

pub fn itamp1f(&self) -> ITAMP1F_R

Bit 16 - ITAMP1F

pub fn itamp3f(&self) -> ITAMP3F_R

Bit 18 - ITAMP3F

pub fn itamp4f(&self) -> ITAMP4F_R

Bit 19 - ITAMP4F

pub fn itamp5f(&self) -> ITAMP5F_R

Bit 20 - ITAMP5F

pub fn itamp6f(&self) -> ITAMP6F_R

Bit 21 - ITAMP6F

pub fn itamp7f(&self) -> ITAMP7F_R

Bit 22 - ITAMP7F

impl R<u32, Reg<u32, _MISR>>

pub fn tamp1mf(&self) -> TAMP1MF_R

Bit 0 - TAMP1MF:

pub fn tamp2mf(&self) -> TAMP2MF_R

Bit 1 - TAMP2MF

pub fn itamp1mf(&self) -> ITAMP1MF_R

Bit 16 - ITAMP1MF

pub fn itamp3mf(&self) -> ITAMP3MF_R

Bit 18 - ITAMP3MF

pub fn itamp4mf(&self) -> ITAMP4MF_R

Bit 19 - ITAMP4MF

pub fn itamp5mf(&self) -> ITAMP5MF_R

Bit 20 - ITAMP5MF

pub fn itamp6mf(&self) -> ITAMP6MF_R

Bit 21 - ITAMP6MF

impl R<u32, Reg<u32, _BKP0R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP1R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP2R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP3R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP4R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn ptionreg_out(&self) -> PTIONREG_OUT_R

Bits 0:7 - PTIONREG_OUT

pub fn trust_zone(&self) -> TRUST_ZONE_R

Bits 8:11 - TRUST_ZONE

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn backup_regs(&self) -> BACKUP_REGS_R

Bits 0:7 - BACKUP_REGS

pub fn tamper(&self) -> TAMPER_R

Bits 8:11 - TAMPER

pub fn active_tamper(&self) -> ACTIVE_TAMPER_R

Bits 12:15 - ACTIVE_TAMPER

pub fn int_tamper(&self) -> INT_TAMPER_R

Bits 16:31 - INT_TAMPER

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CFG1>>

pub fn hbitclkdiv(&self) -> HBITCLKDIV_R

Bits 0:5 - HBITCLKDIV

pub fn ifrgap(&self) -> IFRGAP_R

Bits 6:10 - IFRGAP

pub fn transwin(&self) -> TRANSWIN_R

Bits 11:15 - TRANSWIN

pub fn psc_usbpdclk(&self) -> PSC_USBPDCLK_R

Bits 17:19 - PSC_USBPDCLK

pub fn rxordseten(&self) -> RXORDSETEN_R

Bits 20:28 - RXORDSETEN

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 29 - TXDMAEN

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 30 - RXDMAEN:

pub fn ucpden(&self) -> UCPDEN_R

Bit 31 - UCPDEN

impl R<u32, Reg<u32, _CFG2>>

pub fn rxfiltdis(&self) -> RXFILTDIS_R

Bit 0 - RXFILTDIS

pub fn rxfilt2n3(&self) -> RXFILT2N3_R

Bit 1 - RXFILT2N3

pub fn forceclk(&self) -> FORCECLK_R

Bit 2 - FORCECLK

pub fn wupen(&self) -> WUPEN_R

Bit 3 - WUPEN

impl R<u32, Reg<u32, _CFG3>>

pub fn trim1_ng_ccrpd(&self) -> TRIM1_NG_CCRPD_R

Bits 0:3 - TRIM1_NG_CCRPD

pub fn trim1_ng_cc1a5(&self) -> TRIM1_NG_CC1A5_R

Bits 4:8 - TRIM1_NG_CC1A5

pub fn trim1_ng_cc3a0(&self) -> TRIM1_NG_CC3A0_R

Bits 9:12 - TRIM1_NG_CC3A0

pub fn trim2_ng_ccrpd(&self) -> TRIM2_NG_CCRPD_R

Bits 16:19 - TRIM2_NG_CCRPD

pub fn trim2_ng_cc1a5(&self) -> TRIM2_NG_CC1A5_R

Bits 20:24 - TRIM2_NG_CC1A5

pub fn trim2_ng_cc3a0(&self) -> TRIM2_NG_CC3A0_R

Bits 25:28 - TRIM2_NG_CC3A0

impl R<u32, Reg<u32, _CR>>

pub fn txmode(&self) -> TXMODE_R

Bits 0:1 - TXMODE

pub fn txsend(&self) -> TXSEND_R

Bit 2 - TXSEND

pub fn txhrst(&self) -> TXHRST_R

Bit 3 - TXHRST

pub fn rxmode(&self) -> RXMODE_R

Bit 4 - RXMODE

pub fn phyrxen(&self) -> PHYRXEN_R

Bit 5 - PHYRXEN

pub fn phyccsel(&self) -> PHYCCSEL_R

Bit 6 - PHYCCSEL

pub fn anasubmode(&self) -> ANASUBMODE_R

Bits 7:8 - ANASUBMODE

pub fn anamode(&self) -> ANAMODE_R

Bit 9 - ANAMODE

pub fn ccenable(&self) -> CCENABLE_R

Bits 10:11 - CCENABLE

pub fn dbatten(&self) -> DBATTEN_R

Bit 15 - DBATTEN

pub fn frsrxen(&self) -> FRSRXEN_R

Bit 16 - FRSRXEN

pub fn frstx(&self) -> FRSTX_R

Bit 17 - FRSTX

pub fn rdch(&self) -> RDCH_R

Bit 18 - RDCH

pub fn cc1tcdis(&self) -> CC1TCDIS_R

Bit 20 - CC1TCDIS

pub fn cc2tcdis(&self) -> CC2TCDIS_R

Bit 21 - CC2TCDIS

impl R<u32, Reg<u32, _IMR>>

pub fn txisie(&self) -> TXISIE_R

Bit 0 - TXISIE

pub fn txmsgdiscie(&self) -> TXMSGDISCIE_R

Bit 1 - TXMSGDISCIE

pub fn txmsgsentie(&self) -> TXMSGSENTIE_R

Bit 2 - TXMSGSENTIE

pub fn txmsgabtie(&self) -> TXMSGABTIE_R

Bit 3 - TXMSGABTIE

pub fn hrstdiscie(&self) -> HRSTDISCIE_R

Bit 4 - HRSTDISCIE

pub fn hrstsentie(&self) -> HRSTSENTIE_R

Bit 5 - HRSTSENTIE

pub fn txundie(&self) -> TXUNDIE_R

Bit 6 - TXUNDIE

pub fn rxneie(&self) -> RXNEIE_R

Bit 8 - RXNEIE

pub fn rxorddetie(&self) -> RXORDDETIE_R

Bit 9 - RXORDDETIE

pub fn rxhrstdetie(&self) -> RXHRSTDETIE_R

Bit 10 - RXHRSTDETIE

pub fn rxovrie(&self) -> RXOVRIE_R

Bit 11 - RXOVRIE

pub fn rxmsgendie(&self) -> RXMSGENDIE_R

Bit 12 - RXMSGENDIE

pub fn typecevt1ie(&self) -> TYPECEVT1IE_R

Bit 14 - TYPECEVT1IE

pub fn typecevt2ie(&self) -> TYPECEVT2IE_R

Bit 15 - TYPECEVT2IE

pub fn frsevtie(&self) -> FRSEVTIE_R

Bit 20 - FRSEVTIE

impl R<u32, Reg<u32, _SR>>

pub fn txis(&self) -> TXIS_R

Bit 0 - TXIS

pub fn txmsgdisc(&self) -> TXMSGDISC_R

Bit 1 - TXMSGDISC

pub fn txmsgsent(&self) -> TXMSGSENT_R

Bit 2 - TXMSGSENT

pub fn txmsgabt(&self) -> TXMSGABT_R

Bit 3 - TXMSGABT

pub fn hrstdisc(&self) -> HRSTDISC_R

Bit 4 - HRSTDISC

pub fn hrstsent(&self) -> HRSTSENT_R

Bit 5 - HRSTSENT

pub fn txund(&self) -> TXUND_R

Bit 6 - TXUND

pub fn rxne(&self) -> RXNE_R

Bit 8 - RXNE

pub fn rxorddet(&self) -> RXORDDET_R

Bit 9 - RXORDDET

pub fn rxhrstdet(&self) -> RXHRSTDET_R

Bit 10 - RXHRSTDET

pub fn rxovr(&self) -> RXOVR_R

Bit 11 - RXOVR

pub fn rxmsgend(&self) -> RXMSGEND_R

Bit 12 - RXMSGEND

pub fn rxerr(&self) -> RXERR_R

Bit 13 - RXERR

pub fn typecevt1(&self) -> TYPECEVT1_R

Bit 14 - TYPECEVT1

pub fn typecevt2(&self) -> TYPECEVT2_R

Bit 15 - TYPECEVT2

pub fn typec_vstate_cc1(&self) -> TYPEC_VSTATE_CC1_R

Bits 16:17 - TYPEC_VSTATE_CC1

pub fn typec_vstate_cc2(&self) -> TYPEC_VSTATE_CC2_R

Bits 18:19 - TYPEC_VSTATE_CC2

pub fn frsevt(&self) -> FRSEVT_R

Bit 20 - FRSEVT

impl R<u32, Reg<u32, _ICR>>

pub fn txmsgdisccf(&self) -> TXMSGDISCCF_R

Bit 1 - TXMSGDISCCF

pub fn txmsgsentcf(&self) -> TXMSGSENTCF_R

Bit 2 - TXMSGSENTCF

pub fn txmsgabtcf(&self) -> TXMSGABTCF_R

Bit 3 - TXMSGABTCF

pub fn hrstdisccf(&self) -> HRSTDISCCF_R

Bit 4 - HRSTDISCCF

pub fn hrstsentcf(&self) -> HRSTSENTCF_R

Bit 5 - HRSTSENTCF

pub fn txundcf(&self) -> TXUNDCF_R

Bit 6 - TXUNDCF

pub fn rxorddetcf(&self) -> RXORDDETCF_R

Bit 9 - RXORDDETCF

pub fn rxhrstdetcf(&self) -> RXHRSTDETCF_R

Bit 10 - RXHRSTDETCF

pub fn rxovrcf(&self) -> RXOVRCF_R

Bit 11 - RXOVRCF

pub fn rxmsgendcf(&self) -> RXMSGENDCF_R

Bit 12 - RXMSGENDCF

pub fn typecevt1cf(&self) -> TYPECEVT1CF_R

Bit 14 - TYPECEVT1CF

pub fn typecevt2cf(&self) -> TYPECEVT2CF_R

Bit 15 - TYPECEVT2CF

pub fn frsevtcf(&self) -> FRSEVTCF_R

Bit 20 - FRSEVTCF

impl R<u32, Reg<u32, _TX_ORDSET>>

pub fn txordset(&self) -> TXORDSET_R

Bits 0:19 - TXORDSET

impl R<u32, Reg<u32, _TX_PAYSZ>>

pub fn txpaysz(&self) -> TXPAYSZ_R

Bits 0:9 - TXPAYSZ

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - TXDATA

impl R<u32, Reg<u32, _RX_ORDSET>>

pub fn rxordset(&self) -> RXORDSET_R

Bits 0:2 - RXORDSET

pub fn rxsop3of4(&self) -> RXSOP3OF4_R

Bit 3 - RXSOP3OF4

pub fn rxsopkinvalid(&self) -> RXSOPKINVALID_R

Bits 4:6 - RXSOPKINVALID

impl R<u32, Reg<u32, _RX_PAYSZ>>

pub fn rxpaysz(&self) -> RXPAYSZ_R

Bits 0:9 - RXPAYSZ

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - RXDATA

impl R<u32, Reg<u32, _RX_ORDEXT1>>

pub fn rxsopx1(&self) -> RXSOPX1_R

Bits 0:19 - RXSOPX1

impl R<u32, Reg<u32, _RX_ORDEXT2>>

pub fn rxsopx2(&self) -> RXSOPX2_R

Bits 0:19 - RXSOPX2

impl R<u32, Reg<u32, _IPVER>>

pub fn ipver(&self) -> IPVER_R

Bits 0:31 - IPVER

impl R<u32, Reg<u32, _IPID>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IPID

impl R<u32, Reg<u32, _MID>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IPID

impl R<u32, Reg<u32, _ISR>>

pub fn down(&self) -> DOWN_R

Bit 6 - Counter direction change up to down

pub fn up(&self) -> UP_R

Bit 5 - Counter direction change down to up

pub fn arrok(&self) -> ARROK_R

Bit 4 - Autoreload register update OK

pub fn cmpok(&self) -> CMPOK_R

Bit 3 - Compare register update OK

pub fn exttrig(&self) -> EXTTRIG_R

Bit 2 - External trigger edge event

pub fn arrm(&self) -> ARRM_R

Bit 1 - Autoreload match

pub fn cmpm(&self) -> CMPM_R

Bit 0 - Compare match

impl R<u32, Reg<u32, _IER>>

pub fn downie(&self) -> DOWNIE_R

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&self) -> UPIE_R

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&self) -> ARROKIE_R

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&self) -> CMPOKIE_R

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&self) -> EXTTRIGIE_R

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&self) -> ARRMIE_R

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&self) -> CMPMIE_R

Bit 0 - Compare match Interrupt Enable

impl R<u32, Reg<u32, _CFGR>>

pub fn enc(&self) -> ENC_R

Bit 24 - Encoder mode enable

pub fn countmode(&self) -> COUNTMODE_R

Bit 23 - counter mode enabled

pub fn preload(&self) -> PRELOAD_R

Bit 22 - Registers update mode

pub fn wavpol(&self) -> WAVPOL_R

Bit 21 - Waveform shape polarity

pub fn wave(&self) -> WAVE_R

Bit 20 - Waveform shape

pub fn timout(&self) -> TIMOUT_R

Bit 19 - Timeout enable

pub fn trigen(&self) -> TRIGEN_R

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&self) -> TRIGSEL_R

Bits 13:15 - Trigger selector

pub fn presc(&self) -> PRESC_R

Bits 9:11 - Clock prescaler

pub fn trgflt(&self) -> TRGFLT_R

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&self) -> CKFLT_R

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&self) -> CKPOL_R

Bits 1:2 - Clock Polarity

pub fn cksel(&self) -> CKSEL_R

Bit 0 - Clock selector

impl R<u32, Reg<u32, _CR>>

pub fn rstare(&self) -> RSTARE_R

Bit 4 - Reset after read enable

pub fn countrst(&self) -> COUNTRST_R

Bit 3 - Counter reset

pub fn cntstrt(&self) -> CNTSTRT_R

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&self) -> SNGSTRT_R

Bit 1 - LPTIM start in single mode

pub fn enable(&self) -> ENABLE_R

Bit 0 - LPTIM Enable

impl R<u32, Reg<u32, _CMP>>

pub fn cmp(&self) -> CMP_R

Bits 0:15 - Compare value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto reload value

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Counter value

impl R<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&self) -> IN2SEL_R

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&self) -> IN1SEL_R

Bits 0:1 - LPTIMx Input 1 selection

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT0

pub fn dedt0(&self) -> DEDT0_R

Bits 16:20 - DEDT0

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr(&self) -> BRR_R

Bits 0:19 - BRR

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn cfg1(&self) -> CFG1_R

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&self) -> CFG2_R

Bits 4:7 - LUART hardware configuration 2

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn cfg1(&self) -> CFG1_R

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&self) -> CFG2_R

Bits 4:7 - LUART hardware configuration 2

pub fn cfg3(&self) -> CFG3_R

Bits 8:11 - LUART hardware configuration 1

pub fn cfg4(&self) -> CFG4_R

Bits 12:15 - LUART hardware configuration 2

pub fn cfg5(&self) -> CFG5_R

Bits 16:19 - LUART hardware configuration 2

pub fn cfg6(&self) -> CFG6_R

Bits 20:23 - LUART hardware configuration 2

pub fn cfg7(&self) -> CFG7_R

Bits 24:27 - LUART hardware configuration 2

pub fn cfg8(&self) -> CFG8_R

Bits 28:31 - LUART hardware configuration 2

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CEC_CR>>

pub fn cecen(&self) -> CECEN_R

Bit 0 - CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.

pub fn txsom(&self) -> TXSOM_R

Bit 1 - Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception

pub fn txeom(&self) -> TXEOM_R

Bit 2 - Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message)

impl R<u32, Reg<u32, _CEC_CFGR>>

pub fn sft(&self) -> SFT_R

Bits 0:2 - Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods

pub fn rxtol(&self) -> RXTOL_R

Bit 3 - Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall

pub fn brestp(&self) -> BRESTP_R

Bit 4 - Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software.

pub fn bregen(&self) -> BREGEN_R

Bit 5 - Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0

pub fn lbpegen(&self) -> LBPEGEN_R

Bit 6 - Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0

pub fn brdnogen(&self) -> BRDNOGEN_R

Bit 7 - Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software.

pub fn sftopt(&self) -> SFTOPT_R

Bit 8 - SFT Option Bit The SFTOPT bit is set and cleared by software.

pub fn oar(&self) -> OAR_R

Bits 16:30 - Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.

pub fn lstn(&self) -> LSTN_R

Bit 31 - Listen mode LSTN bit is set and cleared by software.

impl R<u32, Reg<u32, _CEC_RXDR>>

pub fn rxd(&self) -> RXD_R

Bits 0:7 - Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line.

impl R<u32, Reg<u32, _CEC_ISR>>

pub fn rxbr(&self) -> RXBR_R

Bit 0 - Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1.

pub fn rxend(&self) -> RXEND_R

Bit 1 - End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1.

pub fn rxovr(&self) -> RXOVR_R

Bit 2 - Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1.

pub fn bre(&self) -> BRE_R

Bit 3 - Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1.

pub fn sbpe(&self) -> SBPE_R

Bit 4 - Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1.

pub fn lbpe(&self) -> LBPE_R

Bit 5 - Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1.

pub fn rxacke(&self) -> RXACKE_R

Bit 6 - Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1.

pub fn arblst(&self) -> ARBLST_R

Bit 7 - Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1.

pub fn txbr(&self) -> TXBR_R

Bit 8 - Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1.

pub fn txend(&self) -> TXEND_R

Bit 9 - End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1.

pub fn txudr(&self) -> TXUDR_R

Bit 10 - Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1

pub fn txerr(&self) -> TXERR_R

Bit 11 - Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1.

pub fn txacke(&self) -> TXACKE_R

Bit 12 - Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1.

impl R<u32, Reg<u32, _CEC_IER>>

pub fn rxbrie(&self) -> RXBRIE_R

Bit 0 - Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software.

pub fn rxendie(&self) -> RXENDIE_R

Bit 1 - End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software.

pub fn rxovrie(&self) -> RXOVRIE_R

Bit 2 - Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software.

pub fn breie(&self) -> BREIE_R

Bit 3 - Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software.

pub fn sbpeie(&self) -> SBPEIE_R

Bit 4 - Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software.

pub fn lbpeie(&self) -> LBPEIE_R

Bit 5 - Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software.

pub fn rxackie(&self) -> RXACKIE_R

Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software.

pub fn arblstie(&self) -> ARBLSTIE_R

Bit 7 - Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software.

pub fn txbrie(&self) -> TXBRIE_R

Bit 8 - Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software.

pub fn txendie(&self) -> TXENDIE_R

Bit 9 - Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software.

pub fn txudrie(&self) -> TXUDRIE_R

Bit 10 - Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software.

pub fn txerrie(&self) -> TXERRIE_R

Bit 11 - Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software.

pub fn txackie(&self) -> TXACKIE_R

Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software.

impl R<u32, Reg<u32, _DAC_CR>>

pub fn en1(&self) -> EN1_R

Bit 0 - DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.

pub fn ten1(&self) -> TEN1_R

Bit 1 - DAC channel1 trigger enable

pub fn tsel1(&self) -> TSEL1_R

Bits 2:5 - DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn wave1(&self) -> WAVE1_R

Bits 6:7 - DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn mamp1(&self) -> MAMP1_R

Bits 8:11 - DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen1(&self) -> DMAEN1_R

Bit 12 - DAC channel1 DMA enable This bit is set and cleared by software.

pub fn dmaudrie1(&self) -> DMAUDRIE1_R

Bit 13 - DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.

pub fn cen1(&self) -> CEN1_R

Bit 14 - DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

pub fn en2(&self) -> EN2_R

Bit 16 - DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.

pub fn ten2(&self) -> TEN2_R

Bit 17 - DAC channel2 trigger enable

pub fn tsel2(&self) -> TSEL2_R

Bits 18:21 - DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

pub fn wave2(&self) -> WAVE2_R

Bits 22:23 - DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)

pub fn mamp2(&self) -> MAMP2_R

Bits 24:27 - DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen2(&self) -> DMAEN2_R

Bit 28 - DAC channel2 DMA enable This bit is set and cleared by software.

pub fn dmaudrie2(&self) -> DMAUDRIE2_R

Bit 29 - DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.

pub fn cen2(&self) -> CEN2_R

Bit 30 - DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

impl R<u32, Reg<u32, _DAC_DHR12R1>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl R<u32, Reg<u32, _DAC_DHR12L1>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl R<u32, Reg<u32, _DAC_DHR8R1>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

impl R<u32, Reg<u32, _DAC_DHR12R2>>

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 0:11 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR12L2>>

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 4:15 - DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR8R2>>

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 0:7 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR12RD>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 16:27 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR12LD>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 20:31 - DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR8RD>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 8:15 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DOR1>>

pub fn dacc1dor(&self) -> DACC1DOR_R

Bits 0:11 - DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.

impl R<u32, Reg<u32, _DAC_DOR2>>

pub fn dacc2dor(&self) -> DACC2DOR_R

Bits 0:11 - DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.

impl R<u32, Reg<u32, _DAC_SR>>

pub fn dmaudr1(&self) -> DMAUDR1_R

Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag1(&self) -> CAL_FLAG1_R

Bit 14 - DAC Channel 1 calibration offset status This bit is set and cleared by hardware

pub fn bwst1(&self) -> BWST1_R

Bit 15 - DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).

pub fn dmaudr2(&self) -> DMAUDR2_R

Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag2(&self) -> CAL_FLAG2_R

Bit 30 - DAC Channel 2 calibration offset status This bit is set and cleared by hardware

pub fn bwst2(&self) -> BWST2_R

Bit 31 - DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).

impl R<u32, Reg<u32, _DAC_CCR>>

pub fn otrim1(&self) -> OTRIM1_R

Bits 0:4 - DAC Channel 1 offset trimming value

pub fn otrim2(&self) -> OTRIM2_R

Bits 16:20 - DAC Channel 2 offset trimming value

impl R<u32, Reg<u32, _DAC_MCR>>

pub fn mode1(&self) -> MODE1_R

Bits 0:2 - DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode

pub fn mode2(&self) -> MODE2_R

Bits 16:18 - DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode

impl R<u32, Reg<u32, _DAC_SHSR1>>

pub fn tsample1(&self) -> TSAMPLE1_R

Bits 0:9 - DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.

impl R<u32, Reg<u32, _DAC_SHSR2>>

pub fn tsample2(&self) -> TSAMPLE2_R

Bits 0:9 - DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.

impl R<u32, Reg<u32, _DAC_SHHR>>

pub fn thold1(&self) -> THOLD1_R

Bits 0:9 - DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI

pub fn thold2(&self) -> THOLD2_R

Bits 16:25 - DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI

impl R<u32, Reg<u32, _DAC_SHRR>>

pub fn trefresh1(&self) -> TREFRESH1_R

Bits 0:7 - DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

pub fn trefresh2(&self) -> TREFRESH2_R

Bits 16:23 - DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

impl R<u32, Reg<u32, _IP_HWCFGR0>>

pub fn dual(&self) -> DUAL_R

Bits 0:3 - Dual DAC capability

pub fn lfsr(&self) -> LFSR_R

Bits 4:7 - Pseudonoise wave generation capability

pub fn triangle(&self) -> TRIANGLE_R

Bits 8:11 - Triangle wave generation capability

pub fn sample(&self) -> SAMPLE_R

Bits 12:15 - Sample and hold mode capability

pub fn or_cfg(&self) -> OR_CFG_R

Bits 16:23 - option register bit width

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn pe(&self) -> PE_R

Bit 0 - Peripheral enable

pub fn txie(&self) -> TXIE_R

Bit 1 - TX Interrupt enable

pub fn rxie(&self) -> RXIE_R

Bit 2 - RX Interrupt enable

pub fn addrie(&self) -> ADDRIE_R

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&self) -> NACKIE_R

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&self) -> STOPIE_R

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 7 - Error interrupts enable

pub fn dnf(&self) -> DNF_R

Bits 8:11 - Digital noise filter

pub fn anfoff(&self) -> ANFOFF_R

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 15 - DMA reception requests enable

pub fn sbc(&self) -> SBC_R

Bit 16 - Slave byte control

pub fn nostretch(&self) -> NOSTRETCH_R

Bit 17 - Clock stretching disable

pub fn wupen(&self) -> WUPEN_R

Bit 18 - Wakeup from STOP enable

pub fn gcen(&self) -> GCEN_R

Bit 19 - General call enable

pub fn smbhen(&self) -> SMBHEN_R

Bit 20 - SMBus Host address enable

pub fn smbden(&self) -> SMBDEN_R

Bit 21 - SMBus Device Default address enable

pub fn alerten(&self) -> ALERTEN_R

Bit 22 - SMBUS alert enable

pub fn pecen(&self) -> PECEN_R

Bit 23 - PEC enable

impl R<u32, Reg<u32, _CR2>>

pub fn pecbyte(&self) -> PECBYTE_R

Bit 26 - Packet error checking byte

pub fn autoend(&self) -> AUTOEND_R

Bit 25 - Automatic end mode (master mode)

pub fn reload(&self) -> RELOAD_R

Bit 24 - NBYTES reload mode

pub fn nbytes(&self) -> NBYTES_R

Bits 16:23 - Number of bytes

pub fn nack(&self) -> NACK_R

Bit 15 - NACK generation (slave mode)

pub fn stop(&self) -> STOP_R

Bit 14 - Stop generation (master mode)

pub fn start(&self) -> START_R

Bit 13 - Start generation

pub fn head10r(&self) -> HEAD10R_R

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&self) -> ADD10_R

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&self) -> RD_WRN_R

Bit 10 - Transfer direction (master mode)

pub fn sadd(&self) -> SADD_R

Bits 0:9 - Slave address bit (master mode)

impl R<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&self) -> OA1_0_R

Bit 0 - Interface address

pub fn oa1_7_1(&self) -> OA1_7_1_R

Bits 1:7 - Interface address

pub fn oa1_8_9(&self) -> OA1_8_9_R

Bits 8:9 - Interface address

pub fn oa1mode(&self) -> OA1MODE_R

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&self) -> OA1EN_R

Bit 15 - Own Address 1 enable

impl R<u32, Reg<u32, _OAR2>>

pub fn oa2(&self) -> OA2_R

Bits 1:7 - Interface address

pub fn oa2msk(&self) -> OA2MSK_R

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&self) -> OA2EN_R

Bit 15 - Own Address 2 enable

impl R<u32, Reg<u32, _TIMINGR>>

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler

impl R<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&self) -> TIMEOUTA_R

Bits 0:11 - Bus timeout A

pub fn tidle(&self) -> TIDLE_R

Bit 12 - Idle clock timeout detection

pub fn timouten(&self) -> TIMOUTEN_R

Bit 15 - Clock timeout enable

pub fn timeoutb(&self) -> TIMEOUTB_R

Bits 16:27 - Bus timeout B

pub fn texten(&self) -> TEXTEN_R

Bit 31 - Extended clock timeout enable

impl R<u32, Reg<u32, _ISR>>

pub fn addcode(&self) -> ADDCODE_R

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R

Bit 0 - Transmit data register empty (transmitters)

impl R<u32, Reg<u32, _PECR>>

pub fn pec(&self) -> PEC_R

Bits 0:7 - Packet error checking register

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - 8-bit receive data

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - 8-bit transmit data

impl R<u32, Reg<u32, _TR>>

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _DR>>

pub fn yt(&self) -> YT_R

Bits 20:23 - Year tens in BCD format

pub fn yu(&self) -> YU_R

Bits 16:19 - Year units in BCD format

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _SSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ICSR>>

pub fn alrawf(&self) -> ALRAWF_R

Bit 0 - Alarm A write flag

pub fn alrbwf(&self) -> ALRBWF_R

Bit 1 - Alarm B write flag

pub fn wutwf(&self) -> WUTWF_R

Bit 2 - Wakeup timer write flag

pub fn shpf(&self) -> SHPF_R

Bit 3 - Shift operation pending

pub fn inits(&self) -> INITS_R

Bit 4 - Initialization status flag

pub fn rsf(&self) -> RSF_R

Bit 5 - Registers synchronization flag

pub fn initf(&self) -> INITF_R

Bit 6 - Initialization flag

pub fn init(&self) -> INIT_R

Bit 7 - Initialization mode

pub fn recalpf(&self) -> RECALPF_R

Bit 16 - Recalibration pending Flag

impl R<u32, Reg<u32, _PRER>>

pub fn prediv_a(&self) -> PREDIV_A_R

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&self) -> PREDIV_S_R

Bits 0:14 - Synchronous prescaler factor

impl R<u32, Reg<u32, _WUTR>>

pub fn wut(&self) -> WUT_R

Bits 0:15 - Wakeup auto-reload value bits

impl R<u32, Reg<u32, _CR>>

pub fn wucksel(&self) -> WUCKSEL_R

Bits 0:2 - WUCKSEL

pub fn tsedge(&self) -> TSEDGE_R

Bit 3 - TSEDGE

pub fn refckon(&self) -> REFCKON_R

Bit 4 - REFCKON

pub fn bypshad(&self) -> BYPSHAD_R

Bit 5 - BYPSHAD

pub fn fmt(&self) -> FMT_R

Bit 6 - FMT

pub fn alrae(&self) -> ALRAE_R

Bit 8 - ALRAE

pub fn alrbe(&self) -> ALRBE_R

Bit 9 - ALRBE

pub fn wute(&self) -> WUTE_R

Bit 10 - WUTE

pub fn tse(&self) -> TSE_R

Bit 11 - TSE

pub fn alraie(&self) -> ALRAIE_R

Bit 12 - ALRAIE

pub fn alrbie(&self) -> ALRBIE_R

Bit 13 - ALRBIE

pub fn wutie(&self) -> WUTIE_R

Bit 14 - WUTIE

pub fn tsie(&self) -> TSIE_R

Bit 15 - TSIE

pub fn add1h(&self) -> ADD1H_R

Bit 16 - ADD1H

pub fn sub1h(&self) -> SUB1H_R

Bit 17 - SUB1H

pub fn bkp(&self) -> BKP_R

Bit 18 - BKP

pub fn cosel(&self) -> COSEL_R

Bit 19 - COSEL

pub fn pol(&self) -> POL_R

Bit 20 - POL

pub fn osel(&self) -> OSEL_R

Bits 21:22 - OSEL

pub fn coe(&self) -> COE_R

Bit 23 - COE

pub fn itse(&self) -> ITSE_R

Bit 24 - ITSE

pub fn tampts(&self) -> TAMPTS_R

Bit 25 - TAMPTS

pub fn tampoe(&self) -> TAMPOE_R

Bit 26 - TAMPOE

pub fn tampalrm_pu(&self) -> TAMPALRM_PU_R

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&self) -> TAMPALRM_TYPE_R

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&self) -> OUT2EN_R

Bit 31 - OUT2EN

impl R<u32, Reg<u32, _CALR>>

pub fn calp(&self) -> CALP_R

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&self) -> CALW8_R

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&self) -> CALW16_R

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&self) -> CALM_R

Bits 0:8 - Calibration minus

impl R<u32, Reg<u32, _TSTR>>

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

impl R<u32, Reg<u32, _TSDR>>

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _TSSSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm A date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm A hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm A minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm A seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm B date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm B hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm B minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm B seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _SR>>

pub fn alraf(&self) -> ALRAF_R

Bit 0 - ALRAF

pub fn alrbf(&self) -> ALRBF_R

Bit 1 - ALRBF

pub fn wutf(&self) -> WUTF_R

Bit 2 - WUTF

pub fn tsf(&self) -> TSF_R

Bit 3 - TSF

pub fn tsovf(&self) -> TSOVF_R

Bit 4 - TSOVF

pub fn itsf(&self) -> ITSF_R

Bit 5 - ITSF

impl R<u32, Reg<u32, _MISR>>

pub fn alramf(&self) -> ALRAMF_R

Bit 0 - ALRAMF

pub fn alrbmf(&self) -> ALRBMF_R

Bit 1 - ALRBMF

pub fn wutmf(&self) -> WUTMF_R

Bit 2 - WUTMF

pub fn tsmf(&self) -> TSMF_R

Bit 3 - TSMF

pub fn tsovmf(&self) -> TSOVMF_R

Bit 4 - TSOVMF

pub fn itsmf(&self) -> ITSMF_R

Bit 5 - ITSMF

impl R<u32, Reg<u32, _SCR>>

pub fn calraf(&self) -> CALRAF_R

Bit 0 - CALRAF

pub fn calrbf(&self) -> CALRBF_R

Bit 1 - CALRBF

pub fn cwutf(&self) -> CWUTF_R

Bit 2 - CWUTF

pub fn ctsf(&self) -> CTSF_R

Bit 3 - CTSF

pub fn ctsovf(&self) -> CTSOVF_R

Bit 4 - CTSOVF

pub fn citsf(&self) -> CITSF_R

Bit 5 - CITSF

impl R<u32, Reg<u32, _HWCFGR>>

pub fn alarmb(&self) -> ALARMB_R

Bits 0:3 - ALARMB

pub fn wakeup(&self) -> WAKEUP_R

Bits 4:7 - WAKEUP

pub fn smooth_calib(&self) -> SMOOTH_CALIB_R

Bits 8:11 - SMOOTH_CALIB

pub fn timestamp(&self) -> TIMESTAMP_R

Bits 12:15 - TIMESTAMP

pub fn optionreg_out(&self) -> OPTIONREG_OUT_R

Bits 16:23 - OPTIONREG_OUT

pub fn trust_zone(&self) -> TRUST_ZONE_R

Bits 24:27 - TRUST_ZONE

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _DIER>>

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - CC1S

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - OC1FE

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - OC1PE

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - OC1M

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - OC1CE

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&self) -> ICPCS_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _TISEL>>

pub fn tisel(&self) -> TISEL_R

Bits 0:3 - TI1[0] to TI1[15] input selection

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

impl R<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&self) -> TS_4_3_R

Bits 20:21 - Trigger selection

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&self) -> IC3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt_h(&self) -> CNT_H_R

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&self) -> CNT_L_R

Bits 0:15 - Low counter value

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr_h(&self) -> ARR_H_R

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&self) -> ARR_L_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&self) -> CCR1_H_R

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&self) -> CCR1_L_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&self) -> CCR2_H_R

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&self) -> CCR2_L_R

Bits 0:15 - Low Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&self) -> CCR3_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&self) -> CCR3_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&self) -> CCR4_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&self) -> CCR4_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&self) -> IOCREF_CLR_R

Bit 0 - IOCREF_CLR

impl R<u32, Reg<u32, _AF1>>

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:17 - External trigger source selection

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - TI1SEL

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - TI2SEL

impl R<u32, Reg<u32, _CSR>>

pub fn enable(&self) -> ENABLE_R

Bit 0 - Counter enable

pub fn tickint(&self) -> TICKINT_R

Bit 1 - SysTick exception request enable

pub fn clksource(&self) -> CLKSOURCE_R

Bit 2 - Clock source selection

pub fn countflag(&self) -> COUNTFLAG_R

Bit 16 - COUNTFLAG

impl R<u32, Reg<u32, _RVR>>

pub fn reload(&self) -> RELOAD_R

Bits 0:23 - RELOAD value

impl R<u32, Reg<u32, _CVR>>

pub fn current(&self) -> CURRENT_R

Bits 0:23 - Current counter value

impl R<u32, Reg<u32, _CALIB>>

pub fn tenms(&self) -> TENMS_R

Bits 0:23 - Calibration value

pub fn skew(&self) -> SKEW_R

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&self) -> NOREF_R

Bit 31 - NOREF flag. Reads as zero

impl R<u32, Reg<u32, _PR>>

pub fn pr(&self) -> PR_R

Bits 0:2 - Prescaler divider

impl R<u32, Reg<u32, _RLR>>

pub fn rl(&self) -> RL_R

Bits 0:11 - Watchdog counter reload value

impl R<u32, Reg<u32, _SR>>

pub fn wvu(&self) -> WVU_R

Bit 2 - Watchdog counter window value update

pub fn rvu(&self) -> RVU_R

Bit 1 - Watchdog counter reload value update

pub fn pvu(&self) -> PVU_R

Bit 0 - Watchdog prescaler value update

impl R<u32, Reg<u32, _WINR>>

pub fn win(&self) -> WIN_R

Bits 0:11 - Watchdog counter window value

impl R<u32, Reg<u32, _HWCFGR>>

pub fn window(&self) -> WINDOW_R

Bits 0:3 - Support of Window function

pub fn pr_default(&self) -> PR_DEFAULT_R

Bits 4:7 - Prescaler default value

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR>>

pub fn wdga(&self) -> WDGA_R

Bit 7 - Activation bit

pub fn t(&self) -> T_R

Bits 0:6 - 7-bit counter (MSB to LSB)

impl R<u32, Reg<u32, _CFR>>

pub fn wdgtb(&self) -> WDGTB_R

Bits 11:13 - Timer base

pub fn ewi(&self) -> EWI_R

Bit 9 - Early wakeup interrupt

pub fn w(&self) -> W_R

Bits 0:6 - 7-bit window value

impl R<u32, Reg<u32, _SR>>

pub fn ewif(&self) -> EWIF_R

Bit 0 - Early wakeup interrupt flag

impl R<u32, Reg<u32, _ACR>>

pub fn latency(&self) -> LATENCY_R

Bits 0:2 - Latency

pub fn prften(&self) -> PRFTEN_R

Bit 8 - Prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - Instruction cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - Instruction cache reset

pub fn empty(&self) -> EMPTY_R

Bit 16 - Flash User area empty

pub fn dbg_swen(&self) -> DBG_SWEN_R

Bit 18 - Debug access software enable

impl R<u32, Reg<u32, _SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - Write protected error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn miserr(&self) -> MISERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn optverr(&self) -> OPTVERR_R

Bit 15 - Option and Engineering bits loading validity error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy.

impl R<u32, Reg<u32, _CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - Mass erase

pub fn pnb(&self) -> PNB_R

Bits 3:8 - Page number

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn optstrt(&self) -> OPTSTRT_R

Bit 17 - Options modification start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&self) -> OBL_LAUNCH_R

Bit 27 - Force the option byte loading

pub fn sec_prot(&self) -> SEC_PROT_R

Bit 28 - Securable memory area protection enable

pub fn optlock(&self) -> OPTLOCK_R

Bit 30 - Options Lock

pub fn lock(&self) -> LOCK_R

Bit 31 - FLASH_CR Lock

impl R<u32, Reg<u32, _ECCR>>

pub fn addr_ecc(&self) -> ADDR_ECC_R

Bits 0:13 - ECC fail address

pub fn sysf_ecc(&self) -> SYSF_ECC_R

Bit 20 - ECC fail for Corrected ECC Error or Double ECC Error in info block

pub fn eccie(&self) -> ECCIE_R

Bit 24 - ECC correction interrupt enable

pub fn eccc(&self) -> ECCC_R

Bit 30 - ECC correction

pub fn eccd(&self) -> ECCD_R

Bit 31 - ECC detection

impl R<u32, Reg<u32, _OPTR>>

pub fn rdp(&self) -> RDP_R

Bits 0:7 - Read protection level

pub fn boren(&self) -> BOREN_R

Bit 8 - BOR reset Level

pub fn borf_lev(&self) -> BORF_LEV_R

Bits 9:10 - These bits contain the VDD supply level threshold that activates the reset

pub fn borr_lev(&self) -> BORR_LEV_R

Bits 11:12 - These bits contain the VDD supply level threshold that releases the reset.

pub fn n_rst_stop(&self) -> NRST_STOP_R

Bit 13 - nRST_STOP

pub fn n_rst_stdby(&self) -> NRST_STDBY_R

Bit 14 - nRST_STDBY

pub fn n_rsts_hdw(&self) -> NRSTS_HDW_R

Bit 15 - nRSTS_HDW

pub fn idwg_sw(&self) -> IDWG_SW_R

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&self) -> IWDG_STOP_R

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&self) -> IWDG_STDBY_R

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&self) -> WWDG_SW_R

Bit 19 - Window watchdog selection

pub fn ram_parity_check(&self) -> RAM_PARITY_CHECK_R

Bit 22 - SRAM parity check control

pub fn n_boot_sel(&self) -> NBOOT_SEL_R

Bit 24 - nBOOT_SEL

pub fn n_boot1(&self) -> NBOOT1_R

Bit 25 - Boot configuration

pub fn n_boot0(&self) -> NBOOT0_R

Bit 26 - nBOOT0 option bit

pub fn nrst_mode(&self) -> NRST_MODE_R

Bits 27:28 - NRST_MODE

pub fn irhen(&self) -> IRHEN_R

Bit 29 - Internal reset holder enable bit

impl R<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R

Bits 0:7 - PCROP1A area start offset

impl R<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&self) -> PCROP1A_END_R

Bits 0:7 - PCROP1A area end offset

pub fn pcrop_rdp(&self) -> PCROP_RDP_R

Bit 31 - PCROP area preserved when RDP level decreased

impl R<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&self) -> WRP1A_STRT_R

Bits 0:5 - WRP area A start offset

pub fn wrp1a_end(&self) -> WRP1A_END_R

Bits 16:21 - WRP area A end offset

impl R<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&self) -> WRP1B_STRT_R

Bits 0:5 - WRP area B start offset

pub fn wrp1b_end(&self) -> WRP1B_END_R

Bits 16:21 - WRP area B end offset

impl R<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R

Bits 0:7 - PCROP1B area start offset

impl R<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&self) -> PCROP1B_END_R

Bits 0:7 - PCROP1B area end offset

impl R<u32, Reg<u32, _SECR>>

pub fn sec_size(&self) -> SEC_SIZE_R

Bits 0:6 - Securable memory area size

pub fn boot_lock(&self) -> BOOT_LOCK_R

Bit 16 - used to force boot from user area

impl R<u32, Reg<u32, _IDCODE>>

pub fn dev_id(&self) -> DEV_ID_R

Bits 0:15 - Device Identifier

pub fn rev_id(&self) -> REV_ID_R

Bits 16:31 - Revision Identifier

impl R<u32, Reg<u32, _CR>>

pub fn dbg_stop(&self) -> DBG_STOP_R

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&self) -> DBG_STANDBY_R

Bit 2 - Debug Standby Mode

impl R<u32, Reg<u32, _APB_FZ1>>

pub fn dbg_timer2_stop(&self) -> DBG_TIMER2_STOP_R

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_timer6_stop(&self) -> DBG_TIMER6_STOP_R

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 30 - Clocking of LPTIMER2 counter when the core is halted

pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R

Bit 31 - Clocking of LPTIMER1 counter when the core is halted

impl R<u32, Reg<u32, _APB_FZ2>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - DBG_TIM1_STOP

pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R

Bit 15 - DBG_TIM14_STOP

pub fn dbg_tim15_stop(&self) -> DBG_TIM15_STOP_R

Bit 16 - DBG_TIM15_STOP

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - DBG_TIM16_STOP

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - DBG_TIM17_STOP

impl R<u32, Reg<u32, _CR>>

pub fn hsion(&self) -> HSION_R

Bit 8 - HSI16 clock enable

pub fn hsikeron(&self) -> HSIKERON_R

Bit 9 - HSI16 always enable for peripheral kernels

pub fn hsirdy(&self) -> HSIRDY_R

Bit 10 - HSI16 clock ready flag

pub fn hsidiv(&self) -> HSIDIV_R

Bits 11:13 - HSI16 clock division factor

pub fn hseon(&self) -> HSEON_R

Bit 16 - HSE clock enable

pub fn hserdy(&self) -> HSERDY_R

Bit 17 - HSE clock ready flag

pub fn hsebyp(&self) -> HSEBYP_R

Bit 18 - HSE crystal oscillator bypass

pub fn csson(&self) -> CSSON_R

Bit 19 - Clock security system enable

pub fn pllon(&self) -> PLLON_R

Bit 24 - PLL enable

pub fn pllrdy(&self) -> PLLRDY_R

Bit 25 - PLL clock ready flag

impl R<u32, Reg<u32, _ICSCR>>

pub fn hsical(&self) -> HSICAL_R

Bits 0:7 - HSI16 clock calibration

pub fn hsitrim(&self) -> HSITRIM_R

Bits 8:14 - HSI16 clock trimming

impl R<u32, Reg<u32, _CFGR>>

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&self) -> MCOSEL_R

Bits 24:26 - Microcontroller clock output

pub fn ppre(&self) -> PPRE_R

Bits 12:14 - APB prescaler

pub fn hpre(&self) -> HPRE_R

Bits 8:11 - AHB prescaler

pub fn sws(&self) -> SWS_R

Bits 3:5 - System clock switch status

pub fn sw(&self) -> SW_R

Bits 0:2 - System clock switch

impl R<u32, Reg<u32, _PLLSYSCFGR>>

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - PLL input clock source

pub fn pllm(&self) -> PLLM_R

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&self) -> PLLN_R

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&self) -> PLLREN_R

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output

impl R<u32, Reg<u32, _CIER>>

pub fn lsirdyie(&self) -> LSIRDYIE_R

Bit 0 - LSI ready interrupt enable

pub fn lserdyie(&self) -> LSERDYIE_R

Bit 1 - LSE ready interrupt enable

pub fn hsirdyie(&self) -> HSIRDYIE_R

Bit 3 - HSI ready interrupt enable

pub fn hserdyie(&self) -> HSERDYIE_R

Bit 4 - HSE ready interrupt enable

pub fn pllsysrdyie(&self) -> PLLSYSRDYIE_R

Bit 5 - PLL ready interrupt enable

impl R<u32, Reg<u32, _CIFR>>

pub fn lsirdyf(&self) -> LSIRDYF_R

Bit 0 - LSI ready interrupt flag

pub fn lserdyf(&self) -> LSERDYF_R

Bit 1 - LSE ready interrupt flag

pub fn hsirdyf(&self) -> HSIRDYF_R

Bit 3 - HSI ready interrupt flag

pub fn hserdyf(&self) -> HSERDYF_R

Bit 4 - HSE ready interrupt flag

pub fn pllsysrdyf(&self) -> PLLSYSRDYF_R

Bit 5 - PLL ready interrupt flag

pub fn cssf(&self) -> CSSF_R

Bit 8 - Clock security system interrupt flag

pub fn lsecssf(&self) -> LSECSSF_R

Bit 9 - LSE Clock security system interrupt flag

impl R<u32, Reg<u32, _AHBRSTR>>

pub fn dmarst(&self) -> DMARST_R

Bit 0 - DMA1 reset

pub fn flashrst(&self) -> FLASHRST_R

Bit 8 - FLITF reset

pub fn crcrst(&self) -> CRCRST_R

Bit 12 - CRC reset

pub fn aesrst(&self) -> AESRST_R

Bit 16 - AES hardware accelerator reset

pub fn rngrst(&self) -> RNGRST_R

Bit 18 - Random number generator reset

impl R<u32, Reg<u32, _IOPRSTR>>

pub fn ioparst(&self) -> IOPARST_R

Bit 0 - I/O port A reset

pub fn iopbrst(&self) -> IOPBRST_R

Bit 1 - I/O port B reset

pub fn iopcrst(&self) -> IOPCRST_R

Bit 2 - I/O port C reset

pub fn iopdrst(&self) -> IOPDRST_R

Bit 3 - I/O port D reset

pub fn iopfrst(&self) -> IOPFRST_R

Bit 5 - I/O port F reset

impl R<u32, Reg<u32, _APBRSTR1>>

pub fn tim2rst(&self) -> TIM2RST_R

Bit 0 - TIM2 timer reset

pub fn tim3rst(&self) -> TIM3RST_R

Bit 1 - TIM3 timer reset

pub fn tim6rst(&self) -> TIM6RST_R

Bit 4 - TIM6 timer reset

pub fn tim7rst(&self) -> TIM7RST_R

Bit 5 - TIM7 timer reset

pub fn spi2rst(&self) -> SPI2RST_R

Bit 14 - SPI2 reset

pub fn usart2rst(&self) -> USART2RST_R

Bit 17 - USART2 reset

pub fn usart3rst(&self) -> USART3RST_R

Bit 18 - USART3 reset

pub fn usart4rst(&self) -> USART4RST_R

Bit 19 - USART4 reset

pub fn lpuart1rst(&self) -> LPUART1RST_R

Bit 20 - LPUART1 reset

pub fn i2c1rst(&self) -> I2C1RST_R

Bit 21 - I2C1 reset

pub fn i2c2rst(&self) -> I2C2RST_R

Bit 22 - I2C2 reset

pub fn cecrst(&self) -> CECRST_R

Bit 24 - HDMI CEC reset

pub fn ucpd1rst(&self) -> UCPD1RST_R

Bit 25 - UCPD1 reset

pub fn ucpd2rst(&self) -> UCPD2RST_R

Bit 26 - UCPD2 reset

pub fn dbgrst(&self) -> DBGRST_R

Bit 27 - Debug support reset

pub fn pwrrst(&self) -> PWRRST_R

Bit 28 - Power interface reset

pub fn dac1rst(&self) -> DAC1RST_R

Bit 29 - DAC1 interface reset

pub fn lptim2rst(&self) -> LPTIM2RST_R

Bit 30 - Low Power Timer 2 reset

pub fn lptim1rst(&self) -> LPTIM1RST_R

Bit 31 - Low Power Timer 1 reset

impl R<u32, Reg<u32, _APBRSTR2>>

pub fn syscfgrst(&self) -> SYSCFGRST_R

Bit 0 - SYSCFG, COMP and VREFBUF reset

pub fn tim1rst(&self) -> TIM1RST_R

Bit 11 - TIM1 timer reset

pub fn spi1rst(&self) -> SPI1RST_R

Bit 12 - SPI1 reset

pub fn usart1rst(&self) -> USART1RST_R

Bit 14 - USART1 reset

pub fn tim14rst(&self) -> TIM14RST_R

Bit 15 - TIM14 timer reset

pub fn tim15rst(&self) -> TIM15RST_R

Bit 16 - TIM15 timer reset

pub fn tim16rst(&self) -> TIM16RST_R

Bit 17 - TIM16 timer reset

pub fn tim17rst(&self) -> TIM17RST_R

Bit 18 - TIM17 timer reset

pub fn adcrst(&self) -> ADCRST_R

Bit 20 - ADC reset

impl R<u32, Reg<u32, _IOPENR>>

pub fn iopaen(&self) -> IOPAEN_R

Bit 0 - I/O port A clock enable

pub fn iopben(&self) -> IOPBEN_R

Bit 1 - I/O port B clock enable

pub fn iopcen(&self) -> IOPCEN_R

Bit 2 - I/O port C clock enable

pub fn iopden(&self) -> IOPDEN_R

Bit 3 - I/O port D clock enable

pub fn iopfen(&self) -> IOPFEN_R

Bit 5 - I/O port F clock enable

impl R<u32, Reg<u32, _AHBENR>>

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - DMA clock enable

pub fn flashen(&self) -> FLASHEN_R

Bit 8 - Flash memory interface clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CRC clock enable

pub fn aesen(&self) -> AESEN_R

Bit 16 - AES hardware accelerator

pub fn rngen(&self) -> RNGEN_R

Bit 18 - Random number generator clock enable

impl R<u32, Reg<u32, _APBENR1>>

pub fn tim2en(&self) -> TIM2EN_R

Bit 0 - TIM2 timer clock enable

pub fn tim3en(&self) -> TIM3EN_R

Bit 1 - TIM3 timer clock enable

pub fn tim6en(&self) -> TIM6EN_R

Bit 4 - TIM6 timer clock enable

pub fn tim7en(&self) -> TIM7EN_R

Bit 5 - TIM7 timer clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - RTC APB clock enable

pub fn wwdgen(&self) -> WWDGEN_R

Bit 11 - WWDG clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - SPI2 clock enable

pub fn usart2en(&self) -> USART2EN_R

Bit 17 - USART2 clock enable

pub fn usart3en(&self) -> USART3EN_R

Bit 18 - USART3 clock enable

pub fn usart4en(&self) -> USART4EN_R

Bit 19 - USART4 clock enable

pub fn lpuart1en(&self) -> LPUART1EN_R

Bit 20 - LPUART1 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - I2C1 clock enable

pub fn i2c2en(&self) -> I2C2EN_R

Bit 22 - I2C2 clock enable

pub fn cecen(&self) -> CECEN_R

Bit 24 - HDMI CEC clock enable

pub fn ucpd1en(&self) -> UCPD1EN_R

Bit 25 - UCPD1 clock enable

pub fn ucpd2en(&self) -> UCPD2EN_R

Bit 26 - UCPD2 clock enable

pub fn dbgen(&self) -> DBGEN_R

Bit 27 - Debug support clock enable

pub fn pwren(&self) -> PWREN_R

Bit 28 - Power interface clock enable

pub fn dac1en(&self) -> DAC1EN_R

Bit 29 - DAC1 interface clock enable

pub fn lptim2en(&self) -> LPTIM2EN_R

Bit 30 - LPTIM2 clock enable

pub fn lptim1en(&self) -> LPTIM1EN_R

Bit 31 - LPTIM1 clock enable

impl R<u32, Reg<u32, _APBENR2>>

pub fn syscfgen(&self) -> SYSCFGEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - TIM1 timer clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - SPI1 clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - USART1 clock enable

pub fn tim14en(&self) -> TIM14EN_R

Bit 15 - TIM14 timer clock enable

pub fn tim15en(&self) -> TIM15EN_R

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - TIM16 timer clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 20 - ADC clock enable

impl R<u32, Reg<u32, _IOPSMENR>>

pub fn iopasmen(&self) -> IOPASMEN_R

Bit 0 - I/O port A clock enable during Sleep mode

pub fn iopbsmen(&self) -> IOPBSMEN_R

Bit 1 - I/O port B clock enable during Sleep mode

pub fn iopcsmen(&self) -> IOPCSMEN_R

Bit 2 - I/O port C clock enable during Sleep mode

pub fn iopdsmen(&self) -> IOPDSMEN_R

Bit 3 - I/O port D clock enable during Sleep mode

pub fn iopfsmen(&self) -> IOPFSMEN_R

Bit 5 - I/O port F clock enable during Sleep mode

impl R<u32, Reg<u32, _AHBSMENR>>

pub fn dmasmen(&self) -> DMASMEN_R

Bit 0 - DMA clock enable during Sleep mode

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 8 - Flash memory interface clock enable during Sleep mode

pub fn sramsmen(&self) -> SRAMSMEN_R

Bit 9 - SRAM clock enable during Sleep mode

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CRC clock enable during Sleep mode

pub fn aessmen(&self) -> AESSMEN_R

Bit 16 - AES hardware accelerator clock enable during Sleep mode

pub fn rngsmen(&self) -> RNGSMEN_R

Bit 18 - Random number generator clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR1>>

pub fn tim2smen(&self) -> TIM2SMEN_R

Bit 0 - TIM2 timer clock enable during Sleep mode

pub fn tim3smen(&self) -> TIM3SMEN_R

Bit 1 - TIM3 timer clock enable during Sleep mode

pub fn tim6smen(&self) -> TIM6SMEN_R

Bit 4 - TIM6 timer clock enable during Sleep mode

pub fn tim7smen(&self) -> TIM7SMEN_R

Bit 5 - TIM7 timer clock enable during Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clock enable during Sleep mode

pub fn wwdgsmen(&self) -> WWDGSMEN_R

Bit 11 - WWDG clock enable during Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clock enable during Sleep mode

pub fn usart2smen(&self) -> USART2SMEN_R

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3smen(&self) -> USART3SMEN_R

Bit 18 - USART3 clock enable during Sleep mode

pub fn usart4smen(&self) -> USART4SMEN_R

Bit 19 - USART4 clock enable during Sleep mode

pub fn lpuart1smen(&self) -> LPUART1SMEN_R

Bit 20 - LPUART1 clock enable during Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2smen(&self) -> I2C2SMEN_R

Bit 22 - I2C2 clock enable during Sleep mode

pub fn cecsmen(&self) -> CECSMEN_R

Bit 24 - HDMI CEC clock enable during Sleep mode

pub fn ucpd1smen(&self) -> UCPD1SMEN_R

Bit 25 - UCPD1 clock enable during Sleep mode

pub fn ucpd2smen(&self) -> UCPD2SMEN_R

Bit 26 - UCPD2 clock enable during Sleep mode

pub fn dbgsmen(&self) -> DBGSMEN_R

Bit 27 - Debug support clock enable during Sleep mode

pub fn pwrsmen(&self) -> PWRSMEN_R

Bit 28 - Power interface clock enable during Sleep mode

pub fn dac1smen(&self) -> DAC1SMEN_R

Bit 29 - DAC1 interface clock enable during Sleep mode

pub fn lptim2smen(&self) -> LPTIM2SMEN_R

Bit 30 - Low Power Timer 2 clock enable during Sleep mode

pub fn lptim1smen(&self) -> LPTIM1SMEN_R

Bit 31 - Low Power Timer 1 clock enable during Sleep mode

impl R<u32, Reg<u32, _APBSMENR2>>

pub fn syscfgsmen(&self) -> SYSCFGSMEN_R

Bit 0 - SYSCFG, COMP and VREFBUF clock enable during Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clock enable during Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clock enable during Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1 clock enable during Sleep mode

pub fn tim14smen(&self) -> TIM14SMEN_R

Bit 15 - TIM14 timer clock enable during Sleep mode

pub fn tim15smen(&self) -> TIM15SMEN_R

Bit 16 - TIM15 timer clock enable during Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clock enable during Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM16 timer clock enable during Sleep mode

pub fn adcsmen(&self) -> ADCSMEN_R

Bit 20 - ADC clock enable during Sleep mode

impl R<u32, Reg<u32, _CCIPR>>

pub fn usart1sel(&self) -> USART1SEL_R

Bits 0:1 - USART1 clock source selection

pub fn usart2sel(&self) -> USART2SEL_R

Bits 2:3 - USART2 clock source selection

pub fn cecsel(&self) -> CECSEL_R

Bit 6 - HDMI CEC clock source selection

pub fn lpuart1sel(&self) -> LPUART1SEL_R

Bits 10:11 - LPUART1 clock source selection

pub fn i2c1sel(&self) -> I2C1SEL_R

Bits 12:13 - I2C1 clock source selection

pub fn i2s2sel(&self) -> I2S2SEL_R

Bits 14:15 - I2S1 clock source selection

pub fn lptim1sel(&self) -> LPTIM1SEL_R

Bits 18:19 - LPTIM1 clock source selection

pub fn lptim2sel(&self) -> LPTIM2SEL_R

Bits 20:21 - LPTIM2 clock source selection

pub fn tim1sel(&self) -> TIM1SEL_R

Bit 22 - TIM1 clock source selection

pub fn tim15sel(&self) -> TIM15SEL_R

Bit 24 - TIM15 clock source selection

pub fn rngsel(&self) -> RNGSEL_R

Bits 26:27 - RNG clock source selection

pub fn rngdiv(&self) -> RNGDIV_R

Bits 28:29 - Division factor of RNG clock divider

pub fn adcsel(&self) -> ADCSEL_R

Bits 30:31 - ADCs clock source selection

impl R<u32, Reg<u32, _BDCR>>

pub fn lseon(&self) -> LSEON_R

Bit 0 - LSE oscillator enable

pub fn lserdy(&self) -> LSERDY_R

Bit 1 - LSE oscillator ready

pub fn lsebyp(&self) -> LSEBYP_R

Bit 2 - LSE oscillator bypass

pub fn lsedrv(&self) -> LSEDRV_R

Bits 3:4 - LSE oscillator drive capability

pub fn lsecsson(&self) -> LSECSSON_R

Bit 5 - CSS on LSE enable

pub fn lsecssd(&self) -> LSECSSD_R

Bit 6 - CSS on LSE failure Detection

pub fn rtcsel(&self) -> RTCSEL_R

Bits 8:9 - RTC clock source selection

pub fn rtcen(&self) -> RTCEN_R

Bit 15 - RTC clock enable

pub fn bdrst(&self) -> BDRST_R

Bit 16 - RTC domain software reset

pub fn lscoen(&self) -> LSCOEN_R

Bit 24 - Low-speed clock output (LSCO) enable

pub fn lscosel(&self) -> LSCOSEL_R

Bit 25 - Low-speed clock output selection

impl R<u32, Reg<u32, _CSR>>

pub fn lsion(&self) -> LSION_R

Bit 0 - LSI oscillator enable

pub fn lsirdy(&self) -> LSIRDY_R

Bit 1 - LSI oscillator ready

pub fn rmvf(&self) -> RMVF_R

Bit 23 - Remove reset flags

pub fn oblrstf(&self) -> OBLRSTF_R

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&self) -> PINRSTF_R

Bit 26 - Pin reset flag

pub fn pwrrstf(&self) -> PWRRSTF_R

Bit 27 - BOR or POR/PDR flag

pub fn sftrstf(&self) -> SFTRSTF_R

Bit 28 - Software reset flag

pub fn iwdgrstf(&self) -> IWDGRSTF_R

Bit 29 - Independent window watchdog reset flag

pub fn wwdgrstf(&self) -> WWDGRSTF_R

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&self) -> LPWRRSTF_R

Bit 31 - Low-power reset flag

impl R<u32, Reg<u32, _CR1>>

pub fn lpr(&self) -> LPR_R

Bit 14 - Low-power run

pub fn vos(&self) -> VOS_R

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&self) -> DBP_R

Bit 8 - Disable backup domain write protection

pub fn fpd_lpslp(&self) -> FPD_LPSLP_R

Bit 5 - Flash memory powered down during Low-power sleep mode

pub fn fpd_lprun(&self) -> FPD_LPRUN_R

Bit 4 - Flash memory powered down during Low-power run mode

pub fn fpd_stop(&self) -> FPD_STOP_R

Bit 3 - Flash memory powered down during Stop mode

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection

impl R<u32, Reg<u32, _CR2>>

pub fn pvde(&self) -> PVDE_R

Bit 0 - Power voltage detector enable

pub fn pvdft(&self) -> PVDFT_R

Bits 1:3 - Power voltage detector falling threshold selection

pub fn pvdrt(&self) -> PVDRT_R

Bits 4:6 - Power voltage detector rising threshold selection

impl R<u32, Reg<u32, _CR3>>

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable WKUP5 wakeup pin

pub fn ewup6(&self) -> EWUP6_R

Bit 5 - Enable WKUP6 wakeup pin

pub fn rrs(&self) -> RRS_R

Bit 8 - SRAM retention in Standby mode

pub fn ulpen(&self) -> ULPEN_R

Bit 9 - Enable the periodical sampling mode for PDR detection

pub fn apc(&self) -> APC_R

Bit 10 - Apply pull-up and pull-down configuration

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line

impl R<u32, Reg<u32, _CR4>>

pub fn wp1(&self) -> WP1_R

Bit 0 - Wakeup pin WKUP1 polarity

pub fn wp2(&self) -> WP2_R

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp4(&self) -> WP4_R

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp5(&self) -> WP5_R

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp6(&self) -> WP6_R

Bit 5 - WKUP6 wakeup pin polarity

pub fn vbe(&self) -> VBE_R

Bit 8 - VBAT battery charging enable

pub fn vbrs(&self) -> VBRS_R

Bit 9 - VBAT battery charging resistor selection

impl R<u32, Reg<u32, _SR1>>

pub fn wuf1(&self) -> WUF1_R

Bit 0 - Wakeup flag 1

pub fn wuf2(&self) -> WUF2_R

Bit 1 - Wakeup flag 2

pub fn wuf4(&self) -> WUF4_R

Bit 3 - Wakeup flag 4

pub fn wuf5(&self) -> WUF5_R

Bit 4 - Wakeup flag 5

pub fn wuf6(&self) -> WUF6_R

Bit 5 - Wakeup flag 6

pub fn sbf(&self) -> SBF_R

Bit 8 - Standby flag

pub fn wufi(&self) -> WUFI_R

Bit 15 - Wakeup flag internal

impl R<u32, Reg<u32, _SR2>>

pub fn pvdo(&self) -> PVDO_R

Bit 11 - Power voltage detector output

pub fn vosf(&self) -> VOSF_R

Bit 10 - Voltage scaling flag

pub fn reglpf(&self) -> REGLPF_R

Bit 9 - Low-power regulator flag

pub fn reglps(&self) -> REGLPS_R

Bit 8 - Low-power regulator started

pub fn flash_rdy(&self) -> FLASH_RDY_R

Bit 7 - Flash ready flag

impl R<u32, Reg<u32, _PUCRA>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port A pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRA>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port A pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRB>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port B pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRB>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port B pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRC>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port C pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRC>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port C pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRD>>

pub fn pu9(&self) -> PU9_R

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port D pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRD>>

pub fn pd9(&self) -> PD9_R

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port D pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRF>>

pub fn pu2(&self) -> PU2_R

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port F pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRF>>

pub fn pd2(&self) -> PD2_R

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port F pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _CR>>

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

impl R<u32, Reg<u32, _NDTR>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _PAR>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _MAR>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _ISR>>

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel 1 global interrupt flag

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel 1 transfer complete flag

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel 1 half transfer flag

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel 1 transfer error flag

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel 2 global interrupt flag

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel 2 transfer complete flag

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel 2 half transfer flag

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel 2 transfer error flag

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel 3 global interrupt flag

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel 3 transfer complete flag

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel 3 half transfer flag

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel 3 transfer error flag

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel 4 global interrupt flag

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel 4 transfer complete flag

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel 4 half transfer flag

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel 4 transfer error flag

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel 5 global interrupt flag

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel 5 transfer complete flag

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel 5 half transfer flag

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel 5 transfer error flag

pub fn gif6(&self) -> GIF6_R

Bit 20 - Channel 6 global interrupt flag

pub fn tcif6(&self) -> TCIF6_R

Bit 21 - Channel 6 transfer complete flag

pub fn htif6(&self) -> HTIF6_R

Bit 22 - Channel 6 half transfer flag

pub fn teif6(&self) -> TEIF6_R

Bit 23 - Channel 6 transfer error flag

pub fn gif7(&self) -> GIF7_R

Bit 24 - Channel 7 global interrupt flag

pub fn tcif7(&self) -> TCIF7_R

Bit 25 - Channel 7 transfer complete flag

pub fn htif7(&self) -> HTIF7_R

Bit 26 - Channel 7 half transfer flag

pub fn teif7(&self) -> TEIF7_R

Bit 27 - Channel 7 transfer error flag

impl R<u32, Reg<u32, _DMAMUX_C0CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C1CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C2CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C3CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C4CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C5CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_C6CR>>

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - Input DMA request line selected

pub fn soie(&self) -> SOIE_R

Bit 8 - Interrupt enable at synchronization event overrun

pub fn ege(&self) -> EGE_R

Bit 9 - Event generation enable/disable

pub fn se(&self) -> SE_R

Bit 16 - Synchronous operating mode enable/disable

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Synchronization event type selector Defines the synchronization event on the selected synchronization input:

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - Synchronization input selected

impl R<u32, Reg<u32, _DMAMUX_RG0CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG1CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG2CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RG3CR>>

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - DMA request trigger input selected

pub fn oie(&self) -> OIE_R

Bit 8 - Interrupt enable at trigger event overrun

pub fn ge(&self) -> GE_R

Bit 16 - DMA request generator channel enable/disable

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.

impl R<u32, Reg<u32, _DMAMUX_RGSR>>

pub fn of(&self) -> OF_R

Bits 0:3 - Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.

impl R<u32, Reg<u32, _DMAMUX_CSR>>

pub fn sof(&self) -> SOF_R

Bits 0:6 - Synchronization overrun event flag

impl R<u32, Reg<u32, _DMAMUX_SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size identification

impl R<u32, Reg<u32, _DMAMUX_IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - IP identification

impl R<u32, Reg<u32, _DMAMUX_VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor IP revision

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major IP revision

impl R<u32, Reg<u32, _DMAMUX_HWCFGR1>>

pub fn num_dma_streams(&self) -> NUM_DMA_STREAMS_R

Bits 0:7 - number of DMA request line multiplexer (output) channels

pub fn num_dma_periph_req(&self) -> NUM_DMA_PERIPH_REQ_R

Bits 8:15 - number of DMA request lines from peripherals

pub fn num_dma_trig(&self) -> NUM_DMA_TRIG_R

Bits 16:23 - number of synchronization inputs

pub fn num_dma_reqgen(&self) -> NUM_DMA_REQGEN_R

Bits 24:31 - number of DMA request generator channels

impl R<u32, Reg<u32, _DMAMUX_HWCFGR2>>

pub fn num_dma_ext_req(&self) -> NUM_DMA_EXT_REQ_R

Bits 0:7 - Number of DMA request trigger inputs

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _CR>>

pub fn npblb(&self) -> NPBLB_R

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&self) -> KEYSIZE_R

Bit 18 - Key size selection

pub fn chmod2(&self) -> CHMOD2_R

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&self) -> GCMPH_R

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&self) -> DMAOUTEN_R

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&self) -> DMAINEN_R

Bit 11 - Enable DMA management of data input phase

pub fn errie(&self) -> ERRIE_R

Bit 10 - Error interrupt enable

pub fn ccfie(&self) -> CCFIE_R

Bit 9 - CCF flag interrupt enable

pub fn errc(&self) -> ERRC_R

Bit 8 - Error clear

pub fn ccfc(&self) -> CCFC_R

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&self) -> CHMOD10_R

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&self) -> MODE_R

Bits 3:4 - AES operating mode

pub fn datatype(&self) -> DATATYPE_R

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&self) -> EN_R

Bit 0 - AES enable

impl R<u32, Reg<u32, _SR>>

pub fn busy(&self) -> BUSY_R

Bit 3 - Busy flag

pub fn wrerr(&self) -> WRERR_R

Bit 2 - Write error flag

pub fn rderr(&self) -> RDERR_R

Bit 1 - Read error flag

pub fn ccf(&self) -> CCF_R

Bit 0 - Computation complete flag

impl R<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&self) -> AES_DINR_R

Bits 0:31 - Data Input Register

impl R<u32, Reg<u32, _DOUTR>>

pub fn aes_doutr(&self) -> AES_DOUTR_R

Bits 0:31 - Data output register

impl R<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&self) -> AES_KEYR0_R

Bits 0:31 - Data Output Register (LSB key [31:0])

impl R<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&self) -> AES_KEYR1_R

Bits 0:31 - AES key register (key [63:32])

impl R<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&self) -> AES_KEYR2_R

Bits 0:31 - AES key register (key [95:64])

impl R<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&self) -> AES_KEYR3_R

Bits 0:31 - AES key register (MSB key [127:96])

impl R<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&self) -> AES_IVR0_R

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl R<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&self) -> AES_IVR1_R

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl R<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&self) -> AES_IVR2_R

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl R<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&self) -> AES_IVR3_R

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl R<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&self) -> AES_KEYR4_R

Bits 0:31 - AES key register (MSB key [159:128])

impl R<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&self) -> AES_KEYR5_R

Bits 0:31 - AES key register (MSB key [191:160])

impl R<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&self) -> AES_KEYR6_R

Bits 0:31 - AES key register (MSB key [223:192])

impl R<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&self) -> AES_KEYR7_R

Bits 0:31 - AES key register (MSB key [255:224])

impl R<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&self) -> AES_SUSP0R_R

Bits 0:31 - AES suspend register 0

impl R<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&self) -> AES_SUSP1R_R

Bits 0:31 - AES suspend register 1

impl R<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&self) -> AES_SUSP2R_R

Bits 0:31 - AES suspend register 2

impl R<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&self) -> AES_SUSP3R_R

Bits 0:31 - AES suspend register 3

impl R<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&self) -> AES_SUSP4R_R

Bits 0:31 - AES suspend register 4

impl R<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&self) -> AES_SUSP5R_R

Bits 0:31 - AES suspend register 5

impl R<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&self) -> AES_SUSP6R_R

Bits 0:31 - AES suspend register 6

impl R<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&self) -> AES_SUSP7R_R

Bits 0:31 - AES suspend register 7

impl R<u32, Reg<u32, _HWCFR>>

pub fn cfg4(&self) -> CFG4_R

Bits 12:15 - HW Generic 4

pub fn cfg3(&self) -> CFG3_R

Bits 8:11 - HW Generic 3

pub fn cfg2(&self) -> CFG2_R

Bits 4:7 - HW Generic 2

pub fn cfg1(&self) -> CFG1_R

Bits 0:3 - HW Generic 1

impl R<u32, Reg<u32, _VERR>>

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major revision

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor revision

impl R<u32, Reg<u32, _IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Identification code

impl R<u32, Reg<u32, _SIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Size Identification code

impl R<u32, Reg<u32, _CR>>

pub fn rngen(&self) -> RNGEN_R

Bit 2 - Random number generator enable

pub fn ie(&self) -> IE_R

Bit 3 - Interrupt enable

pub fn ced(&self) -> CED_R

Bit 5 - Clock error detection

pub fn byp(&self) -> BYP_R

Bit 6 - Bypass mode enable

impl R<u32, Reg<u32, _SR>>

pub fn seis(&self) -> SEIS_R

Bit 6 - Seed error interrupt status

pub fn ceis(&self) -> CEIS_R

Bit 5 - Clock error interrupt status

pub fn secs(&self) -> SECS_R

Bit 2 - Seed error current status

pub fn cecs(&self) -> CECS_R

Bit 1 - Clock error current status

pub fn drdy(&self) -> DRDY_R

Bit 0 - Data ready

impl R<u32, Reg<u32, _DR>>

pub fn rndata(&self) -> RNDATA_R

Bits 0:31 - Random data

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:31 - Data register bits

impl R<u32, Reg<u32, _IDR>>

pub fn idr(&self) -> IDR_R

Bits 0:31 - General-purpose 32-bit data register bits

impl R<u32, Reg<u32, _CR>>

pub fn rev_out(&self) -> REV_OUT_R

Bit 7 - Reverse output data

pub fn rev_in(&self) -> REV_IN_R

Bits 5:6 - Reverse input data

pub fn polysize(&self) -> POLYSIZE_R

Bits 3:4 - Polynomial size

impl R<u32, Reg<u32, _INIT>>

pub fn crc_init(&self) -> CRC_INIT_R

Bits 0:31 - Programmable initial CRC value

impl R<u32, Reg<u32, _POL>>

pub fn pol(&self) -> POL_R

Bits 0:31 - Programmable polynomial

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _RTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&self) -> TR17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&self) -> TR18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, TR0_A>

pub fn variant(&self) -> TR0_A

Get enumerated values variant

pub fn is_disabled(&self) -> bool

Checks if the value of the field is DISABLED

pub fn is_enabled(&self) -> bool

Checks if the value of the field is ENABLED

impl R<u32, Reg<u32, _FTSR1>>

pub fn tr0(&self) -> TR0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn tr1(&self) -> TR1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn tr2(&self) -> TR2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn tr3(&self) -> TR3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn tr4(&self) -> TR4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn tr5(&self) -> TR5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn tr6(&self) -> TR6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn tr7(&self) -> TR7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn tr8(&self) -> TR8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn tr9(&self) -> TR9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn tr10(&self) -> TR10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn tr11(&self) -> TR11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn tr12(&self) -> TR12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn tr13(&self) -> TR13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn tr14(&self) -> TR14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn tr15(&self) -> TR15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn tr16(&self) -> TR16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn tr17(&self) -> TR17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn tr18(&self) -> TR18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, SWIER0_A>

pub fn variant(&self) -> Variant<bool, SWIER0_A>

Get enumerated values variant

pub fn is_pend(&self) -> bool

Checks if the value of the field is PEND

impl R<u32, Reg<u32, _SWIER1>>

pub fn swier0(&self) -> SWIER0_R

Bit 0 - Rising trigger event configuration bit of Configurable Event input

pub fn swier1(&self) -> SWIER1_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn swier2(&self) -> SWIER2_R

Bit 2 - Rising trigger event configuration bit of Configurable Event input

pub fn swier3(&self) -> SWIER3_R

Bit 3 - Rising trigger event configuration bit of Configurable Event input

pub fn swier4(&self) -> SWIER4_R

Bit 4 - Rising trigger event configuration bit of Configurable Event input

pub fn swier5(&self) -> SWIER5_R

Bit 5 - Rising trigger event configuration bit of Configurable Event input

pub fn swier6(&self) -> SWIER6_R

Bit 6 - Rising trigger event configuration bit of Configurable Event input

pub fn swier7(&self) -> SWIER7_R

Bit 7 - Rising trigger event configuration bit of Configurable Event input

pub fn swier8(&self) -> SWIER8_R

Bit 8 - Rising trigger event configuration bit of Configurable Event input

pub fn swier9(&self) -> SWIER9_R

Bit 9 - Rising trigger event configuration bit of Configurable Event input

pub fn swier10(&self) -> SWIER10_R

Bit 10 - Rising trigger event configuration bit of Configurable Event input

pub fn swier11(&self) -> SWIER11_R

Bit 11 - Rising trigger event configuration bit of Configurable Event input

pub fn swier12(&self) -> SWIER12_R

Bit 12 - Rising trigger event configuration bit of Configurable Event input

pub fn swier13(&self) -> SWIER13_R

Bit 13 - Rising trigger event configuration bit of Configurable Event input

pub fn swier14(&self) -> SWIER14_R

Bit 14 - Rising trigger event configuration bit of Configurable Event input

pub fn swier15(&self) -> SWIER15_R

Bit 15 - Rising trigger event configuration bit of Configurable Event input

pub fn swier16(&self) -> SWIER16_R

Bit 16 - Rising trigger event configuration bit of Configurable Event input

pub fn swier17(&self) -> SWIER17_R

Bit 17 - Rising trigger event configuration bit of Configurable Event input

pub fn swier18(&self) -> SWIER18_R

Bit 18 - Rising trigger event configuration bit of Configurable Event input

impl R<bool, RPIF0_A>

pub fn variant(&self) -> RPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _RPR1>>

pub fn rpif0(&self) -> RPIF0_R

Bit 0 - configurable event inputs x rising edge Pending bit.

pub fn rpif1(&self) -> RPIF1_R

Bit 1 - configurable event inputs x rising edge Pending bit.

pub fn rpif2(&self) -> RPIF2_R

Bit 2 - configurable event inputs x rising edge Pending bit.

pub fn rpif3(&self) -> RPIF3_R

Bit 3 - configurable event inputs x rising edge Pending bit.

pub fn rpif4(&self) -> RPIF4_R

Bit 4 - configurable event inputs x rising edge Pending bit.

pub fn rpif5(&self) -> RPIF5_R

Bit 5 - configurable event inputs x rising edge Pending bit

pub fn rpif6(&self) -> RPIF6_R

Bit 6 - configurable event inputs x rising edge Pending bit.

pub fn rpif7(&self) -> RPIF7_R

Bit 7 - configurable event inputs x rising edge Pending bit.

pub fn rpif8(&self) -> RPIF8_R

Bit 8 - configurable event inputs x rising edge Pending bit.

pub fn rpif9(&self) -> RPIF9_R

Bit 9 - configurable event inputs x rising edge Pending bit.

pub fn rpif10(&self) -> RPIF10_R

Bit 10 - configurable event inputs x rising edge Pending bit.

pub fn rpif11(&self) -> RPIF11_R

Bit 11 - configurable event inputs x rising edge Pending bit.

pub fn rpif12(&self) -> RPIF12_R

Bit 12 - configurable event inputs x rising edge Pending bit.

pub fn rpif13(&self) -> RPIF13_R

Bit 13 - configurable event inputs x rising edge Pending bit.

pub fn rpif14(&self) -> RPIF14_R

Bit 14 - configurable event inputs x rising edge Pending bit.

pub fn rpif15(&self) -> RPIF15_R

Bit 15 - configurable event inputs x rising edge Pending bit.

pub fn rpif16(&self) -> RPIF16_R

Bit 16 - configurable event inputs x rising edge Pending bit.

pub fn rpif17(&self) -> RPIF17_R

Bit 17 - configurable event inputs x rising edge Pending bit.

pub fn rpif18(&self) -> RPIF18_R

Bit 18 - configurable event inputs x rising edge Pending bit.

impl R<bool, FPIF0_A>

pub fn variant(&self) -> FPIF0_A

Get enumerated values variant

pub fn is_not_pending(&self) -> bool

Checks if the value of the field is NOTPENDING

pub fn is_pending(&self) -> bool

Checks if the value of the field is PENDING

impl R<u32, Reg<u32, _FPR1>>

pub fn fpif0(&self) -> FPIF0_R

Bit 0 - configurable event inputs x falling edge pending bit.

pub fn fpif1(&self) -> FPIF1_R

Bit 1 - configurable event inputs x falling edge pending bit.

pub fn fpif2(&self) -> FPIF2_R

Bit 2 - configurable event inputs x falling edge pending bit.

pub fn fpif3(&self) -> FPIF3_R

Bit 3 - configurable event inputs x falling edge pending bit.

pub fn fpif4(&self) -> FPIF4_R

Bit 4 - configurable event inputs x falling edge pending bit.

pub fn fpif5(&self) -> FPIF5_R

Bit 5 - configurable event inputs x falling edge pending bit.

pub fn fpif6(&self) -> FPIF6_R

Bit 6 - configurable event inputs x falling edge pending bit.

pub fn fpif7(&self) -> FPIF7_R

Bit 7 - configurable event inputs x falling edge pending bit.

pub fn fpif8(&self) -> FPIF8_R

Bit 8 - configurable event inputs x falling edge pending bit.

pub fn fpif9(&self) -> FPIF9_R

Bit 9 - configurable event inputs x falling edge pending bit.

pub fn fpif10(&self) -> FPIF10_R

Bit 10 - configurable event inputs x falling edge pending bit.

pub fn fpif11(&self) -> FPIF11_R

Bit 11 - configurable event inputs x falling edge pending bit.

pub fn fpif12(&self) -> FPIF12_R

Bit 12 - configurable event inputs x falling edge pending bit.

pub fn fpif13(&self) -> FPIF13_R

Bit 13 - configurable event inputs x falling edge pending bit.

pub fn fpif14(&self) -> FPIF14_R

Bit 14 - configurable event inputs x falling edge pending bit.

pub fn fpif15(&self) -> FPIF15_R

Bit 15 - configurable event inputs x falling edge pending bit.

pub fn fpif16(&self) -> FPIF16_R

Bit 16 - configurable event inputs x falling edge pending bit.

pub fn fpif17(&self) -> FPIF17_R

Bit 17 - configurable event inputs x falling edge pending bit.

pub fn fpif18(&self) -> FPIF18_R

Bit 18 - configurable event inputs x falling edge pending bit.

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR1>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR2>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR3>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<u8, EXTI0_7_A>

pub fn variant(&self) -> Variant<u8, EXTI0_7_A>

Get enumerated values variant

pub fn is_pa(&self) -> bool

Checks if the value of the field is PA

pub fn is_pb(&self) -> bool

Checks if the value of the field is PB

pub fn is_pc(&self) -> bool

Checks if the value of the field is PC

pub fn is_pd(&self) -> bool

Checks if the value of the field is PD

pub fn is_pf(&self) -> bool

Checks if the value of the field is PF

impl R<u32, Reg<u32, _EXTICR4>>

pub fn exti0_7(&self) -> EXTI0_7_R

Bits 0:7 - GPIO port selection

pub fn exti8_15(&self) -> EXTI8_15_R

Bits 8:15 - GPIO port selection

pub fn exti16_23(&self) -> EXTI16_23_R

Bits 16:23 - GPIO port selection

pub fn exti24_31(&self) -> EXTI24_31_R

Bits 24:31 - GPIO port selection

impl R<bool, IM0_A>

pub fn variant(&self) -> IM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR1>>

pub fn im0(&self) -> IM0_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im1(&self) -> IM1_R

Bit 1 - CPU wakeup with interrupt mask on event input

pub fn im2(&self) -> IM2_R

Bit 2 - CPU wakeup with interrupt mask on event input

pub fn im3(&self) -> IM3_R

Bit 3 - CPU wakeup with interrupt mask on event input

pub fn im4(&self) -> IM4_R

Bit 4 - CPU wakeup with interrupt mask on event input

pub fn im5(&self) -> IM5_R

Bit 5 - CPU wakeup with interrupt mask on event input

pub fn im6(&self) -> IM6_R

Bit 6 - CPU wakeup with interrupt mask on event input

pub fn im7(&self) -> IM7_R

Bit 7 - CPU wakeup with interrupt mask on event input

pub fn im8(&self) -> IM8_R

Bit 8 - CPU wakeup with interrupt mask on event input

pub fn im9(&self) -> IM9_R

Bit 9 - CPU wakeup with interrupt mask on event input

pub fn im10(&self) -> IM10_R

Bit 10 - CPU wakeup with interrupt mask on event input

pub fn im11(&self) -> IM11_R

Bit 11 - CPU wakeup with interrupt mask on event input

pub fn im12(&self) -> IM12_R

Bit 12 - CPU wakeup with interrupt mask on event input

pub fn im13(&self) -> IM13_R

Bit 13 - CPU wakeup with interrupt mask on event input

pub fn im14(&self) -> IM14_R

Bit 14 - CPU wakeup with interrupt mask on event input

pub fn im15(&self) -> IM15_R

Bit 15 - CPU wakeup with interrupt mask on event input

pub fn im16(&self) -> IM16_R

Bit 16 - CPU wakeup with interrupt mask on event input

pub fn im17(&self) -> IM17_R

Bit 17 - CPU wakeup with interrupt mask on event input

pub fn im18(&self) -> IM18_R

Bit 18 - CPU wakeup with interrupt mask on event input

pub fn im19(&self) -> IM19_R

Bit 19 - CPU wakeup with interrupt mask on event input

pub fn im20(&self) -> IM20_R

Bit 20 - CPU wakeup with interrupt mask on event input

pub fn im21(&self) -> IM21_R

Bit 21 - CPU wakeup with interrupt mask on event input

pub fn im22(&self) -> IM22_R

Bit 22 - CPU wakeup with interrupt mask on event input

pub fn im23(&self) -> IM23_R

Bit 23 - CPU wakeup with interrupt mask on event input

pub fn im24(&self) -> IM24_R

Bit 24 - CPU wakeup with interrupt mask on event input

pub fn im25(&self) -> IM25_R

Bit 25 - CPU wakeup with interrupt mask on event input

pub fn im26(&self) -> IM26_R

Bit 26 - CPU wakeup with interrupt mask on event input

pub fn im27(&self) -> IM27_R

Bit 27 - CPU wakeup with interrupt mask on event input

pub fn im28(&self) -> IM28_R

Bit 28 - CPU wakeup with interrupt mask on event input

pub fn im29(&self) -> IM29_R

Bit 29 - CPU wakeup with interrupt mask on event input

pub fn im30(&self) -> IM30_R

Bit 30 - CPU wakeup with interrupt mask on event input

pub fn im31(&self) -> IM31_R

Bit 31 - CPU wakeup with interrupt mask on event input

impl R<bool, EM0_A>

pub fn variant(&self) -> EM0_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR1>>

pub fn em0(&self) -> EM0_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em1(&self) -> EM1_R

Bit 1 - CPU wakeup with event mask on event input

pub fn em2(&self) -> EM2_R

Bit 2 - CPU wakeup with event mask on event input

pub fn em3(&self) -> EM3_R

Bit 3 - CPU wakeup with event mask on event input

pub fn em4(&self) -> EM4_R

Bit 4 - CPU wakeup with event mask on event input

pub fn em5(&self) -> EM5_R

Bit 5 - CPU wakeup with event mask on event input

pub fn em6(&self) -> EM6_R

Bit 6 - CPU wakeup with event mask on event input

pub fn em7(&self) -> EM7_R

Bit 7 - CPU wakeup with event mask on event input

pub fn em8(&self) -> EM8_R

Bit 8 - CPU wakeup with event mask on event input

pub fn em9(&self) -> EM9_R

Bit 9 - CPU wakeup with event mask on event input

pub fn em10(&self) -> EM10_R

Bit 10 - CPU wakeup with event mask on event input

pub fn em11(&self) -> EM11_R

Bit 11 - CPU wakeup with event mask on event input

pub fn em12(&self) -> EM12_R

Bit 12 - CPU wakeup with event mask on event input

pub fn em13(&self) -> EM13_R

Bit 13 - CPU wakeup with event mask on event input

pub fn em14(&self) -> EM14_R

Bit 14 - CPU wakeup with event mask on event input

pub fn em15(&self) -> EM15_R

Bit 15 - CPU wakeup with event mask on event input

pub fn em16(&self) -> EM16_R

Bit 16 - CPU wakeup with event mask on event input

pub fn em17(&self) -> EM17_R

Bit 17 - CPU wakeup with event mask on event input

pub fn em18(&self) -> EM18_R

Bit 18 - CPU wakeup with event mask on event input

pub fn em19(&self) -> EM19_R

Bit 19 - CPU wakeup with event mask on event input

pub fn em21(&self) -> EM21_R

Bit 21 - CPU wakeup with event mask on event input

pub fn em23(&self) -> EM23_R

Bit 23 - CPU wakeup with event mask on event input

pub fn em25(&self) -> EM25_R

Bit 25 - CPU wakeup with event mask on event input

pub fn em26(&self) -> EM26_R

Bit 26 - CPU wakeup with event mask on event input

pub fn em27(&self) -> EM27_R

Bit 27 - CPU wakeup with event mask on event input

pub fn em28(&self) -> EM28_R

Bit 28 - CPU wakeup with event mask on event input

pub fn em29(&self) -> EM29_R

Bit 29 - CPU wakeup with event mask on event input

pub fn em30(&self) -> EM30_R

Bit 30 - CPU wakeup with event mask on event input

pub fn em31(&self) -> EM31_R

Bit 31 - CPU wakeup with event mask on event input

impl R<bool, IM32_A>

pub fn variant(&self) -> IM32_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _IMR2>>

pub fn im32(&self) -> IM32_R

Bit 0 - CPU wakeup with interrupt mask on event input

pub fn im33(&self) -> IM33_R

Bit 1 - CPU wakeup with interrupt mask on event input

impl R<bool, EM32_A>

pub fn variant(&self) -> EM32_A

Get enumerated values variant

pub fn is_masked(&self) -> bool

Checks if the value of the field is MASKED

pub fn is_unmasked(&self) -> bool

Checks if the value of the field is UNMASKED

impl R<u32, Reg<u32, _EMR2>>

pub fn em32(&self) -> EM32_R

Bit 0 - CPU wakeup with event mask on event input

pub fn em33(&self) -> EM33_R

Bit 1 - CPU wakeup with event mask on event input

impl R<u32, Reg<u32, _HWCFGR7>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR6>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR5>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR4>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR3>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn nbioport(&self) -> NBIOPORT_R

Bits 16:23 - HW configuration of number of IO ports

pub fn cpuevten(&self) -> CPUEVTEN_R

Bits 12:15 - HW configuration of CPU event output enable

pub fn nbcpus(&self) -> NBCPUS_R

Bits 8:11 - configuration number of CPUs

pub fn nbevents(&self) -> NBEVENTS_R

Bits 0:7 - configuration number of event

impl R<u32, Reg<u32, _VERR>>

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major revision

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor revision

impl R<u32, Reg<u32, _IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Identification code

impl R<u32, Reg<u32, _SIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Size Identification code

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&self) -> BKDFBK1E_R

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - selects input

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT

pub fn dedt(&self) -> DEDT_R

Bits 16:20 - DEDT

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn rtoen(&self) -> RTOEN_R

Bit 23 - Receiver timeout enable

pub fn abrmod(&self) -> ABRMOD_R

Bits 21:22 - Auto baud rate mode

pub fn abren(&self) -> ABREN_R

Bit 20 - Auto baud rate enable

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn linen(&self) -> LINEN_R

Bit 14 - LIN mode enable

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn clken(&self) -> CLKEN_R

Bit 11 - Clock enable

pub fn cpol(&self) -> CPOL_R

Bit 10 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 9 - Clock phase

pub fn lbcl(&self) -> LBCL_R

Bit 8 - Last bit clock pulse

pub fn lbdie(&self) -> LBDIE_R

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&self) -> LBDL_R

Bit 5 - LIN break detection length

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&self) -> DIS_NSS_R

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&self) -> SLVEN_R

Bit 0 - Synchronous Slave mode enable

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&self) -> TCBGTIE_R

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&self) -> SCARCNT_R

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn onebit(&self) -> ONEBIT_R

Bit 11 - One sample bit method enable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn scen(&self) -> SCEN_R

Bit 5 - Smartcard mode enable

pub fn nack(&self) -> NACK_R

Bit 4 - Smartcard NACK enable

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn irlp(&self) -> IRLP_R

Bit 2 - Ir low-power

pub fn iren(&self) -> IREN_R

Bit 1 - Ir mode enable

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr_4_15(&self) -> BRR_4_15_R

Bits 4:15 - BRR_4_15

pub fn brr_0_3(&self) -> BRR_0_3_R

Bits 0:3 - BRR_0_3

impl R<u32, Reg<u32, _GTPR>>

pub fn gt(&self) -> GT_R

Bits 8:15 - Guard time value

pub fn psc(&self) -> PSC_R

Bits 0:7 - Prescaler value

impl R<u32, Reg<u32, _RTOR>>

pub fn blen(&self) -> BLEN_R

Bits 24:31 - Block Length

pub fn rto(&self) -> RTO_R

Bits 0:23 - Receiver timeout value

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn tcbgt(&self) -> TCBGT_R

Bit 25 - Transmission complete before guard time flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn abrf(&self) -> ABRF_R

Bit 15 - ABRF

pub fn abre(&self) -> ABRE_R

Bit 14 - ABRE

pub fn udr(&self) -> UDR_R

Bit 13 - SPI slave underrun error flag

pub fn eobf(&self) -> EOBF_R

Bit 12 - EOBF

pub fn rtof(&self) -> RTOF_R

Bit 11 - RTOF

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn lbdf(&self) -> LBDF_R

Bit 8 - LBDF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn bidimode(&self) -> BIDIMODE_R

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&self) -> BIDIOE_R

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&self) -> CRCEN_R

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&self) -> CRCNEXT_R

Bit 12 - CRC transfer next

pub fn dff(&self) -> DFF_R

Bit 11 - Data frame format

pub fn rxonly(&self) -> RXONLY_R

Bit 10 - Receive only

pub fn ssm(&self) -> SSM_R

Bit 9 - Software slave management

pub fn ssi(&self) -> SSI_R

Bit 8 - Internal slave select

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 7 - Frame format

pub fn spe(&self) -> SPE_R

Bit 6 - SPI enable

pub fn br(&self) -> BR_R

Bits 3:5 - Baud rate control

pub fn mstr(&self) -> MSTR_R

Bit 2 - Master selection

pub fn cpol(&self) -> CPOL_R

Bit 1 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 0 - Clock phase

impl R<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&self) -> SSOE_R

Bit 2 - SS output enable

pub fn nssp(&self) -> NSSP_R

Bit 3 - NSS pulse management

pub fn frf(&self) -> FRF_R

Bit 4 - Frame format

pub fn errie(&self) -> ERRIE_R

Bit 5 - Error interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&self) -> DS_R

Bits 8:11 - Data size

pub fn frxth(&self) -> FRXTH_R

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&self) -> LDMA_RX_R

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&self) -> LDMA_TX_R

Bit 14 - Last DMA transfer for transmission

impl R<u32, Reg<u32, _SR>>

pub fn rxne(&self) -> RXNE_R

Bit 0 - Receive buffer not empty

pub fn txe(&self) -> TXE_R

Bit 1 - Transmit buffer empty

pub fn chside(&self) -> CHSIDE_R

Bit 2 - Channel side

pub fn udr(&self) -> UDR_R

Bit 3 - Underrun flag

pub fn crcerr(&self) -> CRCERR_R

Bit 4 - CRC error flag

pub fn modf(&self) -> MODF_R

Bit 5 - Mode fault

pub fn ovr(&self) -> OVR_R

Bit 6 - Overrun flag

pub fn bsy(&self) -> BSY_R

Bit 7 - Busy flag

pub fn tifrfe(&self) -> TIFRFE_R

Bit 8 - TI frame format error

pub fn frlvl(&self) -> FRLVL_R

Bits 9:10 - FIFO reception level

pub fn ftlvl(&self) -> FTLVL_R

Bits 11:12 - FIFO transmission level

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:15 - Data register

impl R<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&self) -> CRCPOLY_R

Bits 0:15 - CRC polynomial register

impl R<u32, Reg<u32, _RXCRCR>>

pub fn rx_crc(&self) -> RXCRC_R

Bits 0:15 - Rx CRC register

impl R<u32, Reg<u32, _TXCRCR>>

pub fn tx_crc(&self) -> TXCRC_R

Bits 0:15 - Tx CRC register

impl R<u32, Reg<u32, _I2SCFGR>>

pub fn chlen(&self) -> CHLEN_R

Bit 0 - Channel length (number of bits per audio channel)

pub fn datlen(&self) -> DATLEN_R

Bits 1:2 - Data length to be transferred

pub fn ckpol(&self) -> CKPOL_R

Bit 3 - Inactive state clock polarity

pub fn i2sstd(&self) -> I2SSTD_R

Bits 4:5 - standard selection

pub fn pcmsync(&self) -> PCMSYNC_R

Bit 7 - PCM frame synchronization

pub fn i2scfg(&self) -> I2SCFG_R

Bits 8:9 - I2S configuration mode

pub fn se2(&self) -> SE2_R

Bit 10 - I2S enable

pub fn i2smod(&self) -> I2SMOD_R

Bit 11 - I2S mode selection

impl R<u32, Reg<u32, _I2SPR>>

pub fn i2sdiv(&self) -> I2SDIV_R

Bits 0:7 - linear prescaler

pub fn odd(&self) -> ODD_R

Bit 8 - Odd factor for the prescaler

pub fn mckoe(&self) -> MCKOE_R

Bit 9 - Master clock output enable

impl R<u32, Reg<u32, _HWCFGR>>

pub fn crccfg(&self) -> CRCCFG_R

Bits 0:3 - CRC capable at SPI mode

pub fn i2scfg(&self) -> I2SCFG_R

Bits 4:7 - I2S mode implementation

pub fn i2sckcfg(&self) -> I2SCKCFG_R

Bits 8:11 - I2S master clock generator at I2S mode

pub fn dscfg(&self) -> DSCFG_R

Bits 12:15 - SPI data size configuration

pub fn nsscfg(&self) -> NSSCFG_R

Bits 16:19 - NSS pulse feature enhancement at SPI master

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn ts_4(&self) -> TS_4_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn ts(&self) -> TS_R

Bits 20:21 - Trigger selection

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag

pub fn cc5if(&self) -> CC5IF_R

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&self) -> CC6IF_R

Bit 17 - Compare 6 interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

impl R<u32, Reg<u32, _CCER>>

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&self) -> CC2NE_R

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&self) -> CC3NE_R

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&self) -> CC5E_R

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&self) -> CC5P_R

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&self) -> CC6E_R

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&self) -> CC6P_R

Bit 21 - Capture/Compare 6 output polarity

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:15 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3(&self) -> CCR3_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4(&self) -> CCR4_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bk2f(&self) -> BK2F_R

Bits 20:23 - Break 2 filter

pub fn bk2e(&self) -> BK2E_R

Bit 24 - Break 2 enable

pub fn bk2p(&self) -> BK2P_R

Bit 25 - Break 2 polarity

pub fn bkdsrm(&self) -> BKDSRM_R

Bit 26 - Break Disarm

pub fn bk2dsrm(&self) -> BK2DSRM_R

Bit 27 - Break2 Disarm

pub fn bkbid(&self) -> BKBID_R

Bit 28 - Break Bidirectional

pub fn bk2id(&self) -> BK2ID_R

Bit 29 - Break2 bidirectional

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn ocref_clr(&self) -> OCREF_CLR_R

Bit 0 - Ocref_clr source selection

impl R<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&self) -> OC6M_BIT3_R

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&self) -> OC5M_BIT3_R

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&self) -> OC6CE_R

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&self) -> OC6M_R

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&self) -> OC6PE_R

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&self) -> OC6FE_R

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&self) -> OC5CE_R

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&self) -> OC5M_R

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&self) -> OC5PE_R

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&self) -> OC5FE_R

Bit 2 - Output compare 5 fast enable

impl R<u32, Reg<u32, _CCR5>>

pub fn ccr5(&self) -> CCR5_R

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&self) -> GC5C1_R

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&self) -> GC5C2_R

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&self) -> GC5C3_R

Bit 31 - Group Channel 5 and Channel 3

impl R<u32, Reg<u32, _CCR6>>

pub fn ccr6(&self) -> CCR6_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - ETR source selection

impl R<u32, Reg<u32, _AF2>>

pub fn bk2ine(&self) -> BK2INE_R

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&self) -> BK2CMP1E_R

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&self) -> BK2CMP2E_R

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&self) -> BK2INP_R

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&self) -> BK2CMP1P_R

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&self) -> BK2CMP2P_R

Bit 11 - BRK2 COMP2 input polarity

impl R<u32, Reg<u32, _ISR>>

pub fn ccrdy(&self) -> CCRDY_R

Bit 13 - Channel Configuration Ready flag

pub fn eocal(&self) -> EOCAL_R

Bit 11 - End Of Calibration flag

pub fn awd3(&self) -> AWD3_R

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&self) -> AWD2_R

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&self) -> AWD1_R

Bit 7 - ADC analog watchdog 1 flag

pub fn ovr(&self) -> OVR_R

Bit 4 - ADC group regular overrun flag

pub fn eos(&self) -> EOS_R

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&self) -> EOC_R

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&self) -> EOSMP_R

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&self) -> ADRDY_R

Bit 0 - ADC ready flag

impl R<u32, Reg<u32, _IER>>

pub fn ccrdyie(&self) -> CCRDYIE_R

Bit 13 - Channel Configuration Ready Interrupt enable

pub fn eocalie(&self) -> EOCALIE_R

Bit 11 - End of calibration interrupt enable

pub fn awd3ie(&self) -> AWD3IE_R

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&self) -> AWD2IE_R

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&self) -> AWD1IE_R

Bit 7 - ADC analog watchdog 1 interrupt

pub fn ovrie(&self) -> OVRIE_R

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&self) -> EOSIE_R

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&self) -> EOCIE_R

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&self) -> EOSMPIE_R

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&self) -> ADRDYIE_R

Bit 0 - ADC ready interrupt

impl R<u32, Reg<u32, _CR>>

pub fn adcal(&self) -> ADCAL_R

Bit 31 - ADC calibration

pub fn advregen(&self) -> ADVREGEN_R

Bit 28 - ADC voltage regulator enable

pub fn adstp(&self) -> ADSTP_R

Bit 4 - ADC group regular conversion stop

pub fn adstart(&self) -> ADSTART_R

Bit 2 - ADC group regular conversion start

pub fn addis(&self) -> ADDIS_R

Bit 1 - ADC disable

pub fn aden(&self) -> ADEN_R

Bit 0 - ADC enable

impl R<u32, Reg<u32, _CFGR1>>

pub fn awdch1ch(&self) -> AWDCH1CH_R

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn awd1en(&self) -> AWD1EN_R

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGL_R

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn chselrmod(&self) -> CHSELRMOD_R

Bit 21 - Mode selection of the ADC_CHSELR register

pub fn discen(&self) -> DISCEN_R

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autoff(&self) -> AUTOFF_R

Bit 15 - Auto-off mode

pub fn wait(&self) -> WAIT_R

Bit 14 - Wait conversion mode

pub fn cont(&self) -> CONT_R

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMOD_R

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTEN_R

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSEL_R

Bits 6:8 - ADC group regular external trigger source

pub fn align(&self) -> ALIGN_R

Bit 5 - ADC data alignement

pub fn res(&self) -> RES_R

Bits 3:4 - ADC data resolution

pub fn scandir(&self) -> SCANDIR_R

Bit 2 - Scan sequence direction

pub fn dmacfg(&self) -> DMACFG_R

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - ADC DMA transfer enable

impl R<u32, Reg<u32, _CFGR2>>

pub fn ckmode(&self) -> CKMODE_R

Bits 30:31 - ADC clock mode

pub fn lftrig(&self) -> LFTRIG_R

Bit 29 - Low frequency trigger mode enable

pub fn tovs(&self) -> TOVS_R

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&self) -> OVSS_R

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&self) -> OVSR_R

Bits 2:4 - ADC oversampling ratio

pub fn ovse(&self) -> OVSE_R

Bit 0 - ADC oversampler enable on scope ADC group regular

impl R<u32, Reg<u32, _SMPR>>

pub fn smp1(&self) -> SMP1_R

Bits 0:2 - Sampling time selection

pub fn smp2(&self) -> SMP2_R

Bits 4:6 - Sampling time selection

pub fn smpsel(&self) -> SMPSEL_R

Bits 8:26 - Channel sampling time selection

impl R<u32, Reg<u32, _AWD1TR>>

pub fn ht1(&self) -> HT1_R

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&self) -> LT1_R

Bits 0:11 - ADC analog watchdog 1 threshold low

impl R<u32, Reg<u32, _AWD2TR>>

pub fn ht2(&self) -> HT2_R

Bits 16:27 - ADC analog watchdog 2 threshold high

pub fn lt2(&self) -> LT2_R

Bits 0:11 - ADC analog watchdog 2 threshold low

impl R<u32, Reg<u32, _CHSELR>>

pub fn chsel(&self) -> CHSEL_R

Bits 0:18 - Channel-x selection

impl R<u32, Reg<u32, _CHSELR_1>>

pub fn sq1(&self) -> SQ1_R

Bits 0:3 - conversion of the sequence

pub fn sq2(&self) -> SQ2_R

Bits 4:7 - conversion of the sequence

pub fn sq3(&self) -> SQ3_R

Bits 8:11 - conversion of the sequence

pub fn sq4(&self) -> SQ4_R

Bits 12:15 - conversion of the sequence

pub fn sq5(&self) -> SQ5_R

Bits 16:19 - conversion of the sequence

pub fn sq6(&self) -> SQ6_R

Bits 20:23 - conversion of the sequence

pub fn sq7(&self) -> SQ7_R

Bits 24:27 - conversion of the sequence

pub fn sq8(&self) -> SQ8_R

Bits 28:31 - conversion of the sequence

impl R<u32, Reg<u32, _AWD3TR>>

pub fn ht3(&self) -> HT3_R

Bits 16:27 - ADC analog watchdog 3 threshold high

pub fn lt3(&self) -> LT3_R

Bits 0:11 - ADC analog watchdog 3 threshold high

impl R<u32, Reg<u32, _DR>>

pub fn regular_data(&self) -> REGULARDATA_R

Bits 0:15 - ADC group regular conversion data

impl R<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&self) -> AWD2CH_R

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl R<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&self) -> AWD3CH_R

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl R<u32, Reg<u32, _CALFACT>>

pub fn calfact(&self) -> CALFACT_R

Bits 0:6 - ADC calibration factor in single-ended mode

impl R<u32, Reg<u32, _CCR>>

pub fn presc(&self) -> PRESC_R

Bits 18:21 - ADC prescaler

pub fn vrefen(&self) -> VREFEN_R

Bit 22 - VREFINT enable

pub fn tsen(&self) -> TSEN_R

Bit 23 - Temperature sensor enable

pub fn vbaten(&self) -> VBATEN_R

Bit 24 - VBAT enable

impl R<u32, Reg<u32, _HWCFGR6>>

pub fn chmap20(&self) -> CHMAP20_R

Bits 0:4 - Input channel mapping

pub fn chmap21(&self) -> CHMAP21_R

Bits 8:12 - Input channel mapping

pub fn chmap22(&self) -> CHMAP22_R

Bits 16:20 - Input channel mapping

pub fn chmap23(&self) -> CHMAP23_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR5>>

pub fn chmap19(&self) -> CHMAP19_R

Bits 0:4 - Input channel mapping

pub fn chmap18(&self) -> CHMAP18_R

Bits 8:12 - Input channel mapping

pub fn chmap17(&self) -> CHMAP17_R

Bits 16:20 - Input channel mapping

pub fn chmap16(&self) -> CHMAP16_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR4>>

pub fn chmap15(&self) -> CHMAP15_R

Bits 0:4 - Input channel mapping

pub fn chmap14(&self) -> CHMAP14_R

Bits 8:12 - Input channel mapping

pub fn chmap13(&self) -> CHMAP13_R

Bits 16:20 - Input channel mapping

pub fn chmap12(&self) -> CHMAP12_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR3>>

pub fn chmap11(&self) -> CHMAP11_R

Bits 0:4 - Input channel mapping

pub fn chmap10(&self) -> CHMAP10_R

Bits 8:12 - Input channel mapping

pub fn chmap9(&self) -> CHMAP9_R

Bits 16:20 - Input channel mapping

pub fn chmap8(&self) -> CHMAP8_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn chmap7(&self) -> CHMAP7_R

Bits 0:4 - Input channel mapping

pub fn chmap6(&self) -> CHMAP6_R

Bits 8:12 - Input channel mapping

pub fn chmap5(&self) -> CHMAP5_R

Bits 16:20 - Input channel mapping

pub fn chmap4(&self) -> CHMAP4_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn chmap3(&self) -> CHMAP3_R

Bits 0:4 - Input channel mapping

pub fn chmap2(&self) -> CHMAP2_R

Bits 8:12 - Input channel mapping

pub fn chmap1(&self) -> CHMAP1_R

Bits 16:20 - Input channel mapping

pub fn chmap0(&self) -> CHMAP0_R

Bits 24:28 - Input channel mapping

impl R<u32, Reg<u32, _HWCFGR0>>

pub fn num_chan_24(&self) -> NUM_CHAN_24_R

Bits 0:3 - NUM_CHAN_24

pub fn extra_awds(&self) -> EXTRA_AWDS_R

Bits 4:7 - Extra analog watchdog

pub fn ovs(&self) -> OVS_R

Bits 8:11 - Oversampling

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _COMP1_CSR>>

pub fn en(&self) -> EN_R

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&self) -> INMSEL_R

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&self) -> INPSEL_R

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&self) -> WINMODE_R

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&self) -> WINOUT_R

Bit 14 - Comparator 2 output selector

pub fn polarity(&self) -> POLARITY_R

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&self) -> HYST_R

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&self) -> PWRMODE_R

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&self) -> BLANKSEL_R

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&self) -> VALUE_R

Bit 30 - Comparator 2 output status

pub fn lock(&self) -> LOCK_R

Bit 31 - COMP2_CSR register lock

impl R<u32, Reg<u32, _COMP2_CSR>>

pub fn en(&self) -> EN_R

Bit 0 - COMP channel 1 enable bit

pub fn inmsel(&self) -> INMSEL_R

Bits 4:7 - Comparator 2 signal selector for inverting input INM

pub fn inpsel(&self) -> INPSEL_R

Bits 8:9 - Comparator 2 signal selector for non-inverting input

pub fn winmode(&self) -> WINMODE_R

Bit 11 - Comparator 2 non-inverting input selector for window mode

pub fn winout(&self) -> WINOUT_R

Bit 14 - Comparator 2 output selector

pub fn polarity(&self) -> POLARITY_R

Bit 15 - Comparator 2 polarity selector

pub fn hyst(&self) -> HYST_R

Bits 16:17 - Comparator 2 hysteresis selector

pub fn pwrmode(&self) -> PWRMODE_R

Bits 18:19 - Comparator 2 power mode selector

pub fn blanksel(&self) -> BLANKSEL_R

Bits 20:24 - Comparator 2 blanking source selector

pub fn value(&self) -> VALUE_R

Bit 30 - Comparator 2 output status

pub fn lock(&self) -> LOCK_R

Bit 31 - COMP2_CSR register lock

impl R<u32, Reg<u32, _VREFBUF_CSR>>

pub fn envr(&self) -> ENVR_R

Bit 0 - Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.

pub fn hiz(&self) -> HIZ_R

Bit 1 - High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

pub fn vrr(&self) -> VRR_R

Bit 3 - Voltage reference buffer ready

pub fn vrs(&self) -> VRS_R

Bits 4:6 - Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved

impl R<u32, Reg<u32, _VREFBUF_CCR>>

pub fn trim(&self) -> TRIM_R

Bits 0:5 - Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.

impl R<u32, Reg<u32, _CFGR1>>

pub fn i2c_pax_fmp(&self) -> I2C_PAX_FMP_R

Bits 22:23 - Fast Mode Plus (FM+) driving capability activation bits

pub fn i2c2_fmp(&self) -> I2C2_FMP_R

Bit 21 - FM+ driving capability activation for I2C2

pub fn i2c1_fmp(&self) -> I2C1_FMP_R

Bit 20 - FM+ driving capability activation for I2C1

pub fn i2c_pbx_fmp(&self) -> I2C_PBX_FMP_R

Bits 16:19 - Fast Mode Plus (FM+) driving capability activation bits

pub fn ucpd2_strobe(&self) -> UCPD2_STROBE_R

Bit 10 - Strobe signal bit for UCPD2

pub fn ucpd1_strobe(&self) -> UCPD1_STROBE_R

Bit 9 - Strobe signal bit for UCPD1

pub fn boosten(&self) -> BOOSTEN_R

Bit 8 - I/O analog switch voltage booster enable

pub fn ir_mod(&self) -> IR_MOD_R

Bits 6:7 - IR Modulation Envelope signal selection.

pub fn ir_pol(&self) -> IR_POL_R

Bit 5 - IR output polarity selection

pub fn pa11_pa12_rmp(&self) -> PA11_PA12_RMP_R

Bit 4 - PA11 and PA12 remapping bit.

pub fn mem_mode(&self) -> MEM_MODE_R

Bits 0:1 - Memory mapping selection bits

impl R<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&self) -> LOCKUP_LOCK_R

Bit 0 - Cortex-M0+ LOCKUP bit enable bit

pub fn sram_parity_lock(&self) -> SRAM_PARITY_LOCK_R

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&self) -> PVD_LOCK_R

Bit 2 - PVD lock enable bit

pub fn ecc_lock(&self) -> ECC_LOCK_R

Bit 3 - ECC error lock bit

pub fn sram_pef(&self) -> SRAM_PEF_R

Bit 8 - SRAM parity error flag

impl R<u32, Reg<u32, _ITLINE0>>

pub fn wwdg(&self) -> WWDG_R

Bit 0 - Window watchdog interrupt pending flag

impl R<u32, Reg<u32, _ITLINE1>>

pub fn pvdout(&self) -> PVDOUT_R

Bit 0 - PVD supply monitoring interrupt request pending (EXTI line 16).

impl R<u32, Reg<u32, _ITLINE2>>

pub fn tamp(&self) -> TAMP_R

Bit 0 - TAMP

pub fn rtc(&self) -> RTC_R

Bit 1 - RTC

impl R<u32, Reg<u32, _ITLINE3>>

pub fn flash_itf(&self) -> FLASH_ITF_R

Bit 0 - FLASH_ITF

pub fn flash_ecc(&self) -> FLASH_ECC_R

Bit 1 - FLASH_ECC

impl R<u32, Reg<u32, _ITLINE4>>

pub fn rcc(&self) -> RCC_R

Bit 0 - RCC

impl R<u32, Reg<u32, _ITLINE5>>

pub fn exti0(&self) -> EXTI0_R

Bit 0 - EXTI0

pub fn exti1(&self) -> EXTI1_R

Bit 1 - EXTI1

impl R<u32, Reg<u32, _ITLINE6>>

pub fn exti2(&self) -> EXTI2_R

Bit 0 - EXTI2

pub fn exti3(&self) -> EXTI3_R

Bit 1 - EXTI3

impl R<u32, Reg<u32, _ITLINE7>>

pub fn exti4(&self) -> EXTI4_R

Bit 0 - EXTI4

pub fn exti5(&self) -> EXTI5_R

Bit 1 - EXTI5

pub fn exti6(&self) -> EXTI6_R

Bit 2 - EXTI6

pub fn exti7(&self) -> EXTI7_R

Bit 3 - EXTI7

pub fn exti8(&self) -> EXTI8_R

Bit 4 - EXTI8

pub fn exti9(&self) -> EXTI9_R

Bit 5 - EXTI9

pub fn exti10(&self) -> EXTI10_R

Bit 6 - EXTI10

pub fn exti11(&self) -> EXTI11_R

Bit 7 - EXTI11

pub fn exti12(&self) -> EXTI12_R

Bit 8 - EXTI12

pub fn exti13(&self) -> EXTI13_R

Bit 9 - EXTI13

pub fn exti14(&self) -> EXTI14_R

Bit 10 - EXTI14

pub fn exti15(&self) -> EXTI15_R

Bit 11 - EXTI15

impl R<u32, Reg<u32, _ITLINE8>>

pub fn ucpd1(&self) -> UCPD1_R

Bit 0 - UCPD1

pub fn ucpd2(&self) -> UCPD2_R

Bit 1 - UCPD2

impl R<u32, Reg<u32, _ITLINE9>>

pub fn dma1_ch1(&self) -> DMA1_CH1_R

Bit 0 - DMA1_CH1

impl R<u32, Reg<u32, _ITLINE10>>

pub fn dma1_ch2(&self) -> DMA1_CH2_R

Bit 0 - DMA1_CH1

pub fn dma1_ch3(&self) -> DMA1_CH3_R

Bit 1 - DMA1_CH3

impl R<u32, Reg<u32, _ITLINE11>>

pub fn dmamux(&self) -> DMAMUX_R

Bit 0 - DMAMUX

pub fn dma1_ch4(&self) -> DMA1_CH4_R

Bit 1 - DMA1_CH4

pub fn dma1_ch5(&self) -> DMA1_CH5_R

Bit 2 - DMA1_CH5

pub fn dma1_ch6(&self) -> DMA1_CH6_R

Bit 3 - DMA1_CH6

pub fn dma1_ch7(&self) -> DMA1_CH7_R

Bit 4 - DMA1_CH7

impl R<u32, Reg<u32, _ITLINE12>>

pub fn adc(&self) -> ADC_R

Bit 0 - ADC

pub fn comp1(&self) -> COMP1_R

Bit 1 - COMP1

pub fn comp2(&self) -> COMP2_R

Bit 2 - COMP2

impl R<u32, Reg<u32, _ITLINE13>>

pub fn tim1_ccu(&self) -> TIM1_CCU_R

Bit 0 - TIM1_CCU

pub fn tim1_trg(&self) -> TIM1_TRG_R

Bit 1 - TIM1_TRG

pub fn tim1_upd(&self) -> TIM1_UPD_R

Bit 2 - TIM1_UPD

pub fn tim1_brk(&self) -> TIM1_BRK_R

Bit 3 - TIM1_BRK

impl R<u32, Reg<u32, _ITLINE14>>

pub fn tim1_cc(&self) -> TIM1_CC_R

Bit 0 - TIM1_CC

impl R<u32, Reg<u32, _ITLINE15>>

pub fn tim2(&self) -> TIM2_R

Bit 0 - TIM2

impl R<u32, Reg<u32, _ITLINE16>>

pub fn tim3(&self) -> TIM3_R

Bit 0 - TIM3

impl R<u32, Reg<u32, _ITLINE17>>

pub fn tim6(&self) -> TIM6_R

Bit 0 - TIM6

pub fn dac(&self) -> DAC_R

Bit 1 - DAC

pub fn lptim1(&self) -> LPTIM1_R

Bit 2 - LPTIM1

impl R<u32, Reg<u32, _ITLINE18>>

pub fn tim7(&self) -> TIM7_R

Bit 0 - TIM7

pub fn lptim2(&self) -> LPTIM2_R

Bit 1 - LPTIM2

impl R<u32, Reg<u32, _ITLINE19>>

pub fn tim14(&self) -> TIM14_R

Bit 0 - TIM14

impl R<u32, Reg<u32, _ITLINE20>>

pub fn tim15(&self) -> TIM15_R

Bit 0 - TIM15

impl R<u32, Reg<u32, _ITLINE21>>

pub fn tim16(&self) -> TIM16_R

Bit 0 - TIM16

impl R<u32, Reg<u32, _ITLINE22>>

pub fn tim17(&self) -> TIM17_R

Bit 0 - TIM17

impl R<u32, Reg<u32, _ITLINE23>>

pub fn i2c1(&self) -> I2C1_R

Bit 0 - I2C1

impl R<u32, Reg<u32, _ITLINE24>>

pub fn i2c2(&self) -> I2C2_R

Bit 0 - I2C2

impl R<u32, Reg<u32, _ITLINE25>>

pub fn spi1(&self) -> SPI1_R

Bit 0 - SPI1

impl R<u32, Reg<u32, _ITLINE26>>

pub fn spi2(&self) -> SPI2_R

Bit 0 - SPI2

impl R<u32, Reg<u32, _ITLINE27>>

pub fn usart1(&self) -> USART1_R

Bit 0 - USART1

impl R<u32, Reg<u32, _ITLINE28>>

pub fn usart2(&self) -> USART2_R

Bit 0 - USART2

impl R<u32, Reg<u32, _ITLINE29>>

pub fn usart3(&self) -> USART3_R

Bit 0 - USART3

pub fn usart4(&self) -> USART4_R

Bit 1 - USART4

pub fn usart5(&self) -> USART5_R

Bit 2 - USART5

impl R<u32, Reg<u32, _ITLINE30>>

pub fn usart2(&self) -> USART2_R

Bit 0 - CEC

impl R<u32, Reg<u32, _ITLINE31>>

pub fn rng(&self) -> RNG_R

Bit 0 - RNG

pub fn aes(&self) -> AES_R

Bit 1 - AES

impl R<u32, Reg<u32, _CR1>>

pub fn tamp1e(&self) -> TAMP1E_R

Bit 0 - TAMP1E

pub fn tamp2e(&self) -> TAMP2E_R

Bit 1 - TAMP2E

pub fn itamp1e(&self) -> ITAMP1E_R

Bit 16 - ITAMP1E

pub fn itamp3e(&self) -> ITAMP3E_R

Bit 18 - ITAMP3E

pub fn itamp4e(&self) -> ITAMP4E_R

Bit 19 - ITAMP4E

pub fn itamp5e(&self) -> ITAMP5E_R

Bit 20 - ITAMP5E

pub fn itamp6e(&self) -> ITAMP6E_R

Bit 21 - ITAMP6E

impl R<u32, Reg<u32, _CR2>>

pub fn tamp1noer(&self) -> TAMP1NOER_R

Bit 0 - TAMP1NOER

pub fn tamp2noer(&self) -> TAMP2NOER_R

Bit 1 - TAMP2NOER

pub fn tamp1msk(&self) -> TAMP1MSK_R

Bit 16 - TAMP1MSK

pub fn tamp2msk(&self) -> TAMP2MSK_R

Bit 17 - TAMP2MSK

pub fn tamp1trg(&self) -> TAMP1TRG_R

Bit 24 - TAMP1TRG

pub fn tamp2trg(&self) -> TAMP2TRG_R

Bit 25 - TAMP2TRG

impl R<u32, Reg<u32, _FLTCR>>

pub fn tampfreq(&self) -> TAMPFREQ_R

Bits 0:2 - TAMPFREQ

pub fn tampflt(&self) -> TAMPFLT_R

Bits 3:4 - TAMPFLT

pub fn tampprch(&self) -> TAMPPRCH_R

Bits 5:6 - TAMPPRCH

pub fn tamppudis(&self) -> TAMPPUDIS_R

Bit 7 - TAMPPUDIS

impl R<u32, Reg<u32, _IER>>

pub fn tamp1ie(&self) -> TAMP1IE_R

Bit 0 - TAMP1IE

pub fn tamp2ie(&self) -> TAMP2IE_R

Bit 1 - TAMP2IE

pub fn itamp1ie(&self) -> ITAMP1IE_R

Bit 16 - ITAMP1IE

pub fn itamp3ie(&self) -> ITAMP3IE_R

Bit 18 - ITAMP3IE

pub fn itamp4ie(&self) -> ITAMP4IE_R

Bit 19 - ITAMP4IE

pub fn itamp5ie(&self) -> ITAMP5IE_R

Bit 20 - ITAMP5IE

pub fn itamp6ie(&self) -> ITAMP6IE_R

Bit 21 - ITAMP6IE

impl R<u32, Reg<u32, _SR>>

pub fn tamp1f(&self) -> TAMP1F_R

Bit 0 - TAMP1F

pub fn tamp2f(&self) -> TAMP2F_R

Bit 1 - TAMP2F

pub fn itamp1f(&self) -> ITAMP1F_R

Bit 16 - ITAMP1F

pub fn itamp3f(&self) -> ITAMP3F_R

Bit 18 - ITAMP3F

pub fn itamp4f(&self) -> ITAMP4F_R

Bit 19 - ITAMP4F

pub fn itamp5f(&self) -> ITAMP5F_R

Bit 20 - ITAMP5F

pub fn itamp6f(&self) -> ITAMP6F_R

Bit 21 - ITAMP6F

pub fn itamp7f(&self) -> ITAMP7F_R

Bit 22 - ITAMP7F

impl R<u32, Reg<u32, _MISR>>

pub fn tamp1mf(&self) -> TAMP1MF_R

Bit 0 - TAMP1MF:

pub fn tamp2mf(&self) -> TAMP2MF_R

Bit 1 - TAMP2MF

pub fn itamp1mf(&self) -> ITAMP1MF_R

Bit 16 - ITAMP1MF

pub fn itamp3mf(&self) -> ITAMP3MF_R

Bit 18 - ITAMP3MF

pub fn itamp4mf(&self) -> ITAMP4MF_R

Bit 19 - ITAMP4MF

pub fn itamp5mf(&self) -> ITAMP5MF_R

Bit 20 - ITAMP5MF

pub fn itamp6mf(&self) -> ITAMP6MF_R

Bit 21 - ITAMP6MF

impl R<u32, Reg<u32, _BKP0R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP1R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP2R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP3R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP4R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn ptionreg_out(&self) -> PTIONREG_OUT_R

Bits 0:7 - PTIONREG_OUT

pub fn trust_zone(&self) -> TRUST_ZONE_R

Bits 8:11 - TRUST_ZONE

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn backup_regs(&self) -> BACKUP_REGS_R

Bits 0:7 - BACKUP_REGS

pub fn tamper(&self) -> TAMPER_R

Bits 8:11 - TAMPER

pub fn active_tamper(&self) -> ACTIVE_TAMPER_R

Bits 12:15 - ACTIVE_TAMPER

pub fn int_tamper(&self) -> INT_TAMPER_R

Bits 16:31 - INT_TAMPER

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CFG1>>

pub fn hbitclkdiv(&self) -> HBITCLKDIV_R

Bits 0:5 - HBITCLKDIV

pub fn ifrgap(&self) -> IFRGAP_R

Bits 6:10 - IFRGAP

pub fn transwin(&self) -> TRANSWIN_R

Bits 11:15 - TRANSWIN

pub fn psc_usbpdclk(&self) -> PSC_USBPDCLK_R

Bits 17:19 - PSC_USBPDCLK

pub fn rxordseten(&self) -> RXORDSETEN_R

Bits 20:28 - RXORDSETEN

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 29 - TXDMAEN

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 30 - RXDMAEN:

pub fn ucpden(&self) -> UCPDEN_R

Bit 31 - UCPDEN

impl R<u32, Reg<u32, _CFG2>>

pub fn rxfiltdis(&self) -> RXFILTDIS_R

Bit 0 - RXFILTDIS

pub fn rxfilt2n3(&self) -> RXFILT2N3_R

Bit 1 - RXFILT2N3

pub fn forceclk(&self) -> FORCECLK_R

Bit 2 - FORCECLK

pub fn wupen(&self) -> WUPEN_R

Bit 3 - WUPEN

impl R<u32, Reg<u32, _CFG3>>

pub fn trim1_ng_ccrpd(&self) -> TRIM1_NG_CCRPD_R

Bits 0:3 - TRIM1_NG_CCRPD

pub fn trim1_ng_cc1a5(&self) -> TRIM1_NG_CC1A5_R

Bits 4:8 - TRIM1_NG_CC1A5

pub fn trim1_ng_cc3a0(&self) -> TRIM1_NG_CC3A0_R

Bits 9:12 - TRIM1_NG_CC3A0

pub fn trim2_ng_ccrpd(&self) -> TRIM2_NG_CCRPD_R

Bits 16:19 - TRIM2_NG_CCRPD

pub fn trim2_ng_cc1a5(&self) -> TRIM2_NG_CC1A5_R

Bits 20:24 - TRIM2_NG_CC1A5

pub fn trim2_ng_cc3a0(&self) -> TRIM2_NG_CC3A0_R

Bits 25:28 - TRIM2_NG_CC3A0

impl R<u32, Reg<u32, _CR>>

pub fn txmode(&self) -> TXMODE_R

Bits 0:1 - TXMODE

pub fn txsend(&self) -> TXSEND_R

Bit 2 - TXSEND

pub fn txhrst(&self) -> TXHRST_R

Bit 3 - TXHRST

pub fn rxmode(&self) -> RXMODE_R

Bit 4 - RXMODE

pub fn phyrxen(&self) -> PHYRXEN_R

Bit 5 - PHYRXEN

pub fn phyccsel(&self) -> PHYCCSEL_R

Bit 6 - PHYCCSEL

pub fn anasubmode(&self) -> ANASUBMODE_R

Bits 7:8 - ANASUBMODE

pub fn anamode(&self) -> ANAMODE_R

Bit 9 - ANAMODE

pub fn ccenable(&self) -> CCENABLE_R

Bits 10:11 - CCENABLE

pub fn dbatten(&self) -> DBATTEN_R

Bit 15 - DBATTEN

pub fn frsrxen(&self) -> FRSRXEN_R

Bit 16 - FRSRXEN

pub fn frstx(&self) -> FRSTX_R

Bit 17 - FRSTX

pub fn rdch(&self) -> RDCH_R

Bit 18 - RDCH

pub fn cc1tcdis(&self) -> CC1TCDIS_R

Bit 20 - CC1TCDIS

pub fn cc2tcdis(&self) -> CC2TCDIS_R

Bit 21 - CC2TCDIS

impl R<u32, Reg<u32, _IMR>>

pub fn txisie(&self) -> TXISIE_R

Bit 0 - TXISIE

pub fn txmsgdiscie(&self) -> TXMSGDISCIE_R

Bit 1 - TXMSGDISCIE

pub fn txmsgsentie(&self) -> TXMSGSENTIE_R

Bit 2 - TXMSGSENTIE

pub fn txmsgabtie(&self) -> TXMSGABTIE_R

Bit 3 - TXMSGABTIE

pub fn hrstdiscie(&self) -> HRSTDISCIE_R

Bit 4 - HRSTDISCIE

pub fn hrstsentie(&self) -> HRSTSENTIE_R

Bit 5 - HRSTSENTIE

pub fn txundie(&self) -> TXUNDIE_R

Bit 6 - TXUNDIE

pub fn rxneie(&self) -> RXNEIE_R

Bit 8 - RXNEIE

pub fn rxorddetie(&self) -> RXORDDETIE_R

Bit 9 - RXORDDETIE

pub fn rxhrstdetie(&self) -> RXHRSTDETIE_R

Bit 10 - RXHRSTDETIE

pub fn rxovrie(&self) -> RXOVRIE_R

Bit 11 - RXOVRIE

pub fn rxmsgendie(&self) -> RXMSGENDIE_R

Bit 12 - RXMSGENDIE

pub fn typecevt1ie(&self) -> TYPECEVT1IE_R

Bit 14 - TYPECEVT1IE

pub fn typecevt2ie(&self) -> TYPECEVT2IE_R

Bit 15 - TYPECEVT2IE

pub fn frsevtie(&self) -> FRSEVTIE_R

Bit 20 - FRSEVTIE

impl R<u32, Reg<u32, _SR>>

pub fn txis(&self) -> TXIS_R

Bit 0 - TXIS

pub fn txmsgdisc(&self) -> TXMSGDISC_R

Bit 1 - TXMSGDISC

pub fn txmsgsent(&self) -> TXMSGSENT_R

Bit 2 - TXMSGSENT

pub fn txmsgabt(&self) -> TXMSGABT_R

Bit 3 - TXMSGABT

pub fn hrstdisc(&self) -> HRSTDISC_R

Bit 4 - HRSTDISC

pub fn hrstsent(&self) -> HRSTSENT_R

Bit 5 - HRSTSENT

pub fn txund(&self) -> TXUND_R

Bit 6 - TXUND

pub fn rxne(&self) -> RXNE_R

Bit 8 - RXNE

pub fn rxorddet(&self) -> RXORDDET_R

Bit 9 - RXORDDET

pub fn rxhrstdet(&self) -> RXHRSTDET_R

Bit 10 - RXHRSTDET

pub fn rxovr(&self) -> RXOVR_R

Bit 11 - RXOVR

pub fn rxmsgend(&self) -> RXMSGEND_R

Bit 12 - RXMSGEND

pub fn rxerr(&self) -> RXERR_R

Bit 13 - RXERR

pub fn typecevt1(&self) -> TYPECEVT1_R

Bit 14 - TYPECEVT1

pub fn typecevt2(&self) -> TYPECEVT2_R

Bit 15 - TYPECEVT2

pub fn typec_vstate_cc1(&self) -> TYPEC_VSTATE_CC1_R

Bits 16:17 - TYPEC_VSTATE_CC1

pub fn typec_vstate_cc2(&self) -> TYPEC_VSTATE_CC2_R

Bits 18:19 - TYPEC_VSTATE_CC2

pub fn frsevt(&self) -> FRSEVT_R

Bit 20 - FRSEVT

impl R<u32, Reg<u32, _ICR>>

pub fn txmsgdisccf(&self) -> TXMSGDISCCF_R

Bit 1 - TXMSGDISCCF

pub fn txmsgsentcf(&self) -> TXMSGSENTCF_R

Bit 2 - TXMSGSENTCF

pub fn txmsgabtcf(&self) -> TXMSGABTCF_R

Bit 3 - TXMSGABTCF

pub fn hrstdisccf(&self) -> HRSTDISCCF_R

Bit 4 - HRSTDISCCF

pub fn hrstsentcf(&self) -> HRSTSENTCF_R

Bit 5 - HRSTSENTCF

pub fn txundcf(&self) -> TXUNDCF_R

Bit 6 - TXUNDCF

pub fn rxorddetcf(&self) -> RXORDDETCF_R

Bit 9 - RXORDDETCF

pub fn rxhrstdetcf(&self) -> RXHRSTDETCF_R

Bit 10 - RXHRSTDETCF

pub fn rxovrcf(&self) -> RXOVRCF_R

Bit 11 - RXOVRCF

pub fn rxmsgendcf(&self) -> RXMSGENDCF_R

Bit 12 - RXMSGENDCF

pub fn typecevt1cf(&self) -> TYPECEVT1CF_R

Bit 14 - TYPECEVT1CF

pub fn typecevt2cf(&self) -> TYPECEVT2CF_R

Bit 15 - TYPECEVT2CF

pub fn frsevtcf(&self) -> FRSEVTCF_R

Bit 20 - FRSEVTCF

impl R<u32, Reg<u32, _TX_ORDSET>>

pub fn txordset(&self) -> TXORDSET_R

Bits 0:19 - TXORDSET

impl R<u32, Reg<u32, _TX_PAYSZ>>

pub fn txpaysz(&self) -> TXPAYSZ_R

Bits 0:9 - TXPAYSZ

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - TXDATA

impl R<u32, Reg<u32, _RX_ORDSET>>

pub fn rxordset(&self) -> RXORDSET_R

Bits 0:2 - RXORDSET

pub fn rxsop3of4(&self) -> RXSOP3OF4_R

Bit 3 - RXSOP3OF4

pub fn rxsopkinvalid(&self) -> RXSOPKINVALID_R

Bits 4:6 - RXSOPKINVALID

impl R<u32, Reg<u32, _RX_PAYSZ>>

pub fn rxpaysz(&self) -> RXPAYSZ_R

Bits 0:9 - RXPAYSZ

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - RXDATA

impl R<u32, Reg<u32, _RX_ORDEXT1>>

pub fn rxsopx1(&self) -> RXSOPX1_R

Bits 0:19 - RXSOPX1

impl R<u32, Reg<u32, _RX_ORDEXT2>>

pub fn rxsopx2(&self) -> RXSOPX2_R

Bits 0:19 - RXSOPX2

impl R<u32, Reg<u32, _IPVER>>

pub fn ipver(&self) -> IPVER_R

Bits 0:31 - IPVER

impl R<u32, Reg<u32, _IPID>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IPID

impl R<u32, Reg<u32, _MID>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IPID

impl R<u32, Reg<u32, _ISR>>

pub fn down(&self) -> DOWN_R

Bit 6 - Counter direction change up to down

pub fn up(&self) -> UP_R

Bit 5 - Counter direction change down to up

pub fn arrok(&self) -> ARROK_R

Bit 4 - Autoreload register update OK

pub fn cmpok(&self) -> CMPOK_R

Bit 3 - Compare register update OK

pub fn exttrig(&self) -> EXTTRIG_R

Bit 2 - External trigger edge event

pub fn arrm(&self) -> ARRM_R

Bit 1 - Autoreload match

pub fn cmpm(&self) -> CMPM_R

Bit 0 - Compare match

impl R<u32, Reg<u32, _IER>>

pub fn downie(&self) -> DOWNIE_R

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&self) -> UPIE_R

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&self) -> ARROKIE_R

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&self) -> CMPOKIE_R

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&self) -> EXTTRIGIE_R

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&self) -> ARRMIE_R

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&self) -> CMPMIE_R

Bit 0 - Compare match Interrupt Enable

impl R<u32, Reg<u32, _CFGR>>

pub fn enc(&self) -> ENC_R

Bit 24 - Encoder mode enable

pub fn countmode(&self) -> COUNTMODE_R

Bit 23 - counter mode enabled

pub fn preload(&self) -> PRELOAD_R

Bit 22 - Registers update mode

pub fn wavpol(&self) -> WAVPOL_R

Bit 21 - Waveform shape polarity

pub fn wave(&self) -> WAVE_R

Bit 20 - Waveform shape

pub fn timout(&self) -> TIMOUT_R

Bit 19 - Timeout enable

pub fn trigen(&self) -> TRIGEN_R

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&self) -> TRIGSEL_R

Bits 13:15 - Trigger selector

pub fn presc(&self) -> PRESC_R

Bits 9:11 - Clock prescaler

pub fn trgflt(&self) -> TRGFLT_R

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&self) -> CKFLT_R

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&self) -> CKPOL_R

Bits 1:2 - Clock Polarity

pub fn cksel(&self) -> CKSEL_R

Bit 0 - Clock selector

impl R<u32, Reg<u32, _CR>>

pub fn rstare(&self) -> RSTARE_R

Bit 4 - Reset after read enable

pub fn countrst(&self) -> COUNTRST_R

Bit 3 - Counter reset

pub fn cntstrt(&self) -> CNTSTRT_R

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&self) -> SNGSTRT_R

Bit 1 - LPTIM start in single mode

pub fn enable(&self) -> ENABLE_R

Bit 0 - LPTIM Enable

impl R<u32, Reg<u32, _CMP>>

pub fn cmp(&self) -> CMP_R

Bits 0:15 - Compare value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto reload value

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Counter value

impl R<u32, Reg<u32, _CFGR2>>

pub fn in2sel(&self) -> IN2SEL_R

Bits 4:5 - LPTIM1 Input 2 selection

pub fn in1sel(&self) -> IN1SEL_R

Bits 0:1 - LPTIMx Input 1 selection

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn deat(&self) -> DEAT_R

Bits 21:25 - DEAT0

pub fn dedt0(&self) -> DEDT0_R

Bits 16:20 - DEDT0

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr(&self) -> BRR_R

Bits 0:19 - BRR

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn cfg1(&self) -> CFG1_R

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&self) -> CFG2_R

Bits 4:7 - LUART hardware configuration 2

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn cfg1(&self) -> CFG1_R

Bits 0:3 - LUART hardware configuration 1

pub fn cfg2(&self) -> CFG2_R

Bits 4:7 - LUART hardware configuration 2

pub fn cfg3(&self) -> CFG3_R

Bits 8:11 - LUART hardware configuration 1

pub fn cfg4(&self) -> CFG4_R

Bits 12:15 - LUART hardware configuration 2

pub fn cfg5(&self) -> CFG5_R

Bits 16:19 - LUART hardware configuration 2

pub fn cfg6(&self) -> CFG6_R

Bits 20:23 - LUART hardware configuration 2

pub fn cfg7(&self) -> CFG7_R

Bits 24:27 - LUART hardware configuration 2

pub fn cfg8(&self) -> CFG8_R

Bits 28:31 - LUART hardware configuration 2

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CEC_CR>>

pub fn cecen(&self) -> CECEN_R

Bit 0 - CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.

pub fn txsom(&self) -> TXSOM_R

Bit 1 - Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception

pub fn txeom(&self) -> TXEOM_R

Bit 2 - Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message)

impl R<u32, Reg<u32, _CEC_CFGR>>

pub fn sft(&self) -> SFT_R

Bits 0:2 - Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods

pub fn rxtol(&self) -> RXTOL_R

Bit 3 - Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall

pub fn brestp(&self) -> BRESTP_R

Bit 4 - Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software.

pub fn bregen(&self) -> BREGEN_R

Bit 5 - Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0

pub fn lbpegen(&self) -> LBPEGEN_R

Bit 6 - Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0

pub fn brdnogen(&self) -> BRDNOGEN_R

Bit 7 - Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software.

pub fn sftopt(&self) -> SFTOPT_R

Bit 8 - SFT Option Bit The SFTOPT bit is set and cleared by software.

pub fn oar(&self) -> OAR_R

Bits 16:30 - Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.

pub fn lstn(&self) -> LSTN_R

Bit 31 - Listen mode LSTN bit is set and cleared by software.

impl R<u32, Reg<u32, _CEC_RXDR>>

pub fn rxd(&self) -> RXD_R

Bits 0:7 - Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line.

impl R<u32, Reg<u32, _CEC_ISR>>

pub fn rxbr(&self) -> RXBR_R

Bit 0 - Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1.

pub fn rxend(&self) -> RXEND_R

Bit 1 - End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1.

pub fn rxovr(&self) -> RXOVR_R

Bit 2 - Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1.

pub fn bre(&self) -> BRE_R

Bit 3 - Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1.

pub fn sbpe(&self) -> SBPE_R

Bit 4 - Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1.

pub fn lbpe(&self) -> LBPE_R

Bit 5 - Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1.

pub fn rxacke(&self) -> RXACKE_R

Bit 6 - Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1.

pub fn arblst(&self) -> ARBLST_R

Bit 7 - Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1.

pub fn txbr(&self) -> TXBR_R

Bit 8 - Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1.

pub fn txend(&self) -> TXEND_R

Bit 9 - End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1.

pub fn txudr(&self) -> TXUDR_R

Bit 10 - Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1

pub fn txerr(&self) -> TXERR_R

Bit 11 - Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1.

pub fn txacke(&self) -> TXACKE_R

Bit 12 - Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1.

impl R<u32, Reg<u32, _CEC_IER>>

pub fn rxbrie(&self) -> RXBRIE_R

Bit 0 - Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software.

pub fn rxendie(&self) -> RXENDIE_R

Bit 1 - End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software.

pub fn rxovrie(&self) -> RXOVRIE_R

Bit 2 - Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software.

pub fn breie(&self) -> BREIE_R

Bit 3 - Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software.

pub fn sbpeie(&self) -> SBPEIE_R

Bit 4 - Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software.

pub fn lbpeie(&self) -> LBPEIE_R

Bit 5 - Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software.

pub fn rxackie(&self) -> RXACKIE_R

Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software.

pub fn arblstie(&self) -> ARBLSTIE_R

Bit 7 - Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software.

pub fn txbrie(&self) -> TXBRIE_R

Bit 8 - Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software.

pub fn txendie(&self) -> TXENDIE_R

Bit 9 - Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software.

pub fn txudrie(&self) -> TXUDRIE_R

Bit 10 - Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software.

pub fn txerrie(&self) -> TXERRIE_R

Bit 11 - Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software.

pub fn txackie(&self) -> TXACKIE_R

Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software.

impl R<u32, Reg<u32, _DAC_CR>>

pub fn en1(&self) -> EN1_R

Bit 0 - DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.

pub fn ten1(&self) -> TEN1_R

Bit 1 - DAC channel1 trigger enable

pub fn tsel1(&self) -> TSEL1_R

Bits 2:5 - DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn wave1(&self) -> WAVE1_R

Bits 6:7 - DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

pub fn mamp1(&self) -> MAMP1_R

Bits 8:11 - DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen1(&self) -> DMAEN1_R

Bit 12 - DAC channel1 DMA enable This bit is set and cleared by software.

pub fn dmaudrie1(&self) -> DMAUDRIE1_R

Bit 13 - DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.

pub fn cen1(&self) -> CEN1_R

Bit 14 - DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

pub fn en2(&self) -> EN2_R

Bit 16 - DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.

pub fn ten2(&self) -> TEN2_R

Bit 17 - DAC channel2 trigger enable

pub fn tsel2(&self) -> TSEL2_R

Bits 18:21 - DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

pub fn wave2(&self) -> WAVE2_R

Bits 22:23 - DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)

pub fn mamp2(&self) -> MAMP2_R

Bits 24:27 - DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

pub fn dmaen2(&self) -> DMAEN2_R

Bit 28 - DAC channel2 DMA enable This bit is set and cleared by software.

pub fn dmaudrie2(&self) -> DMAUDRIE2_R

Bit 29 - DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.

pub fn cen2(&self) -> CEN2_R

Bit 30 - DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

impl R<u32, Reg<u32, _DAC_DHR12R1>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl R<u32, Reg<u32, _DAC_DHR12L1>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

impl R<u32, Reg<u32, _DAC_DHR8R1>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

impl R<u32, Reg<u32, _DAC_DHR12R2>>

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 0:11 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR12L2>>

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 4:15 - DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR8R2>>

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 0:7 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR12RD>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:11 - DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 16:27 - DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR12LD>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 4:15 - DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 20:31 - DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DHR8RD>>

pub fn dacc1dhr(&self) -> DACC1DHR_R

Bits 0:7 - DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.

pub fn dacc2dhr(&self) -> DACC2DHR_R

Bits 8:15 - DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.

impl R<u32, Reg<u32, _DAC_DOR1>>

pub fn dacc1dor(&self) -> DACC1DOR_R

Bits 0:11 - DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.

impl R<u32, Reg<u32, _DAC_DOR2>>

pub fn dacc2dor(&self) -> DACC2DOR_R

Bits 0:11 - DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.

impl R<u32, Reg<u32, _DAC_SR>>

pub fn dmaudr1(&self) -> DMAUDR1_R

Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag1(&self) -> CAL_FLAG1_R

Bit 14 - DAC Channel 1 calibration offset status This bit is set and cleared by hardware

pub fn bwst1(&self) -> BWST1_R

Bit 15 - DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).

pub fn dmaudr2(&self) -> DMAUDR2_R

Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag2(&self) -> CAL_FLAG2_R

Bit 30 - DAC Channel 2 calibration offset status This bit is set and cleared by hardware

pub fn bwst2(&self) -> BWST2_R

Bit 31 - DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).

impl R<u32, Reg<u32, _DAC_CCR>>

pub fn otrim1(&self) -> OTRIM1_R

Bits 0:4 - DAC Channel 1 offset trimming value

pub fn otrim2(&self) -> OTRIM2_R

Bits 16:20 - DAC Channel 2 offset trimming value

impl R<u32, Reg<u32, _DAC_MCR>>

pub fn mode1(&self) -> MODE1_R

Bits 0:2 - DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode

pub fn mode2(&self) -> MODE2_R

Bits 16:18 - DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode

impl R<u32, Reg<u32, _DAC_SHSR1>>

pub fn tsample1(&self) -> TSAMPLE1_R

Bits 0:9 - DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.

impl R<u32, Reg<u32, _DAC_SHSR2>>

pub fn tsample2(&self) -> TSAMPLE2_R

Bits 0:9 - DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.

impl R<u32, Reg<u32, _DAC_SHHR>>

pub fn thold1(&self) -> THOLD1_R

Bits 0:9 - DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI

pub fn thold2(&self) -> THOLD2_R

Bits 16:25 - DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI

impl R<u32, Reg<u32, _DAC_SHRR>>

pub fn trefresh1(&self) -> TREFRESH1_R

Bits 0:7 - DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

pub fn trefresh2(&self) -> TREFRESH2_R

Bits 16:23 - DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

impl R<u32, Reg<u32, _IP_HWCFGR0>>

pub fn dual(&self) -> DUAL_R

Bits 0:3 - Dual DAC capability

pub fn lfsr(&self) -> LFSR_R

Bits 4:7 - Pseudonoise wave generation capability

pub fn triangle(&self) -> TRIANGLE_R

Bits 8:11 - Triangle wave generation capability

pub fn sample(&self) -> SAMPLE_R

Bits 12:15 - Sample and hold mode capability

pub fn or_cfg(&self) -> OR_CFG_R

Bits 16:23 - option register bit width

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn pe(&self) -> PE_R

Bit 0 - Peripheral enable

pub fn txie(&self) -> TXIE_R

Bit 1 - TX Interrupt enable

pub fn rxie(&self) -> RXIE_R

Bit 2 - RX Interrupt enable

pub fn addrie(&self) -> ADDRIE_R

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&self) -> NACKIE_R

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&self) -> STOPIE_R

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 7 - Error interrupts enable

pub fn dnf(&self) -> DNF_R

Bits 8:11 - Digital noise filter

pub fn anfoff(&self) -> ANFOFF_R

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 15 - DMA reception requests enable

pub fn sbc(&self) -> SBC_R

Bit 16 - Slave byte control

pub fn nostretch(&self) -> NOSTRETCH_R

Bit 17 - Clock stretching disable

pub fn wupen(&self) -> WUPEN_R

Bit 18 - Wakeup from STOP enable

pub fn gcen(&self) -> GCEN_R

Bit 19 - General call enable

pub fn smbhen(&self) -> SMBHEN_R

Bit 20 - SMBus Host address enable

pub fn smbden(&self) -> SMBDEN_R

Bit 21 - SMBus Device Default address enable

pub fn alerten(&self) -> ALERTEN_R

Bit 22 - SMBUS alert enable

pub fn pecen(&self) -> PECEN_R

Bit 23 - PEC enable

impl R<u32, Reg<u32, _CR2>>

pub fn pecbyte(&self) -> PECBYTE_R

Bit 26 - Packet error checking byte

pub fn autoend(&self) -> AUTOEND_R

Bit 25 - Automatic end mode (master mode)

pub fn reload(&self) -> RELOAD_R

Bit 24 - NBYTES reload mode

pub fn nbytes(&self) -> NBYTES_R

Bits 16:23 - Number of bytes

pub fn nack(&self) -> NACK_R

Bit 15 - NACK generation (slave mode)

pub fn stop(&self) -> STOP_R

Bit 14 - Stop generation (master mode)

pub fn start(&self) -> START_R

Bit 13 - Start generation

pub fn head10r(&self) -> HEAD10R_R

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&self) -> ADD10_R

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&self) -> RD_WRN_R

Bit 10 - Transfer direction (master mode)

pub fn sadd(&self) -> SADD_R

Bits 0:9 - Slave address bit (master mode)

impl R<u32, Reg<u32, _OAR1>>

pub fn oa1_0(&self) -> OA1_0_R

Bit 0 - Interface address

pub fn oa1_7_1(&self) -> OA1_7_1_R

Bits 1:7 - Interface address

pub fn oa1_8_9(&self) -> OA1_8_9_R

Bits 8:9 - Interface address

pub fn oa1mode(&self) -> OA1MODE_R

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&self) -> OA1EN_R

Bit 15 - Own Address 1 enable

impl R<u32, Reg<u32, _OAR2>>

pub fn oa2(&self) -> OA2_R

Bits 1:7 - Interface address

pub fn oa2msk(&self) -> OA2MSK_R

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&self) -> OA2EN_R

Bit 15 - Own Address 2 enable

impl R<u32, Reg<u32, _TIMINGR>>

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler

impl R<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&self) -> TIMEOUTA_R

Bits 0:11 - Bus timeout A

pub fn tidle(&self) -> TIDLE_R

Bit 12 - Idle clock timeout detection

pub fn timouten(&self) -> TIMOUTEN_R

Bit 15 - Clock timeout enable

pub fn timeoutb(&self) -> TIMEOUTB_R

Bits 16:27 - Bus timeout B

pub fn texten(&self) -> TEXTEN_R

Bit 31 - Extended clock timeout enable

impl R<u32, Reg<u32, _ISR>>

pub fn addcode(&self) -> ADDCODE_R

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R

Bit 0 - Transmit data register empty (transmitters)

impl R<u32, Reg<u32, _PECR>>

pub fn pec(&self) -> PEC_R

Bits 0:7 - Packet error checking register

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - 8-bit receive data

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - 8-bit transmit data

impl R<u32, Reg<u32, _TR>>

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _DR>>

pub fn yt(&self) -> YT_R

Bits 20:23 - Year tens in BCD format

pub fn yu(&self) -> YU_R

Bits 16:19 - Year units in BCD format

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _SSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ICSR>>

pub fn alrawf(&self) -> ALRAWF_R

Bit 0 - Alarm A write flag

pub fn alrbwf(&self) -> ALRBWF_R

Bit 1 - Alarm B write flag

pub fn wutwf(&self) -> WUTWF_R

Bit 2 - Wakeup timer write flag

pub fn shpf(&self) -> SHPF_R

Bit 3 - Shift operation pending

pub fn inits(&self) -> INITS_R

Bit 4 - Initialization status flag

pub fn rsf(&self) -> RSF_R

Bit 5 - Registers synchronization flag

pub fn initf(&self) -> INITF_R

Bit 6 - Initialization flag

pub fn init(&self) -> INIT_R

Bit 7 - Initialization mode

pub fn recalpf(&self) -> RECALPF_R

Bit 16 - Recalibration pending Flag

impl R<u32, Reg<u32, _PRER>>

pub fn prediv_a(&self) -> PREDIV_A_R

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&self) -> PREDIV_S_R

Bits 0:14 - Synchronous prescaler factor

impl R<u32, Reg<u32, _WUTR>>

pub fn wut(&self) -> WUT_R

Bits 0:15 - Wakeup auto-reload value bits

impl R<u32, Reg<u32, _CR>>

pub fn wucksel(&self) -> WUCKSEL_R

Bits 0:2 - WUCKSEL

pub fn tsedge(&self) -> TSEDGE_R

Bit 3 - TSEDGE

pub fn refckon(&self) -> REFCKON_R

Bit 4 - REFCKON

pub fn bypshad(&self) -> BYPSHAD_R

Bit 5 - BYPSHAD

pub fn fmt(&self) -> FMT_R

Bit 6 - FMT

pub fn alrae(&self) -> ALRAE_R

Bit 8 - ALRAE

pub fn alrbe(&self) -> ALRBE_R

Bit 9 - ALRBE

pub fn wute(&self) -> WUTE_R

Bit 10 - WUTE

pub fn tse(&self) -> TSE_R

Bit 11 - TSE

pub fn alraie(&self) -> ALRAIE_R

Bit 12 - ALRAIE

pub fn alrbie(&self) -> ALRBIE_R

Bit 13 - ALRBIE

pub fn wutie(&self) -> WUTIE_R

Bit 14 - WUTIE

pub fn tsie(&self) -> TSIE_R

Bit 15 - TSIE

pub fn add1h(&self) -> ADD1H_R

Bit 16 - ADD1H

pub fn sub1h(&self) -> SUB1H_R

Bit 17 - SUB1H

pub fn bkp(&self) -> BKP_R

Bit 18 - BKP

pub fn cosel(&self) -> COSEL_R

Bit 19 - COSEL

pub fn pol(&self) -> POL_R

Bit 20 - POL

pub fn osel(&self) -> OSEL_R

Bits 21:22 - OSEL

pub fn coe(&self) -> COE_R

Bit 23 - COE

pub fn itse(&self) -> ITSE_R

Bit 24 - ITSE

pub fn tampts(&self) -> TAMPTS_R

Bit 25 - TAMPTS

pub fn tampoe(&self) -> TAMPOE_R

Bit 26 - TAMPOE

pub fn tampalrm_pu(&self) -> TAMPALRM_PU_R

Bit 29 - TAMPALRM_PU

pub fn tampalrm_type(&self) -> TAMPALRM_TYPE_R

Bit 30 - TAMPALRM_TYPE

pub fn out2en(&self) -> OUT2EN_R

Bit 31 - OUT2EN

impl R<u32, Reg<u32, _CALR>>

pub fn calp(&self) -> CALP_R

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&self) -> CALW8_R

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&self) -> CALW16_R

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&self) -> CALM_R

Bits 0:8 - Calibration minus

impl R<u32, Reg<u32, _TSTR>>

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

impl R<u32, Reg<u32, _TSDR>>

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _TSSSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm A date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm A hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm A minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm A seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm B date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm B hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm B minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm B seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _SR>>

pub fn alraf(&self) -> ALRAF_R

Bit 0 - ALRAF

pub fn alrbf(&self) -> ALRBF_R

Bit 1 - ALRBF

pub fn wutf(&self) -> WUTF_R

Bit 2 - WUTF

pub fn tsf(&self) -> TSF_R

Bit 3 - TSF

pub fn tsovf(&self) -> TSOVF_R

Bit 4 - TSOVF

pub fn itsf(&self) -> ITSF_R

Bit 5 - ITSF

impl R<u32, Reg<u32, _MISR>>

pub fn alramf(&self) -> ALRAMF_R

Bit 0 - ALRAMF

pub fn alrbmf(&self) -> ALRBMF_R

Bit 1 - ALRBMF

pub fn wutmf(&self) -> WUTMF_R

Bit 2 - WUTMF

pub fn tsmf(&self) -> TSMF_R

Bit 3 - TSMF

pub fn tsovmf(&self) -> TSOVMF_R

Bit 4 - TSOVMF

pub fn itsmf(&self) -> ITSMF_R

Bit 5 - ITSMF

impl R<u32, Reg<u32, _SCR>>

pub fn calraf(&self) -> CALRAF_R

Bit 0 - CALRAF

pub fn calrbf(&self) -> CALRBF_R

Bit 1 - CALRBF

pub fn cwutf(&self) -> CWUTF_R

Bit 2 - CWUTF

pub fn ctsf(&self) -> CTSF_R

Bit 3 - CTSF

pub fn ctsovf(&self) -> CTSOVF_R

Bit 4 - CTSOVF

pub fn citsf(&self) -> CITSF_R

Bit 5 - CITSF

impl R<u32, Reg<u32, _HWCFGR>>

pub fn alarmb(&self) -> ALARMB_R

Bits 0:3 - ALARMB

pub fn wakeup(&self) -> WAKEUP_R

Bits 4:7 - WAKEUP

pub fn smooth_calib(&self) -> SMOOTH_CALIB_R

Bits 8:11 - SMOOTH_CALIB

pub fn timestamp(&self) -> TIMESTAMP_R

Bits 12:15 - TIMESTAMP

pub fn optionreg_out(&self) -> OPTIONREG_OUT_R

Bits 16:23 - OPTIONREG_OUT

pub fn trust_zone(&self) -> TRUST_ZONE_R

Bits 24:27 - TRUST_ZONE

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _DIER>>

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - CC1S

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - OC1FE

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - OC1PE

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - OC1M

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - OC1CE

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn icpcs(&self) -> ICPCS_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _TISEL>>

pub fn tisel(&self) -> TISEL_R

Bits 0:3 - TI1[0] to TI1[15] input selection

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

impl R<u32, Reg<u32, _SMCR>>

pub fn ts_4_3(&self) -> TS_4_3_R

Bits 20:21 - Trigger selection

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&self) -> IC3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt_h(&self) -> CNT_H_R

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt_l(&self) -> CNT_L_R

Bits 0:15 - Low counter value

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr_h(&self) -> ARR_H_R

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&self) -> ARR_L_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&self) -> CCR1_H_R

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&self) -> CCR1_L_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&self) -> CCR2_H_R

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&self) -> CCR2_L_R

Bits 0:15 - Low Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&self) -> CCR3_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&self) -> CCR3_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&self) -> CCR4_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&self) -> CCR4_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR1>>

pub fn iocref_clr(&self) -> IOCREF_CLR_R

Bit 0 - IOCREF_CLR

impl R<u32, Reg<u32, _AF1>>

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:17 - External trigger source selection

impl R<u32, Reg<u32, _TISEL>>

pub fn ti1sel(&self) -> TI1SEL_R

Bits 0:3 - TI1SEL

pub fn ti2sel(&self) -> TI2SEL_R

Bits 8:11 - TI2SEL

impl R<u32, Reg<u32, _CSR>>

pub fn enable(&self) -> ENABLE_R

Bit 0 - Counter enable

pub fn tickint(&self) -> TICKINT_R

Bit 1 - SysTick exception request enable

pub fn clksource(&self) -> CLKSOURCE_R

Bit 2 - Clock source selection

pub fn countflag(&self) -> COUNTFLAG_R

Bit 16 - COUNTFLAG

impl R<u32, Reg<u32, _RVR>>

pub fn reload(&self) -> RELOAD_R

Bits 0:23 - RELOAD value

impl R<u32, Reg<u32, _CVR>>

pub fn current(&self) -> CURRENT_R

Bits 0:23 - Current counter value

impl R<u32, Reg<u32, _CALIB>>

pub fn tenms(&self) -> TENMS_R

Bits 0:23 - Calibration value

pub fn skew(&self) -> SKEW_R

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&self) -> NOREF_R

Bit 31 - NOREF flag. Reads as zero

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 

fn eq(&self, other: &FI) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]pub fn ne(&self, other: &Rhs) -> bool

This method tests for !=.