Struct CFGR

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pub struct CFGR { /* private fields */ }
Expand description

Clock configuration register.

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impl CFGR

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pub fn hse(self, hse: HSEClock) -> Self

Configures the HSE oscillator.

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pub fn hclk(self, freq: Hertz) -> Self

Sets HCLK frequency.

The HCLK is used for the AHB bus, core, memory and DMA.

§Panics

Panics if the frequency is larger than 216 MHz.

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pub fn sysclk(self, sysclk: Hertz) -> Self

Sets the SYSCLK frequency.

This sets the SYSCLK frequency and sets up the USB clock if defined. The provided frequency must be between 12.5 Mhz and 216 Mhz. 12.5 Mhz is the VCO minimum frequency and SYSCLK PLLP divider limitation. If the ethernet peripheral is on, the user should set a frequency higher than 25 Mhz.

§Panics

Panics if the frequency is not between 12.5 MHz and 216 MHz.

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pub fn pclk1(self, freq: Hertz) -> Self

Sets the PCLK1 clock (APB1 clock).

If this method isn’t called the maximum allowed frequency is used for PCLK1.

§Panics

Panics if the frequency is not between 12.5 MHz and 54 MHz.

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pub fn pclk2(self, freq: Hertz) -> Self

Sets PCLK2 clock (APB2 clock).

If this method isn’t called the maximum allowed frequency is used for PCLK2.

§Panics

Panics if the frequency is not between 12.5 MHz and 108 MHz.

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pub fn lse(self, lse: LSEClock) -> Self

Sets the LSE clock source to 32.768 kHz.

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pub fn lsi(self) -> Self

Sets the LSI clock source to 32 kHz.

Be aware that the tolerance is up to ±47% (Min 17 kHz, Typ 32 kHz, Max 47 kHz).

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pub fn use_pll(self) -> Self

Sets the SYSCLK clock source to the main PLL.

Note: sysclk must be specified or use_pll48clk must be set to true, otherwise use_pll is reset to false.

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pub fn use_pll48clk(self, pll48clk: PLL48CLK) -> Self

Sets the 48 MHz clock source.

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pub fn pllm(self, pllm: u8) -> Self

Sets the common PLL division factor.

§Panics

Panics if the division factor isn’t between 2 and 63.

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pub fn plln(self, plln: u16) -> Self

Sets the PLL multiplication factor for the main PLL.

§Panics

Panics if the multiplication factor isn’t between 50 and 432 (inclusive).

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pub fn pllp(self, pllp: PLLP) -> Self

Sets the PLL division factor for the main PLL.

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pub fn pllq(self, pllq: u8) -> Self

Sets the PLL division factor for the 48 MHz clock.

§Panics

Panics if the division factor isn’t between 2 and 15 (inclusive).

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pub fn use_pllsai(self) -> Self

Enables the PLLSAI clock source.

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pub fn pllsain(self, pllsain: u16) -> Self

Sets the PLLSAIN multiplication factor for PLLSAI.

§Panics

Panics if the multiplication factor isn’t between 50 and 432.

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pub fn pllsaip(self, pllsaip: PLLSAIP) -> Self

Sets the PLLSAIP division factor for PLLSAI.

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pub fn pllsaiq(self, pllsaiq: u8) -> Self

Sets the PLLSAIQ division factor for PLLSAIS.

§Panics

Panics if the division factor isn’t between 2 and 15.

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pub fn use_plli2s(self) -> Self

Enables the PLLI2S clock source.

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pub fn plli2sn(self, plli2sn: u16) -> Self

Sets the PLLI2SN multiplication factor for PLLI2S.

§Panics

Panics if the multiplication factor isn’t between 50 and 432.

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pub fn plli2sq(self, plli2sq: u8) -> Self

Sets the PLLI2SQ division factor for PLLI2S.

§Panics

Panics if the division factor isn’t between 2 and 15.

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pub fn plli2sr(self, plli2sr: u8) -> Self

Sets the PLLI2SR division factor for PLLI2S.

§Panics

Panics if the division factor isn’t between 2 and 7.

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pub fn mco1(self, mco1: MCO1) -> Self

Sets the MCO1 source

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pub fn mco1pre(self, mco1pre: MCOPRE) -> Self

Sets the MCO1 division factors

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pub fn mco2(self, mco2: MCO2) -> Self

Sets the MCO2 source

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pub fn mco2pre(self, mco2pre: MCOPRE) -> Self

Sets the MCO2 division factors

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pub fn set_defaults(self) -> Self

Configures the default clock settings.

Set SYSCLK as 216 Mhz and setup USB clock if defined.

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pub fn freeze(self) -> Clocks

Configure the “mandatory” clocks (sysclk, hclk, pclk1 and pclk2') and return them via the Clocks` struct.

The user shouldn’t call freeze more than once as the clocks parameters cannot be changed after the clocks have started.

The implementation makes the following choice: HSI is always chosen over HSE except when HSE is provided. When HSE is provided, HSE is used wherever it is possible.

Trait Implementations§

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impl Debug for CFGR

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl PartialEq for CFGR

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fn eq(&self, other: &CFGR) -> bool

Tests for self and other values to be equal, and is used by ==.
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fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl Eq for CFGR

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impl StructuralPartialEq for CFGR

Auto Trait Implementations§

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impl Freeze for CFGR

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impl RefUnwindSafe for CFGR

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impl Send for CFGR

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impl Sync for CFGR

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impl Unpin for CFGR

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impl UnwindSafe for CFGR

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.