Expand description
Reset and clock control.
Structs§
- AHB1
- Advanced High-performance Bus 1 (AHB1) registers
- AHB2
- Advanced High-performance Bus 2 (AHB2) registers
- AHB3
- Advanced High-performance Bus 3 (AHB3) registers
- APB1
- Advanced Peripheral Bus 1 (APB1) registers
- APB2
- Advanced Peripheral Bus 2 (APB2) registers
- BDCR
- Backup Domain Control register (RCC_BDCR)
- CFGR
- Clock configuration register.
- Clocks
- Frozen clock frequencies
- HSEClock
- HSE Clock.
- LSEClock
- LSE Clock.
- Rcc
- Constrained RCC peripheral
Enums§
- HSEClock
Mode - HSE clock mode.
- LSEClock
Mode - LSE clock mode.
- MCO1
- Microcontroller clock output 1
- MCO2
- Microcontroller clock output 2
- MCOPRE
- MCO prescaler
- PLL48CLK
- PLL48CLK clock source selection
- PLLP
- PLL P division factors.
- PLLSAIP
- PLLSAIP division factors.
Traits§
- BusClock
- Frequency on bus that peripheral is connected in
- BusTimer
Clock - Frequency on bus that timer is connected in
- Enable
- Enable/disable peripheral
- LPEnable
- Enable/disable peripheral in low power mode
- RccBus
- Bus associated to peripheral
- RccExt
- Extension trait that constrains the
RCCperipheral - Reset
- Reset peripheral