pub struct RCC { /* private fields */ }
Expand description
Reset and clock control
See peripheral structure
Implementations§
Source§impl RCC
impl RCC
Sourcepub const PTR: *const RegisterBlock = {0x40023800 as *const stm32f4_staging::stm32f429::rcc::RegisterBlock}
pub const PTR: *const RegisterBlock = {0x40023800 as *const stm32f4_staging::stm32f429::rcc::RegisterBlock}
Pointer to the register block
Sourcepub const fn ptr() -> *const RegisterBlock
pub const fn ptr() -> *const RegisterBlock
Return the pointer to the register block
Sourcepub unsafe fn steal() -> RCC
pub unsafe fn steal() -> RCC
Steal an instance of this peripheral
§Safety
Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.
Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.
Methods from Deref<Target = RegisterBlock>§
Sourcepub fn ahb1rstr(&self) -> &Reg<AHB1RSTRrs>
pub fn ahb1rstr(&self) -> &Reg<AHB1RSTRrs>
0x10 - AHB1 peripheral reset register
Sourcepub fn ahb2rstr(&self) -> &Reg<AHB2RSTRrs>
pub fn ahb2rstr(&self) -> &Reg<AHB2RSTRrs>
0x14 - AHB2 peripheral reset register
Sourcepub fn ahb3rstr(&self) -> &Reg<AHB3RSTRrs>
pub fn ahb3rstr(&self) -> &Reg<AHB3RSTRrs>
0x18 - AHB3 peripheral reset register
Sourcepub fn apb1rstr(&self) -> &Reg<APB1RSTRrs>
pub fn apb1rstr(&self) -> &Reg<APB1RSTRrs>
0x20 - APB1 peripheral reset register
Sourcepub fn apb2rstr(&self) -> &Reg<APB2RSTRrs>
pub fn apb2rstr(&self) -> &Reg<APB2RSTRrs>
0x24 - APB2 peripheral reset register
Sourcepub fn ahb1lpenr(&self) -> &Reg<AHB1LPENRrs>
pub fn ahb1lpenr(&self) -> &Reg<AHB1LPENRrs>
0x50 - AHB1 peripheral clock enable in low power mode register
Sourcepub fn ahb2lpenr(&self) -> &Reg<AHB2LPENRrs>
pub fn ahb2lpenr(&self) -> &Reg<AHB2LPENRrs>
0x54 - AHB2 peripheral clock enable in low power mode register
Sourcepub fn ahb3lpenr(&self) -> &Reg<AHB3LPENRrs>
pub fn ahb3lpenr(&self) -> &Reg<AHB3LPENRrs>
0x58 - AHB3 peripheral clock enable in low power mode register
Sourcepub fn apb1lpenr(&self) -> &Reg<APB1LPENRrs>
pub fn apb1lpenr(&self) -> &Reg<APB1LPENRrs>
0x60 - APB1 peripheral clock enable in low power mode register
Sourcepub fn apb2lpenr(&self) -> &Reg<APB2LPENRrs>
pub fn apb2lpenr(&self) -> &Reg<APB2LPENRrs>
0x64 - APB2 peripheral clock enabled in low power mode register
Sourcepub fn plli2scfgr(&self) -> &Reg<PLLI2SCFGRrs>
pub fn plli2scfgr(&self) -> &Reg<PLLI2SCFGRrs>
0x84 - PLLI2S configuration register
Sourcepub fn pllsaicfgr(&self) -> &Reg<PLLSAICFGRrs>
pub fn pllsaicfgr(&self) -> &Reg<PLLSAICFGRrs>
0x88 - RCC PLL configuration register