pub struct Timer<TIM> { /* private fields */ }
Expand description
Hardware timers
Implementations§
Source§impl Timer<TIM1>
impl Timer<TIM1>
Sourcepub fn tim1<T>(tim: TIM1, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
pub fn tim1<T>(tim: TIM1, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM2>
impl Timer<TIM2>
Sourcepub fn tim2<T>(tim: TIM2, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
pub fn tim2<T>(tim: TIM2, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM3>
impl Timer<TIM3>
Sourcepub fn tim3<T>(tim: TIM3, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
pub fn tim3<T>(tim: TIM3, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM4>
impl Timer<TIM4>
Sourcepub fn tim4<T>(tim: TIM4, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
pub fn tim4<T>(tim: TIM4, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM6>
impl Timer<TIM6>
Sourcepub fn tim6<T>(tim: TIM6, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
pub fn tim6<T>(tim: TIM6, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM7>
impl Timer<TIM7>
Sourcepub fn tim7<T>(tim: TIM7, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
pub fn tim7<T>(tim: TIM7, timeout: T, clocks: Clocks, apb1: &mut APB1) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM8>
impl Timer<TIM8>
Sourcepub fn tim8<T>(tim: TIM8, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
pub fn tim8<T>(tim: TIM8, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM15>
impl Timer<TIM15>
Sourcepub fn tim15<T>(tim: TIM15, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
pub fn tim15<T>(tim: TIM15, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM16>
impl Timer<TIM16>
Sourcepub fn tim16<T>(tim: TIM16, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
pub fn tim16<T>(tim: TIM16, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM17>
impl Timer<TIM17>
Sourcepub fn tim17<T>(tim: TIM17, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
pub fn tim17<T>(tim: TIM17, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM20>
impl Timer<TIM20>
Sourcepub fn tim20<T>(tim: TIM20, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
pub fn tim20<T>(tim: TIM20, timeout: T, clocks: Clocks, apb2: &mut APB2) -> Self
Configures a TIM peripheral as a periodic count down timer
Sourcepub fn clear_update_interrupt_flag(&mut self)
pub fn clear_update_interrupt_flag(&mut self)
Clears Update Interrupt Flag
Sourcepub fn set_period(
&mut self,
period: f32,
clocks: &Clocks,
) -> Result<(), ValueError>
pub fn set_period( &mut self, period: f32, clocks: &Clocks, ) -> Result<(), ValueError>
Set the timer period, in seconds. Overrides the period or frequency set in the constructor. This allows you to set periods greater than 1hz.
Sourcepub fn reset_countdown(&mut self)
pub fn reset_countdown(&mut self)
Reset the countdown; set the counter to 0.
Source§impl Timer<TIM2>
impl Timer<TIM2>
Sourcepub fn set_resolution(&mut self, word: u32)
pub fn set_resolution(&mut self, word: u32)
Set the value of the auto-reload resolution. Use a lower value to increase precision. If you wish for a precise tick speed, multiply the system clock speed by the desired frequency, then round to the nearest integer.
Sourcepub fn set_output_compare(&mut self, channel: Channel, mode: OutputCompare)
pub fn set_output_compare(&mut self, channel: Channel, mode: OutputCompare)
Set Output Compare Mode. See docs on the OutputCompare
enum.
Sourcepub fn get_duty(&self, channel: Channel) -> u32
pub fn get_duty(&self, channel: Channel) -> u32
Return the set duty period for a given channel. Divide by get_max_duty()
to find the portion of the duty cycle used.
Sourcepub fn set_duty(&mut self, channel: Channel, duty: u32)
pub fn set_duty(&mut self, channel: Channel, duty: u32)
Set the duty cycle, as a portion of get_max_duty()
.
Sourcepub fn get_max_duty(&self) -> u32
pub fn get_max_duty(&self) -> u32
Return the integer associated with the maximum duty period. todo: Duty could be u16 for low-precision timers.
Sourcepub fn set_alignment(&mut self, alignment: Alignment)
pub fn set_alignment(&mut self, alignment: Alignment)
Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
Sourcepub fn set_polarity(&mut self, channel: Channel, polarity: Polarity)
pub fn set_polarity(&mut self, channel: Channel, polarity: Polarity)
Set output polarity. See docs on the Polarity
enum.
Sourcepub fn set_complementary_polarity(
&mut self,
channel: Channel,
polarity: Polarity,
)
pub fn set_complementary_polarity( &mut self, channel: Channel, polarity: Polarity, )
Set complementary output polarity. See docs on the Polarity
enum.
Sourcepub fn set_capture_compare(&mut self, channel: Channel, mode: CaptureCompare)
pub fn set_capture_compare(&mut self, channel: Channel, mode: CaptureCompare)
Set Capture Compare Mode. See docs on the CaptureCompare
enum.
Sourcepub fn set_preload(&mut self, channel: Channel, value: bool)
pub fn set_preload(&mut self, channel: Channel, value: bool)
Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Setting preload is required to enable PWM.
Source§impl Timer<TIM3>
impl Timer<TIM3>
Sourcepub fn set_resolution(&mut self, word: u16)
pub fn set_resolution(&mut self, word: u16)
Set the value of the auto-reload resolution. Use a lower value to increase precision. If you wish for a precise tick speed, multiply the system clock speed by the desired frequency, then round to the nearest integer.
Sourcepub fn set_output_compare(&mut self, channel: Channel, mode: OutputCompare)
pub fn set_output_compare(&mut self, channel: Channel, mode: OutputCompare)
Set Output Compare Mode. See docs on the OutputCompare
enum.
Sourcepub fn get_duty(&self, channel: Channel) -> u16
pub fn get_duty(&self, channel: Channel) -> u16
Return the set duty period for a given channel. Divide by get_max_duty()
to find the portion of the duty cycle used.
Sourcepub fn set_duty(&mut self, channel: Channel, duty: u16)
pub fn set_duty(&mut self, channel: Channel, duty: u16)
Set the duty cycle, as a portion of get_max_duty()
.
Sourcepub fn get_max_duty(&self) -> u16
pub fn get_max_duty(&self) -> u16
Return the integer associated with the maximum duty period. todo: Duty could be u16 for low-precision timers.
Sourcepub fn set_alignment(&mut self, alignment: Alignment)
pub fn set_alignment(&mut self, alignment: Alignment)
Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
Sourcepub fn set_polarity(&mut self, channel: Channel, polarity: Polarity)
pub fn set_polarity(&mut self, channel: Channel, polarity: Polarity)
Set output polarity. See docs on the Polarity
enum.
Sourcepub fn set_complementary_polarity(
&mut self,
channel: Channel,
polarity: Polarity,
)
pub fn set_complementary_polarity( &mut self, channel: Channel, polarity: Polarity, )
Set complementary output polarity. See docs on the Polarity
enum.
Sourcepub fn set_capture_compare(&mut self, channel: Channel, mode: CaptureCompare)
pub fn set_capture_compare(&mut self, channel: Channel, mode: CaptureCompare)
Set Capture Compare Mode. See docs on the CaptureCompare
enum.
Sourcepub fn set_preload(&mut self, channel: Channel, value: bool)
pub fn set_preload(&mut self, channel: Channel, value: bool)
Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Setting preload is required to enable PWM.
Source§impl Timer<TIM4>
impl Timer<TIM4>
Sourcepub fn set_resolution(&mut self, word: u16)
pub fn set_resolution(&mut self, word: u16)
Set the value of the auto-reload resolution. Use a lower value to increase precision. If you wish for a precise tick speed, multiply the system clock speed by the desired frequency, then round to the nearest integer.
Sourcepub fn set_output_compare(&mut self, channel: Channel, mode: OutputCompare)
pub fn set_output_compare(&mut self, channel: Channel, mode: OutputCompare)
Set Output Compare Mode. See docs on the OutputCompare
enum.
Sourcepub fn get_duty(&self, channel: Channel) -> u16
pub fn get_duty(&self, channel: Channel) -> u16
Return the set duty period for a given channel. Divide by get_max_duty()
to find the portion of the duty cycle used.
Sourcepub fn set_duty(&mut self, channel: Channel, duty: u16)
pub fn set_duty(&mut self, channel: Channel, duty: u16)
Set the duty cycle, as a portion of get_max_duty()
.
Sourcepub fn get_max_duty(&self) -> u16
pub fn get_max_duty(&self) -> u16
Return the integer associated with the maximum duty period. todo: Duty could be u16 for low-precision timers.
Sourcepub fn set_alignment(&mut self, alignment: Alignment)
pub fn set_alignment(&mut self, alignment: Alignment)
Set timer alignment to Edge, or one of 3 center modes. STM32F303 ref man, section 21.4.1: Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
Sourcepub fn set_polarity(&mut self, channel: Channel, polarity: Polarity)
pub fn set_polarity(&mut self, channel: Channel, polarity: Polarity)
Set output polarity. See docs on the Polarity
enum.
Sourcepub fn set_complementary_polarity(
&mut self,
channel: Channel,
polarity: Polarity,
)
pub fn set_complementary_polarity( &mut self, channel: Channel, polarity: Polarity, )
Set complementary output polarity. See docs on the Polarity
enum.
Sourcepub fn set_capture_compare(&mut self, channel: Channel, mode: CaptureCompare)
pub fn set_capture_compare(&mut self, channel: Channel, mode: CaptureCompare)
Set Capture Compare Mode. See docs on the CaptureCompare
enum.
Sourcepub fn set_preload(&mut self, channel: Channel, value: bool)
pub fn set_preload(&mut self, channel: Channel, value: bool)
Set preload mode. OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Setting preload is required to enable PWM.