pub struct W<U, REG> { /* fields omitted */ }
Expand description
Register writer
Used as an argument to the closures in the write
and modify
methods of the register
pub unsafe fn bits(&mut self, bits: U) -> &mut Self
[src]
Writes raw bits to the register
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bit 15
Bit 14 - Port x configuration bit 14
Bit 13 - Port x configuration bit 13
Bit 12 - Port x configuration bit 12
Bit 11 - Port x configuration bit 11
Bit 10 - Port x configuration bit 10
Bit 9 - Port x configuration bit 9
Bit 8 - Port x configuration bit 8
Bit 7 - Port x configuration bit 7
Bit 6 - Port x configuration bit 6
Bit 5 - Port x configuration bit 5
Bit 4 - Port x configuration bit 4
Bit 3 - Port x configuration bit 3
Bit 2 - Port x configuration bit 2
Bit 1 - Port x configuration bit 1
Bit 0 - Port x configuration bit 0
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 28:31 - Charge transfer pulse high
Bits 24:27 - Charge transfer pulse low
Bits 17:23 - Spread spectrum deviation
Bit 16 - Spread spectrum enable
Bit 15 - Spread spectrum prescaler
Bits 12:14 - pulse generator prescaler
Bits 5:7 - Max count value
Bit 3 - Synchronization pin polarity
Bit 1 - Start a new acquisition
Bit 0 - Touch sensing controller enable
Bit 1 - Max count error interrupt enable
Bit 0 - End of acquisition interrupt enable
Bit 1 - Max count error interrupt clear
Bit 0 - End of acquisition interrupt clear
Bit 1 - Max count error flag
Bit 0 - End of acquisition flag
Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
Bit 24 - G7_IO1 Schmitt trigger hysteresis mode
Bit 25 - G7_IO2 Schmitt trigger hysteresis mode
Bit 26 - G7_IO3 Schmitt trigger hysteresis mode
Bit 27 - G7_IO4 Schmitt trigger hysteresis mode
Bit 28 - G8_IO1 Schmitt trigger hysteresis mode
Bit 29 - G8_IO2 Schmitt trigger hysteresis mode
Bit 30 - G8_IO3 Schmitt trigger hysteresis mode
Bit 31 - G8_IO4 Schmitt trigger hysteresis mode
Bit 0 - G1_IO1 analog switch enable
Bit 1 - G1_IO2 analog switch enable
Bit 2 - G1_IO3 analog switch enable
Bit 3 - G1_IO4 analog switch enable
Bit 4 - G2_IO1 analog switch enable
Bit 5 - G2_IO2 analog switch enable
Bit 6 - G2_IO3 analog switch enable
Bit 7 - G2_IO4 analog switch enable
Bit 8 - G3_IO1 analog switch enable
Bit 9 - G3_IO2 analog switch enable
Bit 10 - G3_IO3 analog switch enable
Bit 11 - G3_IO4 analog switch enable
Bit 12 - G4_IO1 analog switch enable
Bit 13 - G4_IO2 analog switch enable
Bit 14 - G4_IO3 analog switch enable
Bit 15 - G4_IO4 analog switch enable
Bit 16 - G5_IO1 analog switch enable
Bit 17 - G5_IO2 analog switch enable
Bit 18 - G5_IO3 analog switch enable
Bit 19 - G5_IO4 analog switch enable
Bit 20 - G6_IO1 analog switch enable
Bit 21 - G6_IO2 analog switch enable
Bit 22 - G6_IO3 analog switch enable
Bit 23 - G6_IO4 analog switch enable
Bit 24 - G7_IO1 analog switch enable
Bit 25 - G7_IO2 analog switch enable
Bit 26 - G7_IO3 analog switch enable
Bit 27 - G7_IO4 analog switch enable
Bit 28 - G8_IO1 analog switch enable
Bit 29 - G8_IO2 analog switch enable
Bit 30 - G8_IO3 analog switch enable
Bit 31 - G8_IO4 analog switch enable
Bit 0 - G1_IO1 sampling mode
Bit 1 - G1_IO2 sampling mode
Bit 2 - G1_IO3 sampling mode
Bit 3 - G1_IO4 sampling mode
Bit 4 - G2_IO1 sampling mode
Bit 5 - G2_IO2 sampling mode
Bit 6 - G2_IO3 sampling mode
Bit 7 - G2_IO4 sampling mode
Bit 8 - G3_IO1 sampling mode
Bit 9 - G3_IO2 sampling mode
Bit 10 - G3_IO3 sampling mode
Bit 11 - G3_IO4 sampling mode
Bit 12 - G4_IO1 sampling mode
Bit 13 - G4_IO2 sampling mode
Bit 14 - G4_IO3 sampling mode
Bit 15 - G4_IO4 sampling mode
Bit 16 - G5_IO1 sampling mode
Bit 17 - G5_IO2 sampling mode
Bit 18 - G5_IO3 sampling mode
Bit 19 - G5_IO4 sampling mode
Bit 20 - G6_IO1 sampling mode
Bit 21 - G6_IO2 sampling mode
Bit 22 - G6_IO3 sampling mode
Bit 23 - G6_IO4 sampling mode
Bit 24 - G7_IO1 sampling mode
Bit 25 - G7_IO2 sampling mode
Bit 26 - G7_IO3 sampling mode
Bit 27 - G7_IO4 sampling mode
Bit 28 - G8_IO1 sampling mode
Bit 29 - G8_IO2 sampling mode
Bit 30 - G8_IO3 sampling mode
Bit 31 - G8_IO4 sampling mode
Bit 0 - G1_IO1 channel mode
Bit 1 - G1_IO2 channel mode
Bit 2 - G1_IO3 channel mode
Bit 3 - G1_IO4 channel mode
Bit 4 - G2_IO1 channel mode
Bit 5 - G2_IO2 channel mode
Bit 6 - G2_IO3 channel mode
Bit 7 - G2_IO4 channel mode
Bit 8 - G3_IO1 channel mode
Bit 9 - G3_IO2 channel mode
Bit 10 - G3_IO3 channel mode
Bit 11 - G3_IO4 channel mode
Bit 12 - G4_IO1 channel mode
Bit 13 - G4_IO2 channel mode
Bit 14 - G4_IO3 channel mode
Bit 15 - G4_IO4 channel mode
Bit 16 - G5_IO1 channel mode
Bit 17 - G5_IO2 channel mode
Bit 18 - G5_IO3 channel mode
Bit 19 - G5_IO4 channel mode
Bit 20 - G6_IO1 channel mode
Bit 21 - G6_IO2 channel mode
Bit 22 - G6_IO3 channel mode
Bit 23 - G6_IO4 channel mode
Bit 24 - G7_IO1 channel mode
Bit 25 - G7_IO2 channel mode
Bit 26 - G7_IO3 channel mode
Bit 27 - G7_IO4 channel mode
Bit 28 - G8_IO1 channel mode
Bit 29 - G8_IO2 channel mode
Bit 30 - G8_IO3 channel mode
Bit 31 - G8_IO4 channel mode
Bit 23 - Analog I/O group x status
Bit 22 - Analog I/O group x status
Bit 7 - Analog I/O group x enable
Bit 6 - Analog I/O group x enable
Bit 5 - Analog I/O group x enable
Bit 4 - Analog I/O group x enable
Bit 3 - Analog I/O group x enable
Bit 2 - Analog I/O group x enable
Bit 1 - Analog I/O group x enable
Bit 0 - Analog I/O group x enable
Bits 0:31 - Data register bits
Bits 0:7 - General-purpose 8-bit data register bits
Bits 3:4 - Polynomial size
Bits 5:6 - Reverse input data
Bit 7 - Reverse output data
Bits 0:31 - Programmable initial CRC value
Bits 0:31 - Programmable polynomial
Bits 0:7 - Data register bits
Bits 0:15 - Data register bits
Bit 3 - Flash half cycle access enable
Bits 0:31 - Option byte key
Bit 4 - Write protection error
Bit 2 - Programming error
Bit 13 - Force option byte loading
Bit 12 - End of operation interrupt enable
Bit 10 - Error interrupt enable
Bit 9 - Option bytes write enable
Bit 5 - Option byte erase
Bit 4 - Option byte programming
Bits 0:31 - Flash address
Bit 0 - Internal High Speed clock enable
Bits 3:7 - Internal High Speed clock trimming
Bit 16 - External High Speed clock enable
Bit 18 - External High Speed clock Bypass
Bit 19 - Clock Security System enable
Bits 0:1 - System clock Switch
Bits 8:10 - APB Low speed prescaler (APB1)
Bits 11:13 - APB high speed prescaler (APB2)
Bits 15:16 - PLL entry clock source
Bit 17 - HSE divider for PLL entry
Bits 18:21 - PLL Multiplication Factor
Bits 24:26 - Microcontroller clock output
Bit 23 - I2S external clock source selection
Bits 28:30 - Microcontroller Clock Output Prescaler
Bit 31 - Do not divide PLL to MCO
Bit 8 - LSI Ready Interrupt Enable
Bit 9 - LSE Ready Interrupt Enable
Bit 10 - HSI Ready Interrupt Enable
Bit 11 - HSE Ready Interrupt Enable
Bit 12 - PLL Ready Interrupt Enable
Bit 16 - LSI Ready Interrupt Clear
Bit 17 - LSE Ready Interrupt Clear
Bit 18 - HSI Ready Interrupt Clear
Bit 19 - HSE Ready Interrupt Clear
Bit 20 - PLL Ready Interrupt Clear
Bit 23 - Clock security system interrupt clear
Bit 0 - SYSCFG and COMP reset
Bit 11 - TIM1 timer reset
Bit 16 - TIM15 timer reset
Bit 17 - TIM16 timer reset
Bit 18 - TIM17 timer reset
Bit 11 - Window watchdog reset
Bit 28 - Power interface reset
Bit 29 - DAC interface reset
Bit 0 - DMA1 clock enable
Bit 1 - DMA2 clock enable
Bit 2 - SRAM interface clock enable
Bit 4 - FLITF clock enable
Bit 17 - I/O port A clock enable
Bit 18 - I/O port B clock enable
Bit 19 - I/O port C clock enable
Bit 20 - I/O port D clock enable
Bit 21 - I/O port E clock enable
Bit 22 - I/O port F clock enable
Bit 24 - Touch sensing controller clock enable
Bit 28 - ADC1 and ADC2 clock enable
Bit 16 - IO port H clock enable
Bit 23 - IO port G clock enable
Bit 0 - SYSCFG clock enable
Bit 11 - TIM1 Timer clock enable
Bit 12 - SPI 1 clock enable
Bit 14 - USART1 clock enable
Bit 16 - TIM15 timer clock enable
Bit 17 - TIM16 timer clock enable
Bit 18 - TIM17 timer clock enable
Bit 15 - SPI4 clock enable
Bit 0 - Timer 2 clock enable
Bit 1 - Timer 3 clock enable
Bit 2 - Timer 4 clock enable
Bit 4 - Timer 6 clock enable
Bit 11 - Window watchdog clock enable
Bit 14 - SPI 2 clock enable
Bit 15 - SPI 3 clock enable
Bit 17 - USART 2 clock enable
Bit 21 - I2C 1 clock enable
Bit 22 - I2C 2 clock enable
Bit 23 - USB clock enable
Bit 25 - CAN clock enable
Bit 28 - Power interface clock enable
Bit 29 - DAC interface clock enable
Bit 18 - USART3 clock enable
Bit 19 - UART4 clock enable
Bit 20 - UART5 clock enable
Bit 30 - I2C3 clock enable
Bit 0 - External Low Speed oscillator enable
Bit 2 - External Low Speed oscillator bypass
Bits 3:4 - LSE oscillator drive capability
Bits 8:9 - RTC clock source selection
Bit 15 - RTC clock enable
Bit 16 - Backup domain software reset
Bit 0 - Internal low speed oscillator enable
Bit 24 - Remove reset flag
Bit 25 - Option byte loader reset flag
Bit 27 - POR/PDR reset flag
Bit 28 - Software reset flag
Bit 29 - Independent watchdog reset flag
Bit 30 - Window watchdog reset flag
Bit 31 - Low-power reset flag
Bit 23 - Reset flag of the 1.8 V domain
Bit 17 - I/O port A reset
Bit 18 - I/O port B reset
Bit 19 - I/O port C reset
Bit 20 - I/O port D reset
Bit 21 - I/O port E reset
Bit 22 - I/O port F reset
Bit 24 - Touch sensing controller reset
Bit 28 - ADC1 and ADC2 reset
Bits 0:3 - PREDIV division factor
Bits 4:8 - ADC1 and ADC2 prescaler
Bits 0:1 - USART1 clock source selection
Bit 4 - I2C1 clock source selection
Bit 5 - I2C2 clock source selection
Bits 16:17 - USART2 clock source selection
Bits 18:19 - USART3 clock source selection
Bit 8 - Timer1 clock source selection
Bits 20:21 - UART4 clock source selection
Bits 22:23 - UART5 clock source selection
Bit 6 - I2C3 clock source selection
Bit 10 - Timer15 clock source selection
Bit 11 - Timer16 clock source selection
Bit 13 - Timer17 clock source selection
Bit 24 - Timer2 clock source selection
Bit 25 - Timer34 clock source selection
Bit 1 - Transfer complete interrupt enable
Bit 2 - Half Transfer interrupt enable
Bit 3 - Transfer error interrupt enable
Bit 4 - Data transfer direction
Bit 6 - Peripheral increment mode
Bit 7 - Memory increment mode
Bits 8:9 - Peripheral size
Bits 12:13 - Channel Priority level
Bit 14 - Memory to memory mode
Bits 0:15 - Number of data to transfer
Bits 0:31 - Peripheral address
Bits 0:31 - Memory address
Bit 0 - Channel 1 Global interrupt clear
Bit 1 - Channel 1 Transfer Complete clear
Bit 2 - Channel 1 Half Transfer clear
Bit 3 - Channel 1 Transfer Error clear
Bit 4 - Channel 2 Global interrupt clear
Bit 5 - Channel 2 Transfer Complete clear
Bit 6 - Channel 2 Half Transfer clear
Bit 7 - Channel 2 Transfer Error clear
Bit 8 - Channel 3 Global interrupt clear
Bit 9 - Channel 3 Transfer Complete clear
Bit 10 - Channel 3 Half Transfer clear
Bit 11 - Channel 3 Transfer Error clear
Bit 12 - Channel 4 Global interrupt clear
Bit 13 - Channel 4 Transfer Complete clear
Bit 14 - Channel 4 Half Transfer clear
Bit 15 - Channel 4 Transfer Error clear
Bit 16 - Channel 5 Global interrupt clear
Bit 17 - Channel 5 Transfer Complete clear
Bit 18 - Channel 5 Half Transfer clear
Bit 19 - Channel 5 Transfer Error clear
Bit 20 - Channel 6 Global interrupt clear
Bit 21 - Channel 6 Transfer Complete clear
Bit 22 - Channel 6 Half Transfer clear
Bit 23 - Channel 6 Transfer Error clear
Bit 24 - Channel 7 Global interrupt clear
Bit 25 - Channel 7 Transfer Complete clear
Bit 26 - Channel 7 Half Transfer clear
Bit 27 - Channel 7 Transfer Error clear
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit3
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output compare 1 fast enable
Bit 3 - Output compare 1 preload enable
Bits 4:6 - Output compare 1 mode
Bit 7 - Output compare 1 clear enable
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output compare 2 fast enable
Bit 11 - Output compare 2 preload enable
Bits 12:14 - Output compare 2 mode
Bit 15 - Output compare 2 clear enable
Bit 16 - Output compare 1 mode bit 3
Bit 24 - Output compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bits 0:1 - Capture/Compare 3 selection
Bit 2 - Output compare 3 fast enable
Bit 3 - Output compare 3 preload enable
Bits 4:6 - Output compare 3 mode
Bit 7 - Output compare 3 clear enable
Bits 8:9 - Capture/Compare 4 selection
Bit 10 - Output compare 4 fast enable
Bit 11 - Output compare 4 preload enable
Bits 12:14 - Output compare 4 mode
Bit 15 - Output compare 4 clear enable
Bit 16 - Output compare 3 mode bit3
Bit 24 - Output compare 4 mode bit3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:31 - Low counter value
Bits 0:15 - Prescaler value
Bits 0:31 - Low Auto-reload value
Bits 0:31 - Low Capture/Compare 1 value
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 0 - Capture/compare preloaded control
Bit 2 - Capture/compare control update selection
Bit 3 - Capture/compare DMA selection
Bits 4:6 - Master mode selection
Bit 8 - Output Idle state 1
Bit 9 - Output Idle state 1
Bit 10 - Output Idle state 2
Bits 0:2 - Slave mode selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bit 16 - Slave mode selection bit 3
Bit 0 - Update interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 5 - COM interrupt enable
Bit 6 - Trigger interrupt enable
Bit 7 - Break interrupt enable
Bit 8 - Update DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 13 - COM DMA request enable
Bit 14 - Trigger DMA request enable
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output Compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output Compare 2 fast enable
Bit 11 - Output Compare 2 preload enable
Bits 12:14 - Output Compare 2 mode
Bit 16 - Output Compare 1 mode bit 3
Bit 24 - Output Compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:15 - Capture/Compare 2 value
Bit 15 - Main output enable
Bit 14 - Automatic output enable
Bit 11 - Off-state selection for Run mode
Bit 10 - Off-state selection for Idle mode
Bits 8:9 - Lock configuration
Bits 0:7 - Dead-time generator setup
Bits 16:19 - Break filter
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
Bit 0 - Update interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 5 - COM interrupt enable
Bit 6 - Trigger interrupt enable
Bit 7 - Break interrupt enable
Bit 8 - Update DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 13 - COM DMA request enable
Bit 14 - Trigger DMA request enable
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output Compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bit 16 - Output Compare 1 mode
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
Bit 0 - Update interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 5 - COM interrupt enable
Bit 6 - Trigger interrupt enable
Bit 7 - Break interrupt enable
Bit 8 - Update DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 13 - COM DMA request enable
Bit 14 - Trigger DMA request enable
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output Compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bit 16 - Output Compare 1 mode
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 27 - End of Block interrupt enable
Bit 26 - Receiver timeout interrupt enable
Bits 21:25 - Driver Enable assertion time
Bits 16:20 - Driver Enable deassertion time
Bit 15 - Oversampling mode
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
Bit 3 - Transmitter enable
Bit 1 - USART enable in Stop mode
Bit 23 - Receiver timeout enable
Bits 21:22 - Auto baud rate mode
Bit 20 - Auto baud rate enable
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 8 - Last bit clock pulse
Bit 6 - LIN break detection interrupt enable
Bit 5 - LIN break detection length
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bits 17:19 - Smartcard auto-retry count
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 11 - One sample bit method enable
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 5 - Smartcard mode enable
Bit 4 - Smartcard NACK enable
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
Bits 0:15 - mantissa of USARTDIV
Bits 8:15 - Guard time value
Bits 0:7 - Prescaler value
Bits 24:31 - Block Length
Bits 0:23 - Receiver timeout value
Bit 4 - Transmit data flush request
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
Bit 0 - Auto baud rate request
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 12 - End of timeout clear flag
Bit 11 - Receiver timeout clear flag
Bit 8 - LIN break detection clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
Bits 0:8 - Transmit data value
Bit 15 - Bidirectional data mode enable
Bit 14 - Output enable in bidirectional mode
Bit 13 - Hardware CRC calculation enable
Bit 12 - CRC transfer next
Bit 9 - Software slave management
Bit 8 - Internal slave select
Bits 3:5 - Baud rate control
Bit 0 - Rx buffer DMA enable
Bit 1 - Tx buffer DMA enable
Bit 3 - NSS pulse management
Bit 5 - Error interrupt enable
Bit 6 - RX buffer not empty interrupt enable
Bit 7 - Tx buffer empty interrupt enable
Bit 12 - FIFO reception threshold
Bit 13 - Last DMA transfer for reception
Bit 14 - Last DMA transfer for transmission
Bits 0:15 - Data register
Bits 0:15 - CRC polynomial register
Bit 11 - I2S mode selection
Bits 8:9 - I2S configuration mode
Bit 7 - PCM frame synchronization
Bits 4:5 - I2S standard selection
Bit 3 - Steady state clock polarity
Bits 1:2 - Data length to be transferred
Bit 0 - Channel length (number of bits per audio channel)
Bit 9 - Master clock output enable
Bit 8 - Odd factor for the prescaler
Bits 0:7 - I2S Linear prescaler
Bit 0 - Interrupt Mask on line 0
Bit 1 - Interrupt Mask on line 1
Bit 2 - Interrupt Mask on line 2
Bit 3 - Interrupt Mask on line 3
Bit 4 - Interrupt Mask on line 4
Bit 5 - Interrupt Mask on line 5
Bit 6 - Interrupt Mask on line 6
Bit 7 - Interrupt Mask on line 7
Bit 8 - Interrupt Mask on line 8
Bit 9 - Interrupt Mask on line 9
Bit 10 - Interrupt Mask on line 10
Bit 11 - Interrupt Mask on line 11
Bit 12 - Interrupt Mask on line 12
Bit 13 - Interrupt Mask on line 13
Bit 14 - Interrupt Mask on line 14
Bit 15 - Interrupt Mask on line 15
Bit 16 - Interrupt Mask on line 16
Bit 17 - Interrupt Mask on line 17
Bit 18 - Interrupt Mask on line 18
Bit 19 - Interrupt Mask on line 19
Bit 20 - Interrupt Mask on line 20
Bit 21 - Interrupt Mask on line 21
Bit 22 - Interrupt Mask on line 22
Bit 23 - Interrupt Mask on line 23
Bit 24 - Interrupt Mask on line 24
Bit 25 - Interrupt Mask on line 25
Bit 26 - Interrupt Mask on line 26
Bit 27 - Interrupt Mask on line 27
Bit 28 - Interrupt Mask on line 28
Bit 29 - Interrupt Mask on line 29
Bit 30 - Interrupt Mask on line 30
Bit 31 - Interrupt Mask on line 31
Bit 0 - Event Mask on line 0
Bit 1 - Event Mask on line 1
Bit 2 - Event Mask on line 2
Bit 3 - Event Mask on line 3
Bit 4 - Event Mask on line 4
Bit 5 - Event Mask on line 5
Bit 6 - Event Mask on line 6
Bit 7 - Event Mask on line 7
Bit 8 - Event Mask on line 8
Bit 9 - Event Mask on line 9
Bit 10 - Event Mask on line 10
Bit 11 - Event Mask on line 11
Bit 12 - Event Mask on line 12
Bit 13 - Event Mask on line 13
Bit 14 - Event Mask on line 14
Bit 15 - Event Mask on line 15
Bit 16 - Event Mask on line 16
Bit 17 - Event Mask on line 17
Bit 18 - Event Mask on line 18
Bit 19 - Event Mask on line 19
Bit 20 - Event Mask on line 20
Bit 21 - Event Mask on line 21
Bit 22 - Event Mask on line 22
Bit 23 - Event Mask on line 23
Bit 24 - Event Mask on line 24
Bit 25 - Event Mask on line 25
Bit 26 - Event Mask on line 26
Bit 27 - Event Mask on line 27
Bit 28 - Event Mask on line 28
Bit 29 - Event Mask on line 29
Bit 30 - Event Mask on line 30
Bit 31 - Event Mask on line 31
Bit 0 - Rising trigger event configuration of line 0
Bit 1 - Rising trigger event configuration of line 1
Bit 2 - Rising trigger event configuration of line 2
Bit 3 - Rising trigger event configuration of line 3
Bit 4 - Rising trigger event configuration of line 4
Bit 5 - Rising trigger event configuration of line 5
Bit 6 - Rising trigger event configuration of line 6
Bit 7 - Rising trigger event configuration of line 7
Bit 8 - Rising trigger event configuration of line 8
Bit 9 - Rising trigger event configuration of line 9
Bit 10 - Rising trigger event configuration of line 10
Bit 11 - Rising trigger event configuration of line 11
Bit 12 - Rising trigger event configuration of line 12
Bit 13 - Rising trigger event configuration of line 13
Bit 14 - Rising trigger event configuration of line 14
Bit 15 - Rising trigger event configuration of line 15
Bit 16 - Rising trigger event configuration of line 16
Bit 17 - Rising trigger event configuration of line 17
Bit 18 - Rising trigger event configuration of line 18
Bit 19 - Rising trigger event configuration of line 19
Bit 20 - Rising trigger event configuration of line 20
Bit 21 - Rising trigger event configuration of line 21
Bit 22 - Rising trigger event configuration of line 22
Bit 29 - Rising trigger event configuration of line 29
Bit 30 - Rising trigger event configuration of line 30
Bit 31 - Rising trigger event configuration of line 31
Bit 0 - Falling trigger event configuration of line 0
Bit 1 - Falling trigger event configuration of line 1
Bit 2 - Falling trigger event configuration of line 2
Bit 3 - Falling trigger event configuration of line 3
Bit 4 - Falling trigger event configuration of line 4
Bit 5 - Falling trigger event configuration of line 5
Bit 6 - Falling trigger event configuration of line 6
Bit 7 - Falling trigger event configuration of line 7
Bit 8 - Falling trigger event configuration of line 8
Bit 9 - Falling trigger event configuration of line 9
Bit 10 - Falling trigger event configuration of line 10
Bit 11 - Falling trigger event configuration of line 11
Bit 12 - Falling trigger event configuration of line 12
Bit 13 - Falling trigger event configuration of line 13
Bit 14 - Falling trigger event configuration of line 14
Bit 15 - Falling trigger event configuration of line 15
Bit 16 - Falling trigger event configuration of line 16
Bit 17 - Falling trigger event configuration of line 17
Bit 18 - Falling trigger event configuration of line 18
Bit 19 - Falling trigger event configuration of line 19
Bit 20 - Falling trigger event configuration of line 20
Bit 21 - Falling trigger event configuration of line 21
Bit 22 - Falling trigger event configuration of line 22
Bit 29 - Falling trigger event configuration of line 29
Bit 30 - Falling trigger event configuration of line 30.
Bit 31 - Falling trigger event configuration of line 31
Bit 0 - Software Interrupt on line 0
Bit 1 - Software Interrupt on line 1
Bit 2 - Software Interrupt on line 2
Bit 3 - Software Interrupt on line 3
Bit 4 - Software Interrupt on line 4
Bit 5 - Software Interrupt on line 5
Bit 6 - Software Interrupt on line 6
Bit 7 - Software Interrupt on line 7
Bit 8 - Software Interrupt on line 8
Bit 9 - Software Interrupt on line 9
Bit 10 - Software Interrupt on line 10
Bit 11 - Software Interrupt on line 11
Bit 12 - Software Interrupt on line 12
Bit 13 - Software Interrupt on line 13
Bit 14 - Software Interrupt on line 14
Bit 15 - Software Interrupt on line 15
Bit 16 - Software Interrupt on line 16
Bit 17 - Software Interrupt on line 17
Bit 18 - Software Interrupt on line 18
Bit 19 - Software Interrupt on line 19
Bit 20 - Software Interrupt on line 20
Bit 21 - Software Interrupt on line 21
Bit 22 - Software Interrupt on line 22
Bit 29 - Software Interrupt on line 29
Bit 30 - Software Interrupt on line 309
Bit 31 - Software Interrupt on line 319
Bit 0 - Interrupt Mask on external/internal line 32
Bit 1 - Interrupt Mask on external/internal line 33
Bit 2 - Interrupt Mask on external/internal line 34
Bit 3 - Interrupt Mask on external/internal line 35
Bit 0 - Event mask on external/internal line 32
Bit 1 - Event mask on external/internal line 33
Bit 2 - Event mask on external/internal line 34
Bit 3 - Event mask on external/internal line 35
Bit 0 - Rising trigger event configuration bit of line 32
Bit 1 - Rising trigger event configuration bit of line 33
Bit 0 - Falling trigger event configuration bit of line 32
Bit 1 - Falling trigger event configuration bit of line 33
Bit 0 - Software interrupt on line 32
Bit 1 - Software interrupt on line 33
Bit 0 - Pending bit on line 32
Bit 1 - Pending bit on line 33
Bit 0 - Low-power deep sleep
Bit 1 - Power down deepsleep
Bit 2 - Clear wakeup flag
Bit 3 - Clear standby flag
Bit 4 - Power voltage detector enable
Bits 5:7 - PVD level selection
Bit 8 - Disable backup domain write protection
Bits 8:13 - CAN2 start bank
Bit 0 - Filter scale configuration
Bit 1 - Filter scale configuration
Bit 2 - Filter scale configuration
Bit 3 - Filter scale configuration
Bit 4 - Filter scale configuration
Bit 5 - Filter scale configuration
Bit 6 - Filter scale configuration
Bit 7 - Filter scale configuration
Bit 8 - Filter scale configuration
Bit 9 - Filter scale configuration
Bit 10 - Filter scale configuration
Bit 11 - Filter scale configuration
Bit 12 - Filter scale configuration
Bit 13 - Filter scale configuration
Bit 14 - Filter scale configuration
Bit 15 - Filter scale configuration
Bit 16 - Filter scale configuration
Bit 17 - Filter scale configuration
Bit 18 - Filter scale configuration
Bit 19 - Filter scale configuration
Bit 20 - Filter scale configuration
Bit 21 - Filter scale configuration
Bit 22 - Filter scale configuration
Bit 23 - Filter scale configuration
Bit 24 - Filter scale configuration
Bit 25 - Filter scale configuration
Bit 26 - Filter scale configuration
Bit 27 - Filter scale configuration
Bit 0 - Filter FIFO assignment for filter 0
Bit 1 - Filter FIFO assignment for filter 1
Bit 2 - Filter FIFO assignment for filter 2
Bit 3 - Filter FIFO assignment for filter 3
Bit 4 - Filter FIFO assignment for filter 4
Bit 5 - Filter FIFO assignment for filter 5
Bit 6 - Filter FIFO assignment for filter 6
Bit 7 - Filter FIFO assignment for filter 7
Bit 8 - Filter FIFO assignment for filter 8
Bit 9 - Filter FIFO assignment for filter 9
Bit 10 - Filter FIFO assignment for filter 10
Bit 11 - Filter FIFO assignment for filter 11
Bit 12 - Filter FIFO assignment for filter 12
Bit 13 - Filter FIFO assignment for filter 13
Bit 14 - Filter FIFO assignment for filter 14
Bit 15 - Filter FIFO assignment for filter 15
Bit 16 - Filter FIFO assignment for filter 16
Bit 17 - Filter FIFO assignment for filter 17
Bit 18 - Filter FIFO assignment for filter 18
Bit 19 - Filter FIFO assignment for filter 19
Bit 20 - Filter FIFO assignment for filter 20
Bit 21 - Filter FIFO assignment for filter 21
Bit 22 - Filter FIFO assignment for filter 22
Bit 23 - Filter FIFO assignment for filter 23
Bit 24 - Filter FIFO assignment for filter 24
Bit 25 - Filter FIFO assignment for filter 25
Bit 26 - Filter FIFO assignment for filter 26
Bit 27 - Filter FIFO assignment for filter 27
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bit 8 - Expected start of frame interrupt mask
Bit 9 - Start of frame interrupt mask
Bit 10 - USB reset interrupt mask
Bit 11 - Suspend mode interrupt mask
Bit 12 - Wakeup interrupt mask
Bit 13 - Error interrupt mask
Bit 14 - Packet memory area over / underrun interrupt mask
Bit 15 - Correct transfer interrupt mask
Bit 8 - Expected start frame
Bit 11 - Suspend mode request
Bit 14 - Packet memory area over / underrun
Bit 0 - Peripheral enable
Bit 1 - TX Interrupt enable
Bit 2 - RX Interrupt enable
Bit 3 - Address match interrupt enable (slave only)
Bit 4 - Not acknowledge received interrupt enable
Bit 5 - STOP detection Interrupt enable
Bit 6 - Transfer Complete interrupt enable
Bit 7 - Error interrupts enable
Bits 8:11 - Digital noise filter
Bit 12 - Analog noise filter OFF
Bit 14 - DMA transmission requests enable
Bit 15 - DMA reception requests enable
Bit 16 - Slave byte control
Bit 17 - Clock stretching disable
Bit 18 - Wakeup from STOP enable
Bit 19 - General call enable
Bit 20 - SMBus Host address enable
Bit 21 - SMBus Device Default address enable
Bit 22 - SMBUS alert enable
Bit 26 - Packet error checking byte
Bit 25 - Automatic end mode (master mode)
Bit 24 - NBYTES reload mode
Bits 16:23 - Number of bytes
Bit 15 - NACK generation (slave mode)
Bit 14 - Stop generation (master mode)
Bit 13 - Start generation
Bit 12 - 10-bit address header only read direction (master receiver mode)
Bit 11 - 10-bit addressing mode (master mode)
Bit 10 - Transfer direction (master mode)
Bits 0:9 - Slave address bit 9:8 (master mode)
Bit 10 - Own Address 1 10-bit mode
Bit 15 - Own Address 1 enable
Bits 0:9 - Interface address
Bits 1:7 - Interface address
Bits 8:10 - Own Address 2 masks
Bit 15 - Own Address 2 enable
Bits 0:7 - SCL low period (master mode)
Bits 8:15 - SCL high period (master mode)
Bits 16:19 - Data hold time
Bits 20:23 - Data setup time
Bits 28:31 - Timing prescaler
Bits 0:11 - Bus timeout A
Bit 12 - Idle clock timeout detection
Bit 15 - Clock timeout enable
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
[src]
Bit 31 - Extended clock timeout enable
Bit 1 - Transmit interrupt status (transmitters)
Bit 0 - Transmit data register empty (transmitters)
Bit 13 - Alert flag clear
Bit 12 - Timeout detection flag clear
Bit 11 - PEC Error flag clear
Bit 10 - Overrun/Underrun flag clear
Bit 9 - Arbitration lost flag clear
Bit 8 - Bus error flag clear
Bit 5 - Stop detection flag clear
Bit 4 - Not Acknowledge flag clear
Bit 3 - Address Matched flag clear
Bits 0:7 - 8-bit transmit data
Bits 0:2 - Prescaler divider
Bits 0:11 - Watchdog counter reload value
Bits 0:11 - Watchdog counter window value
Bit 9 - Early wakeup interrupt
Bits 0:6 - 7-bit window value
Bit 0 - Early wakeup interrupt flag
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bits 20:23 - Year tens in BCD format
Bits 16:19 - Year units in BCD format
Bits 13:15 - Week day units
Bit 12 - Month tens in BCD format
Bits 8:11 - Month units in BCD format
Bits 4:5 - Date tens in BCD format
Bits 0:3 - Date units in BCD format
Bits 0:2 - Wakeup clock selection
Bit 3 - Time-stamp event active edge
Bit 4 - Reference clock detection enable (50 or 60 Hz)
Bit 5 - Bypass the shadow registers
Bit 10 - Wakeup timer enable
Bit 11 - Time stamp enable
Bit 12 - Alarm A interrupt enable
Bit 13 - Alarm B interrupt enable
Bit 14 - Wakeup timer interrupt enable
Bit 15 - Time-stamp interrupt enable
Bit 16 - Add 1 hour (summer time change)
Bit 17 - Subtract 1 hour (winter time change)
Bit 19 - Calibration output selection
Bits 21:22 - Output selection
Bit 23 - Calibration output enable
Bit 3 - Shift operation pending
Bit 5 - Registers synchronization flag
Bit 7 - Initialization mode
Bit 10 - Wakeup timer flag
Bit 12 - Time-stamp overflow flag
Bit 13 - Tamper detection flag
Bit 14 - RTC_TAMP2 detection flag
Bit 15 - RTC_TAMP3 detection flag
Bits 16:22 - Asynchronous prescaler factor
Bits 0:14 - Synchronous prescaler factor
Bits 0:15 - Wakeup auto-reload value bits
Bit 31 - Alarm A date mask
Bit 30 - Week day selection
Bits 28:29 - Date tens in BCD format
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm A hours mask
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm A minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm A seconds mask
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bit 31 - Alarm B date mask
Bit 30 - Week day selection
Bits 28:29 - Date tens in BCD format
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm B hours mask
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm B minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm B seconds mask
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bits 0:7 - Write protection key
Bits 0:14 - Subtract a fraction of a second
Bit 15 - Increase frequency of RTC by 488.5 ppm
Bit 14 - Use an 8-second calibration cycle period
Bit 13 - Use a 16-second calibration cycle period
Bits 0:8 - Calibration minus
Bit 0 - Tamper 1 detection enable
Bit 1 - Active level for tamper 1
Bit 2 - Tamper interrupt enable
Bit 3 - Tamper 2 detection enable
Bit 4 - Active level for tamper 2
Bit 5 - Tamper 3 detection enable
Bit 6 - Active level for tamper 3
Bit 7 - Activate timestamp on tamper detection event
Bits 8:10 - Tamper sampling frequency
Bits 11:12 - Tamper filter count
Bits 13:14 - Tamper precharge duration
Bit 15 - TAMPER pull-up disable
Bits 24:27 - Mask the most-significant bits starting at this bit
Bits 0:14 - Sub seconds value
Bits 24:27 - Mask the most-significant bits starting at this bit
Bits 0:14 - Sub seconds value
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 8 - Update DMA request enable
Bit 0 - Update interrupt enable
Bit 0 - Update interrupt flag
Bit 0 - Update generation
Bits 0:15 - Low counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Low Auto-reload value
Bit 29 - DAC channel2 DMA underrun interrupt enable
Bit 28 - DAC channel2 DMA enable
Bits 24:27 - DAC channel2 mask/amplitude selector
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
Bits 19:21 - DAC channel2 trigger selection
Bit 18 - DAC channel2 trigger enable
Bit 17 - DAC channel2 output buffer disable
Bit 16 - DAC channel2 enable
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
Bit 12 - DAC channel1 DMA enable
Bits 8:11 - DAC channel1 mask/amplitude selector
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
Bits 3:5 - DAC channel1 trigger selection
Bit 2 - DAC channel1 trigger enable
Bit 1 - DAC channel1 output buffer disable
Bit 0 - DAC channel1 enable
Bit 1 - DAC channel2 software trigger
Bit 0 - DAC channel1 software trigger
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bits 0:11 - DAC channel2 12-bit right-aligned data
Bits 4:15 - DAC channel2 12-bit left-aligned data
Bits 0:7 - DAC channel2 8-bit right-aligned data
Bits 16:27 - DAC channel2 12-bit right-aligned data
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 20:31 - DAC channel2 12-bit left-aligned data
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 8:15 - DAC channel2 8-bit right-aligned data
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bit 29 - DAC channel2 DMA underrun flag
Bit 13 - DAC channel1 DMA underrun flag
Bit 2 - Debug Standby Mode
Bit 5 - Trace pin assignment control
Bits 6:7 - Trace pin assignment control
Bit 0 - Debug Timer 2 stopped when Core is halted
Bit 1 - Debug Timer 3 stopped when Core is halted
Bit 2 - Debug Timer 4 stopped when Core is halted
Bit 3 - Debug Timer 5 stopped when Core is halted
Bit 4 - Debug Timer 6 stopped when Core is halted
Bit 5 - Debug Timer 7 stopped when Core is halted
Bit 6 - Debug Timer 12 stopped when Core is halted
Bit 7 - Debug Timer 13 stopped when Core is halted
Bit 8 - Debug Timer 14 stopped when Core is halted
Bit 9 - Debug Timer 18 stopped when Core is halted
Bit 10 - Debug RTC stopped when Core is halted
Bit 11 - Debug Window Wachdog stopped when Core is halted
Bit 12 - Debug Independent Wachdog stopped when Core is halted
Bit 21 - SMBUS timeout mode stopped when Core is halted
Bit 22 - SMBUS timeout mode stopped when Core is halted
Bit 25 - Debug CAN stopped when core is halted
Bit 2 - Debug Timer 15 stopped when Core is halted
Bit 3 - Debug Timer 16 stopped when Core is halted
Bit 4 - Debug Timer 17 stopped when Core is halted
Bit 5 - Debug Timer 19 stopped when Core is halted
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 0 - Capture/compare preloaded control
Bit 2 - Capture/compare control update selection
Bit 3 - Capture/compare DMA selection
Bits 4:6 - Master mode selection
Bit 8 - Output Idle state 1
Bit 9 - Output Idle state 1
Bit 10 - Output Idle state 2
Bit 11 - Output Idle state 2
Bit 12 - Output Idle state 3
Bit 13 - Output Idle state 3
Bit 14 - Output Idle state 4
Bit 16 - Output Idle state 5
Bit 18 - Output Idle state 6
Bits 20:23 - Master mode selection 2
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit 3
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 0 - Update interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 5 - COM interrupt flag
Bit 6 - Trigger interrupt flag
Bit 7 - Break interrupt flag
Bit 8 - Break 2 interrupt flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 12 - Capture/Compare 4 overcapture flag
Bit 16 - Capture/Compare 5 interrupt flag
Bit 17 - Capture/Compare 6 interrupt flag
Bit 0 - Update generation
Bit 1 - Capture/compare 1 generation
Bit 2 - Capture/compare 2 generation
Bit 3 - Capture/compare 3 generation
Bit 4 - Capture/compare 4 generation
Bit 5 - Capture/Compare control update generation
Bit 6 - Trigger generation
Bit 8 - Break 2 generation
Bit 15 - Output Compare 2 clear enable
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output Compare 1 clear enable
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bit 16 - Output Compare 1 mode bit 3
Bit 24 - Output Compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
Bit 16 - Output Compare 3 mode bit 3
Bit 24 - Output Compare 4 mode bit 3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 4 output Polarity
Bit 16 - Capture/Compare 5 output enable
Bit 17 - Capture/Compare 5 output Polarity
Bit 20 - Capture/Compare 6 output enable
Bit 21 - Capture/Compare 6 output Polarity
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:15 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 20:23 - Break 2 filter
Bit 25 - Break 2 polarity
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Output compare 5 fast enable
Bit 3 - Output compare 5 preload enable
Bits 4:6 - Output compare 5 mode
Bit 7 - Output compare 5 clear enable
Bit 10 - Output compare 6 fast enable
Bit 11 - Output compare 6 preload enable
Bits 12:14 - Output compare 6 mode
Bit 15 - Output compare 6 clear enable
Bit 16 - Outout Compare 5 mode bit 3
Bit 24 - Outout Compare 6 mode bit 3
Bits 0:15 - Capture/Compare 5 value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
Bits 0:15 - Capture/Compare 6 value
Bits 0:1 - TIM1_ETR_ADC1 remapping capability
Bits 2:3 - TIM1_ETR_ADC4 remapping capability
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 0 - Capture/compare preloaded control
Bit 2 - Capture/compare control update selection
Bit 3 - Capture/compare DMA selection
Bits 4:6 - Master mode selection
Bit 8 - Output Idle state 1
Bit 9 - Output Idle state 1
Bit 10 - Output Idle state 2
Bit 11 - Output Idle state 2
Bit 12 - Output Idle state 3
Bit 13 - Output Idle state 3
Bit 14 - Output Idle state 4
Bit 16 - Output Idle state 5
Bit 18 - Output Idle state 6
Bits 20:23 - Master mode selection 2
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit 3
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 0 - Update interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 5 - COM interrupt flag
Bit 6 - Trigger interrupt flag
Bit 7 - Break interrupt flag
Bit 8 - Break 2 interrupt flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 12 - Capture/Compare 4 overcapture flag
Bit 16 - Capture/Compare 5 interrupt flag
Bit 17 - Capture/Compare 6 interrupt flag
Bit 0 - Update generation
Bit 1 - Capture/compare 1 generation
Bit 2 - Capture/compare 2 generation
Bit 3 - Capture/compare 3 generation
Bit 4 - Capture/compare 4 generation
Bit 5 - Capture/Compare control update generation
Bit 6 - Trigger generation
Bit 8 - Break 2 generation
Bit 15 - Output Compare 2 clear enable
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output Compare 1 clear enable
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bit 16 - Output Compare 1 mode bit 3
Bit 24 - Output Compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
Bit 16 - Output Compare 3 mode bit 3
Bit 24 - Output Compare 4 mode bit 3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 4 output Polarity
Bit 16 - Capture/Compare 5 output enable
Bit 17 - Capture/Compare 5 output Polarity
Bit 20 - Capture/Compare 6 output enable
Bit 21 - Capture/Compare 6 output Polarity
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:15 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 20:23 - Break 2 filter
Bit 25 - Break 2 polarity
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Output compare 5 fast enable
Bit 3 - Output compare 5 preload enable
Bits 4:6 - Output compare 5 mode
Bit 7 - Output compare 5 clear enable
Bit 10 - Output compare 6 fast enable
Bit 11 - Output compare 6 preload enable
Bits 12:14 - Output compare 6 mode
Bit 15 - Output compare 6 clear enable
Bit 16 - Outout Compare 5 mode bit 3
Bit 24 - Outout Compare 6 mode bit 3
Bits 0:15 - Capture/Compare 5 value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
Bits 0:15 - Capture/Compare 6 value
Bits 0:1 - TIM8_ETR_ADC2 remapping capability
Bits 2:3 - TIM8_ETR_ADC3 remapping capability
Bit 0 - Differential mode for channels 15 to 1
Bit 1 - Differential mode for channels 15 to 1
Bit 2 - Differential mode for channels 15 to 1
Bit 3 - Differential mode for channels 15 to 1
Bit 4 - Differential mode for channels 15 to 1
Bit 5 - Differential mode for channels 15 to 1
Bit 6 - Differential mode for channels 15 to 1
Bit 7 - Differential mode for channels 15 to 1
Bit 8 - Differential mode for channels 15 to 1
Bit 9 - Differential mode for channels 15 to 1
Bit 10 - Differential mode for channels 15 to 1
Bit 11 - Differential mode for channels 15 to 1
Bit 12 - Differential mode for channels 15 to 1
Bit 13 - Differential mode for channels 15 to 1
Bit 14 - Differential mode for channels 15 to 1
Bit 15 - Differential mode for channels 15 to 1
Bit 16 - Differential mode for channels 15 to 1
Bit 17 - Differential mode for channels 15 to 1
Bits 0:4 - Dual ADC mode selection
Bits 8:11 - Delay between 2 sampling phases
Bit 13 - DMA configuration (for multi-ADC mode)
Bits 14:15 - Direct memory access mode for multi ADC mode
Bits 16:17 - ADC clock mode
Bit 23 - Temperature sensor enable
Bits 16:19 - Bus turnaround phase duration
Bits 16:19 - Bus turnaround phase duration
Bits 16:19 - Bus turnaround phase duration
Bits 16:19 - Bus turnaround phase duration
Bits 0:2 - Memory mapping selection bits
Bit 5 - USB interrupt remap
Bit 6 - Timer 1 ITR3 selection
Bit 7 - DAC trigger remap (when TSEL = 001)
Bit 8 - ADC24 DMA remapping bit
Bit 11 - TIM16 DMA request remapping bit
Bit 12 - TIM17 DMA request remapping bit
Bit 13 - TIM6 and DAC1 DMA request remapping bit
Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 20 - I2C1 Fast Mode Plus
Bit 21 - I2C2 Fast Mode Plus
Bits 22:23 - Encoder mode
Bit 31 - Inexact interrupt enable
Bit 30 - Input denormal interrupt enable
Bit 29 - Overflow interrupt enable
Bit 28 - Underflow interrupt enable
Bit 27 - Devide-by-zero interrupt enable
Bit 26 - Invalid operation interrupt enable
Bit 24 - I2C3 Fast Mode Plus
Bits 12:15 - EXTI 3 configuration bits
Bits 8:11 - EXTI 2 configuration bits
Bits 4:7 - EXTI 1 configuration bits
Bits 0:3 - EXTI 0 configuration bits
Bits 12:15 - EXTI 7 configuration bits
Bits 8:11 - EXTI 6 configuration bits
Bits 4:7 - EXTI 5 configuration bits
Bits 0:3 - EXTI 4 configuration bits
Bits 12:15 - EXTI 11 configuration bits
Bits 8:11 - EXTI 10 configuration bits
Bits 4:7 - EXTI 9 configuration bits
Bits 0:3 - EXTI 8 configuration bits
Bits 12:15 - EXTI 15 configuration bits
Bits 8:11 - EXTI 14 configuration bits
Bits 4:7 - EXTI 13 configuration bits
Bits 0:3 - EXTI 12 configuration bits
Bit 0 - Cortex-M0 LOCKUP bit enable bit
Bit 1 - SRAM parity lock bit
Bit 2 - PVD lock enable bit
Bit 4 - Bypass address bit 29 in parity calculation
Bits 3:31 - Location of unpopulated floating-point
Bit 0 - Invalid operation cumulative exception bit
Bit 1 - Division by zero cumulative exception bit.
Bit 2 - Overflow cumulative exception bit
Bit 3 - Underflow cumulative exception bit
Bit 4 - Inexact cumulative exception bit
Bit 7 - Input denormal cumulative exception bit.
Bits 22:23 - Rounding Mode control field
Bit 24 - Flush-to-zero mode control bit:
Bit 25 - Default NaN mode control bit
Bit 26 - Alternative half-precision control bit
Bit 28 - Overflow condition code flag
Bit 29 - Carry condition code flag
Bit 30 - Zero condition code flag
Bit 31 - Negative condition code flag
Bit 1 - SysTick exception request enable
Bit 2 - Clock source selection
Bits 0:23 - Current counter value
Bits 0:23 - Calibration value
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
Bit 31 - NOREF flag. Reads as zero
Bits 0:8 - Software generated interrupt ID
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit3
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output compare 1 fast enable
Bit 3 - Output compare 1 preload enable
Bits 4:6 - Output compare 1 mode
Bit 7 - Output compare 1 clear enable
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output compare 2 fast enable
Bit 11 - Output compare 2 preload enable
Bits 12:14 - Output compare 2 mode
Bit 15 - Output compare 2 clear enable
Bit 16 - Output compare 1 mode bit 3
Bit 24 - Output compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bits 0:1 - Capture/Compare 3 selection
Bit 2 - Output compare 3 fast enable
Bit 3 - Output compare 3 preload enable
Bits 4:6 - Output compare 3 mode
Bit 7 - Output compare 3 clear enable
Bits 8:9 - Capture/Compare 4 selection
Bit 10 - Output compare 4 fast enable
Bit 11 - Output compare 4 preload enable
Bits 12:14 - Output compare 4 mode
Bit 15 - Output compare 4 clear enable
Bit 16 - Output compare 3 mode bit3
Bit 24 - Output compare 4 mode bit3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:15 - Counter value
Bits 16:30 - High counter value
Bit 31 - if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 16:31 - High Auto-reload value
Bits 0:15 - Capture/Compare 1 value
Bits 16:31 - High Capture/Compare 1 value (on TIM2)
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit3
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output compare 1 fast enable
Bit 3 - Output compare 1 preload enable
Bits 4:6 - Output compare 1 mode
Bit 7 - Output compare 1 clear enable
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output compare 2 fast enable
Bit 11 - Output compare 2 preload enable
Bits 12:14 - Output compare 2 mode
Bit 15 - Output compare 2 clear enable
Bit 16 - Output compare 1 mode bit 3
Bit 24 - Output compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bits 0:1 - Capture/Compare 3 selection
Bit 2 - Output compare 3 fast enable
Bit 3 - Output compare 3 preload enable
Bits 4:6 - Output compare 3 mode
Bit 7 - Output compare 3 clear enable
Bits 8:9 - Capture/Compare 4 selection
Bit 10 - Output compare 4 fast enable
Bit 11 - Output compare 4 preload enable
Bits 12:14 - Output compare 4 mode
Bit 15 - Output compare 4 clear enable
Bit 16 - Output compare 3 mode bit3
Bit 24 - Output compare 4 mode bit3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:15 - Counter value
Bits 16:30 - High counter value
Bit 31 - if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 16:31 - High Auto-reload value
Bits 0:15 - Capture/Compare 1 value
Bits 16:31 - High Capture/Compare 1 value (on TIM2)
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 2:3 - OPAMP Non inverting input selection
Bits 5:6 - OPAMP inverting input selection
Bit 7 - Timer controlled Mux mode enable
Bit 8 - OPAMP inverting input secondary selection
Bits 9:10 - OPAMP Non inverting input secondary selection
Bit 11 - Calibration mode enable
Bits 12:13 - Calibration selection
Bits 14:17 - Gain in PGA mode
Bit 18 - User trimming enable
Bits 19:23 - Offset trimming value (PMOS)
Bits 24:28 - Offset trimming value (NMOS)
Bits 2:3 - OPAMP Non inverting input selection
Bits 5:6 - OPAMP inverting input selection
Bit 7 - Timer controlled Mux mode enable
Bit 8 - OPAMP inverting input secondary selection
Bits 9:10 - OPAMP Non inverting input secondary selection
Bit 11 - Calibration mode enable
Bits 12:13 - Calibration selection
Bits 14:17 - Gain in PGA mode
Bit 18 - User trimming enable
Bits 19:23 - Offset trimming value (PMOS)
Bits 24:28 - Offset trimming value (NMOS)
Bit 0 - Comparator 2 enable
Bits 4:6 - Comparator 2 inverting input selection
Bits 10:13 - Comparator 2 output selection
Bit 15 - Comparator 2 output polarity
Bits 18:20 - Comparator 2 blanking source
Bit 31 - Comparator 2 lock
Bits 2:3 - Comparator 2 mode
Bit 7 - Comparator 2 non inverted input
Bit 9 - Comparator 2 window mode
Bits 16:17 - Comparator 2 hysteresis
Bit 1 - Comparator 2 non inverting input connection to DAC output
Bit 0 - Comparator 4 enable
Bits 4:6 - Comparator 4 inverting input selection
Bits 10:13 - Comparator 4 output selection
Bit 15 - Comparator 4 output polarity
Bits 18:20 - Comparator 4 blanking source
Bit 31 - Comparator 4 lock
Bits 2:3 - Comparator 4 mode
Bit 7 - Comparator 4 non inverted input
Bits 16:17 - Comparator 4 hysteresis
Bit 0 - Comparator 6 enable
Bits 4:6 - Comparator 6 inverting input selection
Bits 10:13 - Comparator 6 output selection
Bit 15 - Comparator 6 output polarity
Bits 18:20 - Comparator 6 blanking source
Bit 31 - Comparator 6 lock
Bits 2:3 - Comparator 6 mode
Bit 7 - Comparator 6 non inverted input
Bits 16:17 - Comparator 6 hysteresis
Bit 0 - Comparator 1 enable
Bit 1 - Comparator 1 non inverting input connection to DAC output
Bits 2:3 - Comparator 1 mode
Bits 4:6 - Comparator 1 inverting input selection
Bits 10:13 - Comparator 1 output selection
Bit 15 - Comparator 1 output polarity
Bits 16:17 - Comparator 1 hysteresis
Bits 18:20 - Comparator 1 blanking source
Bit 31 - Comparator 1 lock
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bit 15
Bit 14 - Port x configuration bit 14
Bit 13 - Port x configuration bit 13
Bit 12 - Port x configuration bit 12
Bit 11 - Port x configuration bit 11
Bit 10 - Port x configuration bit 10
Bit 9 - Port x configuration bit 9
Bit 8 - Port x configuration bit 8
Bit 7 - Port x configuration bit 7
Bit 6 - Port x configuration bit 6
Bit 5 - Port x configuration bit 5
Bit 4 - Port x configuration bit 4
Bit 3 - Port x configuration bit 3
Bit 2 - Port x configuration bit 2
Bit 1 - Port x configuration bit 1
Bit 0 - Port x configuration bit 0
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 28:31 - Charge transfer pulse high
Bits 24:27 - Charge transfer pulse low
Bits 17:23 - Spread spectrum deviation
Bit 16 - Spread spectrum enable
Bit 15 - Spread spectrum prescaler
Bits 12:14 - pulse generator prescaler
Bits 5:7 - Max count value
Bit 3 - Synchronization pin polarity
Bit 1 - Start a new acquisition
Bit 0 - Touch sensing controller enable
Bit 1 - Max count error interrupt enable
Bit 0 - End of acquisition interrupt enable
Bit 1 - Max count error interrupt clear
Bit 0 - End of acquisition interrupt clear
Bit 1 - Max count error flag
Bit 0 - End of acquisition flag
Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
Bit 24 - G7_IO1 Schmitt trigger hysteresis mode
Bit 25 - G7_IO2 Schmitt trigger hysteresis mode
Bit 26 - G7_IO3 Schmitt trigger hysteresis mode
Bit 27 - G7_IO4 Schmitt trigger hysteresis mode
Bit 28 - G8_IO1 Schmitt trigger hysteresis mode
Bit 29 - G8_IO2 Schmitt trigger hysteresis mode
Bit 30 - G8_IO3 Schmitt trigger hysteresis mode
Bit 31 - G8_IO4 Schmitt trigger hysteresis mode
Bit 0 - G1_IO1 analog switch enable
Bit 1 - G1_IO2 analog switch enable
Bit 2 - G1_IO3 analog switch enable
Bit 3 - G1_IO4 analog switch enable
Bit 4 - G2_IO1 analog switch enable
Bit 5 - G2_IO2 analog switch enable
Bit 6 - G2_IO3 analog switch enable
Bit 7 - G2_IO4 analog switch enable
Bit 8 - G3_IO1 analog switch enable
Bit 9 - G3_IO2 analog switch enable
Bit 10 - G3_IO3 analog switch enable
Bit 11 - G3_IO4 analog switch enable
Bit 12 - G4_IO1 analog switch enable
Bit 13 - G4_IO2 analog switch enable
Bit 14 - G4_IO3 analog switch enable
Bit 15 - G4_IO4 analog switch enable
Bit 16 - G5_IO1 analog switch enable
Bit 17 - G5_IO2 analog switch enable
Bit 18 - G5_IO3 analog switch enable
Bit 19 - G5_IO4 analog switch enable
Bit 20 - G6_IO1 analog switch enable
Bit 21 - G6_IO2 analog switch enable
Bit 22 - G6_IO3 analog switch enable
Bit 23 - G6_IO4 analog switch enable
Bit 24 - G7_IO1 analog switch enable
Bit 25 - G7_IO2 analog switch enable
Bit 26 - G7_IO3 analog switch enable
Bit 27 - G7_IO4 analog switch enable
Bit 28 - G8_IO1 analog switch enable
Bit 29 - G8_IO2 analog switch enable
Bit 30 - G8_IO3 analog switch enable
Bit 31 - G8_IO4 analog switch enable
Bit 0 - G1_IO1 sampling mode
Bit 1 - G1_IO2 sampling mode
Bit 2 - G1_IO3 sampling mode
Bit 3 - G1_IO4 sampling mode
Bit 4 - G2_IO1 sampling mode
Bit 5 - G2_IO2 sampling mode
Bit 6 - G2_IO3 sampling mode
Bit 7 - G2_IO4 sampling mode
Bit 8 - G3_IO1 sampling mode
Bit 9 - G3_IO2 sampling mode
Bit 10 - G3_IO3 sampling mode
Bit 11 - G3_IO4 sampling mode
Bit 12 - G4_IO1 sampling mode
Bit 13 - G4_IO2 sampling mode
Bit 14 - G4_IO3 sampling mode
Bit 15 - G4_IO4 sampling mode
Bit 16 - G5_IO1 sampling mode
Bit 17 - G5_IO2 sampling mode
Bit 18 - G5_IO3 sampling mode
Bit 19 - G5_IO4 sampling mode
Bit 20 - G6_IO1 sampling mode
Bit 21 - G6_IO2 sampling mode
Bit 22 - G6_IO3 sampling mode
Bit 23 - G6_IO4 sampling mode
Bit 24 - G7_IO1 sampling mode
Bit 25 - G7_IO2 sampling mode
Bit 26 - G7_IO3 sampling mode
Bit 27 - G7_IO4 sampling mode
Bit 28 - G8_IO1 sampling mode
Bit 29 - G8_IO2 sampling mode
Bit 30 - G8_IO3 sampling mode
Bit 31 - G8_IO4 sampling mode
Bit 0 - G1_IO1 channel mode
Bit 1 - G1_IO2 channel mode
Bit 2 - G1_IO3 channel mode
Bit 3 - G1_IO4 channel mode
Bit 4 - G2_IO1 channel mode
Bit 5 - G2_IO2 channel mode
Bit 6 - G2_IO3 channel mode
Bit 7 - G2_IO4 channel mode
Bit 8 - G3_IO1 channel mode
Bit 9 - G3_IO2 channel mode
Bit 10 - G3_IO3 channel mode
Bit 11 - G3_IO4 channel mode
Bit 12 - G4_IO1 channel mode
Bit 13 - G4_IO2 channel mode
Bit 14 - G4_IO3 channel mode
Bit 15 - G4_IO4 channel mode
Bit 16 - G5_IO1 channel mode
Bit 17 - G5_IO2 channel mode
Bit 18 - G5_IO3 channel mode
Bit 19 - G5_IO4 channel mode
Bit 20 - G6_IO1 channel mode
Bit 21 - G6_IO2 channel mode
Bit 22 - G6_IO3 channel mode
Bit 23 - G6_IO4 channel mode
Bit 24 - G7_IO1 channel mode
Bit 25 - G7_IO2 channel mode
Bit 26 - G7_IO3 channel mode
Bit 27 - G7_IO4 channel mode
Bit 28 - G8_IO1 channel mode
Bit 29 - G8_IO2 channel mode
Bit 30 - G8_IO3 channel mode
Bit 31 - G8_IO4 channel mode
Bit 23 - Analog I/O group x status
Bit 22 - Analog I/O group x status
Bit 7 - Analog I/O group x enable
Bit 6 - Analog I/O group x enable
Bit 5 - Analog I/O group x enable
Bit 4 - Analog I/O group x enable
Bit 3 - Analog I/O group x enable
Bit 2 - Analog I/O group x enable
Bit 1 - Analog I/O group x enable
Bit 0 - Analog I/O group x enable
Bits 0:31 - Data register bits
Bits 0:7 - General-purpose 8-bit data register bits
Bits 3:4 - Polynomial size
Bits 5:6 - Reverse input data
Bit 7 - Reverse output data
Bits 0:31 - Programmable initial CRC value
Bits 0:31 - Programmable polynomial
Bits 0:7 - Data register bits
Bits 0:15 - Data register bits
Bit 3 - Flash half cycle access enable
Bits 0:31 - Option byte key
Bit 4 - Write protection error
Bit 2 - Programming error
Bit 13 - Force option byte loading
Bit 12 - End of operation interrupt enable
Bit 10 - Error interrupt enable
Bit 9 - Option bytes write enable
Bit 5 - Option byte erase
Bit 4 - Option byte programming
Bits 0:31 - Flash address
Bit 0 - Internal High Speed clock enable
Bits 3:7 - Internal High Speed clock trimming
Bit 16 - External High Speed clock enable
Bit 18 - External High Speed clock Bypass
Bit 19 - Clock Security System enable
Bits 0:1 - System clock Switch
Bits 8:10 - APB Low speed prescaler (APB1)
Bits 11:13 - APB high speed prescaler (APB2)
Bits 15:16 - PLL entry clock source
Bit 17 - HSE divider for PLL entry
Bits 18:21 - PLL Multiplication Factor
Bits 24:26 - Microcontroller clock output
Bit 23 - I2S external clock source selection
Bits 28:30 - Microcontroller Clock Output Prescaler
Bit 31 - Do not divide PLL to MCO
Bit 8 - LSI Ready Interrupt Enable
Bit 9 - LSE Ready Interrupt Enable
Bit 10 - HSI Ready Interrupt Enable
Bit 11 - HSE Ready Interrupt Enable
Bit 12 - PLL Ready Interrupt Enable
Bit 16 - LSI Ready Interrupt Clear
Bit 17 - LSE Ready Interrupt Clear
Bit 18 - HSI Ready Interrupt Clear
Bit 19 - HSE Ready Interrupt Clear
Bit 20 - PLL Ready Interrupt Clear
Bit 23 - Clock security system interrupt clear
Bit 0 - SYSCFG and COMP reset
Bit 11 - TIM1 timer reset
Bit 13 - TIM8 timer reset
Bit 16 - TIM15 timer reset
Bit 17 - TIM16 timer reset
Bit 18 - TIM17 timer reset
Bit 20 - TIM20 timer reset
Bit 11 - Window watchdog reset
Bit 28 - Power interface reset
Bit 29 - DAC interface reset
Bit 26 - DAC2 interface reset
Bit 0 - DMA1 clock enable
Bit 1 - DMA2 clock enable
Bit 2 - SRAM interface clock enable
Bit 4 - FLITF clock enable
Bit 16 - IO port H clock enable
Bit 17 - I/O port A clock enable
Bit 18 - I/O port B clock enable
Bit 19 - I/O port C clock enable
Bit 20 - I/O port D clock enable
Bit 21 - I/O port E clock enable
Bit 22 - I/O port F clock enable
Bit 23 - I/O port G clock enable
Bit 24 - Touch sensing controller clock enable
Bit 28 - ADC1 and ADC2 clock enable
Bit 29 - ADC3 and ADC4 clock enable
Bit 0 - SYSCFG clock enable
Bit 11 - TIM1 Timer clock enable
Bit 12 - SPI 1 clock enable
Bit 13 - TIM8 Timer clock enable
Bit 14 - USART1 clock enable
Bit 16 - TIM15 timer clock enable
Bit 17 - TIM16 timer clock enable
Bit 18 - TIM17 timer clock enable
Bit 15 - SPI4 clock enable
Bit 20 - TIM20 timer clock enable
Bit 0 - Timer 2 clock enable
Bit 1 - Timer 3 clock enable
Bit 2 - Timer 4 clock enable
Bit 4 - Timer 6 clock enable
Bit 5 - Timer 7 clock enable
Bit 11 - Window watchdog clock enable
Bit 14 - SPI 2 clock enable
Bit 15 - SPI 3 clock enable
Bit 17 - USART 2 clock enable
Bit 18 - USART 3 clock enable
Bit 19 - USART 4 clock enable
Bit 20 - USART 5 clock enable
Bit 21 - I2C 1 clock enable
Bit 22 - I2C 2 clock enable
Bit 23 - USB clock enable
Bit 25 - CAN clock enable
Bit 26 - DAC2 interface clock enable
Bit 28 - Power interface clock enable
Bit 29 - DAC interface clock enable
Bit 30 - I2C3 clock enable
Bit 0 - External Low Speed oscillator enable
Bit 2 - External Low Speed oscillator bypass
Bits 3:4 - LSE oscillator drive capability
Bits 8:9 - RTC clock source selection
Bit 15 - RTC clock enable
Bit 16 - Backup domain software reset
Bit 0 - Internal low speed oscillator enable
Bit 24 - Remove reset flag
Bit 25 - Option byte loader reset flag
Bit 27 - POR/PDR reset flag
Bit 28 - Software reset flag
Bit 29 - Independent watchdog reset flag
Bit 30 - Window watchdog reset flag
Bit 31 - Low-power reset flag
Bit 23 - Reset flag of the 1.8 V domain
Bit 16 - I/O port H reset
Bit 17 - I/O port A reset
Bit 18 - I/O port B reset
Bit 19 - I/O port C reset
Bit 20 - I/O port D reset
Bit 21 - I/O port E reset
Bit 22 - I/O port F reset
Bit 23 - Touch sensing controller reset
Bit 24 - Touch sensing controller reset
Bit 28 - ADC1 and ADC2 reset
Bit 29 - ADC3 and ADC4 reset
Bits 0:3 - PREDIV division factor
Bits 4:8 - ADC1 and ADC2 prescaler
Bits 9:13 - ADC3 and ADC4 prescaler
Bits 0:1 - USART1 clock source selection
Bit 4 - I2C1 clock source selection
Bit 5 - I2C2 clock source selection
Bit 6 - I2C3 clock source selection
Bits 16:17 - USART2 clock source selection
Bits 18:19 - USART3 clock source selection
Bit 8 - Timer1 clock source selection
Bit 9 - Timer8 clock source selection
Bits 20:21 - UART4 clock source selection
Bits 22:23 - UART5 clock source selection
Bit 15 - Timer20 clock source selection
Bit 10 - Timer15 clock source selection
Bit 11 - Timer16 clock source selection
Bit 13 - Timer17 clock source selection
Bit 24 - Timer2 clock source selection
Bit 25 - Timer34 clock source selection
Bit 1 - Transfer complete interrupt enable
Bit 2 - Half Transfer interrupt enable
Bit 3 - Transfer error interrupt enable
Bit 4 - Data transfer direction
Bit 6 - Peripheral increment mode
Bit 7 - Memory increment mode
Bits 8:9 - Peripheral size
Bits 12:13 - Channel Priority level
Bit 14 - Memory to memory mode
Bits 0:15 - Number of data to transfer
Bits 0:31 - Peripheral address
Bits 0:31 - Memory address
Bit 0 - Channel 1 Global interrupt clear
Bit 1 - Channel 1 Transfer Complete clear
Bit 2 - Channel 1 Half Transfer clear
Bit 3 - Channel 1 Transfer Error clear
Bit 4 - Channel 2 Global interrupt clear
Bit 5 - Channel 2 Transfer Complete clear
Bit 6 - Channel 2 Half Transfer clear
Bit 7 - Channel 2 Transfer Error clear
Bit 8 - Channel 3 Global interrupt clear
Bit 9 - Channel 3 Transfer Complete clear
Bit 10 - Channel 3 Half Transfer clear
Bit 11 - Channel 3 Transfer Error clear
Bit 12 - Channel 4 Global interrupt clear
Bit 13 - Channel 4 Transfer Complete clear
Bit 14 - Channel 4 Half Transfer clear
Bit 15 - Channel 4 Transfer Error clear
Bit 16 - Channel 5 Global interrupt clear
Bit 17 - Channel 5 Transfer Complete clear
Bit 18 - Channel 5 Half Transfer clear
Bit 19 - Channel 5 Transfer Error clear
Bit 20 - Channel 6 Global interrupt clear
Bit 21 - Channel 6 Transfer Complete clear
Bit 22 - Channel 6 Half Transfer clear
Bit 23 - Channel 6 Transfer Error clear
Bit 24 - Channel 7 Global interrupt clear
Bit 25 - Channel 7 Transfer Complete clear
Bit 26 - Channel 7 Half Transfer clear
Bit 27 - Channel 7 Transfer Error clear
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit3
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output compare 1 fast enable
Bit 3 - Output compare 1 preload enable
Bits 4:6 - Output compare 1 mode
Bit 7 - Output compare 1 clear enable
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output compare 2 fast enable
Bit 11 - Output compare 2 preload enable
Bits 12:14 - Output compare 2 mode
Bit 15 - Output compare 2 clear enable
Bit 16 - Output compare 1 mode bit 3
Bit 24 - Output compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bits 0:1 - Capture/Compare 3 selection
Bit 2 - Output compare 3 fast enable
Bit 3 - Output compare 3 preload enable
Bits 4:6 - Output compare 3 mode
Bit 7 - Output compare 3 clear enable
Bits 8:9 - Capture/Compare 4 selection
Bit 10 - Output compare 4 fast enable
Bit 11 - Output compare 4 preload enable
Bits 12:14 - Output compare 4 mode
Bit 15 - Output compare 4 clear enable
Bit 16 - Output compare 3 mode bit3
Bit 24 - Output compare 4 mode bit3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:31 - Low counter value
Bits 0:15 - Prescaler value
Bits 0:31 - Low Auto-reload value
Bits 0:31 - Low Capture/Compare 1 value
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 0 - Capture/compare preloaded control
Bit 2 - Capture/compare control update selection
Bit 3 - Capture/compare DMA selection
Bits 4:6 - Master mode selection
Bit 8 - Output Idle state 1
Bit 9 - Output Idle state 1
Bit 10 - Output Idle state 2
Bits 0:2 - Slave mode selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bit 16 - Slave mode selection bit 3
Bit 0 - Update interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 5 - COM interrupt enable
Bit 6 - Trigger interrupt enable
Bit 7 - Break interrupt enable
Bit 8 - Update DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 13 - COM DMA request enable
Bit 14 - Trigger DMA request enable
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output Compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output Compare 2 fast enable
Bit 11 - Output Compare 2 preload enable
Bits 12:14 - Output Compare 2 mode
Bit 16 - Output Compare 1 mode bit 3
Bit 24 - Output Compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:15 - Capture/Compare 2 value
Bit 15 - Main output enable
Bit 14 - Automatic output enable
Bit 11 - Off-state selection for Run mode
Bit 10 - Off-state selection for Idle mode
Bits 8:9 - Lock configuration
Bits 0:7 - Dead-time generator setup
Bits 16:19 - Break filter
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
Bit 0 - Update interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 5 - COM interrupt enable
Bit 6 - Trigger interrupt enable
Bit 7 - Break interrupt enable
Bit 8 - Update DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 13 - COM DMA request enable
Bit 14 - Trigger DMA request enable
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output Compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bit 16 - Output Compare 1 mode
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
Bit 0 - Update interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 5 - COM interrupt enable
Bit 6 - Trigger interrupt enable
Bit 7 - Break interrupt enable
Bit 8 - Update DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 13 - COM DMA request enable
Bit 14 - Trigger DMA request enable
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output Compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bit 16 - Output Compare 1 mode
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 27 - End of Block interrupt enable
Bit 26 - Receiver timeout interrupt enable
Bits 21:25 - Driver Enable assertion time
Bits 16:20 - Driver Enable deassertion time
Bit 15 - Oversampling mode
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
Bit 3 - Transmitter enable
Bit 1 - USART enable in Stop mode
Bit 23 - Receiver timeout enable
Bits 21:22 - Auto baud rate mode
Bit 20 - Auto baud rate enable
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 8 - Last bit clock pulse
Bit 6 - LIN break detection interrupt enable
Bit 5 - LIN break detection length
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bits 17:19 - Smartcard auto-retry count
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 11 - One sample bit method enable
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 5 - Smartcard mode enable
Bit 4 - Smartcard NACK enable
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
Bits 0:15 - mantissa of USARTDIV
Bits 8:15 - Guard time value
Bits 0:7 - Prescaler value
Bits 24:31 - Block Length
Bits 0:23 - Receiver timeout value
Bit 4 - Transmit data flush request
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
Bit 0 - Auto baud rate request
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 12 - End of timeout clear flag
Bit 11 - Receiver timeout clear flag
Bit 8 - LIN break detection clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
Bits 0:8 - Transmit data value
Bit 15 - Bidirectional data mode enable
Bit 14 - Output enable in bidirectional mode
Bit 13 - Hardware CRC calculation enable
Bit 12 - CRC transfer next
Bit 9 - Software slave management
Bit 8 - Internal slave select
Bits 3:5 - Baud rate control
Bit 0 - Rx buffer DMA enable
Bit 1 - Tx buffer DMA enable
Bit 3 - NSS pulse management
Bit 5 - Error interrupt enable
Bit 6 - RX buffer not empty interrupt enable
Bit 7 - Tx buffer empty interrupt enable
Bit 12 - FIFO reception threshold
Bit 13 - Last DMA transfer for reception
Bit 14 - Last DMA transfer for transmission
Bits 0:15 - Data register
Bits 0:15 - CRC polynomial register
Bit 11 - I2S mode selection
Bits 8:9 - I2S configuration mode
Bit 7 - PCM frame synchronization
Bits 4:5 - I2S standard selection
Bit 3 - Steady state clock polarity
Bits 1:2 - Data length to be transferred
Bit 0 - Channel length (number of bits per audio channel)
Bit 9 - Master clock output enable
Bit 8 - Odd factor for the prescaler
Bits 0:7 - I2S Linear prescaler
Bit 0 - Interrupt Mask on line 0
Bit 1 - Interrupt Mask on line 1
Bit 2 - Interrupt Mask on line 2
Bit 3 - Interrupt Mask on line 3
Bit 4 - Interrupt Mask on line 4
Bit 5 - Interrupt Mask on line 5
Bit 6 - Interrupt Mask on line 6
Bit 7 - Interrupt Mask on line 7
Bit 8 - Interrupt Mask on line 8
Bit 9 - Interrupt Mask on line 9
Bit 10 - Interrupt Mask on line 10
Bit 11 - Interrupt Mask on line 11
Bit 12 - Interrupt Mask on line 12
Bit 13 - Interrupt Mask on line 13
Bit 14 - Interrupt Mask on line 14
Bit 15 - Interrupt Mask on line 15
Bit 16 - Interrupt Mask on line 16
Bit 17 - Interrupt Mask on line 17
Bit 18 - Interrupt Mask on line 18
Bit 19 - Interrupt Mask on line 19
Bit 20 - Interrupt Mask on line 20
Bit 21 - Interrupt Mask on line 21
Bit 22 - Interrupt Mask on line 22
Bit 23 - Interrupt Mask on line 23
Bit 24 - Interrupt Mask on line 24
Bit 25 - Interrupt Mask on line 25
Bit 26 - Interrupt Mask on line 26
Bit 27 - Interrupt Mask on line 27
Bit 28 - Interrupt Mask on line 28
Bit 29 - Interrupt Mask on line 29
Bit 30 - Interrupt Mask on line 30
Bit 31 - Interrupt Mask on line 31
Bit 0 - Event Mask on line 0
Bit 1 - Event Mask on line 1
Bit 2 - Event Mask on line 2
Bit 3 - Event Mask on line 3
Bit 4 - Event Mask on line 4
Bit 5 - Event Mask on line 5
Bit 6 - Event Mask on line 6
Bit 7 - Event Mask on line 7
Bit 8 - Event Mask on line 8
Bit 9 - Event Mask on line 9
Bit 10 - Event Mask on line 10
Bit 11 - Event Mask on line 11
Bit 12 - Event Mask on line 12
Bit 13 - Event Mask on line 13
Bit 14 - Event Mask on line 14
Bit 15 - Event Mask on line 15
Bit 16 - Event Mask on line 16
Bit 17 - Event Mask on line 17
Bit 18 - Event Mask on line 18
Bit 19 - Event Mask on line 19
Bit 20 - Event Mask on line 20
Bit 21 - Event Mask on line 21
Bit 22 - Event Mask on line 22
Bit 23 - Event Mask on line 23
Bit 24 - Event Mask on line 24
Bit 25 - Event Mask on line 25
Bit 26 - Event Mask on line 26
Bit 27 - Event Mask on line 27
Bit 28 - Event Mask on line 28
Bit 29 - Event Mask on line 29
Bit 30 - Event Mask on line 30
Bit 31 - Event Mask on line 31
Bit 0 - Rising trigger event configuration of line 0
Bit 1 - Rising trigger event configuration of line 1
Bit 2 - Rising trigger event configuration of line 2
Bit 3 - Rising trigger event configuration of line 3
Bit 4 - Rising trigger event configuration of line 4
Bit 5 - Rising trigger event configuration of line 5
Bit 6 - Rising trigger event configuration of line 6
Bit 7 - Rising trigger event configuration of line 7
Bit 8 - Rising trigger event configuration of line 8
Bit 9 - Rising trigger event configuration of line 9
Bit 10 - Rising trigger event configuration of line 10
Bit 11 - Rising trigger event configuration of line 11
Bit 12 - Rising trigger event configuration of line 12
Bit 13 - Rising trigger event configuration of line 13
Bit 14 - Rising trigger event configuration of line 14
Bit 15 - Rising trigger event configuration of line 15
Bit 16 - Rising trigger event configuration of line 16
Bit 17 - Rising trigger event configuration of line 17
Bit 18 - Rising trigger event configuration of line 18
Bit 19 - Rising trigger event configuration of line 19
Bit 20 - Rising trigger event configuration of line 20
Bit 21 - Rising trigger event configuration of line 21
Bit 22 - Rising trigger event configuration of line 22
Bit 29 - Rising trigger event configuration of line 29
Bit 30 - Rising trigger event configuration of line 30
Bit 31 - Rising trigger event configuration of line 31
Bit 0 - Falling trigger event configuration of line 0
Bit 1 - Falling trigger event configuration of line 1
Bit 2 - Falling trigger event configuration of line 2
Bit 3 - Falling trigger event configuration of line 3
Bit 4 - Falling trigger event configuration of line 4
Bit 5 - Falling trigger event configuration of line 5
Bit 6 - Falling trigger event configuration of line 6
Bit 7 - Falling trigger event configuration of line 7
Bit 8 - Falling trigger event configuration of line 8
Bit 9 - Falling trigger event configuration of line 9
Bit 10 - Falling trigger event configuration of line 10
Bit 11 - Falling trigger event configuration of line 11
Bit 12 - Falling trigger event configuration of line 12
Bit 13 - Falling trigger event configuration of line 13
Bit 14 - Falling trigger event configuration of line 14
Bit 15 - Falling trigger event configuration of line 15
Bit 16 - Falling trigger event configuration of line 16
Bit 17 - Falling trigger event configuration of line 17
Bit 18 - Falling trigger event configuration of line 18
Bit 19 - Falling trigger event configuration of line 19
Bit 20 - Falling trigger event configuration of line 20
Bit 21 - Falling trigger event configuration of line 21
Bit 22 - Falling trigger event configuration of line 22
Bit 29 - Falling trigger event configuration of line 29
Bit 30 - Falling trigger event configuration of line 30.
Bit 31 - Falling trigger event configuration of line 31
Bit 0 - Software Interrupt on line 0
Bit 1 - Software Interrupt on line 1
Bit 2 - Software Interrupt on line 2
Bit 3 - Software Interrupt on line 3
Bit 4 - Software Interrupt on line 4
Bit 5 - Software Interrupt on line 5
Bit 6 - Software Interrupt on line 6
Bit 7 - Software Interrupt on line 7
Bit 8 - Software Interrupt on line 8
Bit 9 - Software Interrupt on line 9
Bit 10 - Software Interrupt on line 10
Bit 11 - Software Interrupt on line 11
Bit 12 - Software Interrupt on line 12
Bit 13 - Software Interrupt on line 13
Bit 14 - Software Interrupt on line 14
Bit 15 - Software Interrupt on line 15
Bit 16 - Software Interrupt on line 16
Bit 17 - Software Interrupt on line 17
Bit 18 - Software Interrupt on line 18
Bit 19 - Software Interrupt on line 19
Bit 20 - Software Interrupt on line 20
Bit 21 - Software Interrupt on line 21
Bit 22 - Software Interrupt on line 22
Bit 29 - Software Interrupt on line 29
Bit 30 - Software Interrupt on line 309
Bit 31 - Software Interrupt on line 319
Bit 0 - Interrupt Mask on external/internal line 32
Bit 1 - Interrupt Mask on external/internal line 33
Bit 2 - Interrupt Mask on external/internal line 34
Bit 3 - Interrupt Mask on external/internal line 35
Bit 0 - Event mask on external/internal line 32
Bit 1 - Event mask on external/internal line 33
Bit 2 - Event mask on external/internal line 34
Bit 3 - Event mask on external/internal line 35
Bit 0 - Rising trigger event configuration bit of line 32
Bit 1 - Rising trigger event configuration bit of line 33
Bit 0 - Falling trigger event configuration bit of line 32
Bit 1 - Falling trigger event configuration bit of line 33
Bit 0 - Software interrupt on line 32
Bit 1 - Software interrupt on line 33
Bit 0 - Pending bit on line 32
Bit 1 - Pending bit on line 33
Bit 0 - Low-power deep sleep
Bit 1 - Power down deepsleep
Bit 2 - Clear wakeup flag
Bit 3 - Clear standby flag
Bit 4 - Power voltage detector enable
Bits 5:7 - PVD level selection
Bit 8 - Disable backup domain write protection
Bit 10 - Enable WKUP3 pin
Bits 8:13 - CAN2 start bank
Bit 0 - Filter scale configuration
Bit 1 - Filter scale configuration
Bit 2 - Filter scale configuration
Bit 3 - Filter scale configuration
Bit 4 - Filter scale configuration
Bit 5 - Filter scale configuration
Bit 6 - Filter scale configuration
Bit 7 - Filter scale configuration
Bit 8 - Filter scale configuration
Bit 9 - Filter scale configuration
Bit 10 - Filter scale configuration
Bit 11 - Filter scale configuration
Bit 12 - Filter scale configuration
Bit 13 - Filter scale configuration
Bit 14 - Filter scale configuration
Bit 15 - Filter scale configuration
Bit 16 - Filter scale configuration
Bit 17 - Filter scale configuration
Bit 18 - Filter scale configuration
Bit 19 - Filter scale configuration
Bit 20 - Filter scale configuration
Bit 21 - Filter scale configuration
Bit 22 - Filter scale configuration
Bit 23 - Filter scale configuration
Bit 24 - Filter scale configuration
Bit 25 - Filter scale configuration
Bit 26 - Filter scale configuration
Bit 27 - Filter scale configuration
Bit 0 - Filter FIFO assignment for filter 0
Bit 1 - Filter FIFO assignment for filter 1
Bit 2 - Filter FIFO assignment for filter 2
Bit 3 - Filter FIFO assignment for filter 3
Bit 4 - Filter FIFO assignment for filter 4
Bit 5 - Filter FIFO assignment for filter 5
Bit 6 - Filter FIFO assignment for filter 6
Bit 7 - Filter FIFO assignment for filter 7
Bit 8 - Filter FIFO assignment for filter 8
Bit 9 - Filter FIFO assignment for filter 9
Bit 10 - Filter FIFO assignment for filter 10
Bit 11 - Filter FIFO assignment for filter 11
Bit 12 - Filter FIFO assignment for filter 12
Bit 13 - Filter FIFO assignment for filter 13
Bit 14 - Filter FIFO assignment for filter 14
Bit 15 - Filter FIFO assignment for filter 15
Bit 16 - Filter FIFO assignment for filter 16
Bit 17 - Filter FIFO assignment for filter 17
Bit 18 - Filter FIFO assignment for filter 18
Bit 19 - Filter FIFO assignment for filter 19
Bit 20 - Filter FIFO assignment for filter 20
Bit 21 - Filter FIFO assignment for filter 21
Bit 22 - Filter FIFO assignment for filter 22
Bit 23 - Filter FIFO assignment for filter 23
Bit 24 - Filter FIFO assignment for filter 24
Bit 25 - Filter FIFO assignment for filter 25
Bit 26 - Filter FIFO assignment for filter 26
Bit 27 - Filter FIFO assignment for filter 27
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bit 8 - Expected start of frame interrupt mask
Bit 9 - Start of frame interrupt mask
Bit 10 - USB reset interrupt mask
Bit 11 - Suspend mode interrupt mask
Bit 12 - Wakeup interrupt mask
Bit 13 - Error interrupt mask
Bit 14 - Packet memory area over / underrun interrupt mask
Bit 15 - Correct transfer interrupt mask
Bit 8 - Expected start frame
Bit 11 - Suspend mode request
Bit 14 - Packet memory area over / underrun
Bit 0 - Peripheral enable
Bit 1 - TX Interrupt enable
Bit 2 - RX Interrupt enable
Bit 3 - Address match interrupt enable (slave only)
Bit 4 - Not acknowledge received interrupt enable
Bit 5 - STOP detection Interrupt enable
Bit 6 - Transfer Complete interrupt enable
Bit 7 - Error interrupts enable
Bits 8:11 - Digital noise filter
Bit 12 - Analog noise filter OFF
Bit 14 - DMA transmission requests enable
Bit 15 - DMA reception requests enable
Bit 16 - Slave byte control
Bit 17 - Clock stretching disable
Bit 18 - Wakeup from STOP enable
Bit 19 - General call enable
Bit 20 - SMBus Host address enable
Bit 21 - SMBus Device Default address enable
Bit 22 - SMBUS alert enable
Bit 26 - Packet error checking byte
Bit 25 - Automatic end mode (master mode)
Bit 24 - NBYTES reload mode
Bits 16:23 - Number of bytes
Bit 15 - NACK generation (slave mode)
Bit 14 - Stop generation (master mode)
Bit 13 - Start generation
Bit 12 - 10-bit address header only read direction (master receiver mode)
Bit 11 - 10-bit addressing mode (master mode)
Bit 10 - Transfer direction (master mode)
Bits 0:9 - Slave address bit 9:8 (master mode)
Bit 10 - Own Address 1 10-bit mode
Bit 15 - Own Address 1 enable
Bits 0:9 - Interface address
Bits 1:7 - Interface address
Bits 8:10 - Own Address 2 masks
Bit 15 - Own Address 2 enable
Bits 0:7 - SCL low period (master mode)
Bits 8:15 - SCL high period (master mode)
Bits 16:19 - Data hold time
Bits 20:23 - Data setup time
Bits 28:31 - Timing prescaler
Bits 0:11 - Bus timeout A
Bit 12 - Idle clock timeout detection
Bit 15 - Clock timeout enable
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
[src]
Bit 31 - Extended clock timeout enable
Bit 1 - Transmit interrupt status (transmitters)
Bit 0 - Transmit data register empty (transmitters)
Bit 13 - Alert flag clear
Bit 12 - Timeout detection flag clear
Bit 11 - PEC Error flag clear
Bit 10 - Overrun/Underrun flag clear
Bit 9 - Arbitration lost flag clear
Bit 8 - Bus error flag clear
Bit 5 - Stop detection flag clear
Bit 4 - Not Acknowledge flag clear
Bit 3 - Address Matched flag clear
Bits 0:7 - 8-bit transmit data
Bits 0:2 - Prescaler divider
Bits 0:11 - Watchdog counter reload value
Bits 0:11 - Watchdog counter window value
Bit 9 - Early wakeup interrupt
Bits 0:6 - 7-bit window value
Bit 0 - Early wakeup interrupt flag
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bits 20:23 - Year tens in BCD format
Bits 16:19 - Year units in BCD format
Bits 13:15 - Week day units
Bit 12 - Month tens in BCD format
Bits 8:11 - Month units in BCD format
Bits 4:5 - Date tens in BCD format
Bits 0:3 - Date units in BCD format
Bits 0:2 - Wakeup clock selection
Bit 3 - Time-stamp event active edge
Bit 4 - Reference clock detection enable (50 or 60 Hz)
Bit 5 - Bypass the shadow registers
Bit 10 - Wakeup timer enable
Bit 11 - Time stamp enable
Bit 12 - Alarm A interrupt enable
Bit 13 - Alarm B interrupt enable
Bit 14 - Wakeup timer interrupt enable
Bit 15 - Time-stamp interrupt enable
Bit 16 - Add 1 hour (summer time change)
Bit 17 - Subtract 1 hour (winter time change)
Bit 19 - Calibration output selection
Bits 21:22 - Output selection
Bit 23 - Calibration output enable
Bit 3 - Shift operation pending
Bit 5 - Registers synchronization flag
Bit 7 - Initialization mode
Bit 10 - Wakeup timer flag
Bit 12 - Time-stamp overflow flag
Bit 13 - Tamper detection flag
Bit 14 - RTC_TAMP2 detection flag
Bit 15 - RTC_TAMP3 detection flag
Bits 16:22 - Asynchronous prescaler factor
Bits 0:14 - Synchronous prescaler factor
Bits 0:15 - Wakeup auto-reload value bits
Bit 31 - Alarm A date mask
Bit 30 - Week day selection
Bits 28:29 - Date tens in BCD format
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm A hours mask
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm A minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm A seconds mask
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bit 31 - Alarm B date mask
Bit 30 - Week day selection
Bits 28:29 - Date tens in BCD format
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm B hours mask
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm B minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm B seconds mask
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bits 0:7 - Write protection key
Bits 0:14 - Subtract a fraction of a second
Bit 15 - Increase frequency of RTC by 488.5 ppm
Bit 14 - Use an 8-second calibration cycle period
Bit 13 - Use a 16-second calibration cycle period
Bits 0:8 - Calibration minus
Bit 0 - Tamper 1 detection enable
Bit 1 - Active level for tamper 1
Bit 2 - Tamper interrupt enable
Bit 3 - Tamper 2 detection enable
Bit 4 - Active level for tamper 2
Bit 5 - Tamper 3 detection enable
Bit 6 - Active level for tamper 3
Bit 7 - Activate timestamp on tamper detection event
Bits 8:10 - Tamper sampling frequency
Bits 11:12 - Tamper filter count
Bits 13:14 - Tamper precharge duration
Bit 15 - TAMPER pull-up disable
Bits 24:27 - Mask the most-significant bits starting at this bit
Bits 0:14 - Sub seconds value
Bits 24:27 - Mask the most-significant bits starting at this bit
Bits 0:14 - Sub seconds value
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 8 - Update DMA request enable
Bit 0 - Update interrupt enable
Bit 0 - Update interrupt flag
Bit 0 - Update generation
Bits 0:15 - Low counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Low Auto-reload value
Bit 29 - DAC channel2 DMA underrun interrupt enable
Bit 28 - DAC channel2 DMA enable
Bits 24:27 - DAC channel2 mask/amplitude selector
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
Bits 19:21 - DAC channel2 trigger selection
Bit 18 - DAC channel2 trigger enable
Bit 17 - DAC channel2 output buffer disable
Bit 16 - DAC channel2 enable
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
Bit 12 - DAC channel1 DMA enable
Bits 8:11 - DAC channel1 mask/amplitude selector
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
Bits 3:5 - DAC channel1 trigger selection
Bit 2 - DAC channel1 trigger enable
Bit 1 - DAC channel1 output buffer disable
Bit 0 - DAC channel1 enable
Bit 1 - DAC channel2 software trigger
Bit 0 - DAC channel1 software trigger
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bits 0:11 - DAC channel2 12-bit right-aligned data
Bits 4:15 - DAC channel2 12-bit left-aligned data
Bits 0:7 - DAC channel2 8-bit right-aligned data
Bits 16:27 - DAC channel2 12-bit right-aligned data
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 20:31 - DAC channel2 12-bit left-aligned data
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 8:15 - DAC channel2 8-bit right-aligned data
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bit 29 - DAC channel2 DMA underrun flag
Bit 13 - DAC channel1 DMA underrun flag
Bit 2 - Debug Standby Mode
Bit 5 - Trace pin assignment control
Bits 6:7 - Trace pin assignment control
Bit 0 - Debug Timer 2 stopped when Core is halted
Bit 1 - Debug Timer 3 stopped when Core is halted
Bit 2 - Debug Timer 4 stopped when Core is halted
Bit 3 - Debug Timer 5 stopped when Core is halted
Bit 4 - Debug Timer 6 stopped when Core is halted
Bit 5 - Debug Timer 7 stopped when Core is halted
Bit 6 - Debug Timer 12 stopped when Core is halted
Bit 7 - Debug Timer 13 stopped when Core is halted
Bit 8 - Debug Timer 14 stopped when Core is halted
Bit 9 - Debug Timer 18 stopped when Core is halted
Bit 10 - Debug RTC stopped when Core is halted
Bit 11 - Debug Window Wachdog stopped when Core is halted
Bit 12 - Debug Independent Wachdog stopped when Core is halted
Bit 21 - SMBUS timeout mode stopped when Core is halted
Bit 22 - SMBUS timeout mode stopped when Core is halted
Bit 25 - Debug CAN stopped when core is halted
Bit 2 - Debug Timer 15 stopped when Core is halted
Bit 3 - Debug Timer 16 stopped when Core is halted
Bit 4 - Debug Timer 17 stopped when Core is halted
Bit 5 - Debug Timer 19 stopped when Core is halted
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 0 - Capture/compare preloaded control
Bit 2 - Capture/compare control update selection
Bit 3 - Capture/compare DMA selection
Bits 4:6 - Master mode selection
Bit 8 - Output Idle state 1
Bit 9 - Output Idle state 1
Bit 10 - Output Idle state 2
Bit 11 - Output Idle state 2
Bit 12 - Output Idle state 3
Bit 13 - Output Idle state 3
Bit 14 - Output Idle state 4
Bit 16 - Output Idle state 5
Bit 18 - Output Idle state 6
Bits 20:23 - Master mode selection 2
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit 3
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 0 - Update interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 5 - COM interrupt flag
Bit 6 - Trigger interrupt flag
Bit 7 - Break interrupt flag
Bit 8 - Break 2 interrupt flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 12 - Capture/Compare 4 overcapture flag
Bit 16 - Capture/Compare 5 interrupt flag
Bit 17 - Capture/Compare 6 interrupt flag
Bit 0 - Update generation
Bit 1 - Capture/compare 1 generation
Bit 2 - Capture/compare 2 generation
Bit 3 - Capture/compare 3 generation
Bit 4 - Capture/compare 4 generation
Bit 5 - Capture/Compare control update generation
Bit 6 - Trigger generation
Bit 8 - Break 2 generation
Bit 15 - Output Compare 2 clear enable
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output Compare 1 clear enable
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bit 16 - Output Compare 1 mode bit 3
Bit 24 - Output Compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
Bit 16 - Output Compare 3 mode bit 3
Bit 24 - Output Compare 4 mode bit 3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 4 output Polarity
Bit 16 - Capture/Compare 5 output enable
Bit 17 - Capture/Compare 5 output Polarity
Bit 20 - Capture/Compare 6 output enable
Bit 21 - Capture/Compare 6 output Polarity
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:15 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 20:23 - Break 2 filter
Bit 25 - Break 2 polarity
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Output compare 5 fast enable
Bit 3 - Output compare 5 preload enable
Bits 4:6 - Output compare 5 mode
Bit 7 - Output compare 5 clear enable
Bit 10 - Output compare 6 fast enable
Bit 11 - Output compare 6 preload enable
Bits 12:14 - Output compare 6 mode
Bit 15 - Output compare 6 clear enable
Bit 16 - Outout Compare 5 mode bit 3
Bit 24 - Outout Compare 6 mode bit 3
Bits 0:15 - Capture/Compare 5 value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
Bits 0:15 - Capture/Compare 6 value
Bits 0:1 - TIM1_ETR_ADC1 remapping capability
Bits 2:3 - TIM1_ETR_ADC4 remapping capability
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bit 0 - Capture/compare preloaded control
Bit 2 - Capture/compare control update selection
Bit 3 - Capture/compare DMA selection
Bits 4:6 - Master mode selection
Bit 8 - Output Idle state 1
Bit 9 - Output Idle state 1
Bit 10 - Output Idle state 2
Bit 11 - Output Idle state 2
Bit 12 - Output Idle state 3
Bit 13 - Output Idle state 3
Bit 14 - Output Idle state 4
Bit 16 - Output Idle state 5
Bit 18 - Output Idle state 6
Bits 20:23 - Master mode selection 2
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit 3
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 0 - Update interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 5 - COM interrupt flag
Bit 6 - Trigger interrupt flag
Bit 7 - Break interrupt flag
Bit 8 - Break 2 interrupt flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 12 - Capture/Compare 4 overcapture flag
Bit 16 - Capture/Compare 5 interrupt flag
Bit 17 - Capture/Compare 6 interrupt flag
Bit 0 - Update generation
Bit 1 - Capture/compare 1 generation
Bit 2 - Capture/compare 2 generation
Bit 3 - Capture/compare 3 generation
Bit 4 - Capture/compare 4 generation
Bit 5 - Capture/Compare control update generation
Bit 6 - Trigger generation
Bit 8 - Break 2 generation
Bit 15 - Output Compare 2 clear enable
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output Compare 1 clear enable
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bit 16 - Output Compare 1 mode bit 3
Bit 24 - Output Compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
Bit 16 - Output Compare 3 mode bit 3
Bit 24 - Output Compare 4 mode bit 3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 4 output Polarity
Bit 16 - Capture/Compare 5 output enable
Bit 17 - Capture/Compare 5 output Polarity
Bit 20 - Capture/Compare 6 output enable
Bit 21 - Capture/Compare 6 output Polarity
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:15 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
Bits 20:23 - Break 2 filter
Bit 25 - Break 2 polarity
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Output compare 5 fast enable
Bit 3 - Output compare 5 preload enable
Bits 4:6 - Output compare 5 mode
Bit 7 - Output compare 5 clear enable
Bit 10 - Output compare 6 fast enable
Bit 11 - Output compare 6 preload enable
Bits 12:14 - Output compare 6 mode
Bit 15 - Output compare 6 clear enable
Bit 16 - Outout Compare 5 mode bit 3
Bit 24 - Outout Compare 6 mode bit 3
Bits 0:15 - Capture/Compare 5 value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
Bits 0:15 - Capture/Compare 6 value
Bits 0:1 - TIM8_ETR_ADC2 remapping capability
Bits 2:3 - TIM8_ETR_ADC3 remapping capability
Bit 0 - Differential mode for channels 15 to 1
Bit 1 - Differential mode for channels 15 to 1
Bit 2 - Differential mode for channels 15 to 1
Bit 3 - Differential mode for channels 15 to 1
Bit 4 - Differential mode for channels 15 to 1
Bit 5 - Differential mode for channels 15 to 1
Bit 6 - Differential mode for channels 15 to 1
Bit 7 - Differential mode for channels 15 to 1
Bit 8 - Differential mode for channels 15 to 1
Bit 9 - Differential mode for channels 15 to 1
Bit 10 - Differential mode for channels 15 to 1
Bit 11 - Differential mode for channels 15 to 1
Bit 12 - Differential mode for channels 15 to 1
Bit 13 - Differential mode for channels 15 to 1
Bit 14 - Differential mode for channels 15 to 1
Bit 15 - Differential mode for channels 15 to 1
Bit 16 - Differential mode for channels 15 to 1
Bit 17 - Differential mode for channels 15 to 1
Bits 0:4 - Dual ADC mode selection
Bits 8:11 - Delay between 2 sampling phases
Bit 13 - DMA configuration (for multi-ADC mode)
Bits 14:15 - Direct memory access mode for multi ADC mode
Bits 16:17 - ADC clock mode
Bit 23 - Temperature sensor enable
Bits 0:2 - Memory mapping selection bits
Bit 5 - USB interrupt remap
Bit 6 - Timer 1 ITR3 selection
Bit 7 - DAC trigger remap (when TSEL = 001)
Bit 8 - ADC24 DMA remapping bit
Bit 11 - TIM16 DMA request remapping bit
Bit 12 - TIM17 DMA request remapping bit
Bit 13 - TIM6 and DAC1 DMA request remapping bit
Bit 14 - TIM7 and DAC2 DMA request remapping bit
Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 20 - I2C1 Fast Mode Plus
Bit 21 - I2C2 Fast Mode Plus
Bits 22:23 - Encoder mode
Bit 31 - Inexact interrupt enable
Bit 30 - Input denormal interrupt enable
Bit 29 - Overflow interrupt enable
Bit 28 - Underflow interrupt enable
Bit 27 - Devide-by-zero interrupt enable
Bit 26 - Invalid operation interrupt enable
Bit 15 - DAC2 channel1 DMA remap
Bit 24 - I2C3 Fast Mode Plus
Bits 12:15 - EXTI 3 configuration bits
Bits 8:11 - EXTI 2 configuration bits
Bits 4:7 - EXTI 1 configuration bits
Bits 0:3 - EXTI 0 configuration bits
Bits 12:15 - EXTI 7 configuration bits
Bits 8:11 - EXTI 6 configuration bits
Bits 4:7 - EXTI 5 configuration bits
Bits 0:3 - EXTI 4 configuration bits
Bits 12:15 - EXTI 11 configuration bits
Bits 8:11 - EXTI 10 configuration bits
Bits 4:7 - EXTI 9 configuration bits
Bits 0:3 - EXTI 8 configuration bits
Bits 12:15 - EXTI 15 configuration bits
Bits 8:11 - EXTI 14 configuration bits
Bits 4:7 - EXTI 13 configuration bits
Bits 0:3 - EXTI 12 configuration bits
Bit 0 - Cortex-M0 LOCKUP bit enable bit
Bit 1 - SRAM parity lock bit
Bit 2 - PVD lock enable bit
Bit 4 - Bypass address bit 29 in parity calculation
Bits 0:1 - SPI1_RX DMA remapping bit
Bits 2:3 - SPI1_TX DMA remapping bit
Bits 4:5 - I2C1_RX DMA remapping bit
Bits 6:7 - I2C1_TX DMA remapping bit
Bits 8:9 - ADC2 DMA remapping bit
Bit 0 - Controls the Input trigger of ADC12 regular channel EXT2
Bit 1 - Controls the Input trigger of ADC12 regular channel EXT3
Bit 2 - Controls the Input trigger of ADC12 regular channel EXT5
Bit 3 - Controls the Input trigger of ADC12 regular channel EXT13
Bit 4 - Controls the Input trigger of ADC12 regular channel EXT15
Bit 5 - Controls the Input trigger of ADC12 injected channel JEXT3
Bit 6 - Controls the Input trigger of ADC12 injected channel JEXT6
Bit 7 - Controls the Input trigger of ADC12 injected channel JEXT13
Bit 8 - Controls the Input trigger of ADC34 regular channel EXT5
Bit 9 - Controls the Input trigger of ADC34 regular channel EXT6
Bit 10 - Controls the Input trigger of ADC34 regular channel EXT15
Bit 11 - Controls the Input trigger of ADC34 injected channel JEXT5
Bit 12 - Controls the Input trigger of ADC34 injected channel JEXT11
Bit 13 - Controls the Input trigger of ADC34 injected channel JEXT14
Bits 16:19 - Bus turnaround phase duration
Bits 16:19 - Bus turnaround phase duration
Bits 16:19 - Bus turnaround phase duration
Bits 16:19 - Bus turnaround phase duration
Bits 3:31 - Location of unpopulated floating-point
Bit 0 - Invalid operation cumulative exception bit
Bit 1 - Division by zero cumulative exception bit.
Bit 2 - Overflow cumulative exception bit
Bit 3 - Underflow cumulative exception bit
Bit 4 - Inexact cumulative exception bit
Bit 7 - Input denormal cumulative exception bit.
Bits 22:23 - Rounding Mode control field
Bit 24 - Flush-to-zero mode control bit:
Bit 25 - Default NaN mode control bit
Bit 26 - Alternative half-precision control bit
Bit 28 - Overflow condition code flag
Bit 29 - Carry condition code flag
Bit 30 - Zero condition code flag
Bit 31 - Negative condition code flag
Bit 1 - SysTick exception request enable
Bit 2 - Clock source selection
Bits 0:23 - Current counter value
Bits 0:23 - Calibration value
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
Bit 31 - NOREF flag. Reads as zero
Bits 0:8 - Software generated interrupt ID
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit3
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output compare 1 fast enable
Bit 3 - Output compare 1 preload enable
Bits 4:6 - Output compare 1 mode
Bit 7 - Output compare 1 clear enable
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output compare 2 fast enable
Bit 11 - Output compare 2 preload enable
Bits 12:14 - Output compare 2 mode
Bit 15 - Output compare 2 clear enable
Bit 16 - Output compare 1 mode bit 3
Bit 24 - Output compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bits 0:1 - Capture/Compare 3 selection
Bit 2 - Output compare 3 fast enable
Bit 3 - Output compare 3 preload enable
Bits 4:6 - Output compare 3 mode
Bit 7 - Output compare 3 clear enable
Bits 8:9 - Capture/Compare 4 selection
Bit 10 - Output compare 4 fast enable
Bit 11 - Output compare 4 preload enable
Bits 12:14 - Output compare 4 mode
Bit 15 - Output compare 4 clear enable
Bit 16 - Output compare 3 mode bit3
Bit 24 - Output compare 4 mode bit3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:15 - Counter value
Bits 16:30 - High counter value
Bit 31 - if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 16:31 - High Auto-reload value
Bits 0:15 - Capture/Compare 1 value
Bits 16:31 - High Capture/Compare 1 value (on TIM2)
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 2 - Update request source
Bits 5:6 - Center-aligned mode selection
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bits 0:2 - Slave mode selection
Bit 3 - OCREF clear selection
Bits 4:6 - Trigger selection
Bit 7 - Master/Slave mode
Bits 8:11 - External trigger filter
Bits 12:13 - External trigger prescaler
Bit 14 - External clock enable
Bit 15 - External trigger polarity
Bit 16 - Slave mode selection bit3
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output compare 1 fast enable
Bit 3 - Output compare 1 preload enable
Bits 4:6 - Output compare 1 mode
Bit 7 - Output compare 1 clear enable
Bits 8:9 - Capture/Compare 2 selection
Bit 10 - Output compare 2 fast enable
Bit 11 - Output compare 2 preload enable
Bits 12:14 - Output compare 2 mode
Bit 15 - Output compare 2 clear enable
Bit 16 - Output compare 1 mode bit 3
Bit 24 - Output compare 2 mode bit 3
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bits 0:1 - Capture/Compare 3 selection
Bit 2 - Output compare 3 fast enable
Bit 3 - Output compare 3 preload enable
Bits 4:6 - Output compare 3 mode
Bit 7 - Output compare 3 clear enable
Bits 8:9 - Capture/Compare 4 selection
Bit 10 - Output compare 4 fast enable
Bit 11 - Output compare 4 preload enable
Bits 12:14 - Output compare 4 mode
Bit 15 - Output compare 4 clear enable
Bit 16 - Output compare 3 mode bit3
Bit 24 - Output compare 4 mode bit3
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:15 - Counter value
Bits 16:30 - High counter value
Bit 31 - if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 16:31 - High Auto-reload value
Bits 0:15 - Capture/Compare 1 value
Bits 16:31 - High Capture/Compare 1 value (on TIM2)
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 2:3 - OPAMP Non inverting input selection
Bits 5:6 - OPAMP inverting input selection
Bit 7 - Timer controlled Mux mode enable
Bit 8 - OPAMP inverting input secondary selection
Bits 9:10 - OPAMP Non inverting input secondary selection
Bit 11 - Calibration mode enable
Bits 12:13 - Calibration selection
Bits 14:17 - Gain in PGA mode
Bit 18 - User trimming enable
Bits 19:23 - Offset trimming value (PMOS)
Bits 24:28 - Offset trimming value (NMOS)
Bits 2:3 - OPAMP Non inverting input selection
Bits 5:6 - OPAMP inverting input selection
Bit 7 - Timer controlled Mux mode enable
Bit 8 - OPAMP inverting input secondary selection
Bits 9:10 - OPAMP Non inverting input secondary selection
Bit 11 - Calibration mode enable
Bits 12:13 - Calibration selection
Bits 14:17 - Gain in PGA mode
Bit 18 - User trimming enable
Bits 19:23 - Offset trimming value (PMOS)
Bits 24:28 - Offset trimming value (NMOS)
Bits 2:3 - OPAMP Non inverting input selection
Bits 5:6 - OPAMP inverting input selection
Bit 7 - Timer controlled Mux mode enable
Bit 8 - OPAMP inverting input secondary selection
Bits 9:10 - OPAMP Non inverting input secondary selection
Bit 11 - Calibration mode enable
Bits 12:13 - Calibration selection
Bits 14:17 - Gain in PGA mode
Bit 18 - User trimming enable
Bits 19:23 - Offset trimming value (PMOS)
Bits 24:28 - Offset trimming value (NMOS)
Bits 2:3 - OPAMP Non inverting input selection
Bits 5:6 - OPAMP inverting input selection
Bit 7 - Timer controlled Mux mode enable
Bit 8 - OPAMP inverting input secondary selection
Bits 9:10 - OPAMP Non inverting input secondary selection
Bit 11 - Calibration mode enable
Bits 12:13 - Calibration selection
Bits 14:17 - Gain in PGA mode
Bit 18 - User trimming enable
Bits 19:23 - Offset trimming value (PMOS)
Bits 24:28 - Offset trimming value (NMOS)
Bit 0 - Comparator 2 enable
Bits 4:6 - Comparator 2 inverting input selection
Bits 10:13 - Comparator 2 output selection
Bit 15 - Comparator 2 output polarity
Bits 18:20 - Comparator 2 blanking source
Bit 31 - Comparator 2 lock
Bits 2:3 - Comparator 2 mode
Bit 7 - Comparator 2 non inverted input
Bit 9 - Comparator 2 window mode
Bits 16:17 - Comparator 2 hysteresis
Bit 22 - Comparator 2 inverting input selection
Bit 0 - Comparator 4 enable
Bits 4:6 - Comparator 4 inverting input selection
Bits 10:13 - Comparator 4 output selection
Bit 15 - Comparator 4 output polarity
Bits 18:20 - Comparator 4 blanking source
Bit 31 - Comparator 4 lock
Bit 9 - Comparator 4 window mode
Bits 2:3 - Comparator 4 mode
Bit 7 - Comparator 4 non inverted input
Bits 16:17 - Comparator 4 hysteresis
Bit 22 - Comparator 4 inverting input selection
Bit 0 - Comparator 6 enable
Bits 4:6 - Comparator 6 inverting input selection
Bits 10:13 - Comparator 6 output selection
Bit 15 - Comparator 6 output polarity
Bits 18:20 - Comparator 6 blanking source
Bit 31 - Comparator 6 lock
Bit 9 - Comparator 6 window mode
Bits 2:3 - Comparator 6 mode
Bit 7 - Comparator 6 non inverted input
Bits 16:17 - Comparator 6 hysteresis
Bit 22 - Comparator 6 inverting input selection
Bit 0 - Comparator 3 enable
Bits 2:3 - Comparator 3 mode
Bits 4:6 - Comparator 3 inverting input selection
Bit 7 - Comparator 3 non inverted input
Bits 10:13 - Comparator 3 output selection
Bit 15 - Comparator 3 output polarity
Bits 16:17 - Comparator 3 hysteresis
Bits 18:20 - Comparator 3 blanking source
Bit 31 - Comparator 3 lock
Bit 0 - Comparator 5 enable
Bits 2:3 - Comparator 5 mode
Bits 4:6 - Comparator 5 inverting input selection
Bit 7 - Comparator 5 non inverted input
Bits 10:13 - Comparator 5 output selection
Bit 15 - Comparator 5 output polarity
Bits 16:17 - Comparator 5 hysteresis
Bits 18:20 - Comparator 5 blanking source
Bit 31 - Comparator 5 lock
Bit 0 - Comparator 7 enable
Bits 2:3 - Comparator 7 mode
Bits 4:6 - Comparator 7 inverting input selection
Bit 7 - Comparator 7 non inverted input
Bits 10:13 - Comparator 7 output selection
Bit 15 - Comparator 7 output polarity
Bits 16:17 - Comparator 7 hysteresis
Bits 18:20 - Comparator 7 blanking source
Bit 31 - Comparator 7 lock
Bit 0 - Comparator 1 enable
Bit 1 - Comparator 1 non inverting input connection to DAC output
Bits 2:3 - Comparator 1 mode
Bits 4:6 - Comparator 1 inverting input selection
Bits 10:13 - Comparator 1 output selection
Bit 15 - Comparator 1 output polarity
Bits 16:17 - Comparator 1 hysteresis
Bits 18:20 - Comparator 1 blanking source
Bit 31 - Comparator 1 lock
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bit 15
Bit 14 - Port x configuration bit 14
Bit 13 - Port x configuration bit 13
Bit 12 - Port x configuration bit 12
Bit 11 - Port x configuration bit 11
Bit 10 - Port x configuration bit 10
Bit 9 - Port x configuration bit 9
Bit 8 - Port x configuration bit 8
Bit 7 - Port x configuration bit 7
Bit 6 - Port x configuration bit 6
Bit 5 - Port x configuration bit 5
Bit 4 - Port x configuration bit 4
Bit 3 - Port x configuration bit 3
Bit 2 - Port x configuration bit 2
Bit 1 - Port x configuration bit 1
Bit 0 - Port x configuration bit 0
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bit 15
Bit 14 - Port x configuration bit 14
Bit 13 - Port x configuration bit 13
Bit 12 - Port x configuration bit 12
Bit 11 - Port x configuration bit 11
Bit 10 - Port x configuration bit 10
Bit 9 - Port x configuration bit 9
Bit 8 - Port x configuration bit 8
Bit 7 - Port x configuration bit 7
Bit 6 - Port x configuration bit 6
Bit 5 - Port x configuration bit 5
Bit 4 - Port x configuration bit 4
Bit 3 - Port x configuration bit 3
Bit 2 - Port x configuration bit 2
Bit 1 - Port x configuration bit 1
Bit 0 - Port x configuration bit 0
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bits 28:31 - Charge transfer pulse high
Bits 24:27 - Charge transfer pulse low
Bits 17:23 - Spread spectrum deviation
Bit 16 - Spread spectrum enable
Bit 15 - Spread spectrum prescaler
Bits 12:14 - pulse generator prescaler
Bits 5:7 - Max count value
Bit 3 - Synchronization pin polarity
Bit 1 - Start a new acquisition
Bit 0 - Touch sensing controller enable
Bit 1 - Max count error interrupt enable
Bit 0 - End of acquisition interrupt enable
Bit 1 - Max count error interrupt clear
Bit 0 - End of acquisition interrupt clear
Bit 1 - Max count error flag
Bit 0 - End of acquisition flag
Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
Bit 24 - G7_IO1 Schmitt trigger hysteresis mode
Bit 25 - G7_IO2 Schmitt trigger hysteresis mode
Bit 26 - G7_IO3 Schmitt trigger hysteresis mode
Bit 27 - G7_IO4 Schmitt trigger hysteresis mode
Bit 28 - G8_IO1 Schmitt trigger hysteresis mode
Bit 29 - G8_IO2 Schmitt trigger hysteresis mode
Bit 30 - G8_IO3 Schmitt trigger hysteresis mode
Bit 31 - G8_IO4 Schmitt trigger hysteresis mode
Bit 0 - G1_IO1 analog switch enable
Bit 1 - G1_IO2 analog switch enable
Bit 2 - G1_IO3 analog switch enable
Bit 3 - G1_IO4 analog switch enable
Bit 4 - G2_IO1 analog switch enable
Bit 5 - G2_IO2 analog switch enable
Bit 6 - G2_IO3 analog switch enable
Bit 7 - G2_IO4 analog switch enable
Bit 8 - G3_IO1 analog switch enable
Bit 9 - G3_IO2 analog switch enable
Bit 10 - G3_IO3 analog switch enable
Bit 11 - G3_IO4 analog switch enable
Bit 12 - G4_IO1 analog switch enable
Bit 13 - G4_IO2 analog switch enable
Bit 14 - G4_IO3 analog switch enable
Bit 15 - G4_IO4 analog switch enable
Bit 16 - G5_IO1 analog switch enable
Bit 17 - G5_IO2 analog switch enable
Bit 18 - G5_IO3 analog switch enable
Bit 19 - G5_IO4 analog switch enable
Bit 20 - G6_IO1 analog switch enable
Bit 21 - G6_IO2 analog switch enable
Bit 22 - G6_IO3 analog switch enable
Bit 23 - G6_IO4 analog switch enable
Bit 24 - G7_IO1 analog switch enable
Bit 25 - G7_IO2 analog switch enable
Bit 26 - G7_IO3 analog switch enable
Bit 27 - G7_IO4 analog switch enable
Bit 28 - G8_IO1 analog switch enable
Bit 29 - G8_IO2 analog switch enable
Bit 30 - G8_IO3 analog switch enable
Bit 31 - G8_IO4 analog switch enable
Bit 0 - G1_IO1 sampling mode
Bit 1 - G1_IO2 sampling mode
Bit 2 - G1_IO3 sampling mode
Bit 3 - G1_IO4 sampling mode
Bit 4 - G2_IO1 sampling mode
Bit 5 - G2_IO2 sampling mode
Bit 6 - G2_IO3 sampling mode
Bit 7 - G2_IO4 sampling mode
Bit 8 - G3_IO1 sampling mode
Bit 9 - G3_IO2 sampling mode
Bit 10 - G3_IO3 sampling mode
Bit 11 - G3_IO4 sampling mode
Bit 12 - G4_IO1 sampling mode
Bit 13 - G4_IO2 sampling mode
Bit 14 - G4_IO3 sampling mode
Bit 15 - G4_IO4 sampling mode
Bit 16 - G5_IO1 sampling mode
Bit 17 - G5_IO2 sampling mode
Bit 18 - G5_IO3 sampling mode
Bit 19 - G5_IO4 sampling mode
Bit 20 - G6_IO1 sampling mode
Bit 21 - G6_IO2 sampling mode
Bit 22 - G6_IO3 sampling mode
Bit 23 - G6_IO4 sampling mode
Bit 24 - G7_IO1 sampling mode
Bit 25 - G7_IO2 sampling mode
Bit 26 - G7_IO3 sampling mode
Bit 27 - G7_IO4 sampling mode
Bit 28 - G8_IO1 sampling mode
Bit 29 - G8_IO2 sampling mode
Bit 30 - G8_IO3 sampling mode
Bit 31 - G8_IO4 sampling mode
Bit 0 - G1_IO1 channel mode
Bit 1 - G1_IO2 channel mode
Bit 2 - G1_IO3 channel mode
Bit 3 - G1_IO4 channel mode
Bit 4 - G2_IO1 channel mode
Bit 5 - G2_IO2 channel mode
Bit 6 - G2_IO3 channel mode
Bit 7 - G2_IO4 channel mode
Bit 8 - G3_IO1 channel mode
Bit 9 - G3_IO2 channel mode
Bit 10 - G3_IO3 channel mode
Bit 11 - G3_IO4 channel mode
Bit 12 - G4_IO1 channel mode
Bit 13 - G4_IO2 channel mode
Bit 14 - G4_IO3 channel mode
Bit 15 - G4_IO4 channel mode
Bit 16 - G5_IO1 channel mode
Bit 17 - G5_IO2 channel mode
Bit 18 - G5_IO3 channel mode
Bit 19 - G5_IO4 channel mode
Bit 20 - G6_IO1 channel mode
Bit 21 - G6_IO2 channel mode
Bit 22 - G6_IO3 channel mode
Bit 23 - G6_IO4 channel mode
Bit 24 - G7_IO1 channel mode
Bit 25 - G7_IO2 channel mode
Bit 26 - G7_IO3 channel mode
Bit 27 - G7_IO4 channel mode
Bit 28 - G8_IO1 channel mode
Bit 29 - G8_IO2 channel mode
Bit 30 - G8_IO3 channel mode
Bit 31 - G8_IO4 channel mode
Bit 23 - Analog I/O group x status
Bit 22 - Analog I/O group x status
Bit 7 - Analog I/O group x enable
Bit 6 - Analog I/O group x enable
Bit 5 - Analog I/O group x enable
Bit 4 - Analog I/O group x enable
Bit 3 - Analog I/O group x enable
Bit 2 - Analog I/O group x enable
Bit 1 - Analog I/O group x enable
Bit 0 - Analog I/O group x enable
Bits 0:31 - Data register bits
Bits 0:7 - General-purpose 8-bit data register bits
Bits 5:6 - Reverse input data
Bit 7 - Reverse output data
Bits 3:4 - Polynomial size
Bits 0:31 - Programmable initial CRC value
Bits 0:31 - Programmable polynomial
Bits 0:7 - Data register bits
Bits 0:15 - Data register bits
Bits 0:31 - Option byte key
Bit 4 - Write protection error
Bit 2 - Programming error
Bit 13 - Force option byte loading
Bit 12 - End of operation interrupt enable
Bit 10 - Error interrupt enable
Bit 9 - Option bytes write enable
Bit 5 - Option byte erase
Bit 4 - Option byte programming
Bits 0:31 - Flash address
Bit 0 - Internal High Speed clock enable
Bits 3:7 - Internal High Speed clock trimming
Bit 16 - External High Speed clock enable
Bit 18 - External High Speed clock Bypass
Bit 19 - Clock Security System enable
Bits 0:1 - System clock Switch
Bits 8:10 - APB Low speed prescaler (APB1)
Bits 11:13 - APB high speed prescaler (APB2)
Bits 14:15 - ADC prescaler
Bit 16 - PLL entry clock source
Bit 17 - HSE divider for PLL entry
Bits 18:21 - PLL Multiplication Factor
Bits 24:26 - Microcontroller clock output
Bits 27:31 - SDADC prescaler
Bit 8 - LSI Ready Interrupt Enable
Bit 9 - LSE Ready Interrupt Enable
Bit 10 - HSI Ready Interrupt Enable
Bit 11 - HSE Ready Interrupt Enable
Bit 12 - PLL Ready Interrupt Enable
Bit 16 - LSI Ready Interrupt Clear
Bit 17 - LSE Ready Interrupt Clear
Bit 18 - HSI Ready Interrupt Clear
Bit 19 - HSE Ready Interrupt Clear
Bit 20 - PLL Ready Interrupt Clear
Bit 23 - Clock security system interrupt clear
Bit 0 - SYSCFG and COMP reset
Bit 9 - ADC interface reset
Bit 16 - TIM15 timer reset
Bit 17 - TIM16 timer reset
Bit 18 - TIM17 timer reset
Bit 19 - TIM19 timer reset
Bit 24 - SDADC1 (Sigma delta ADC 1) reset
Bit 25 - SDADC2 (Sigma delta ADC 2) reset
Bit 26 - SDADC3 (Sigma delta ADC 3) reset
Bit 11 - Window watchdog reset
Bit 28 - Power interface reset
Bit 29 - DAC interface reset
Bit 0 - DMA1 clock enable
Bit 1 - DMA2 clock enable
Bit 2 - SRAM interface clock enable
Bit 4 - FLITF clock enable
Bit 17 - I/O port A clock enable
Bit 18 - I/O port B clock enable
Bit 19 - I/O port C clock enable
Bit 20 - I/O port D clock enable
Bit 21 - I/O port E clock enable
Bit 22 - I/O port F clock enable
Bit 24 - Touch sensing controller clock enable
Bit 0 - SYSCFG clock enable
Bit 9 - ADC 1 interface clock enable
Bit 12 - SPI 1 clock enable
Bit 14 - USART1 clock enable
Bit 16 - TIM15 timer clock enable
Bit 17 - TIM16 timer clock enable
Bit 18 - TIM17 timer clock enable
Bit 19 - TIM19 timer clock enable
Bit 22 - MCU debug module clock enable
Bit 24 - SDADC1 (Sigma Delta ADC 1) clock enable
Bit 25 - SDADC2 (Sigma Delta ADC 2) clock enable
Bit 26 - SDADC3 (Sigma Delta ADC 3) clock enable
Bit 0 - Timer 2 clock enable
Bit 1 - Timer 3 clock enable
Bit 2 - Timer 4 clock enable
Bit 3 - Timer 5 clock enable
Bit 4 - Timer 6 clock enable
Bit 5 - Timer 7 clock enable
Bit 6 - Timer 12 clock enable
Bit 7 - Timer 13 clock enable
Bit 8 - Timer 14 clock enable
Bit 9 - Timer 18 clock enable
Bit 11 - Window watchdog clock enable
Bit 14 - SPI 2 clock enable
Bit 15 - SPI 3 clock enable
Bit 17 - USART 2 clock enable
Bit 18 - USART 3 clock enable
Bit 21 - I2C 1 clock enable
Bit 22 - I2C 2 clock enable
Bit 23 - USB clock enable
Bit 25 - CAN clock enable
Bit 26 - DAC3 interface clock enable
Bit 28 - Power interface clock enable
Bit 29 - DAC interface clock enable
Bit 30 - HDMI CEC interface clock enable
Bit 0 - External Low Speed oscillator enable
Bit 2 - External Low Speed oscillator bypass
Bits 3:4 - LSE oscillator drive capability
Bits 8:9 - RTC clock source selection
Bit 15 - RTC clock enable
Bit 16 - Backup domain software reset
Bit 0 - Internal low speed oscillator enable
Bit 24 - Remove reset flag
Bit 25 - Option byte loader reset flag
Bit 27 - POR/PDR reset flag
Bit 28 - Software reset flag
Bit 29 - Independent watchdog reset flag
Bit 30 - Window watchdog reset flag
Bit 31 - Low-power reset flag
Bit 23 - Reset flag of the 1.8 V domain
Bit 17 - I/O port A reset
Bit 18 - I/O port B reset
Bit 19 - I/O port C reset
Bit 20 - I/O port D reset
Bit 21 - I/O port E reset
Bit 22 - I/O port F reset
Bit 24 - Touch sensing controller reset
Bits 0:3 - PREDIV division factor
Bits 0:1 - USART1 clock source selection
Bit 4 - I2C1 clock source selection
Bit 5 - I2C2 clock source selection
Bit 6 - HDMI CEC clock source selection
Bits 16:17 - USART2 clock source selection
Bits 18:19 - USART3 clock source selection
Bit 1 - Transfer complete interrupt enable
Bit 2 - Half Transfer interrupt enable
Bit 3 - Transfer error interrupt enable
Bit 4 - Data transfer direction
Bit 6 - Peripheral increment mode
Bit 7 - Memory increment mode
Bits 8:9 - Peripheral size
Bits 12:13 - Channel Priority level
Bit 14 - Memory to memory mode
Bits 0:15 - Number of data to transfer
Bits 0:31 - Peripheral address
Bits 0:31 - Memory address
Bit 0 - Channel 1 Global interrupt clear
Bit 1 - Channel 1 Transfer Complete clear
Bit 2 - Channel 1 Half Transfer clear
Bit 3 - Channel 1 Transfer Error clear
Bit 4 - Channel 2 Global interrupt clear
Bit 5 - Channel 2 Transfer Complete clear
Bit 6 - Channel 2 Half Transfer clear
Bit 7 - Channel 2 Transfer Error clear
Bit 8 - Channel 3 Global interrupt clear
Bit 9 - Channel 3 Transfer Complete clear
Bit 10 - Channel 3 Half Transfer clear
Bit 11 - Channel 3 Transfer Error clear
Bit 12 - Channel 4 Global interrupt clear
Bit 13 - Channel 4 Transfer Complete clear
Bit 14 - Channel 4 Half Transfer clear
Bit 15 - Channel 4 Transfer Error clear
Bit 16 - Channel 5 Global interrupt clear
Bit 17 - Channel 5 Transfer Complete clear
Bit 18 - Channel 5 Half Transfer clear
Bit 19 - Channel 5 Transfer Error clear
Bit 20 - Channel 6 Global interrupt clear
Bit 21 - Channel 6 Transfer Complete clear
Bit 22 - Channel 6 Half Transfer clear
Bit 23 - Channel 6 Transfer Error clear
Bit 24 - Channel 7 Global interrupt clear
Bit 25 - Channel 7 Transfer Complete clear
Bit 26 - Channel 7 Half Transfer clear
Bit 27 - Channel 7 Transfer Error clear
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:31 - Low counter value
Bits 0:15 - Prescaler value
Bits 0:31 - Low Auto-reload value
Bits 0:31 - Low Capture/Compare 1 value
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bits 10:11 - Internal trigger 1 remap
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:31 - Low counter value
Bits 0:15 - Prescaler value
Bits 0:31 - Low Auto-reload value
Bits 0:31 - Low Capture/Compare 1 value
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bits 6:7 - Timer Input 4 remap
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
Bit 14 - Trigger DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
Bit 0 - Capture/Compare 1 output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 3 - Capture/Compare 1 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 7 - Capture/Compare 2 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 11 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 13 - Capture/Compare 3 output Polarity
Bit 15 - Capture/Compare 3 output Polarity
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:15 - Capture/Compare 1 value
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bit 2 - Update request source
Bit 10 - Output Idle state 2
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
Bit 7 - Master/Slave mode
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
Bit 14 - Trigger DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bits 0:15 - Capture/Compare 2 value
Bit 15 - Main output enable
Bit 14 - Automatic output enable
Bit 11 - Off-state selection for Run mode
Bit 10 - Off-state selection for Idle mode
Bits 8:9 - Lock configuration
Bits 0:7 - Dead-time generator setup
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bit 2 - Update request source
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
Bit 14 - Trigger DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:7 - Repetition counter value
Bits 0:15 - Capture/Compare 1 value
Bit 15 - Main output enable
Bit 14 - Automatic output enable
Bit 11 - Off-state selection for Run mode
Bit 10 - Off-state selection for Idle mode
Bits 8:9 - Lock configuration
Bits 0:7 - Dead-time generator setup
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
Bits 0:15 - DMA register for burst accesses
Bit 27 - End of Block interrupt enable
Bit 26 - Receiver timeout interrupt enable
Bits 21:25 - Driver Enable assertion time
Bits 16:20 - Driver Enable deassertion time
Bit 15 - Oversampling mode
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
Bit 3 - Transmitter enable
Bit 1 - USART enable in Stop mode
Bit 23 - Receiver timeout enable
Bits 21:22 - Auto baud rate mode
Bit 20 - Auto baud rate enable
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 8 - Last bit clock pulse
Bit 6 - LIN break detection interrupt enable
Bit 5 - LIN break detection length
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bits 17:19 - Smartcard auto-retry count
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 11 - One sample bit method enable
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 5 - Smartcard mode enable
Bit 4 - Smartcard NACK enable
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
Bits 0:15 - mantissa of USARTDIV
Bits 8:15 - Guard time value
Bits 0:7 - Prescaler value
Bits 24:31 - Block Length
Bits 0:23 - Receiver timeout value
Bit 4 - Transmit data flush request
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
Bit 0 - Auto baud rate request
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 12 - End of timeout clear flag
Bit 11 - Receiver timeout clear flag
Bit 8 - LIN break detection clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
Bits 0:8 - Transmit data value
Bit 15 - Bidirectional data mode enable
Bit 14 - Output enable in bidirectional mode
Bit 13 - Hardware CRC calculation enable
Bit 12 - CRC transfer next
Bit 9 - Software slave management
Bit 8 - Internal slave select
Bits 3:5 - Baud rate control
Bit 0 - Rx buffer DMA enable
Bit 1 - Tx buffer DMA enable
Bit 3 - NSS pulse management
Bit 5 - Error interrupt enable
Bit 6 - RX buffer not empty interrupt enable
Bit 7 - Tx buffer empty interrupt enable
Bit 12 - FIFO reception threshold
Bit 13 - Last DMA transfer for reception
Bit 14 - Last DMA transfer for transmission
Bits 0:15 - Data register
Bits 0:15 - CRC polynomial register
Bit 11 - I2S mode selection
Bits 8:9 - I2S configuration mode
Bit 7 - PCM frame synchronization
Bits 4:5 - I2S standard selection
Bit 3 - Steady state clock polarity
Bits 1:2 - Data length to be transferred
Bit 0 - Channel length (number of bits per audio channel)
Bit 9 - Master clock output enable
Bit 8 - Odd factor for the prescaler
Bits 0:7 - I2S Linear prescaler
Bit 4 - Regular channel start flag
Bit 3 - Injected channel start flag
Bit 2 - Injected channel end of conversion
Bit 1 - Regular channel end of conversion
Bit 0 - Analog watchdog flag
Bit 23 - Analog watchdog enable on regular channels
Bit 22 - Analog watchdog enable on injected channels
Bits 13:15 - Discontinuous mode channel count
Bit 12 - Discontinuous mode on injected channels
Bit 11 - Discontinuous mode on regular channels
Bit 10 - Automatic injected group conversion
Bit 9 - Enable the watchdog on a single channel in scan mode
Bit 7 - Interrupt enable for injected channels
Bit 6 - Analog watchdog interrupt enable
Bit 5 - Interrupt enable for EOC
Bits 0:4 - Analog watchdog channel select bits
Bit 23 - Temperature sensor and VREFINT enable
Bit 22 - Start conversion of regular channels
Bit 21 - Start conversion of injected channels
Bit 20 - External trigger conversion mode for regular channels
Bits 17:19 - External event select for regular group
Bit 15 - External trigger conversion mode for injected channels
Bits 12:14 - External event select for injected group
Bit 8 - Direct memory access mode
Bit 3 - Reset calibration
Bit 1 - Continuous conversion
Bit 0 - A/D converter ON / OFF
Bits 0:2 - Channel 10 sampling time selection
Bits 3:5 - Channel 11 sampling time selection
Bits 6:8 - Channel 12 sampling time selection
Bits 9:11 - Channel 13 sampling time selection
Bits 12:14 - Channel 14 sampling time selection
Bits 15:17 - Channel 15 sampling time selection
Bits 18:20 - Channel 16 sampling time selection
Bits 21:23 - Channel 17 sampling time selection
Bits 0:2 - Channel 0 sampling time selection
Bits 3:5 - Channel 1 sampling time selection
Bits 6:8 - Channel 2 sampling time selection
Bits 9:11 - Channel 3 sampling time selection
Bits 12:14 - Channel 4 sampling time selection
Bits 15:17 - Channel 5 sampling time selection
Bits 18:20 - Channel 6 sampling time selection
Bits 21:23 - Channel 7 sampling time selection
Bits 24:26 - Channel 8 sampling time selection
Bits 27:29 - Channel 9 sampling time selection
Bits 0:11 - Data offset for injected channel x
Bits 0:11 - Analog watchdog higher threshold
Bits 0:11 - Analog watchdog lower threshold
Bits 20:23 - Regular channel sequence length
Bits 15:19 - 16th conversion in regular sequence
Bits 10:14 - 15th conversion in regular sequence
Bits 5:9 - 14th conversion in regular sequence
Bits 0:4 - 13th conversion in regular sequence
Bits 25:29 - 12th conversion in regular sequence
Bits 20:24 - 11th conversion in regular sequence
Bits 15:19 - 10th conversion in regular sequence
Bits 10:14 - 9th conversion in regular sequence
Bits 5:9 - 8th conversion in regular sequence
Bits 0:4 - 7th conversion in regular sequence
Bits 25:29 - 6th conversion in regular sequence
Bits 20:24 - 5th conversion in regular sequence
Bits 15:19 - 4th conversion in regular sequence
Bits 10:14 - 3rd conversion in regular sequence
Bits 5:9 - 2nd conversion in regular sequence
Bits 0:4 - 1st conversion in regular sequence
Bits 20:21 - Injected sequence length
Bits 15:19 - 4th conversion in injected sequence
Bits 10:14 - 3rd conversion in injected sequence
Bits 5:9 - 2nd conversion in injected sequence
Bits 0:4 - 1st conversion in injected sequence
Bit 0 - Interrupt Mask on line 0
Bit 1 - Interrupt Mask on line 1
Bit 2 - Interrupt Mask on line 2
Bit 3 - Interrupt Mask on line 3
Bit 4 - Interrupt Mask on line 4
Bit 5 - Interrupt Mask on line 5
Bit 6 - Interrupt Mask on line 6
Bit 7 - Interrupt Mask on line 7
Bit 8 - Interrupt Mask on line 8
Bit 9 - Interrupt Mask on line 9
Bit 10 - Interrupt Mask on line 10
Bit 11 - Interrupt Mask on line 11
Bit 12 - Interrupt Mask on line 12
Bit 13 - Interrupt Mask on line 13
Bit 14 - Interrupt Mask on line 14
Bit 15 - Interrupt Mask on line 15
Bit 16 - Interrupt Mask on line 16
Bit 17 - Interrupt Mask on line 17
Bit 18 - Interrupt Mask on line 18
Bit 19 - Interrupt Mask on line 19
Bit 20 - Interrupt Mask on line 20
Bit 21 - Interrupt Mask on line 21
Bit 22 - Interrupt Mask on line 22
Bit 23 - Interrupt Mask on line 23
Bit 24 - Interrupt Mask on line 24
Bit 25 - Interrupt Mask on line 25
Bit 26 - Interrupt Mask on line 26
Bit 27 - Interrupt Mask on line 27
Bit 28 - Interrupt Mask on line 28
Bit 0 - Event Mask on line 0
Bit 1 - Event Mask on line 1
Bit 2 - Event Mask on line 2
Bit 3 - Event Mask on line 3
Bit 4 - Event Mask on line 4
Bit 5 - Event Mask on line 5
Bit 6 - Event Mask on line 6
Bit 7 - Event Mask on line 7
Bit 8 - Event Mask on line 8
Bit 9 - Event Mask on line 9
Bit 10 - Event Mask on line 10
Bit 11 - Event Mask on line 11
Bit 12 - Event Mask on line 12
Bit 13 - Event Mask on line 13
Bit 14 - Event Mask on line 14
Bit 15 - Event Mask on line 15
Bit 16 - Event Mask on line 16
Bit 17 - Event Mask on line 17
Bit 18 - Event Mask on line 18
Bit 19 - Event Mask on line 19
Bit 20 - Event Mask on line 20
Bit 21 - Event Mask on line 21
Bit 22 - Event Mask on line 22
Bit 23 - Event Mask on line 23
Bit 24 - Event Mask on line 24
Bit 25 - Event Mask on line 25
Bit 26 - Event Mask on line 26
Bit 27 - Event Mask on line 27
Bit 28 - Event Mask on line 28
Bit 0 - Rising trigger event configuration of line 0
Bit 1 - Rising trigger event configuration of line 1
Bit 2 - Rising trigger event configuration of line 2
Bit 3 - Rising trigger event configuration of line 3
Bit 4 - Rising trigger event configuration of line 4
Bit 5 - Rising trigger event configuration of line 5
Bit 6 - Rising trigger event configuration of line 6
Bit 7 - Rising trigger event configuration of line 7
Bit 8 - Rising trigger event configuration of line 8
Bit 9 - Rising trigger event configuration of line 9
Bit 10 - Rising trigger event configuration of line 10
Bit 11 - Rising trigger event configuration of line 11
Bit 12 - Rising trigger event configuration of line 12
Bit 13 - Rising trigger event configuration of line 13
Bit 14 - Rising trigger event configuration of line 14
Bit 15 - Rising trigger event configuration of line 15
Bit 16 - Rising trigger event configuration of line 16
Bit 17 - Rising trigger event configuration of line 17
Bit 18 - Rising trigger event configuration of line 18
Bit 19 - Rising trigger event configuration of line 19
Bit 20 - Rising trigger event configuration of line 20
Bit 21 - Rising trigger event configuration of line 21
Bit 22 - Rising trigger event configuration of line 22
Bit 0 - Falling trigger event configuration of line 0
Bit 1 - Falling trigger event configuration of line 1
Bit 2 - Falling trigger event configuration of line 2
Bit 3 - Falling trigger event configuration of line 3
Bit 4 - Falling trigger event configuration of line 4
Bit 5 - Falling trigger event configuration of line 5
Bit 6 - Falling trigger event configuration of line 6
Bit 7 - Falling trigger event configuration of line 7
Bit 8 - Falling trigger event configuration of line 8
Bit 9 - Falling trigger event configuration of line 9
Bit 10 - Falling trigger event configuration of line 10
Bit 11 - Falling trigger event configuration of line 11
Bit 12 - Falling trigger event configuration of line 12
Bit 13 - Falling trigger event configuration of line 13
Bit 14 - Falling trigger event configuration of line 14
Bit 15 - Falling trigger event configuration of line 15
Bit 16 - Falling trigger event configuration of line 16
Bit 17 - Falling trigger event configuration of line 17
Bit 18 - Rising trigger event configuration of line 18
Bit 19 - Rising trigger event configuration of line 19
Bit 20 - Rising trigger event configuration of line 20
Bit 21 - Rising trigger event configuration of line 21
Bit 22 - Rising trigger event configuration of line 22
Bit 0 - Software Interrupt on line 0
Bit 1 - Software Interrupt on line 1
Bit 2 - Software Interrupt on line 2
Bit 3 - Software Interrupt on line 3
Bit 4 - Software Interrupt on line 4
Bit 5 - Software Interrupt on line 5
Bit 6 - Software Interrupt on line 6
Bit 7 - Software Interrupt on line 7
Bit 8 - Software Interrupt on line 8
Bit 9 - Software Interrupt on line 9
Bit 10 - Software Interrupt on line 10
Bit 11 - Software Interrupt on line 11
Bit 12 - Software Interrupt on line 12
Bit 13 - Software Interrupt on line 13
Bit 14 - Software Interrupt on line 14
Bit 15 - Software Interrupt on line 15
Bit 16 - Software Interrupt on line 16
Bit 17 - Software Interrupt on line 17
Bit 18 - Software Interrupt on line 18
Bit 19 - Software Interrupt on line 19
Bit 20 - Software Interrupt on line 20
Bit 21 - Software Interrupt on line 21
Bit 22 - Software Interrupt on line 22
Bit 2 - Tx End Of Message
Bit 1 - Tx start of message
Bit 11 - Generate Error-Bit on Long Bit Period Error
Bit 10 - Generate error-bit on bit rising error
Bit 9 - Rx-stop on bit rising error
Bits 5:7 - Signal Free Time
Bits 0:7 - Tx Data register
Bit 12 - Tx-Missing acknowledge error
Bit 10 - Tx-Buffer Underrun
Bit 9 - End of Transmission
Bit 6 - Rx-Missing Acknowledge
Bit 5 - Rx-Long Bit Period Error
Bit 4 - Rx-Short Bit period error
Bit 3 - Rx-Bit rising error
Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable
Bit 11 - Tx-Error Interrupt Enable
Bit 10 - Tx-Underrun interrupt enable
Bit 9 - Tx-End of message interrupt enable
Bit 8 - Tx-Byte Request Interrupt Enable
Bit 7 - Arbitration Lost Interrupt Enable
Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable
Bit 5 - Long Bit Period Error Interrupt Enable
Bit 4 - Short Bit Period Error Interrupt Enable
Bit 3 - Bit Rising Error Interrupt Enable
Bit 2 - Rx-Buffer Overrun Interrupt Enable
Bit 1 - End Of Reception Interrupt Enable
Bit 0 - Rx-Byte Received Interrupt Enable
Bit 0 - Low-power deep sleep
Bit 1 - Power down deepsleep
Bit 2 - Clear wakeup flag
Bit 3 - Clear standby flag
Bit 4 - Power voltage detector enable
Bits 5:7 - PVD level selection
Bit 8 - Disable backup domain write protection
Bit 10 - Enable WKUP3 pin
Bit 0 - Filter scale configuration
Bit 1 - Filter scale configuration
Bit 2 - Filter scale configuration
Bit 3 - Filter scale configuration
Bit 4 - Filter scale configuration
Bit 5 - Filter scale configuration
Bit 6 - Filter scale configuration
Bit 7 - Filter scale configuration
Bit 8 - Filter scale configuration
Bit 9 - Filter scale configuration
Bit 10 - Filter scale configuration
Bit 11 - Filter scale configuration
Bit 12 - Filter scale configuration
Bit 13 - Filter scale configuration
Bit 14 - Filter scale configuration
Bit 15 - Filter scale configuration
Bit 16 - Filter scale configuration
Bit 17 - Filter scale configuration
Bit 18 - Filter scale configuration
Bit 19 - Filter scale configuration
Bit 20 - Filter scale configuration
Bit 21 - Filter scale configuration
Bit 22 - Filter scale configuration
Bit 23 - Filter scale configuration
Bit 24 - Filter scale configuration
Bit 25 - Filter scale configuration
Bit 26 - Filter scale configuration
Bit 27 - Filter scale configuration
Bit 0 - Filter FIFO assignment for filter 0
Bit 1 - Filter FIFO assignment for filter 1
Bit 2 - Filter FIFO assignment for filter 2
Bit 3 - Filter FIFO assignment for filter 3
Bit 4 - Filter FIFO assignment for filter 4
Bit 5 - Filter FIFO assignment for filter 5
Bit 6 - Filter FIFO assignment for filter 6
Bit 7 - Filter FIFO assignment for filter 7
Bit 8 - Filter FIFO assignment for filter 8
Bit 9 - Filter FIFO assignment for filter 9
Bit 10 - Filter FIFO assignment for filter 10
Bit 11 - Filter FIFO assignment for filter 11
Bit 12 - Filter FIFO assignment for filter 12
Bit 13 - Filter FIFO assignment for filter 13
Bit 14 - Filter FIFO assignment for filter 14
Bit 15 - Filter FIFO assignment for filter 15
Bit 16 - Filter FIFO assignment for filter 16
Bit 17 - Filter FIFO assignment for filter 17
Bit 18 - Filter FIFO assignment for filter 18
Bit 19 - Filter FIFO assignment for filter 19
Bit 20 - Filter FIFO assignment for filter 20
Bit 21 - Filter FIFO assignment for filter 21
Bit 22 - Filter FIFO assignment for filter 22
Bit 23 - Filter FIFO assignment for filter 23
Bit 24 - Filter FIFO assignment for filter 24
Bit 25 - Filter FIFO assignment for filter 25
Bit 26 - Filter FIFO assignment for filter 26
Bit 27 - Filter FIFO assignment for filter 27
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
Bit 8 - Expected start of frame interrupt mask
Bit 9 - Start of frame interrupt mask
Bit 10 - USB reset interrupt mask
Bit 11 - Suspend mode interrupt mask
Bit 12 - Wakeup interrupt mask
Bit 13 - Error interrupt mask
Bit 14 - Packet memory area over / underrun interrupt mask
Bit 15 - Correct transfer interrupt mask
Bit 8 - Expected start frame
Bit 11 - Suspend mode request
Bit 14 - Packet memory area over / underrun
Bit 0 - Peripheral enable
Bit 1 - TX Interrupt enable
Bit 2 - RX Interrupt enable
Bit 3 - Address match interrupt enable (slave only)
Bit 4 - Not acknowledge received interrupt enable
Bit 5 - STOP detection Interrupt enable
Bit 6 - Transfer Complete interrupt enable
Bit 7 - Error interrupts enable
Bits 8:11 - Digital noise filter
Bit 12 - Analog noise filter OFF
Bit 14 - DMA transmission requests enable
Bit 15 - DMA reception requests enable
Bit 16 - Slave byte control
Bit 17 - Clock stretching disable
Bit 18 - Wakeup from STOP enable
Bit 19 - General call enable
Bit 20 - SMBus Host address enable
Bit 21 - SMBus Device Default address enable
Bit 22 - SMBUS alert enable
Bit 26 - Packet error checking byte
Bit 25 - Automatic end mode (master mode)
Bit 24 - NBYTES reload mode
Bits 16:23 - Number of bytes
Bit 15 - NACK generation (slave mode)
Bit 14 - Stop generation (master mode)
Bit 13 - Start generation
Bit 12 - 10-bit address header only read direction (master receiver mode)
Bit 11 - 10-bit addressing mode (master mode)
Bit 10 - Transfer direction (master mode)
Bits 0:9 - Slave address bit 9:8 (master mode)
Bit 10 - Own Address 1 10-bit mode
Bit 15 - Own Address 1 enable
Bits 0:9 - Interface address
Bits 1:7 - Interface address
Bits 8:10 - Own Address 2 masks
Bit 15 - Own Address 2 enable
Bits 0:7 - SCL low period (master mode)
Bits 8:15 - SCL high period (master mode)
Bits 16:19 - Data hold time
Bits 20:23 - Data setup time
Bits 28:31 - Timing prescaler
Bits 0:11 - Bus timeout A
Bit 12 - Idle clock timeout detection
Bit 15 - Clock timeout enable
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
[src]
Bit 31 - Extended clock timeout enable
Bit 1 - Transmit interrupt status (transmitters)
Bit 0 - Transmit data register empty (transmitters)
Bit 13 - Alert flag clear
Bit 12 - Timeout detection flag clear
Bit 11 - PEC Error flag clear
Bit 10 - Overrun/Underrun flag clear
Bit 9 - Arbitration lost flag clear
Bit 8 - Bus error flag clear
Bit 5 - Stop detection flag clear
Bit 4 - Not Acknowledge flag clear
Bit 3 - Address Matched flag clear
Bits 0:7 - 8-bit transmit data
Bits 0:2 - Prescaler divider
Bits 0:11 - Watchdog counter reload value
Bits 0:11 - Watchdog counter window value
Bit 9 - Early wakeup interrupt
Bits 0:6 - 7-bit window value
Bit 0 - Early wakeup interrupt flag
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bits 20:23 - Year tens in BCD format
Bits 16:19 - Year units in BCD format
Bits 13:15 - Week day units
Bit 12 - Month tens in BCD format
Bits 8:11 - Month units in BCD format
Bits 4:5 - Date tens in BCD format
Bits 0:3 - Date units in BCD format
Bits 0:2 - Wakeup clock selection
Bit 3 - Time-stamp event active edge
Bit 4 - Reference clock detection enable (50 or 60 Hz)
Bit 5 - Bypass the shadow registers
Bit 10 - Wakeup timer enable
Bit 11 - Time stamp enable
Bit 12 - Alarm A interrupt enable
Bit 13 - Alarm B interrupt enable
Bit 14 - Wakeup timer interrupt enable
Bit 15 - Time-stamp interrupt enable
Bit 16 - Add 1 hour (summer time change)
Bit 17 - Subtract 1 hour (winter time change)
Bit 19 - Calibration output selection
Bits 21:22 - Output selection
Bit 23 - Calibration output enable
Bit 13 - Tamper detection flag
Bit 12 - Time-stamp overflow flag
Bit 10 - Wakeup timer flag
Bit 7 - Initialization mode
Bit 5 - Registers synchronization flag
Bit 3 - Shift operation pending
Bit 14 - RTC_TAMP2 detection flag
Bit 15 - RTC_TAMP3 detection flag
Bits 16:22 - Asynchronous prescaler factor
Bits 0:14 - Synchronous prescaler factor
Bits 0:15 - Wakeup auto-reload value bits
Bit 31 - Alarm A date mask
Bit 30 - Week day selection
Bits 28:29 - Date tens in BCD format
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm A hours mask
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm A minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm A seconds mask
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bit 31 - Alarm B date mask
Bit 30 - Week day selection
Bits 28:29 - Date tens in BCD format
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm B hours mask
Bits 20:21 - Hour tens in BCD format
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm B minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm B seconds mask
Bits 4:6 - Second tens in BCD format
Bits 0:3 - Second units in BCD format
Bits 0:7 - Write protection key
Bits 0:14 - Subtract a fraction of a second
Bit 15 - Increase frequency of RTC by 488.5 ppm
Bit 14 - Use an 8-second calibration cycle period
Bit 13 - Use a 16-second calibration cycle period
Bits 0:8 - Calibration minus
Bit 0 - Tamper 1 detection enable
Bit 1 - Active level for tamper 1
Bit 2 - Tamper interrupt enable
Bit 3 - Tamper 2 detection enable
Bit 4 - Active level for tamper 2
Bit 7 - Activate timestamp on tamper detection event
Bits 8:10 - Tamper sampling frequency
Bits 11:12 - Tamper filter count
Bits 13:14 - Tamper precharge duration
Bit 15 - TAMPER pull-up disable
Bits 24:27 - Mask the most-significant bits starting at this bit
Bits 0:14 - Sub seconds value
Bits 24:27 - Mask the most-significant bits starting at this bit
Bits 0:14 - Sub seconds value
Bit 0 - End of calibration interrupt enable
Bit 1 - Injected end of conversion interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 3 - Regular end of conversion interrupt enable
Bit 4 - Regular data overrun interrupt enable
Bits 8:9 - Reference voltage selection
Bit 10 - Slow clock mode enable
Bit 11 - Enter Standby mode when idle
Bit 12 - Enter power down mode when idle
Bit 14 - Launch a injected conversion synchronously with SDADC1
Bit 15 - Launch regular conversion synchronously with SDADC1
Bit 16 - DMA channel enabled to read data for the injected channel group
Bit 17 - DMA channel enabled to read data for the regular channel
Bit 31 - Initialization mode request
Bit 24 - Fast conversion mode selection
Bit 23 - Software start of a conversion on the regular channel
Bit 22 - Continuous mode selection for regular conversions
Bits 16:19 - Regular channel selection
Bit 15 - Start a conversion of the injected group of channels
Bits 13:14 - Trigger enable and trigger edge selection for injected conversions
Bits 8:11 - Trigger signal selection for launching injected conversions
Bit 6 - Delay start of injected conversions.
Bit 5 - Continuous mode selection for injected conversions
Bit 4 - Start calibration
Bits 1:2 - Number of calibration sequences to be performed (number of valid configurations)
Bit 4 - Clear the regular conversion overrun flag
Bit 2 - Clear the injected conversion overrun flag
Bit 0 - Clear the end of calibration flag
Bits 0:8 - Injected channel group selection
Bits 30:31 - Common mode for configuration 0
Bits 26:27 - Single-ended mode for configuration 0
Bits 20:22 - Gain setting for configuration 0
Bits 0:11 - Twelve-bit calibration offset for configuration 0
Bits 30:31 - Common mode for configuration 1
Bits 26:27 - Single-ended mode for configuration 1
Bits 20:22 - Gain setting for configuration 1
Bits 0:11 - Twelve-bit calibration offset for configuration 1
Bits 30:31 - Common mode for configuration 2
Bits 26:27 - Single-ended mode for configuration 2
Bits 20:22 - Gain setting for configuration 2
Bits 0:11 - Twelve-bit calibration offset for configuration 2
Bits 0:1 - Channel 8 configuration
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
Bit 12 - DAC channel1 DMA enable
Bit 11 - DAC channel1 mask/amplitude selector
Bit 7 - DAC channel1 noise/triangle wave generation enable
Bits 3:5 - DAC channel1 trigger selection
Bit 2 - DAC channel1 trigger enable
Bit 1 - DAC channel1 output buffer disable
Bit 0 - DAC channel1 enable
Bit 0 - DAC channel1 software trigger
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bit 13 - DAC channel1 DMA underrun flag
Bit 7 - Auto-reload preload enable
Bit 2 - Update request source
Bits 4:6 - Master mode selection
Bit 8 - Update DMA request enable
Bit 0 - Update interrupt enable
Bit 0 - Update interrupt flag
Bit 0 - Update generation
Bits 0:15 - Low counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Low Auto-reload value
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bit 2 - Update request source
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 9 - Capture/Compare 1 overcapture flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 0:1 - Capture/Compare 1 selection
Bit 2 - Output compare 1 fast enable
Bit 3 - Output Compare 1 preload enable
Bits 4:6 - Output Compare 1 mode
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:15 - Capture/Compare 1 value
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bit 2 - Update request source
Bit 7 - Master/Slave mode
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
Bit 6 - Trigger interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
Bit 6 - Trigger generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
Bit 0 - Update generation
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:6 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
Bits 0:15 - counter value
Bits 0:15 - Prescaler value
Bits 0:15 - Auto-reload value
Bits 0:15 - Capture/Compare 1 value
Bit 29 - DAC channel2 DMA underrun interrupt enable
Bit 28 - DAC channel2 DMA enable
Bits 24:27 - DAC channel2 mask/amplitude selector
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
Bits 19:21 - DAC channel2 trigger selection
Bit 18 - DAC channel2 trigger enable
Bit 17 - DAC channel2 output buffer disable
Bit 16 - DAC channel2 enable
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
Bit 12 - DAC channel1 DMA enable
Bits 8:11 - DAC channel1 mask/amplitude selector
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
Bits 3:5 - DAC channel1 trigger selection
Bit 2 - DAC channel1 trigger enable
Bit 1 - DAC channel1 output buffer disable
Bit 0 - DAC channel1 enable
Bit 1 - DAC channel2 software trigger
Bit 0 - DAC channel1 software trigger
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bits 0:11 - DAC channel2 12-bit right-aligned data
Bits 4:15 - DAC channel2 12-bit left-aligned data
Bits 0:7 - DAC channel2 8-bit right-aligned data
Bits 16:27 - DAC channel2 12-bit right-aligned data
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 20:31 - DAC channel2 12-bit left-aligned data
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 8:15 - DAC channel2 8-bit right-aligned data
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bit 29 - DAC channel2 DMA underrun flag
Bit 13 - DAC channel1 DMA underrun flag
Bits 3:31 - Location of unpopulated floating-point
Bit 0 - Invalid operation cumulative exception bit
Bit 1 - Division by zero cumulative exception bit.
Bit 2 - Overflow cumulative exception bit
Bit 3 - Underflow cumulative exception bit
Bit 4 - Inexact cumulative exception bit
Bit 7 - Input denormal cumulative exception bit.
Bits 22:23 - Rounding Mode control field
Bit 24 - Flush-to-zero mode control bit:
Bit 25 - Default NaN mode control bit
Bit 26 - Alternative half-precision control bit
Bit 28 - Overflow condition code flag
Bit 29 - Carry condition code flag
Bit 30 - Zero condition code flag
Bit 31 - Negative condition code flag
Bit 2 - Debug Standby Mode
Bit 5 - Trace pin assignment control
Bits 6:7 - Trace pin assignment control
Bit 0 - Debug Timer 2 stopped when Core is halted
Bit 1 - Debug Timer 3 stopped when Core is halted
Bit 2 - Debug Timer 4 stopped when Core is halted
Bit 3 - Debug Timer 5 stopped when Core is halted
Bit 4 - Debug Timer 6 stopped when Core is halted
Bit 5 - Debug Timer 7 stopped when Core is halted
Bit 6 - Debug Timer 12 stopped when Core is halted
Bit 7 - Debug Timer 13 stopped when Core is halted
Bit 8 - Debug Timer 14 stopped when Core is halted
Bit 9 - Debug Timer 18 stopped when Core is halted
Bit 10 - Debug RTC stopped when Core is halted
Bit 11 - Debug Window Wachdog stopped when Core is halted
Bit 12 - Debug Independent Wachdog stopped when Core is halted
Bit 21 - SMBUS timeout mode stopped when Core is halted
Bit 22 - SMBUS timeout mode stopped when Core is halted
Bit 25 - Debug CAN stopped when core is halted
Bit 2 - Debug Timer 15 stopped when Core is halted
Bit 3 - Debug Timer 16 stopped when Core is halted
Bit 4 - Debug Timer 17 stopped when Core is halted
Bit 5 - Debug Timer 19 stopped when Core is halted
Bits 0:1 - Memory mapping selection bits
Bit 11 - TIM16 DMA request remapping bit
Bit 12 - TIM17 DMA request remapping bit
Bit 13 - TIM6 and DAC1 DMA request remapping bit
Bit 14 - TIM7 and DAC2 DMA request remapping bit
Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
Bit 20 - I2C1 Fast Mode Plus
Bit 21 - I2C2 Fast Mode Plus
Bit 24 - VBAT monitoring enable
Bit 15 - TIM18 and DAC2_OUT1 DMA request remapping bit
Bit 31 - Inexact interrupt enable
Bit 30 - Input denormal interrupt enable
Bit 29 - Overflow interrupt enable
Bit 28 - Underflow interrupt enable
Bit 27 - Devide-by-zero interrupt enable
Bit 26 - Invalid operation interrupt enable
Bits 12:15 - EXTI 3 configuration bits
Bits 8:11 - EXTI 2 configuration bits
Bits 4:7 - EXTI 1 configuration bits
Bits 0:3 - EXTI 0 configuration bits
Bits 12:15 - EXTI 7 configuration bits
Bits 8:11 - EXTI 6 configuration bits
Bits 4:7 - EXTI 5 configuration bits
Bits 0:3 - EXTI 4 configuration bits
Bits 12:15 - EXTI 11 configuration bits
Bits 8:11 - EXTI 10 configuration bits
Bits 4:7 - EXTI 9 configuration bits
Bits 0:3 - EXTI 8 configuration bits
Bits 12:15 - EXTI 15 configuration bits
Bits 8:11 - EXTI 14 configuration bits
Bits 4:7 - EXTI 13 configuration bits
Bits 0:3 - EXTI 12 configuration bits
Bit 0 - Cortex-M0 LOCKUP bit enable bit
Bit 1 - SRAM parity lock bit
Bit 2 - PVD lock enable bit
Bit 1 - SysTick exception request enable
Bit 2 - Clock source selection
Bits 0:23 - Current counter value
Bits 0:23 - Calibration value
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
Bit 31 - NOREF flag. Reads as zero
Bits 0:8 - Software generated interrupt ID
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port x configuration bit 15
Bit 14 - Port x configuration bit 14
Bit 13 - Port x configuration bit 13
Bit 12 - Port x configuration bit 12
Bit 11 - Port x configuration bit 11
Bit 10 - Port x configuration bit 10
Bit 9 - Port x configuration bit 9
Bit 8 - Port x configuration bit 8
Bit 7 - Port x configuration bit 7
Bit 6 - Port x configuration bit 6
Bit 5 - Port x configuration bit 5
Bit 4 - Port x configuration bit 4
Bit 3 - Port x configuration bit 3
Bit 2 - Port x configuration bit 2
Bit 1 - Port x configuration bit 1
Bit 0 - Port x configuration bit 0
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
Bit 0 - Port x Reset bit y
Bit 1 - Port x Reset bit y
Bit 2 - Port x Reset bit y
Bit 3 - Port x Reset bit y
Bit 4 - Port x Reset bit y
Bit 5 - Port x Reset bit y
Bit 6 - Port x Reset bit y
Bit 7 - Port x Reset bit y
Bit 8 - Port x Reset bit y
Bit 9 - Port x Reset bit y
Bit 10 - Port x Reset bit y
Bit 11 - Port x Reset bit y
Bit 12 - Port x Reset bit y
Bit 13 - Port x Reset bit y
Bit 14 - Port x Reset bit y
Bit 15 - Port x Reset bit y
Bit 0 - Comparator 1 enable
Bits 2:3 - Comparator 1 mode
Bits 4:6 - Comparator 1 inverting input selection
Bits 8:10 - Comparator 1 output selection
Bit 11 - Comparator 1 output polarity
Bits 12:13 - Comparator 1 hysteresis
Bit 15 - Comparator 1 lock
Bit 16 - Comparator 2 enable
Bits 18:19 - Comparator 2 mode
Bits 20:22 - Comparator 2 inverting input selection
Bit 23 - Window mode enable
Bits 24:26 - Comparator 2 output selection
Bit 27 - Comparator 2 output polarity
Bits 28:29 - Comparator 2 hysteresis
Bit 31 - Comparator 2 lock
Bit 1 - Comparator 1 non inverting input connection to DAC output
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more
The type returned in the event of a conversion error.
The type returned in the event of a conversion error.