Struct W

pub struct W<U, REG> { /* private fields */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bit 15

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bit 14

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bit 13

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bit 12

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bit 11

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bit 10

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bit 9

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bit 8

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bit 7

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bit 6

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bit 5

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bit 4

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bit 3

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bit 2

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bit 1

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bit 0

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _CR>>

pub fn ctph(&mut self) -> CTPH_W<'_>

Bits 28:31 - Charge transfer pulse high

pub fn ctpl(&mut self) -> CTPL_W<'_>

Bits 24:27 - Charge transfer pulse low

pub fn ssd(&mut self) -> SSD_W<'_>

Bits 17:23 - Spread spectrum deviation

pub fn sse(&mut self) -> SSE_W<'_>

Bit 16 - Spread spectrum enable

pub fn sspsc(&mut self) -> SSPSC_W<'_>

Bit 15 - Spread spectrum prescaler

pub fn pgpsc(&mut self) -> PGPSC_W<'_>

Bits 12:14 - pulse generator prescaler

pub fn mcv(&mut self) -> MCV_W<'_>

Bits 5:7 - Max count value

pub fn iodef(&mut self) -> IODEF_W<'_>

Bit 4 - I/O Default mode

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 3 - Synchronization pin polarity

pub fn am(&mut self) -> AM_W<'_>

Bit 2 - Acquisition mode

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start a new acquisition

pub fn tsce(&mut self) -> TSCE_W<'_>

Bit 0 - Touch sensing controller enable

impl W<u32, Reg<u32, _IER>>

pub fn mceie(&mut self) -> MCEIE_W<'_>

Bit 1 - Max count error interrupt enable

pub fn eoaie(&mut self) -> EOAIE_W<'_>

Bit 0 - End of acquisition interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn mceic(&mut self) -> MCEIC_W<'_>

Bit 1 - Max count error interrupt clear

pub fn eoaic(&mut self) -> EOAIC_W<'_>

Bit 0 - End of acquisition interrupt clear

impl W<u32, Reg<u32, _ISR>>

pub fn mcef(&mut self) -> MCEF_W<'_>

Bit 1 - Max count error flag

pub fn eoaf(&mut self) -> EOAF_W<'_>

Bit 0 - End of acquisition flag

impl W<u32, Reg<u32, _IOHCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 Schmitt trigger hysteresis mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 Schmitt trigger hysteresis mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 Schmitt trigger hysteresis mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 Schmitt trigger hysteresis mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 Schmitt trigger hysteresis mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 Schmitt trigger hysteresis mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 Schmitt trigger hysteresis mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 Schmitt trigger hysteresis mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 Schmitt trigger hysteresis mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 Schmitt trigger hysteresis mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 Schmitt trigger hysteresis mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 Schmitt trigger hysteresis mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 Schmitt trigger hysteresis mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 Schmitt trigger hysteresis mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 Schmitt trigger hysteresis mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 Schmitt trigger hysteresis mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 Schmitt trigger hysteresis mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 Schmitt trigger hysteresis mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 Schmitt trigger hysteresis mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 Schmitt trigger hysteresis mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 Schmitt trigger hysteresis mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 Schmitt trigger hysteresis mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 Schmitt trigger hysteresis mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 Schmitt trigger hysteresis mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 Schmitt trigger hysteresis mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 Schmitt trigger hysteresis mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 Schmitt trigger hysteresis mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 Schmitt trigger hysteresis mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 Schmitt trigger hysteresis mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 Schmitt trigger hysteresis mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 Schmitt trigger hysteresis mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 Schmitt trigger hysteresis mode

impl W<u32, Reg<u32, _IOASCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 analog switch enable

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 analog switch enable

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 analog switch enable

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 analog switch enable

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 analog switch enable

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 analog switch enable

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 analog switch enable

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 analog switch enable

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 analog switch enable

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 analog switch enable

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 analog switch enable

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 analog switch enable

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 analog switch enable

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 analog switch enable

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 analog switch enable

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 analog switch enable

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 analog switch enable

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 analog switch enable

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 analog switch enable

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 analog switch enable

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 analog switch enable

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 analog switch enable

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 analog switch enable

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 analog switch enable

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 analog switch enable

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 analog switch enable

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 analog switch enable

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 analog switch enable

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 analog switch enable

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 analog switch enable

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 analog switch enable

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 analog switch enable

impl W<u32, Reg<u32, _IOSCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 sampling mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 sampling mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 sampling mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 sampling mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 sampling mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 sampling mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 sampling mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 sampling mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 sampling mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 sampling mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 sampling mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 sampling mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 sampling mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 sampling mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 sampling mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 sampling mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 sampling mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 sampling mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 sampling mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 sampling mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 sampling mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 sampling mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 sampling mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 sampling mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 sampling mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 sampling mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 sampling mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 sampling mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 sampling mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 sampling mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 sampling mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 sampling mode

impl W<u32, Reg<u32, _IOCCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 channel mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 channel mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 channel mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 channel mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 channel mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 channel mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 channel mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 channel mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 channel mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 channel mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 channel mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 channel mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 channel mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 channel mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 channel mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 channel mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 channel mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 channel mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 channel mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 channel mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 channel mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 channel mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 channel mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 channel mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 channel mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 channel mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 channel mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 channel mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 channel mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 channel mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 channel mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 channel mode

impl W<u32, Reg<u32, _IOGCSR>>

pub fn g8s(&mut self) -> G8S_W<'_>

Bit 23 - Analog I/O group x status

pub fn g7s(&mut self) -> G7S_W<'_>

Bit 22 - Analog I/O group x status

pub fn g8e(&mut self) -> G8E_W<'_>

Bit 7 - Analog I/O group x enable

pub fn g7e(&mut self) -> G7E_W<'_>

Bit 6 - Analog I/O group x enable

pub fn g6e(&mut self) -> G6E_W<'_>

Bit 5 - Analog I/O group x enable

pub fn g5e(&mut self) -> G5E_W<'_>

Bit 4 - Analog I/O group x enable

pub fn g4e(&mut self) -> G4E_W<'_>

Bit 3 - Analog I/O group x enable

pub fn g3e(&mut self) -> G3E_W<'_>

Bit 2 - Analog I/O group x enable

pub fn g2e(&mut self) -> G2E_W<'_>

Bit 1 - Analog I/O group x enable

pub fn g1e(&mut self) -> G1E_W<'_>

Bit 0 - Analog I/O group x enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - General-purpose 8-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - reset bit

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

impl W<u32, Reg<u32, _INIT>>

pub fn init(&mut self) -> INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u8, Reg<u8, _DR8>>

pub fn dr8(&mut self) -> DR8_W<'_>

Bits 0:7 - Data register bits

impl W<u16, Reg<u16, _DR16>>

pub fn dr16(&mut self) -> DR16_W<'_>

Bits 0:15 - Data register bits

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - LATENCY

pub fn prftbe(&mut self) -> PRFTBE_W<'_>

Bit 4 - PRFTBE

pub fn hlfcya(&mut self) -> HLFCYA_W<'_>

Bit 3 - Flash half cycle access enable

impl W<u32, Reg<u32, _KEYR>>

pub fn fkeyr(&mut self) -> FKEYR_W<'_>

Bits 0:31 - Flash Key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 13 - Force option byte loading

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash address

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB high speed prescaler (APB2)

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 15:16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn usbpre(&mut self) -> USBPRE_W<'_>

Bit 22 - USB prescaler

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn i2ssrc(&mut self) -> I2SSRC_W<'_>

Bit 23 - I2S external clock source selection

pub fn mcopre(&mut self) -> MCOPRE_W<'_>

Bits 28:30 - Microcontroller Clock Output Prescaler

pub fn pllnodiv(&mut self) -> PLLNODIV_W<'_>

Bit 31 - Do not divide PLL to MCO

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG and COMP reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>

Bit 13 - TIM8 timer reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn spi4rst(&mut self) -> SPI4RST_W<'_>

Bit 15 - SPI4 reset

pub fn tim20rst(&mut self) -> TIM20RST_W<'_>

Bit 20 - TIM20 timer reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - Timer 14 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - Timer 6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - Timer 7 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - UART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - UART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 23 - USB reset

pub fn canrst(&mut self) -> CANRST_W<'_>

Bit 25 - CAN reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dac1rst(&mut self) -> DAC1RST_W<'_>

Bit 29 - DAC interface reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 30 - I2C3 reset

pub fn dac2rst(&mut self) -> DAC2RST_W<'_>

Bit 26 - DAC2 interface reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn fmcen(&mut self) -> FMCEN_W<'_>

Bit 5 - FMC clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

pub fn iophen(&mut self) -> IOPHEN_W<'_>

Bit 16 - IO port H clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 17 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 18 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 19 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 20 - I/O port D clock enable

pub fn iopeen(&mut self) -> IOPEEN_W<'_>

Bit 21 - I/O port E clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 22 - I/O port F clock enable

pub fn iopgen(&mut self) -> IOPGEN_W<'_>

Bit 23 - I/O port G clock enable

pub fn tscen(&mut self) -> TSCEN_W<'_>

Bit 24 - Touch sensing controller clock enable

pub fn adc12en(&mut self) -> ADC12EN_W<'_>

Bit 28 - ADC1 and ADC2 clock enable

pub fn adc34en(&mut self) -> ADC34EN_W<'_>

Bit 29 - ADC3 and ADC4 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 Timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>

Bit 13 - TIM8 Timer clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM17 timer clock enable

pub fn spi4en(&mut self) -> SPI4EN_W<'_>

Bit 15 - SPI4 clock enable

pub fn tim20en(&mut self) -> TIM20EN_W<'_>

Bit 20 - TIM20 timer clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - Timer 4 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - Timer 6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - Timer 7 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI 3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART 3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - USART 4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - USART 5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C 2 clock enable

pub fn usben(&mut self) -> USBEN_W<'_>

Bit 23 - USB clock enable

pub fn canen(&mut self) -> CANEN_W<'_>

Bit 25 - CAN clock enable

pub fn dac2en(&mut self) -> DAC2EN_W<'_>

Bit 26 - DAC2 interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dac1en(&mut self) -> DAC1EN_W<'_>

Bit 29 - DAC interface clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 30 - I2C3 clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

pub fn v18pwrrstf(&mut self) -> V18PWRRSTF_W<'_>

Bit 23 - Reset flag of the 1.8 V domain

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn fmcrst(&mut self) -> FMCRST_W<'_>

Bit 5 - FMC reset

pub fn iophrst(&mut self) -> IOPHRST_W<'_>

Bit 16 - I/O port H reset

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 17 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 18 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 19 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 20 - I/O port D reset

pub fn ioperst(&mut self) -> IOPERST_W<'_>

Bit 21 - I/O port E reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 22 - I/O port F reset

pub fn iopgrst(&mut self) -> IOPGRST_W<'_>

Bit 23 - Touch sensing controller reset

pub fn tscrst(&mut self) -> TSCRST_W<'_>

Bit 24 - Touch sensing controller reset

pub fn adc12rst(&mut self) -> ADC12RST_W<'_>

Bit 28 - ADC1 and ADC2 reset

pub fn adc34rst(&mut self) -> ADC34RST_W<'_>

Bit 29 - ADC3 and ADC4 reset

impl W<u32, Reg<u32, _CFGR2>>

pub fn prediv(&mut self) -> PREDIV_W<'_>

Bits 0:3 - PREDIV division factor

pub fn adc12pres(&mut self) -> ADC12PRES_W<'_>

Bits 4:8 - ADC1 and ADC2 prescaler

pub fn adc34pres(&mut self) -> ADC34PRES_W<'_>

Bits 9:13 - ADC3 and ADC4 prescaler

impl W<u32, Reg<u32, _CFGR3>>

pub fn usart1sw(&mut self) -> USART1SW_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn i2c1sw(&mut self) -> I2C1SW_W<'_>

Bit 4 - I2C1 clock source selection

pub fn i2c2sw(&mut self) -> I2C2SW_W<'_>

Bit 5 - I2C2 clock source selection

pub fn i2c3sw(&mut self) -> I2C3SW_W<'_>

Bit 6 - I2C3 clock source selection

pub fn usart2sw(&mut self) -> USART2SW_W<'_>

Bits 16:17 - USART2 clock source selection

pub fn usart3sw(&mut self) -> USART3SW_W<'_>

Bits 18:19 - USART3 clock source selection

pub fn tim1sw(&mut self) -> TIM1SW_W<'_>

Bit 8 - Timer1 clock source selection

pub fn tim8sw(&mut self) -> TIM8SW_W<'_>

Bit 9 - Timer8 clock source selection

pub fn uart4sw(&mut self) -> UART4SW_W<'_>

Bits 20:21 - UART4 clock source selection

pub fn uart5sw(&mut self) -> UART5SW_W<'_>

Bits 22:23 - UART5 clock source selection

pub fn tim20sw(&mut self) -> TIM20SW_W<'_>

Bit 15 - Timer20 clock source selection

pub fn tim15sw(&mut self) -> TIM15SW_W<'_>

Bit 10 - Timer15 clock source selection

pub fn tim16sw(&mut self) -> TIM16SW_W<'_>

Bit 11 - Timer16 clock source selection

pub fn tim17sw(&mut self) -> TIM17SW_W<'_>

Bit 13 - Timer17 clock source selection

pub fn tim2sw(&mut self) -> TIM2SW_W<'_>

Bit 24 - Timer2 clock source selection

pub fn tim34sw(&mut self) -> TIM34SW_W<'_>

Bit 25 - Timer34 clock source selection

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection bit3

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output compare 1 mode bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output compare 2 mode bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output compare 3 mode bit3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output compare 4 mode bit3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection bit 3

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable deassertion time

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:15 - mantissa of USARTDIV

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of timeout clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn crcl(&mut self) -> CRCL_W<'_>

Bit 11 - CRC length

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _IMR1>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Interrupt Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Interrupt Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Interrupt Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Interrupt Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Interrupt Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Interrupt Mask on line 28

pub fn mr29(&mut self) -> MR29_W<'_>

Bit 29 - Interrupt Mask on line 29

pub fn mr30(&mut self) -> MR30_W<'_>

Bit 30 - Interrupt Mask on line 30

pub fn mr31(&mut self) -> MR31_W<'_>

Bit 31 - Interrupt Mask on line 31

impl W<u32, Reg<u32, _EMR1>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Event Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Event Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Event Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Event Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Event Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Event Mask on line 28

pub fn mr29(&mut self) -> MR29_W<'_>

Bit 29 - Event Mask on line 29

pub fn mr30(&mut self) -> MR30_W<'_>

Bit 30 - Event Mask on line 30

pub fn mr31(&mut self) -> MR31_W<'_>

Bit 31 - Event Mask on line 31

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

pub fn tr29(&mut self) -> TR29_W<'_>

Bit 29 - Rising trigger event configuration of line 29

pub fn tr30(&mut self) -> TR30_W<'_>

Bit 30 - Rising trigger event configuration of line 30

pub fn tr31(&mut self) -> TR31_W<'_>

Bit 31 - Rising trigger event configuration of line 31

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Falling trigger event configuration of line 22

pub fn tr29(&mut self) -> TR29_W<'_>

Bit 29 - Falling trigger event configuration of line 29

pub fn tr30(&mut self) -> TR30_W<'_>

Bit 30 - Falling trigger event configuration of line 30.

pub fn tr31(&mut self) -> TR31_W<'_>

Bit 31 - Falling trigger event configuration of line 31

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

pub fn swier29(&mut self) -> SWIER29_W<'_>

Bit 29 - Software Interrupt on line 29

pub fn swier30(&mut self) -> SWIER30_W<'_>

Bit 30 - Software Interrupt on line 309

pub fn swier31(&mut self) -> SWIER31_W<'_>

Bit 31 - Software Interrupt on line 319

impl W<u32, Reg<u32, _PR1>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

pub fn pr29(&mut self) -> PR29_W<'_>

Bit 29 - Pending bit 29

pub fn pr30(&mut self) -> PR30_W<'_>

Bit 30 - Pending bit 30

pub fn pr31(&mut self) -> PR31_W<'_>

Bit 31 - Pending bit 31

impl W<u32, Reg<u32, _IMR2>>

pub fn mr32(&mut self) -> MR32_W<'_>

Bit 0 - Interrupt Mask on external/internal line 32

pub fn mr33(&mut self) -> MR33_W<'_>

Bit 1 - Interrupt Mask on external/internal line 33

pub fn mr34(&mut self) -> MR34_W<'_>

Bit 2 - Interrupt Mask on external/internal line 34

pub fn mr35(&mut self) -> MR35_W<'_>

Bit 3 - Interrupt Mask on external/internal line 35

impl W<u32, Reg<u32, _EMR2>>

pub fn mr32(&mut self) -> MR32_W<'_>

Bit 0 - Event mask on external/internal line 32

pub fn mr33(&mut self) -> MR33_W<'_>

Bit 1 - Event mask on external/internal line 33

pub fn mr34(&mut self) -> MR34_W<'_>

Bit 2 - Event mask on external/internal line 34

pub fn mr35(&mut self) -> MR35_W<'_>

Bit 3 - Event mask on external/internal line 35

impl W<u32, Reg<u32, _RTSR2>>

pub fn tr32(&mut self) -> TR32_W<'_>

Bit 0 - Rising trigger event configuration bit of line 32

pub fn tr33(&mut self) -> TR33_W<'_>

Bit 1 - Rising trigger event configuration bit of line 33

impl W<u32, Reg<u32, _FTSR2>>

pub fn tr32(&mut self) -> TR32_W<'_>

Bit 0 - Falling trigger event configuration bit of line 32

pub fn tr33(&mut self) -> TR33_W<'_>

Bit 1 - Falling trigger event configuration bit of line 33

impl W<u32, Reg<u32, _SWIER2>>

pub fn swier32(&mut self) -> SWIER32_W<'_>

Bit 0 - Software interrupt on line 32

pub fn swier33(&mut self) -> SWIER33_W<'_>

Bit 1 - Software interrupt on line 33

impl W<u32, Reg<u32, _PR2>>

pub fn pr32(&mut self) -> PR32_W<'_>

Bit 0 - Pending bit on line 32

pub fn pr33(&mut self) -> PR33_W<'_>

Bit 1 - Pending bit on line 33

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low-power deep sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power down deepsleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear wakeup flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear standby flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power voltage detector enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD level selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

impl W<u32, Reg<u32, _CSR>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 8 - Enable WKUP1 pin

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 9 - Enable WKUP2 pin

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb0(&mut self) -> FB0_W<'_>

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>

Bit 31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb0(&mut self) -> FB0_W<'_>

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>

Bit 31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2 start bank

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - Filter init mode

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bit 0 - Device address

pub fn add1(&mut self) -> ADD1_W<'_>

Bit 1 - Device address

pub fn add2(&mut self) -> ADD2_W<'_>

Bit 2 - Device address

pub fn add3(&mut self) -> ADD3_W<'_>

Bit 3 - Device address

pub fn add4(&mut self) -> ADD4_W<'_>

Bit 4 - Device address

pub fn add5(&mut self) -> ADD5_W<'_>

Bit 5 - Device address

pub fn add6(&mut self) -> ADD6_W<'_>

Bit 6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 13 - Software reset

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit 9:8 (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

pub fn oa1(&mut self) -> OA1_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>

Bit 15 - RTC_TAMP3 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAFCR>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp3e(&mut self) -> TAMP3E_W<'_>

Bit 5 - Tamper 3 detection enable

pub fn tamp3trg(&mut self) -> TAMP3TRG_W<'_>

Bit 6 - Active level for tamper 3

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn pc13value(&mut self) -> PC13VALUE_W<'_>

Bit 18 - PC13 value

pub fn pc13mode(&mut self) -> PC13MODE_W<'_>

Bit 19 - PC13 mode

pub fn pc14value(&mut self) -> PC14VALUE_W<'_>

Bit 20 - PC14 value

pub fn pc14mode(&mut self) -> PC14MODE_W<'_>

Bit 21 - PC 14 mode

pub fn pc15value(&mut self) -> PC15VALUE_W<'_>

Bit 22 - PC15 value

pub fn pc15mode(&mut self) -> PC15MODE_W<'_>

Bit 23 - PC15 mode

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - Debug Sleep mode

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - Trace pin assignment control

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - Trace pin assignment control

impl W<u32, Reg<u32, _APB1_FZ>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - Debug Timer 3 stopped when Core is halted

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - Debug Timer 4 stopped when Core is halted

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - Debug Timer 5 stopped when Core is halted

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - Debug Timer 7 stopped when Core is halted

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>

Bit 6 - Debug Timer 12 stopped when Core is halted

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>

Bit 7 - Debug Timer 13 stopped when Core is halted

pub fn dbg_timer14_stop(&mut self) -> DBG_TIMER14_STOP_W<'_>

Bit 8 - Debug Timer 14 stopped when Core is halted

pub fn dbg_tim18_stop(&mut self) -> DBG_TIM18_STOP_W<'_>

Bit 9 - Debug Timer 18 stopped when Core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn i2c1_smbus_timeout(&mut self) -> I2C1_SMBUS_TIMEOUT_W<'_>

Bit 21 - SMBUS timeout mode stopped when Core is halted

pub fn i2c2_smbus_timeout(&mut self) -> I2C2_SMBUS_TIMEOUT_W<'_>

Bit 22 - SMBUS timeout mode stopped when Core is halted

pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>

Bit 25 - Debug CAN stopped when core is halted

impl W<u32, Reg<u32, _APB2FZ>>

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 2 - Debug Timer 15 stopped when Core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 3 - Debug Timer 16 stopped when Core is halted

pub fn dbg_tim17_sto(&mut self) -> DBG_TIM17_STO_W<'_>

Bit 4 - Debug Timer 17 stopped when Core is halted

pub fn dbg_tim19_stop(&mut self) -> DBG_TIM19_STOP_W<'_>

Bit 5 - Debug Timer 19 stopped when Core is halted

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms3(&mut self) -> SMS3_W<'_>

Bit 16 - Slave mode selection bit 3

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn c5if(&mut self) -> C5IF_W<'_>

Bit 16 - Capture/Compare 5 interrupt flag

pub fn c6if(&mut self) -> C6IF_W<'_>

Bit 17 - Capture/Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output Polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc5m_3(&mut self) -> OC5M_3_W<'_>

Bit 16 - Outout Compare 5 mode bit 3

pub fn oc6m_3(&mut self) -> OC6M_3_W<'_>

Bit 24 - Outout Compare 6 mode bit 3

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 5 value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 6 value

impl W<u32, Reg<u32, _OR>>

pub fn tim1_etr_adc1_rmp(&mut self) -> TIM1_ETR_ADC1_RMP_W<'_>

Bits 0:1 - TIM1_ETR_ADC1 remapping capability

pub fn tim1_etr_adc4_rmp(&mut self) -> TIM1_ETR_ADC4_RMP_W<'_>

Bits 2:3 - TIM1_ETR_ADC4 remapping capability

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms3(&mut self) -> SMS3_W<'_>

Bit 16 - Slave mode selection bit 3

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn c5if(&mut self) -> C5IF_W<'_>

Bit 16 - Capture/Compare 5 interrupt flag

pub fn c6if(&mut self) -> C6IF_W<'_>

Bit 17 - Capture/Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output Polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc5m_3(&mut self) -> OC5M_3_W<'_>

Bit 16 - Outout Compare 5 mode bit 3

pub fn oc6m_3(&mut self) -> OC6M_3_W<'_>

Bit 24 - Outout Compare 6 mode bit 3

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 5 value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 6 value

impl W<u32, Reg<u32, _OR>>

pub fn tim8_etr_adc2_rmp(&mut self) -> TIM8_ETR_ADC2_RMP_W<'_>

Bits 0:1 - TIM8_ETR_ADC2 remapping capability

pub fn tim8_etr_adc3_rmp(&mut self) -> TIM8_ETR_ADC3_RMP_W<'_>

Bits 2:3 - TIM8_ETR_ADC3 remapping capability

impl W<u32, Reg<u32, _ISR>>

pub fn jqovf(&mut self) -> JQOVF_W<'_>

Bit 10 - JQOVF

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - AWD3

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - AWD2

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - AWD1

pub fn jeos(&mut self) -> JEOS_W<'_>

Bit 6 - JEOS

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 5 - JEOC

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - OVR

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - EOS

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - EOC

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - EOSMP

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADRDY

impl W<u32, Reg<u32, _IER>>

pub fn jqovfie(&mut self) -> JQOVFIE_W<'_>

Bit 10 - JQOVFIE

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - AWD3IE

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - AWD2IE

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - AWD1IE

pub fn jeosie(&mut self) -> JEOSIE_W<'_>

Bit 6 - JEOSIE

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 5 - JEOCIE

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - OVRIE

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - EOSIE

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - EOCIE

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - EOSMPIE

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADRDYIE

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADCAL

pub fn adcaldif(&mut self) -> ADCALDIF_W<'_>

Bit 30 - ADCALDIF

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bits 28:29 - ADVREGEN

pub fn jadstp(&mut self) -> JADSTP_W<'_>

Bit 5 - JADSTP

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADSTP

pub fn jadstart(&mut self) -> JADSTART_W<'_>

Bit 3 - JADSTART

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADSTART

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADDIS

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADEN

impl W<u32, Reg<u32, _CFGR>>

pub fn awd1ch(&mut self) -> AWD1CH_W<'_>

Bits 26:30 - AWDCH1CH

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 25 - JAUTO

pub fn jawd1en(&mut self) -> JAWD1EN_W<'_>

Bit 24 - JAWD1EN

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - AWD1EN

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - AWD1SGL

pub fn jqm(&mut self) -> JQM_W<'_>

Bit 21 - JQM

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 20 - JDISCEN

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 17:19 - DISCNUM

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - DISCEN

pub fn autdly(&mut self) -> AUTDLY_W<'_>

Bit 14 - AUTDLY

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - CONT

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - OVRMOD

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - EXTEN

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:9 - EXTSEL

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ALIGN

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - RES

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - DMACFG

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMAEN

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - SMP9

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - SMP8

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - SMP7

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - SMP6

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - SMP5

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - SMP4

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - SMP3

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - SMP2

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - SMP1

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - SMP18

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - SMP17

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - SMP16

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - SMP15

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - SMP14

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - SMP13

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - SMP12

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - SMP11

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - SMP10

impl W<u32, Reg<u32, _TR1>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - HT1

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - LT1

impl W<u32, Reg<u32, _TR2>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:23 - HT2

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:7 - LT2

impl W<u32, Reg<u32, _TR3>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:23 - HT3

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:7 - LT3

impl W<u32, Reg<u32, _SQR1>>

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 24:28 - SQ4

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 18:22 - SQ3

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 12:16 - SQ2

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 6:10 - SQ1

pub fn l(&mut self) -> L_W<'_>

Bits 0:3 - L3

impl W<u32, Reg<u32, _SQR2>>

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 24:28 - SQ9

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 18:22 - SQ8

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 12:16 - SQ7

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 6:10 - SQ6

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 0:4 - SQ5

impl W<u32, Reg<u32, _SQR3>>

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 24:28 - SQ14

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 18:22 - SQ13

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 12:16 - SQ12

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 6:10 - SQ11

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 0:4 - SQ10

impl W<u32, Reg<u32, _SQR4>>

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 6:10 - SQ16

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 0:4 - SQ15

impl W<u32, Reg<u32, _JSQR>>

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 26:30 - JSQ4

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 20:24 - JSQ3

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 14:18 - JSQ2

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 8:12 - JSQ1

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 6:7 - JEXTEN

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 2:5 - JEXTSEL

pub fn jl(&mut self) -> JL_W<'_>

Bits 0:1 - JL

impl W<u32, Reg<u32, _OFR1>>

pub fn offset1_en(&mut self) -> OFFSET1_EN_W<'_>

Bit 31 - OFFSET1_EN

pub fn offset1_ch(&mut self) -> OFFSET1_CH_W<'_>

Bits 26:30 - OFFSET1_CH

pub fn offset1(&mut self) -> OFFSET1_W<'_>

Bits 0:11 - OFFSET1

impl W<u32, Reg<u32, _OFR2>>

pub fn offset2_en(&mut self) -> OFFSET2_EN_W<'_>

Bit 31 - OFFSET2_EN

pub fn offset2_ch(&mut self) -> OFFSET2_CH_W<'_>

Bits 26:30 - OFFSET2_CH

pub fn offset2(&mut self) -> OFFSET2_W<'_>

Bits 0:11 - OFFSET2

impl W<u32, Reg<u32, _OFR3>>

pub fn offset3_en(&mut self) -> OFFSET3_EN_W<'_>

Bit 31 - OFFSET3_EN

pub fn offset3_ch(&mut self) -> OFFSET3_CH_W<'_>

Bits 26:30 - OFFSET3_CH

pub fn offset3(&mut self) -> OFFSET3_W<'_>

Bits 0:11 - OFFSET3

impl W<u32, Reg<u32, _OFR4>>

pub fn offset4_en(&mut self) -> OFFSET4_EN_W<'_>

Bit 31 - OFFSET4_EN

pub fn offset4_ch(&mut self) -> OFFSET4_CH_W<'_>

Bits 26:30 - OFFSET4_CH

pub fn offset4(&mut self) -> OFFSET4_W<'_>

Bits 0:11 - OFFSET4

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch0(&mut self) -> AWD2CH0_W<'_>

Bit 0 - AWD2CH

pub fn awd2ch1(&mut self) -> AWD2CH1_W<'_>

Bit 1 - AWD2CH

pub fn awd2ch2(&mut self) -> AWD2CH2_W<'_>

Bit 2 - AWD2CH

pub fn awd2ch3(&mut self) -> AWD2CH3_W<'_>

Bit 3 - AWD2CH

pub fn awd2ch4(&mut self) -> AWD2CH4_W<'_>

Bit 4 - AWD2CH

pub fn awd2ch5(&mut self) -> AWD2CH5_W<'_>

Bit 5 - AWD2CH

pub fn awd2ch6(&mut self) -> AWD2CH6_W<'_>

Bit 6 - AWD2CH

pub fn awd2ch7(&mut self) -> AWD2CH7_W<'_>

Bit 7 - AWD2CH

pub fn awd2ch8(&mut self) -> AWD2CH8_W<'_>

Bit 8 - AWD2CH

pub fn awd2ch9(&mut self) -> AWD2CH9_W<'_>

Bit 9 - AWD2CH

pub fn awd2ch10(&mut self) -> AWD2CH10_W<'_>

Bit 10 - AWD2CH

pub fn awd2ch11(&mut self) -> AWD2CH11_W<'_>

Bit 11 - AWD2CH

pub fn awd2ch12(&mut self) -> AWD2CH12_W<'_>

Bit 12 - AWD2CH

pub fn awd2ch13(&mut self) -> AWD2CH13_W<'_>

Bit 13 - AWD2CH

pub fn awd2ch14(&mut self) -> AWD2CH14_W<'_>

Bit 14 - AWD2CH

pub fn awd2ch15(&mut self) -> AWD2CH15_W<'_>

Bit 15 - AWD2CH

pub fn awd2ch16(&mut self) -> AWD2CH16_W<'_>

Bit 16 - AWD2CH

pub fn awd2ch17(&mut self) -> AWD2CH17_W<'_>

Bit 17 - AWD2CH

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch0(&mut self) -> AWD3CH0_W<'_>

Bit 0 - AWD3CH

pub fn awd3ch1(&mut self) -> AWD3CH1_W<'_>

Bit 1 - AWD3CH

pub fn awd3ch2(&mut self) -> AWD3CH2_W<'_>

Bit 2 - AWD3CH

pub fn awd3ch3(&mut self) -> AWD3CH3_W<'_>

Bit 3 - AWD3CH

pub fn awd3ch4(&mut self) -> AWD3CH4_W<'_>

Bit 4 - AWD3CH

pub fn awd3ch5(&mut self) -> AWD3CH5_W<'_>

Bit 5 - AWD3CH

pub fn awd3ch6(&mut self) -> AWD3CH6_W<'_>

Bit 6 - AWD3CH

pub fn awd3ch7(&mut self) -> AWD3CH7_W<'_>

Bit 7 - AWD3CH

pub fn awd3ch8(&mut self) -> AWD3CH8_W<'_>

Bit 8 - AWD3CH

pub fn awd3ch9(&mut self) -> AWD3CH9_W<'_>

Bit 9 - AWD3CH

pub fn awd3ch10(&mut self) -> AWD3CH10_W<'_>

Bit 10 - AWD3CH

pub fn awd3ch11(&mut self) -> AWD3CH11_W<'_>

Bit 11 - AWD3CH

pub fn awd3ch12(&mut self) -> AWD3CH12_W<'_>

Bit 12 - AWD3CH

pub fn awd3ch13(&mut self) -> AWD3CH13_W<'_>

Bit 13 - AWD3CH

pub fn awd3ch14(&mut self) -> AWD3CH14_W<'_>

Bit 14 - AWD3CH

pub fn awd3ch15(&mut self) -> AWD3CH15_W<'_>

Bit 15 - AWD3CH

pub fn awd3ch16(&mut self) -> AWD3CH16_W<'_>

Bit 16 - AWD3CH

pub fn awd3ch17(&mut self) -> AWD3CH17_W<'_>

Bit 17 - AWD3CH

impl W<u32, Reg<u32, _DIFSEL>>

pub fn difsel_10(&mut self) -> DIFSEL_10_W<'_>

Bit 0 - Differential mode for channels 15 to 1

pub fn difsel_11(&mut self) -> DIFSEL_11_W<'_>

Bit 1 - Differential mode for channels 15 to 1

pub fn difsel_12(&mut self) -> DIFSEL_12_W<'_>

Bit 2 - Differential mode for channels 15 to 1

pub fn difsel_13(&mut self) -> DIFSEL_13_W<'_>

Bit 3 - Differential mode for channels 15 to 1

pub fn difsel_14(&mut self) -> DIFSEL_14_W<'_>

Bit 4 - Differential mode for channels 15 to 1

pub fn difsel_15(&mut self) -> DIFSEL_15_W<'_>

Bit 5 - Differential mode for channels 15 to 1

pub fn difsel_16(&mut self) -> DIFSEL_16_W<'_>

Bit 6 - Differential mode for channels 15 to 1

pub fn difsel_17(&mut self) -> DIFSEL_17_W<'_>

Bit 7 - Differential mode for channels 15 to 1

pub fn difsel_18(&mut self) -> DIFSEL_18_W<'_>

Bit 8 - Differential mode for channels 15 to 1

pub fn difsel_19(&mut self) -> DIFSEL_19_W<'_>

Bit 9 - Differential mode for channels 15 to 1

pub fn difsel_110(&mut self) -> DIFSEL_110_W<'_>

Bit 10 - Differential mode for channels 15 to 1

pub fn difsel_111(&mut self) -> DIFSEL_111_W<'_>

Bit 11 - Differential mode for channels 15 to 1

pub fn difsel_112(&mut self) -> DIFSEL_112_W<'_>

Bit 12 - Differential mode for channels 15 to 1

pub fn difsel_113(&mut self) -> DIFSEL_113_W<'_>

Bit 13 - Differential mode for channels 15 to 1

pub fn difsel_114(&mut self) -> DIFSEL_114_W<'_>

Bit 14 - Differential mode for channels 15 to 1

pub fn difsel_115(&mut self) -> DIFSEL_115_W<'_>

Bit 15 - Differential mode for channels 15 to 1

pub fn difsel_116(&mut self) -> DIFSEL_116_W<'_>

Bit 16 - Differential mode for channels 15 to 1

pub fn difsel_117(&mut self) -> DIFSEL_117_W<'_>

Bit 17 - Differential mode for channels 15 to 1

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact_d(&mut self) -> CALFACT_D_W<'_>

Bits 16:22 - CALFACT_D

pub fn calfact_s(&mut self) -> CALFACT_S_W<'_>

Bits 0:6 - CALFACT_S

impl W<u32, Reg<u32, _CCR>>

pub fn dual(&mut self) -> DUAL_W<'_>

Bits 0:4 - Dual ADC mode selection

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 8:11 - Delay between 2 sampling phases

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 13 - DMA configuration (for multi-ADC mode)

pub fn mdma(&mut self) -> MDMA_W<'_>

Bits 14:15 - Direct memory access mode for multi ADC mode

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 16:17 - ADC clock mode

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _CFGR1>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:2 - Memory mapping selection bits

pub fn usb_it_rmp(&mut self) -> USB_IT_RMP_W<'_>

Bit 5 - USB interrupt remap

pub fn tim1_itr3_rmp(&mut self) -> TIM1_ITR3_RMP_W<'_>

Bit 6 - Timer 1 ITR3 selection

pub fn dac1_trig_rmp(&mut self) -> DAC1_TRIG_RMP_W<'_>

Bit 7 - DAC trigger remap (when TSEL = 001)

pub fn adc2_dma_rmp(&mut self) -> ADC2_DMA_RMP_W<'_>

Bit 8 - ADC24 DMA remapping bit

pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<'_>

Bit 11 - TIM16 DMA request remapping bit

pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<'_>

Bit 12 - TIM17 DMA request remapping bit

pub fn tim6_dac1_ch1_dma_rmp(&mut self) -> TIM6_DAC1_CH1_DMA_RMP_W<'_>

Bit 13 - TIM6 and DAC1 DMA request remapping bit

pub fn tim7_dac1_ch2_dma_rmp(&mut self) -> TIM7_DAC1_CH2_DMA_RMP_W<'_>

Bit 14 - TIM7 and DAC2 DMA request remapping bit

pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>

Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>

Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>

Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>

Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - I2C1 Fast Mode Plus

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - I2C2 Fast Mode Plus

pub fn encoder_mode(&mut self) -> ENCODER_MODE_W<'_>

Bits 22:23 - Encoder mode

pub fn fpu_ie5(&mut self) -> FPU_IE5_W<'_>

Bit 31 - Inexact interrupt enable

pub fn fpu_ie4(&mut self) -> FPU_IE4_W<'_>

Bit 30 - Input denormal interrupt enable

pub fn fpu_ie3(&mut self) -> FPU_IE3_W<'_>

Bit 29 - Overflow interrupt enable

pub fn fpu_ie2(&mut self) -> FPU_IE2_W<'_>

Bit 28 - Underflow interrupt enable

pub fn fpu_ie1(&mut self) -> FPU_IE1_W<'_>

Bit 27 - Devide-by-zero interrupt enable

pub fn fpu_ie0(&mut self) -> FPU_IE0_W<'_>

Bit 26 - Invalid operation interrupt enable

pub fn dac2_ch1_dma_rmp(&mut self) -> DAC2_CH1_DMA_RMP_W<'_>

Bit 15 - DAC2 channel1 DMA remap

pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<'_>

Bit 24 - I2C3 Fast Mode Plus

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI 3 configuration bits

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI 2 configuration bits

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI 1 configuration bits

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI 0 configuration bits

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI 7 configuration bits

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI 6 configuration bits

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI 5 configuration bits

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI 4 configuration bits

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI 11 configuration bits

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI 10 configuration bits

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI 9 configuration bits

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI 8 configuration bits

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI 15 configuration bits

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI 14 configuration bits

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI 13 configuration bits

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI 12 configuration bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0 LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn byp_addr_par(&mut self) -> BYP_ADDR_PAR_W<'_>

Bit 4 - Bypass address bit 29 in parity calculation

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity flag

impl W<u32, Reg<u32, _RCR>>

pub fn page0_wp(&mut self) -> PAGE0_WP_W<'_>

Bit 0 - CCM SRAM page write protection bit

pub fn page1_wp(&mut self) -> PAGE1_WP_W<'_>

Bit 1 - CCM SRAM page write protection bit

pub fn page2_wp(&mut self) -> PAGE2_WP_W<'_>

Bit 2 - CCM SRAM page write protection bit

pub fn page3_wp(&mut self) -> PAGE3_WP_W<'_>

Bit 3 - CCM SRAM page write protection bit

pub fn page4_wp(&mut self) -> PAGE4_WP_W<'_>

Bit 4 - CCM SRAM page write protection bit

pub fn page5_wp(&mut self) -> PAGE5_WP_W<'_>

Bit 5 - CCM SRAM page write protection bit

pub fn page6_wp(&mut self) -> PAGE6_WP_W<'_>

Bit 6 - CCM SRAM page write protection bit

pub fn page7_wp(&mut self) -> PAGE7_WP_W<'_>

Bit 7 - CCM SRAM page write protection bit

pub fn page8_wp(&mut self) -> PAGE8_WP_W<'_>

Bit 8 - CCM SRAM page write protection bit

pub fn page9_wp(&mut self) -> PAGE9_WP_W<'_>

Bit 9 - CCM SRAM page write protection bit

pub fn page10_wp(&mut self) -> PAGE10_WP_W<'_>

Bit 10 - CCM SRAM page write protection bit

pub fn page11_wp(&mut self) -> PAGE11_WP_W<'_>

Bit 11 - CCM SRAM page write protection bit

pub fn page12_wp(&mut self) -> PAGE12_WP_W<'_>

Bit 12 - CCM SRAM page write protection bit

pub fn page13_wp(&mut self) -> PAGE13_WP_W<'_>

Bit 13 - CCM SRAM page write protection bit

pub fn page14_wp(&mut self) -> PAGE14_WP_W<'_>

Bit 14 - CCM SRAM page write protection bit

pub fn page15_wp(&mut self) -> PAGE15_WP_W<'_>

Bit 15 - CCM SRAM page write protection bit

impl W<u32, Reg<u32, _CFGR3>>

pub fn spi1_rx_dma_rmp(&mut self) -> SPI1_RX_DMA_RMP_W<'_>

Bits 0:1 - SPI1_RX DMA remapping bit

pub fn spi1_tx_dma_rmp(&mut self) -> SPI1_TX_DMA_RMP_W<'_>

Bits 2:3 - SPI1_TX DMA remapping bit

pub fn i2c1_rx_dma_rmp(&mut self) -> I2C1_RX_DMA_RMP_W<'_>

Bits 4:5 - I2C1_RX DMA remapping bit

pub fn i2c1_tx_dma_rmp(&mut self) -> I2C1_TX_DMA_RMP_W<'_>

Bits 6:7 - I2C1_TX DMA remapping bit

pub fn adc2_dma_rmp(&mut self) -> ADC2_DMA_RMP_W<'_>

Bits 8:9 - ADC2 DMA remapping bit

impl W<u32, Reg<u32, _CFGR4>>

pub fn adc12_ext2_rmp(&mut self) -> ADC12_EXT2_RMP_W<'_>

Bit 0 - Controls the Input trigger of ADC12 regular channel EXT2

pub fn adc12_ext3_rmp(&mut self) -> ADC12_EXT3_RMP_W<'_>

Bit 1 - Controls the Input trigger of ADC12 regular channel EXT3

pub fn adc12_ext5_rmp(&mut self) -> ADC12_EXT5_RMP_W<'_>

Bit 2 - Controls the Input trigger of ADC12 regular channel EXT5

pub fn adc12_ext13_rmp(&mut self) -> ADC12_EXT13_RMP_W<'_>

Bit 3 - Controls the Input trigger of ADC12 regular channel EXT13

pub fn adc12_ext15_rmp(&mut self) -> ADC12_EXT15_RMP_W<'_>

Bit 4 - Controls the Input trigger of ADC12 regular channel EXT15

pub fn adc12_jext3_rmp(&mut self) -> ADC12_JEXT3_RMP_W<'_>

Bit 5 - Controls the Input trigger of ADC12 injected channel JEXT3

pub fn adc12_jext6_rmp(&mut self) -> ADC12_JEXT6_RMP_W<'_>

Bit 6 - Controls the Input trigger of ADC12 injected channel JEXT6

pub fn adc12_jext13_rmp(&mut self) -> ADC12_JEXT13_RMP_W<'_>

Bit 7 - Controls the Input trigger of ADC12 injected channel JEXT13

pub fn adc34_ext5_rmp(&mut self) -> ADC34_EXT5_RMP_W<'_>

Bit 8 - Controls the Input trigger of ADC34 regular channel EXT5

pub fn adc34_ext6_rmp(&mut self) -> ADC34_EXT6_RMP_W<'_>

Bit 9 - Controls the Input trigger of ADC34 regular channel EXT6

pub fn adc34_ext15_rmp(&mut self) -> ADC34_EXT15_RMP_W<'_>

Bit 10 - Controls the Input trigger of ADC34 regular channel EXT15

pub fn adc34_jext5_rmp(&mut self) -> ADC34_JEXT5_RMP_W<'_>

Bit 11 - Controls the Input trigger of ADC34 injected channel JEXT5

pub fn adc34_jext11_rmp(&mut self) -> ADC34_JEXT11_RMP_W<'_>

Bit 12 - Controls the Input trigger of ADC34 injected channel JEXT11

pub fn adc34_jext14_rmp(&mut self) -> ADC34_JEXT14_RMP_W<'_>

Bit 13 - Controls the Input trigger of ADC34 injected channel JEXT14

impl W<u32, Reg<u32, _BCR1>>

pub fn cclken(&mut self) -> CCLKEN_W<'_>

Bit 20 - CCLKEN

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR1>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR2>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR2>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR3>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR3>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR4>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR4>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _PCR2>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR2>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM2>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT2>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PCR3>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR3>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM3>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT3>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PCR4>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR4>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM4>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT4>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PIO4>>

pub fn iohizx(&mut self) -> IOHIZX_W<'_>

Bits 24:31 - IOHIZx

pub fn ioholdx(&mut self) -> IOHOLDX_W<'_>

Bits 16:23 - IOHOLDx

pub fn iowaitx(&mut self) -> IOWAITX_W<'_>

Bits 8:15 - IOWAITx

pub fn iosetx(&mut self) -> IOSETX_W<'_>

Bits 0:7 - IOSETx

impl W<u32, Reg<u32, _BWTR1>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR2>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR3>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR4>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection bit3

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output compare 1 mode bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output compare 2 mode bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output compare 3 mode bit3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output compare 4 mode bit3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

pub fn cnth(&mut self) -> CNTH_W<'_>

Bits 16:30 - High counter value

pub fn cnt_or_uifcpy(&mut self) -> CNT_OR_UIFCPY_W<'_>

Bit 31 - if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

pub fn arrh(&mut self) -> ARRH_W<'_>

Bits 16:31 - High Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

pub fn ccr1h(&mut self) -> CCR1H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (on TIM2)

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection bit3

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output compare 1 mode bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output compare 2 mode bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output compare 3 mode bit3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output compare 4 mode bit3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

pub fn cnth(&mut self) -> CNTH_W<'_>

Bits 16:30 - High counter value

pub fn cnt_or_uifcpy(&mut self) -> CNT_OR_UIFCPY_W<'_>

Bit 31 - if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

pub fn arrh(&mut self) -> ARRH_W<'_>

Bits 16:31 - High Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

pub fn ccr1h(&mut self) -> CCR1H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (on TIM2)

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _OPAMP2_CSR>>

pub fn opamp2en(&mut self) -> OPAMP2EN_W<'_>

Bit 0 - OPAMP2 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _OPAMP3_CSR>>

pub fn opamp3en(&mut self) -> OPAMP3EN_W<'_>

Bit 0 - OPAMP3 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _OPAMP4_CSR>>

pub fn opamp4en(&mut self) -> OPAMP4EN_W<'_>

Bit 0 - OPAMP4 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _OPAMP1_CSR>>

pub fn opamp1en(&mut self) -> OPAMP1EN_W<'_>

Bit 0 - OPAMP1 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _COMP2_CSR>>

pub fn comp2en(&mut self) -> COMP2EN_W<'_>

Bit 0 - Comparator 2 enable

pub fn comp2inmsel(&mut self) -> COMP2INMSEL_W<'_>

Bits 4:6 - Comparator 2 inverting input selection

pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<'_>

Bits 10:13 - Comparator 2 output selection

pub fn comp2pol(&mut self) -> COMP2POL_W<'_>

Bit 15 - Comparator 2 output polarity

pub fn comp2_blanking(&mut self) -> COMP2_BLANKING_W<'_>

Bits 18:20 - Comparator 2 blanking source

pub fn comp2lock(&mut self) -> COMP2LOCK_W<'_>

Bit 31 - Comparator 2 lock

pub fn comp2mode(&mut self) -> COMP2MODE_W<'_>

Bits 2:3 - Comparator 2 mode

pub fn comp2inpsel(&mut self) -> COMP2INPSEL_W<'_>

Bit 7 - Comparator 2 non inverted input

pub fn comp2winmode(&mut self) -> COMP2WINMODE_W<'_>

Bit 9 - Comparator 2 window mode

pub fn comp2hyst(&mut self) -> COMP2HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis

pub fn comp2inmsel3(&mut self) -> COMP2INMSEL3_W<'_>

Bit 22 - Comparator 2 inverting input selection

impl W<u32, Reg<u32, _COMP4_CSR>>

pub fn comp4en(&mut self) -> COMP4EN_W<'_>

Bit 0 - Comparator 4 enable

pub fn comp4inmsel(&mut self) -> COMP4INMSEL_W<'_>

Bits 4:6 - Comparator 4 inverting input selection

pub fn comp4outsel(&mut self) -> COMP4OUTSEL_W<'_>

Bits 10:13 - Comparator 4 output selection

pub fn comp4pol(&mut self) -> COMP4POL_W<'_>

Bit 15 - Comparator 4 output polarity

pub fn comp4_blanking(&mut self) -> COMP4_BLANKING_W<'_>

Bits 18:20 - Comparator 4 blanking source

pub fn comp4lock(&mut self) -> COMP4LOCK_W<'_>

Bit 31 - Comparator 4 lock

pub fn comp4winmode(&mut self) -> COMP4WINMODE_W<'_>

Bit 9 - Comparator 4 window mode

pub fn comp4mode(&mut self) -> COMP4MODE_W<'_>

Bits 2:3 - Comparator 4 mode

pub fn comp4inpsel(&mut self) -> COMP4INPSEL_W<'_>

Bit 7 - Comparator 4 non inverted input

pub fn comp4hyst(&mut self) -> COMP4HYST_W<'_>

Bits 16:17 - Comparator 4 hysteresis

pub fn comp4inmsel3(&mut self) -> COMP4INMSEL3_W<'_>

Bit 22 - Comparator 4 inverting input selection

impl W<u32, Reg<u32, _COMP6_CSR>>

pub fn comp6en(&mut self) -> COMP6EN_W<'_>

Bit 0 - Comparator 6 enable

pub fn comp6inmsel(&mut self) -> COMP6INMSEL_W<'_>

Bits 4:6 - Comparator 6 inverting input selection

pub fn comp6outsel(&mut self) -> COMP6OUTSEL_W<'_>

Bits 10:13 - Comparator 6 output selection

pub fn comp6pol(&mut self) -> COMP6POL_W<'_>

Bit 15 - Comparator 6 output polarity

pub fn comp6_blanking(&mut self) -> COMP6_BLANKING_W<'_>

Bits 18:20 - Comparator 6 blanking source

pub fn comp6lock(&mut self) -> COMP6LOCK_W<'_>

Bit 31 - Comparator 6 lock

pub fn comp6winmode(&mut self) -> COMP6WINMODE_W<'_>

Bit 9 - Comparator 6 window mode

pub fn comp6mode(&mut self) -> COMP6MODE_W<'_>

Bits 2:3 - Comparator 6 mode

pub fn comp6inpsel(&mut self) -> COMP6INPSEL_W<'_>

Bit 7 - Comparator 6 non inverted input

pub fn comp6hyst(&mut self) -> COMP6HYST_W<'_>

Bits 16:17 - Comparator 6 hysteresis

pub fn comp6inmsel3(&mut self) -> COMP6INMSEL3_W<'_>

Bit 22 - Comparator 6 inverting input selection

impl W<u32, Reg<u32, _COMP3_CSR>>

pub fn comp3en(&mut self) -> COMP3EN_W<'_>

Bit 0 - Comparator 3 enable

pub fn comp3mode(&mut self) -> COMP3MODE_W<'_>

Bits 2:3 - Comparator 3 mode

pub fn comp3inmsel(&mut self) -> COMP3INMSEL_W<'_>

Bits 4:6 - Comparator 3 inverting input selection

pub fn comp3inpsel(&mut self) -> COMP3INPSEL_W<'_>

Bit 7 - Comparator 3 non inverted input

pub fn comp3outsel(&mut self) -> COMP3OUTSEL_W<'_>

Bits 10:13 - Comparator 3 output selection

pub fn comp3pol(&mut self) -> COMP3POL_W<'_>

Bit 15 - Comparator 3 output polarity

pub fn comp3hyst(&mut self) -> COMP3HYST_W<'_>

Bits 16:17 - Comparator 3 hysteresis

pub fn comp3_blanking(&mut self) -> COMP3_BLANKING_W<'_>

Bits 18:20 - Comparator 3 blanking source

pub fn comp3lock(&mut self) -> COMP3LOCK_W<'_>

Bit 31 - Comparator 3 lock

impl W<u32, Reg<u32, _COMP5_CSR>>

pub fn comp5en(&mut self) -> COMP5EN_W<'_>

Bit 0 - Comparator 5 enable

pub fn comp5mode(&mut self) -> COMP5MODE_W<'_>

Bits 2:3 - Comparator 5 mode

pub fn comp5inmsel(&mut self) -> COMP5INMSEL_W<'_>

Bits 4:6 - Comparator 5 inverting input selection

pub fn comp5inpsel(&mut self) -> COMP5INPSEL_W<'_>

Bit 7 - Comparator 5 non inverted input

pub fn comp5outsel(&mut self) -> COMP5OUTSEL_W<'_>

Bits 10:13 - Comparator 5 output selection

pub fn comp5pol(&mut self) -> COMP5POL_W<'_>

Bit 15 - Comparator 5 output polarity

pub fn comp5hyst(&mut self) -> COMP5HYST_W<'_>

Bits 16:17 - Comparator 5 hysteresis

pub fn comp5_blanking(&mut self) -> COMP5_BLANKING_W<'_>

Bits 18:20 - Comparator 5 blanking source

pub fn comp5lock(&mut self) -> COMP5LOCK_W<'_>

Bit 31 - Comparator 5 lock

impl W<u32, Reg<u32, _COMP7_CSR>>

pub fn comp7en(&mut self) -> COMP7EN_W<'_>

Bit 0 - Comparator 7 enable

pub fn comp7mode(&mut self) -> COMP7MODE_W<'_>

Bits 2:3 - Comparator 7 mode

pub fn comp7inmsel(&mut self) -> COMP7INMSEL_W<'_>

Bits 4:6 - Comparator 7 inverting input selection

pub fn comp7inpsel(&mut self) -> COMP7INPSEL_W<'_>

Bit 7 - Comparator 7 non inverted input

pub fn comp7outsel(&mut self) -> COMP7OUTSEL_W<'_>

Bits 10:13 - Comparator 7 output selection

pub fn comp7pol(&mut self) -> COMP7POL_W<'_>

Bit 15 - Comparator 7 output polarity

pub fn comp7hyst(&mut self) -> COMP7HYST_W<'_>

Bits 16:17 - Comparator 7 hysteresis

pub fn comp7_blanking(&mut self) -> COMP7_BLANKING_W<'_>

Bits 18:20 - Comparator 7 blanking source

pub fn comp7lock(&mut self) -> COMP7LOCK_W<'_>

Bit 31 - Comparator 7 lock

impl W<u32, Reg<u32, _COMP1_CSR>>

pub fn comp1en(&mut self) -> COMP1EN_W<'_>

Bit 0 - Comparator 1 enable

pub fn comp1_inp_dac(&mut self) -> COMP1_INP_DAC_W<'_>

Bit 1 - Comparator 1 non inverting input connection to DAC output

pub fn comp1mode(&mut self) -> COMP1MODE_W<'_>

Bits 2:3 - Comparator 1 mode

pub fn comp1inmsel(&mut self) -> COMP1INMSEL_W<'_>

Bits 4:6 - Comparator 1 inverting input selection

pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<'_>

Bits 10:13 - Comparator 1 output selection

pub fn comp1pol(&mut self) -> COMP1POL_W<'_>

Bit 15 - Comparator 1 output polarity

pub fn comp1hyst(&mut self) -> COMP1HYST_W<'_>

Bits 16:17 - Comparator 1 hysteresis

pub fn comp1_blanking(&mut self) -> COMP1_BLANKING_W<'_>

Bits 18:20 - Comparator 1 blanking source

pub fn comp1lock(&mut self) -> COMP1LOCK_W<'_>

Bit 31 - Comparator 1 lock

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bit 15

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bit 14

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bit 13

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bit 12

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bit 11

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bit 10

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bit 9

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bit 8

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bit 7

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bit 6

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bit 5

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bit 4

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bit 3

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bit 2

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bit 1

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bit 0

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bit 15

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bit 14

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bit 13

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bit 12

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bit 11

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bit 10

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bit 9

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bit 8

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bit 7

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bit 6

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bit 5

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bit 4

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bit 3

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bit 2

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bit 1

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bit 0

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _CR>>

pub fn ctph(&mut self) -> CTPH_W<'_>

Bits 28:31 - Charge transfer pulse high

pub fn ctpl(&mut self) -> CTPL_W<'_>

Bits 24:27 - Charge transfer pulse low

pub fn ssd(&mut self) -> SSD_W<'_>

Bits 17:23 - Spread spectrum deviation

pub fn sse(&mut self) -> SSE_W<'_>

Bit 16 - Spread spectrum enable

pub fn sspsc(&mut self) -> SSPSC_W<'_>

Bit 15 - Spread spectrum prescaler

pub fn pgpsc(&mut self) -> PGPSC_W<'_>

Bits 12:14 - pulse generator prescaler

pub fn mcv(&mut self) -> MCV_W<'_>

Bits 5:7 - Max count value

pub fn iodef(&mut self) -> IODEF_W<'_>

Bit 4 - I/O Default mode

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 3 - Synchronization pin polarity

pub fn am(&mut self) -> AM_W<'_>

Bit 2 - Acquisition mode

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start a new acquisition

pub fn tsce(&mut self) -> TSCE_W<'_>

Bit 0 - Touch sensing controller enable

impl W<u32, Reg<u32, _IER>>

pub fn mceie(&mut self) -> MCEIE_W<'_>

Bit 1 - Max count error interrupt enable

pub fn eoaie(&mut self) -> EOAIE_W<'_>

Bit 0 - End of acquisition interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn mceic(&mut self) -> MCEIC_W<'_>

Bit 1 - Max count error interrupt clear

pub fn eoaic(&mut self) -> EOAIC_W<'_>

Bit 0 - End of acquisition interrupt clear

impl W<u32, Reg<u32, _ISR>>

pub fn mcef(&mut self) -> MCEF_W<'_>

Bit 1 - Max count error flag

pub fn eoaf(&mut self) -> EOAF_W<'_>

Bit 0 - End of acquisition flag

impl W<u32, Reg<u32, _IOHCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 Schmitt trigger hysteresis mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 Schmitt trigger hysteresis mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 Schmitt trigger hysteresis mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 Schmitt trigger hysteresis mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 Schmitt trigger hysteresis mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 Schmitt trigger hysteresis mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 Schmitt trigger hysteresis mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 Schmitt trigger hysteresis mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 Schmitt trigger hysteresis mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 Schmitt trigger hysteresis mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 Schmitt trigger hysteresis mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 Schmitt trigger hysteresis mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 Schmitt trigger hysteresis mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 Schmitt trigger hysteresis mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 Schmitt trigger hysteresis mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 Schmitt trigger hysteresis mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 Schmitt trigger hysteresis mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 Schmitt trigger hysteresis mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 Schmitt trigger hysteresis mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 Schmitt trigger hysteresis mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 Schmitt trigger hysteresis mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 Schmitt trigger hysteresis mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 Schmitt trigger hysteresis mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 Schmitt trigger hysteresis mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 Schmitt trigger hysteresis mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 Schmitt trigger hysteresis mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 Schmitt trigger hysteresis mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 Schmitt trigger hysteresis mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 Schmitt trigger hysteresis mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 Schmitt trigger hysteresis mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 Schmitt trigger hysteresis mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 Schmitt trigger hysteresis mode

impl W<u32, Reg<u32, _IOASCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 analog switch enable

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 analog switch enable

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 analog switch enable

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 analog switch enable

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 analog switch enable

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 analog switch enable

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 analog switch enable

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 analog switch enable

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 analog switch enable

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 analog switch enable

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 analog switch enable

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 analog switch enable

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 analog switch enable

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 analog switch enable

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 analog switch enable

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 analog switch enable

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 analog switch enable

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 analog switch enable

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 analog switch enable

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 analog switch enable

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 analog switch enable

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 analog switch enable

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 analog switch enable

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 analog switch enable

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 analog switch enable

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 analog switch enable

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 analog switch enable

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 analog switch enable

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 analog switch enable

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 analog switch enable

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 analog switch enable

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 analog switch enable

impl W<u32, Reg<u32, _IOSCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 sampling mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 sampling mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 sampling mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 sampling mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 sampling mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 sampling mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 sampling mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 sampling mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 sampling mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 sampling mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 sampling mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 sampling mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 sampling mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 sampling mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 sampling mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 sampling mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 sampling mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 sampling mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 sampling mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 sampling mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 sampling mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 sampling mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 sampling mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 sampling mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 sampling mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 sampling mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 sampling mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 sampling mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 sampling mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 sampling mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 sampling mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 sampling mode

impl W<u32, Reg<u32, _IOCCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 channel mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 channel mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 channel mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 channel mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 channel mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 channel mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 channel mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 channel mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 channel mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 channel mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 channel mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 channel mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 channel mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 channel mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 channel mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 channel mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 channel mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 channel mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 channel mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 channel mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 channel mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 channel mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 channel mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 channel mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 channel mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 channel mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 channel mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 channel mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 channel mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 channel mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 channel mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 channel mode

impl W<u32, Reg<u32, _IOGCSR>>

pub fn g8s(&mut self) -> G8S_W<'_>

Bit 23 - Analog I/O group x status

pub fn g7s(&mut self) -> G7S_W<'_>

Bit 22 - Analog I/O group x status

pub fn g8e(&mut self) -> G8E_W<'_>

Bit 7 - Analog I/O group x enable

pub fn g7e(&mut self) -> G7E_W<'_>

Bit 6 - Analog I/O group x enable

pub fn g6e(&mut self) -> G6E_W<'_>

Bit 5 - Analog I/O group x enable

pub fn g5e(&mut self) -> G5E_W<'_>

Bit 4 - Analog I/O group x enable

pub fn g4e(&mut self) -> G4E_W<'_>

Bit 3 - Analog I/O group x enable

pub fn g3e(&mut self) -> G3E_W<'_>

Bit 2 - Analog I/O group x enable

pub fn g2e(&mut self) -> G2E_W<'_>

Bit 1 - Analog I/O group x enable

pub fn g1e(&mut self) -> G1E_W<'_>

Bit 0 - Analog I/O group x enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - General-purpose 8-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - reset bit

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

impl W<u32, Reg<u32, _INIT>>

pub fn init(&mut self) -> INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u8, Reg<u8, _DR8>>

pub fn dr8(&mut self) -> DR8_W<'_>

Bits 0:7 - Data register bits

impl W<u16, Reg<u16, _DR16>>

pub fn dr16(&mut self) -> DR16_W<'_>

Bits 0:15 - Data register bits

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - LATENCY

pub fn prftbe(&mut self) -> PRFTBE_W<'_>

Bit 4 - PRFTBE

impl W<u32, Reg<u32, _KEYR>>

pub fn fkeyr(&mut self) -> FKEYR_W<'_>

Bits 0:31 - Flash Key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 13 - Force option byte loading

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash address

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB high speed prescaler (APB2)

pub fn adcpre(&mut self) -> ADCPRE_W<'_>

Bits 14:15 - ADC prescaler

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bit 16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn usbpre(&mut self) -> USBPRE_W<'_>

Bit 22 - USB prescaler

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn sdpre(&mut self) -> SDPRE_W<'_>

Bits 27:31 - SDADC prescaler

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG and COMP reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 9 - ADC interface reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn tim19rst(&mut self) -> TIM19RST_W<'_>

Bit 19 - TIM19 timer reset

pub fn sdadc1rst(&mut self) -> SDADC1RST_W<'_>

Bit 24 - SDADC1 (Sigma delta ADC 1) reset

pub fn sdadc2rst(&mut self) -> SDADC2RST_W<'_>

Bit 25 - SDADC2 (Sigma delta ADC 2) reset

pub fn sdadc3rst(&mut self) -> SDADC3RST_W<'_>

Bit 26 - SDADC3 (Sigma delta ADC 3) reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - Timer 14 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - Timer 5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - Timer 6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - Timer 7 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>

Bit 6 - Timer 12 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>

Bit 7 - Timer 13 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>

Bit 8 - Timer 14 reset

pub fn tim18rst(&mut self) -> TIM18RST_W<'_>

Bit 9 - Timer 18 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 23 - USB reset

pub fn canrst(&mut self) -> CANRST_W<'_>

Bit 25 - CAN reset

pub fn dac2rst(&mut self) -> DAC2RST_W<'_>

Bit 26 - DAC3 reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dac1rst(&mut self) -> DAC1RST_W<'_>

Bit 29 - DAC interface reset

pub fn cecrst(&mut self) -> CECRST_W<'_>

Bit 30 - HDMI CEC reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 17 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 18 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 19 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 20 - I/O port D clock enable

pub fn iopeen(&mut self) -> IOPEEN_W<'_>

Bit 21 - I/O port E clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 22 - I/O port F clock enable

pub fn tscen(&mut self) -> TSCEN_W<'_>

Bit 24 - Touch sensing controller clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 9 - ADC 1 interface clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM17 timer clock enable

pub fn tim19en(&mut self) -> TIM19EN_W<'_>

Bit 19 - TIM19 timer clock enable

pub fn dbgmcuen(&mut self) -> DBGMCUEN_W<'_>

Bit 22 - MCU debug module clock enable

pub fn sdadc1en(&mut self) -> SDADC1EN_W<'_>

Bit 24 - SDADC1 (Sigma Delta ADC 1) clock enable

pub fn sdadc2en(&mut self) -> SDADC2EN_W<'_>

Bit 25 - SDADC2 (Sigma Delta ADC 2) clock enable

pub fn sdadc3en(&mut self) -> SDADC3EN_W<'_>

Bit 26 - SDADC3 (Sigma Delta ADC 3) clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - Timer 4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - Timer 5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - Timer 6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - Timer 7 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>

Bit 6 - Timer 12 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>

Bit 7 - Timer 13 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>

Bit 8 - Timer 14 clock enable

pub fn tim18en(&mut self) -> TIM18EN_W<'_>

Bit 9 - Timer 18 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI 3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART 3 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C 2 clock enable

pub fn usben(&mut self) -> USBEN_W<'_>

Bit 23 - USB clock enable

pub fn canen(&mut self) -> CANEN_W<'_>

Bit 25 - CAN clock enable

pub fn dac2en(&mut self) -> DAC2EN_W<'_>

Bit 26 - DAC3 interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dac1en(&mut self) -> DAC1EN_W<'_>

Bit 29 - DAC interface clock enable

pub fn cecen(&mut self) -> CECEN_W<'_>

Bit 30 - HDMI CEC interface clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

pub fn v18pwrrstf(&mut self) -> V18PWRRSTF_W<'_>

Bit 23 - Reset flag of the 1.8 V domain

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 17 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 18 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 19 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 20 - I/O port D reset

pub fn ioperst(&mut self) -> IOPERST_W<'_>

Bit 21 - I/O port E reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 22 - I/O port F reset

pub fn tscrst(&mut self) -> TSCRST_W<'_>

Bit 24 - Touch sensing controller reset

impl W<u32, Reg<u32, _CFGR2>>

pub fn prediv(&mut self) -> PREDIV_W<'_>

Bits 0:3 - PREDIV division factor

impl W<u32, Reg<u32, _CFGR3>>

pub fn usart1sw(&mut self) -> USART1SW_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn i2c1sw(&mut self) -> I2C1SW_W<'_>

Bit 4 - I2C1 clock source selection

pub fn i2c2sw(&mut self) -> I2C2SW_W<'_>

Bit 5 - I2C2 clock source selection

pub fn cecsw(&mut self) -> CECSW_W<'_>

Bit 6 - HDMI CEC clock source selection

pub fn usart2sw(&mut self) -> USART2SW_W<'_>

Bits 16:17 - USART2 clock source selection

pub fn usart3sw(&mut self) -> USART3SW_W<'_>

Bits 18:19 - USART3 clock source selection

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>

Bits 10:11 - Internal trigger 1 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn it4_rmp(&mut self) -> IT4_RMP_W<'_>

Bits 6:7 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable deassertion time

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:15 - mantissa of USARTDIV

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of timeout clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn crcl(&mut self) -> CRCL_W<'_>

Bit 11 - CRC length

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _SR>>

pub fn strt(&mut self) -> STRT_W<'_>

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>

pub fn awden(&mut self) -> AWDEN_W<'_>

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>

Bit 23 - Temperature sensor and VREFINT enable

pub fn swstart(&mut self) -> SWSTART_W<'_>

Bit 22 - Start conversion of regular channels

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 21 - Start conversion of injected channels

pub fn exttrig(&mut self) -> EXTTRIG_W<'_>

Bit 20 - External trigger conversion mode for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 17:19 - External event select for regular group

pub fn jexttrig(&mut self) -> JEXTTRIG_W<'_>

Bit 15 - External trigger conversion mode for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 12:14 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 11 - Data alignment

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access mode

pub fn rstcal(&mut self) -> RSTCAL_W<'_>

Bit 3 - Reset calibration

pub fn cal(&mut self) -> CAL_W<'_>

Bit 2 - A/D calibration

pub fn cont(&mut self) -> CONT_W<'_>

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - A/D converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

impl W<u32, Reg<u32, _JOFR>>

pub fn joffset(&mut self) -> JOFFSET_W<'_>

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>

pub fn ht(&mut self) -> HT_W<'_>

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>

pub fn lt(&mut self) -> LT_W<'_>

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>

pub fn l(&mut self) -> L_W<'_>

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>

pub fn jl(&mut self) -> JL_W<'_>

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Interrupt Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Interrupt Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Interrupt Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Interrupt Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Interrupt Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Interrupt Mask on line 28

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Event Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Event Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Event Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Event Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Event Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Event Mask on line 28

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _CR>>

pub fn txeom(&mut self) -> TXEOM_W<'_>

Bit 2 - Tx End Of Message

pub fn txsom(&mut self) -> TXSOM_W<'_>

Bit 1 - Tx start of message

pub fn cecen(&mut self) -> CECEN_W<'_>

Bit 0 - CEC Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn lbpegen(&mut self) -> LBPEGEN_W<'_>

Bit 11 - Generate Error-Bit on Long Bit Period Error

pub fn bregen(&mut self) -> BREGEN_W<'_>

Bit 10 - Generate error-bit on bit rising error

pub fn brestp(&mut self) -> BRESTP_W<'_>

Bit 9 - Rx-stop on bit rising error

pub fn rxtol(&mut self) -> RXTOL_W<'_>

Bit 8 - Rx-Tolerance

pub fn sft(&mut self) -> SFT_W<'_>

Bits 5:7 - Signal Free Time

pub fn lstn(&mut self) -> LSTN_W<'_>

Bit 4 - Listen mode

pub fn oar(&mut self) -> OAR_W<'_>

Bits 0:3 - Own Address

impl W<u32, Reg<u32, _TXDR>>

pub fn txd(&mut self) -> TXD_W<'_>

Bits 0:7 - Tx Data register

impl W<u32, Reg<u32, _ISR>>

pub fn txacke(&mut self) -> TXACKE_W<'_>

Bit 12 - Tx-Missing acknowledge error

pub fn txerr(&mut self) -> TXERR_W<'_>

Bit 11 - Tx-Error

pub fn txudr(&mut self) -> TXUDR_W<'_>

Bit 10 - Tx-Buffer Underrun

pub fn txend(&mut self) -> TXEND_W<'_>

Bit 9 - End of Transmission

pub fn txbr(&mut self) -> TXBR_W<'_>

Bit 8 - Tx-Byte Request

pub fn arblst(&mut self) -> ARBLST_W<'_>

Bit 7 - Arbitration Lost

pub fn rxacke(&mut self) -> RXACKE_W<'_>

Bit 6 - Rx-Missing Acknowledge

pub fn lbpe(&mut self) -> LBPE_W<'_>

Bit 5 - Rx-Long Bit Period Error

pub fn sbpe(&mut self) -> SBPE_W<'_>

Bit 4 - Rx-Short Bit period error

pub fn bre(&mut self) -> BRE_W<'_>

Bit 3 - Rx-Bit rising error

pub fn rxovr(&mut self) -> RXOVR_W<'_>

Bit 2 - Rx-Overrun

pub fn rxend(&mut self) -> RXEND_W<'_>

Bit 1 - End Of Reception

pub fn rxbr(&mut self) -> RXBR_W<'_>

Bit 0 - Rx-Byte Received

impl W<u32, Reg<u32, _IER>>

pub fn txackie(&mut self) -> TXACKIE_W<'_>

Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable

pub fn txerrie(&mut self) -> TXERRIE_W<'_>

Bit 11 - Tx-Error Interrupt Enable

pub fn txudrie(&mut self) -> TXUDRIE_W<'_>

Bit 10 - Tx-Underrun interrupt enable

pub fn txendie(&mut self) -> TXENDIE_W<'_>

Bit 9 - Tx-End of message interrupt enable

pub fn txbrie(&mut self) -> TXBRIE_W<'_>

Bit 8 - Tx-Byte Request Interrupt Enable

pub fn arblstie(&mut self) -> ARBLSTIE_W<'_>

Bit 7 - Arbitration Lost Interrupt Enable

pub fn rxackie(&mut self) -> RXACKIE_W<'_>

Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable

pub fn lbpeie(&mut self) -> LBPEIE_W<'_>

Bit 5 - Long Bit Period Error Interrupt Enable

pub fn sbpeie(&mut self) -> SBPEIE_W<'_>

Bit 4 - Short Bit Period Error Interrupt Enable

pub fn breie(&mut self) -> BREIE_W<'_>

Bit 3 - Bit Rising Error Interrupt Enable

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>

Bit 2 - Rx-Buffer Overrun Interrupt Enable

pub fn rxendie(&mut self) -> RXENDIE_W<'_>

Bit 1 - End Of Reception Interrupt Enable

pub fn rxbrie(&mut self) -> RXBRIE_W<'_>

Bit 0 - Rx-Byte Received Interrupt Enable

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low-power deep sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power down deepsleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear wakeup flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear standby flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power voltage detector enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD level selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn ensd1(&mut self) -> ENSD1_W<'_>

Bit 9 - ENable SD1 ADC

pub fn ensd2(&mut self) -> ENSD2_W<'_>

Bit 10 - ENable SD2 ADC

pub fn ensd3(&mut self) -> ENSD3_W<'_>

Bit 11 - ENable SD3 ADC

impl W<u32, Reg<u32, _CSR>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 8 - Enable WKUP1 pin

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 9 - Enable WKUP2 pin

pub fn ewup3(&mut self) -> EWUP3_W<'_>

Bit 10 - Enable WKUP3 pin

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb0(&mut self) -> FB0_W<'_>

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>

Bit 31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb0(&mut self) -> FB0_W<'_>

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>

Bit 31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bit 0 - Device address

pub fn add1(&mut self) -> ADD1_W<'_>

Bit 1 - Device address

pub fn add2(&mut self) -> ADD2_W<'_>

Bit 2 - Device address

pub fn add3(&mut self) -> ADD3_W<'_>

Bit 3 - Device address

pub fn add4(&mut self) -> ADD4_W<'_>

Bit 4 - Device address

pub fn add5(&mut self) -> ADD5_W<'_>

Bit 5 - Device address

pub fn add6(&mut self) -> ADD6_W<'_>

Bit 6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 13 - Software reset

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit 9:8 (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

pub fn oa1(&mut self) -> OA1_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

impl W<u32, Reg<u32, _ISR>>

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>

Bit 15 - RTC_TAMP3 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAFCR>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn pc13value(&mut self) -> PC13VALUE_W<'_>

Bit 18 - PC13 value

pub fn pc13mode(&mut self) -> PC13MODE_W<'_>

Bit 19 - PC13 mode

pub fn pc14value(&mut self) -> PC14VALUE_W<'_>

Bit 20 - PC14 value

pub fn pc14mode(&mut self) -> PC14MODE_W<'_>

Bit 21 - PC 14 mode

pub fn pc15value(&mut self) -> PC15VALUE_W<'_>

Bit 22 - PC15 value

pub fn pc15mode(&mut self) -> PC15MODE_W<'_>

Bit 23 - PC15 mode

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR1>>

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 0 - End of calibration interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 1 - Injected end of conversion interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 3 - Regular end of conversion interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 4 - Regular data overrun interrupt enable

pub fn refv(&mut self) -> REFV_W<'_>

Bits 8:9 - Reference voltage selection

pub fn slowck(&mut self) -> SLOWCK_W<'_>

Bit 10 - Slow clock mode enable

pub fn sbi(&mut self) -> SBI_W<'_>

Bit 11 - Enter Standby mode when idle

pub fn pdi(&mut self) -> PDI_W<'_>

Bit 12 - Enter power down mode when idle

pub fn jsync(&mut self) -> JSYNC_W<'_>

Bit 14 - Launch a injected conversion synchronously with SDADC1

pub fn rsync(&mut self) -> RSYNC_W<'_>

Bit 15 - Launch regular conversion synchronously with SDADC1

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>

Bit 16 - DMA channel enabled to read data for the injected channel group

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>

Bit 17 - DMA channel enabled to read data for the regular channel

pub fn init(&mut self) -> INIT_W<'_>

Bit 31 - Initialization mode request

impl W<u32, Reg<u32, _CR2>>

pub fn fast(&mut self) -> FAST_W<'_>

Bit 24 - Fast conversion mode selection

pub fn rswstart(&mut self) -> RSWSTART_W<'_>

Bit 23 - Software start of a conversion on the regular channel

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 22 - Continuous mode selection for regular conversions

pub fn rch(&mut self) -> RCH_W<'_>

Bits 16:19 - Regular channel selection

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 15 - Start a conversion of the injected group of channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 8:11 - Trigger signal selection for launching injected conversions

pub fn jds(&mut self) -> JDS_W<'_>

Bit 6 - Delay start of injected conversions.

pub fn jcont(&mut self) -> JCONT_W<'_>

Bit 5 - Continuous mode selection for injected conversions

pub fn startcalib(&mut self) -> STARTCALIB_W<'_>

Bit 4 - Start calibration

pub fn calibcnt(&mut self) -> CALIBCNT_W<'_>

Bits 1:2 - Number of calibration sequences to be performed (number of valid configurations)

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - SDADC enable

impl W<u32, Reg<u32, _CLRISR>>

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>

Bit 4 - Clear the regular conversion overrun flag

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>

Bit 2 - Clear the injected conversion overrun flag

pub fn clreocalf(&mut self) -> CLREOCALF_W<'_>

Bit 0 - Clear the end of calibration flag

impl W<u32, Reg<u32, _JCHGR>>

pub fn jchg(&mut self) -> JCHG_W<'_>

Bits 0:8 - Injected channel group selection

impl W<u32, Reg<u32, _CONF0R>>

pub fn common0(&mut self) -> COMMON0_W<'_>

Bits 30:31 - Common mode for configuration 0

pub fn se0(&mut self) -> SE0_W<'_>

Bits 26:27 - Single-ended mode for configuration 0

pub fn gain0(&mut self) -> GAIN0_W<'_>

Bits 20:22 - Gain setting for configuration 0

pub fn offset0(&mut self) -> OFFSET0_W<'_>

Bits 0:11 - Twelve-bit calibration offset for configuration 0

impl W<u32, Reg<u32, _CONF1R>>

pub fn common1(&mut self) -> COMMON1_W<'_>

Bits 30:31 - Common mode for configuration 1

pub fn se1(&mut self) -> SE1_W<'_>

Bits 26:27 - Single-ended mode for configuration 1

pub fn gain1(&mut self) -> GAIN1_W<'_>

Bits 20:22 - Gain setting for configuration 1

pub fn offset1(&mut self) -> OFFSET1_W<'_>

Bits 0:11 - Twelve-bit calibration offset for configuration 1

impl W<u32, Reg<u32, _CONF2R>>

pub fn common2(&mut self) -> COMMON2_W<'_>

Bits 30:31 - Common mode for configuration 2

pub fn se2(&mut self) -> SE2_W<'_>

Bits 26:27 - Single-ended mode for configuration 2

pub fn gain2(&mut self) -> GAIN2_W<'_>

Bits 20:22 - Gain setting for configuration 2

pub fn offset2(&mut self) -> OFFSET2_W<'_>

Bits 0:11 - Twelve-bit calibration offset for configuration 2

impl W<u32, Reg<u32, _CONFCHR1>>

pub fn confch7(&mut self) -> CONFCH7_W<'_>

Bits 28:29 - CONFCH7

pub fn confch6(&mut self) -> CONFCH6_W<'_>

Bits 24:25 - CONFCH6

pub fn confch5(&mut self) -> CONFCH5_W<'_>

Bits 20:21 - CONFCH5

pub fn confch4(&mut self) -> CONFCH4_W<'_>

Bits 16:17 - CONFCH4

pub fn confch3(&mut self) -> CONFCH3_W<'_>

Bits 12:13 - CONFCH3

pub fn confch2(&mut self) -> CONFCH2_W<'_>

Bits 8:9 - CONFCH2

pub fn confch1(&mut self) -> CONFCH1_W<'_>

Bits 4:5 - CONFCH1

pub fn confch0(&mut self) -> CONFCH0_W<'_>

Bits 0:1 - CONFCH0

impl W<u32, Reg<u32, _CONFCHR2>>

pub fn confch8(&mut self) -> CONFCH8_W<'_>

Bits 0:1 - Channel 8 configuration

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp13(&mut self) -> MAMP13_W<'_>

Bit 11 - DAC channel1 mask/amplitude selector

pub fn mamp12(&mut self) -> MAMP12_W<'_>

Bit 10 - MAMP12

pub fn mamp11(&mut self) -> MAMP11_W<'_>

Bit 9 - MAMP11

pub fn mamp10(&mut self) -> MAMP10_W<'_>

Bit 8 - MAMP10

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bit 7 - DAC channel1 noise/triangle wave generation enable

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bit 6 - WAVE2

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - Debug Sleep mode

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - Trace pin assignment control

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - Trace pin assignment control

impl W<u32, Reg<u32, _APB1_FZ>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - Debug Timer 3 stopped when Core is halted

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - Debug Timer 4 stopped when Core is halted

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - Debug Timer 5 stopped when Core is halted

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - Debug Timer 7 stopped when Core is halted

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>

Bit 6 - Debug Timer 12 stopped when Core is halted

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>

Bit 7 - Debug Timer 13 stopped when Core is halted

pub fn dbg_timer14_stop(&mut self) -> DBG_TIMER14_STOP_W<'_>

Bit 8 - Debug Timer 14 stopped when Core is halted

pub fn dbg_tim18_stop(&mut self) -> DBG_TIM18_STOP_W<'_>

Bit 9 - Debug Timer 18 stopped when Core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn i2c1_smbus_timeout(&mut self) -> I2C1_SMBUS_TIMEOUT_W<'_>

Bit 21 - SMBUS timeout mode stopped when Core is halted

pub fn i2c2_smbus_timeout(&mut self) -> I2C2_SMBUS_TIMEOUT_W<'_>

Bit 22 - SMBUS timeout mode stopped when Core is halted

pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>

Bit 25 - Debug CAN stopped when core is halted

impl W<u32, Reg<u32, _APB2FZ>>

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 2 - Debug Timer 15 stopped when Core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 3 - Debug Timer 16 stopped when Core is halted

pub fn dbg_tim17_sto(&mut self) -> DBG_TIM17_STO_W<'_>

Bit 4 - Debug Timer 17 stopped when Core is halted

pub fn dbg_tim19_stop(&mut self) -> DBG_TIM19_STOP_W<'_>

Bit 5 - Debug Timer 19 stopped when Core is halted

impl W<u32, Reg<u32, _CFGR1>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:1 - Memory mapping selection bits

pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<'_>

Bit 11 - TIM16 DMA request remapping bit

pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<'_>

Bit 12 - TIM17 DMA request remapping bit

pub fn tim6_dac1_out1_dma_rmp(&mut self) -> TIM6_DAC1_OUT1_DMA_RMP_W<'_>

Bit 13 - TIM6 and DAC1 DMA request remapping bit

pub fn tim7_dac1_out2_dma_rmp(&mut self) -> TIM7_DAC1_OUT2_DMA_RMP_W<'_>

Bit 14 - TIM7 and DAC2 DMA request remapping bit

pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>

Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>

Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>

Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>

Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - I2C1 Fast Mode Plus

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - I2C2 Fast Mode Plus

pub fn vbat_mon(&mut self) -> VBAT_MON_W<'_>

Bit 24 - VBAT monitoring enable

pub fn tim18_dac2_out1_dma_rmp(&mut self) -> TIM18_DAC2_OUT1_DMA_RMP_W<'_>

Bit 15 - TIM18 and DAC2_OUT1 DMA request remapping bit

pub fn fpu_ie5(&mut self) -> FPU_IE5_W<'_>

Bit 31 - Inexact interrupt enable

pub fn fpu_ie4(&mut self) -> FPU_IE4_W<'_>

Bit 30 - Input denormal interrupt enable

pub fn fpu_ie3(&mut self) -> FPU_IE3_W<'_>

Bit 29 - Overflow interrupt enable

pub fn fpu_ie2(&mut self) -> FPU_IE2_W<'_>

Bit 28 - Underflow interrupt enable

pub fn fpu_ie1(&mut self) -> FPU_IE1_W<'_>

Bit 27 - Devide-by-zero interrupt enable

pub fn fpu_ie0(&mut self) -> FPU_IE0_W<'_>

Bit 26 - Invalid operation interrupt enable

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI 3 configuration bits

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI 2 configuration bits

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI 1 configuration bits

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI 0 configuration bits

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI 7 configuration bits

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI 6 configuration bits

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI 5 configuration bits

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI 4 configuration bits

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI 11 configuration bits

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI 10 configuration bits

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI 9 configuration bits

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI 8 configuration bits

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI 15 configuration bits

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI 14 configuration bits

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI 13 configuration bits

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI 12 configuration bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0 LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bit 15

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bit 14

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bit 13

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bit 12

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bit 11

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bit 10

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bit 9

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bit 8

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bit 7

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bit 6

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bit 5

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bit 4

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bit 3

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bit 2

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bit 1

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bit 0

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _CSR>>

pub fn comp1en(&mut self) -> COMP1EN_W<'_>

Bit 0 - Comparator 1 enable

pub fn comp1mode(&mut self) -> COMP1MODE_W<'_>

Bits 2:3 - Comparator 1 mode

pub fn comp1insel(&mut self) -> COMP1INSEL_W<'_>

Bits 4:6 - Comparator 1 inverting input selection

pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<'_>

Bits 8:10 - Comparator 1 output selection

pub fn comp1pol(&mut self) -> COMP1POL_W<'_>

Bit 11 - Comparator 1 output polarity

pub fn comp1hyst(&mut self) -> COMP1HYST_W<'_>

Bits 12:13 - Comparator 1 hysteresis

pub fn comp1lock(&mut self) -> COMP1LOCK_W<'_>

Bit 15 - Comparator 1 lock

pub fn comp2en(&mut self) -> COMP2EN_W<'_>

Bit 16 - Comparator 2 enable

pub fn comp2mode(&mut self) -> COMP2MODE_W<'_>

Bits 18:19 - Comparator 2 mode

pub fn comp2insel(&mut self) -> COMP2INSEL_W<'_>

Bits 20:22 - Comparator 2 inverting input selection

pub fn wndwen(&mut self) -> WNDWEN_W<'_>

Bit 23 - Window mode enable

pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<'_>

Bits 24:26 - Comparator 2 output selection

pub fn comp2pol(&mut self) -> COMP2POL_W<'_>

Bit 27 - Comparator 2 output polarity

pub fn comp2hyst(&mut self) -> COMP2HYST_W<'_>

Bits 28:29 - Comparator 2 hysteresis

pub fn comp2lock(&mut self) -> COMP2LOCK_W<'_>

Bit 31 - Comparator 2 lock

pub fn comp1_inp_dac(&mut self) -> COMP1_INP_DAC_W<'_>

Bit 1 - Comparator 1 non inverting input connection to DAC output

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bit 15

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bit 14

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bit 13

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bit 12

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bit 11

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bit 10

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bit 9

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bit 8

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bit 7

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bit 6

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bit 5

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bit 4

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bit 3

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bit 2

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bit 1

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bit 0

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _CR>>

pub fn ctph(&mut self) -> CTPH_W<'_>

Bits 28:31 - Charge transfer pulse high

pub fn ctpl(&mut self) -> CTPL_W<'_>

Bits 24:27 - Charge transfer pulse low

pub fn ssd(&mut self) -> SSD_W<'_>

Bits 17:23 - Spread spectrum deviation

pub fn sse(&mut self) -> SSE_W<'_>

Bit 16 - Spread spectrum enable

pub fn sspsc(&mut self) -> SSPSC_W<'_>

Bit 15 - Spread spectrum prescaler

pub fn pgpsc(&mut self) -> PGPSC_W<'_>

Bits 12:14 - pulse generator prescaler

pub fn mcv(&mut self) -> MCV_W<'_>

Bits 5:7 - Max count value

pub fn iodef(&mut self) -> IODEF_W<'_>

Bit 4 - I/O Default mode

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 3 - Synchronization pin polarity

pub fn am(&mut self) -> AM_W<'_>

Bit 2 - Acquisition mode

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start a new acquisition

pub fn tsce(&mut self) -> TSCE_W<'_>

Bit 0 - Touch sensing controller enable

impl W<u32, Reg<u32, _IER>>

pub fn mceie(&mut self) -> MCEIE_W<'_>

Bit 1 - Max count error interrupt enable

pub fn eoaie(&mut self) -> EOAIE_W<'_>

Bit 0 - End of acquisition interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn mceic(&mut self) -> MCEIC_W<'_>

Bit 1 - Max count error interrupt clear

pub fn eoaic(&mut self) -> EOAIC_W<'_>

Bit 0 - End of acquisition interrupt clear

impl W<u32, Reg<u32, _ISR>>

pub fn mcef(&mut self) -> MCEF_W<'_>

Bit 1 - Max count error flag

pub fn eoaf(&mut self) -> EOAF_W<'_>

Bit 0 - End of acquisition flag

impl W<u32, Reg<u32, _IOHCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 Schmitt trigger hysteresis mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 Schmitt trigger hysteresis mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 Schmitt trigger hysteresis mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 Schmitt trigger hysteresis mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 Schmitt trigger hysteresis mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 Schmitt trigger hysteresis mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 Schmitt trigger hysteresis mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 Schmitt trigger hysteresis mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 Schmitt trigger hysteresis mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 Schmitt trigger hysteresis mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 Schmitt trigger hysteresis mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 Schmitt trigger hysteresis mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 Schmitt trigger hysteresis mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 Schmitt trigger hysteresis mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 Schmitt trigger hysteresis mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 Schmitt trigger hysteresis mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 Schmitt trigger hysteresis mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 Schmitt trigger hysteresis mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 Schmitt trigger hysteresis mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 Schmitt trigger hysteresis mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 Schmitt trigger hysteresis mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 Schmitt trigger hysteresis mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 Schmitt trigger hysteresis mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 Schmitt trigger hysteresis mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 Schmitt trigger hysteresis mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 Schmitt trigger hysteresis mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 Schmitt trigger hysteresis mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 Schmitt trigger hysteresis mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 Schmitt trigger hysteresis mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 Schmitt trigger hysteresis mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 Schmitt trigger hysteresis mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 Schmitt trigger hysteresis mode

impl W<u32, Reg<u32, _IOASCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 analog switch enable

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 analog switch enable

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 analog switch enable

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 analog switch enable

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 analog switch enable

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 analog switch enable

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 analog switch enable

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 analog switch enable

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 analog switch enable

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 analog switch enable

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 analog switch enable

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 analog switch enable

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 analog switch enable

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 analog switch enable

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 analog switch enable

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 analog switch enable

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 analog switch enable

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 analog switch enable

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 analog switch enable

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 analog switch enable

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 analog switch enable

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 analog switch enable

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 analog switch enable

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 analog switch enable

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 analog switch enable

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 analog switch enable

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 analog switch enable

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 analog switch enable

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 analog switch enable

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 analog switch enable

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 analog switch enable

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 analog switch enable

impl W<u32, Reg<u32, _IOSCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 sampling mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 sampling mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 sampling mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 sampling mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 sampling mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 sampling mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 sampling mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 sampling mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 sampling mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 sampling mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 sampling mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 sampling mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 sampling mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 sampling mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 sampling mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 sampling mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 sampling mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 sampling mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 sampling mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 sampling mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 sampling mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 sampling mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 sampling mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 sampling mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 sampling mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 sampling mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 sampling mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 sampling mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 sampling mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 sampling mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 sampling mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 sampling mode

impl W<u32, Reg<u32, _IOCCR>>

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1 channel mode

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2 channel mode

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3 channel mode

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4 channel mode

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1 channel mode

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2 channel mode

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3 channel mode

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4 channel mode

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1 channel mode

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2 channel mode

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3 channel mode

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4 channel mode

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1 channel mode

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2 channel mode

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3 channel mode

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4 channel mode

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1 channel mode

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2 channel mode

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3 channel mode

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4 channel mode

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1 channel mode

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2 channel mode

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3 channel mode

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4 channel mode

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1 channel mode

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2 channel mode

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3 channel mode

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4 channel mode

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1 channel mode

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2 channel mode

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3 channel mode

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4 channel mode

impl W<u32, Reg<u32, _IOGCSR>>

pub fn g8s(&mut self) -> G8S_W<'_>

Bit 23 - Analog I/O group x status

pub fn g7s(&mut self) -> G7S_W<'_>

Bit 22 - Analog I/O group x status

pub fn g8e(&mut self) -> G8E_W<'_>

Bit 7 - Analog I/O group x enable

pub fn g7e(&mut self) -> G7E_W<'_>

Bit 6 - Analog I/O group x enable

pub fn g6e(&mut self) -> G6E_W<'_>

Bit 5 - Analog I/O group x enable

pub fn g5e(&mut self) -> G5E_W<'_>

Bit 4 - Analog I/O group x enable

pub fn g4e(&mut self) -> G4E_W<'_>

Bit 3 - Analog I/O group x enable

pub fn g3e(&mut self) -> G3E_W<'_>

Bit 2 - Analog I/O group x enable

pub fn g2e(&mut self) -> G2E_W<'_>

Bit 1 - Analog I/O group x enable

pub fn g1e(&mut self) -> G1E_W<'_>

Bit 0 - Analog I/O group x enable

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - General-purpose 8-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - reset bit

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

impl W<u32, Reg<u32, _INIT>>

pub fn init(&mut self) -> INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u8, Reg<u8, _DR8>>

pub fn dr8(&mut self) -> DR8_W<'_>

Bits 0:7 - Data register bits

impl W<u16, Reg<u16, _DR16>>

pub fn dr16(&mut self) -> DR16_W<'_>

Bits 0:15 - Data register bits

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - LATENCY

pub fn prftbe(&mut self) -> PRFTBE_W<'_>

Bit 4 - PRFTBE

pub fn hlfcya(&mut self) -> HLFCYA_W<'_>

Bit 3 - Flash half cycle access enable

impl W<u32, Reg<u32, _KEYR>>

pub fn fkeyr(&mut self) -> FKEYR_W<'_>

Bits 0:31 - Flash Key

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 5 - End of operation

pub fn wrprterr(&mut self) -> WRPRTERR_W<'_>

Bit 4 - Write protection error

pub fn pgerr(&mut self) -> PGERR_W<'_>

Bit 2 - Programming error

impl W<u32, Reg<u32, _CR>>

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 13 - Force option byte loading

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 12 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn optwre(&mut self) -> OPTWRE_W<'_>

Bit 9 - Option bytes write enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 7 - Lock

pub fn strt(&mut self) -> STRT_W<'_>

Bit 6 - Start

pub fn opter(&mut self) -> OPTER_W<'_>

Bit 5 - Option byte erase

pub fn optpg(&mut self) -> OPTPG_W<'_>

Bit 4 - Option byte programming

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Mass erase

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

impl W<u32, Reg<u32, _AR>>

pub fn far(&mut self) -> FAR_W<'_>

Bits 0:31 - Flash address

impl W<u32, Reg<u32, _CR>>

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 0 - Internal High Speed clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 3:7 - Internal High Speed clock trimming

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - External High Speed clock enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - External High Speed clock Bypass

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock Security System enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - PLL enable

impl W<u32, Reg<u32, _CFGR>>

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock Switch

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB high speed prescaler (APB2)

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 15:16 - PLL entry clock source

pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>

Bit 17 - HSE divider for PLL entry

pub fn pllmul(&mut self) -> PLLMUL_W<'_>

Bits 18:21 - PLL Multiplication Factor

pub fn usbpre(&mut self) -> USBPRE_W<'_>

Bit 22 - USB prescaler

pub fn mco(&mut self) -> MCO_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn i2ssrc(&mut self) -> I2SSRC_W<'_>

Bit 23 - I2S external clock source selection

pub fn mcopre(&mut self) -> MCOPRE_W<'_>

Bits 28:30 - Microcontroller Clock Output Prescaler

pub fn pllnodiv(&mut self) -> PLLNODIV_W<'_>

Bit 31 - Do not divide PLL to MCO

impl W<u32, Reg<u32, _CIR>>

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 8 - LSI Ready Interrupt Enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 9 - LSE Ready Interrupt Enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 10 - HSI Ready Interrupt Enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 11 - HSE Ready Interrupt Enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 12 - PLL Ready Interrupt Enable

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 16 - LSI Ready Interrupt Clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 17 - LSE Ready Interrupt Clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 18 - HSI Ready Interrupt Clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 19 - HSE Ready Interrupt Clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 20 - PLL Ready Interrupt Clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 23 - Clock security system interrupt clear

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - SYSCFG and COMP reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI 1 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>

Bit 13 - TIM8 timer reset

pub fn spi4rst(&mut self) -> SPI4RST_W<'_>

Bit 15 - SPI4 reset

pub fn tim20rst(&mut self) -> TIM20RST_W<'_>

Bit 20 - TIM20 timer reset

impl W<u32, Reg<u32, _APB1RSTR>>

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - Timer 2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - Timer 3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - Timer 14 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - Timer 6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - Timer 7 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART 2 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 23 - USB reset

pub fn canrst(&mut self) -> CANRST_W<'_>

Bit 25 - CAN reset

pub fn dac2rst(&mut self) -> DAC2RST_W<'_>

Bit 26 - DAC3 reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn dac1rst(&mut self) -> DAC1RST_W<'_>

Bit 29 - DAC interface reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - UART4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - UART5 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 30 - I2C3 reset

impl W<u32, Reg<u32, _AHBENR>>

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn sramen(&mut self) -> SRAMEN_W<'_>

Bit 2 - SRAM interface clock enable

pub fn flitfen(&mut self) -> FLITFEN_W<'_>

Bit 4 - FLITF clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 6 - CRC clock enable

pub fn iopaen(&mut self) -> IOPAEN_W<'_>

Bit 17 - I/O port A clock enable

pub fn iopben(&mut self) -> IOPBEN_W<'_>

Bit 18 - I/O port B clock enable

pub fn iopcen(&mut self) -> IOPCEN_W<'_>

Bit 19 - I/O port C clock enable

pub fn iopden(&mut self) -> IOPDEN_W<'_>

Bit 20 - I/O port D clock enable

pub fn iopeen(&mut self) -> IOPEEN_W<'_>

Bit 21 - I/O port E clock enable

pub fn iopfen(&mut self) -> IOPFEN_W<'_>

Bit 22 - I/O port F clock enable

pub fn tscen(&mut self) -> TSCEN_W<'_>

Bit 24 - Touch sensing controller clock enable

pub fn iophen(&mut self) -> IOPHEN_W<'_>

Bit 16 - I/O port H clock enable

pub fn iopgen(&mut self) -> IOPGEN_W<'_>

Bit 23 - I/O port G clock enable

pub fn adc12en(&mut self) -> ADC12EN_W<'_>

Bit 28 - ADC1 and ADC2 enable

pub fn adc34en(&mut self) -> ADC34EN_W<'_>

Bit 29 - ADC3 and ADC4 enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 Timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI 1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1 clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM17 timer clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>

Bit 13 - TIM8 timer clock enable

pub fn spi4en(&mut self) -> SPI4EN_W<'_>

Bit 15 - SPI4 clock enable

pub fn tim20en(&mut self) -> TIM20EN_W<'_>

Bit 20 - TIM20 timer clock enable

impl W<u32, Reg<u32, _APB1ENR>>

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - Timer 2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - Timer 3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - Timer 4 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - Timer 6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - Timer 7 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI 2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI 3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART 3 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C 1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C 2 clock enable

pub fn usben(&mut self) -> USBEN_W<'_>

Bit 23 - USB clock enable

pub fn canen(&mut self) -> CANEN_W<'_>

Bit 25 - CAN clock enable

pub fn dac2en(&mut self) -> DAC2EN_W<'_>

Bit 26 - DAC3 interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn dac1en(&mut self) -> DAC1EN_W<'_>

Bit 29 - DAC interface clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART5 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 30 - I2C3 clock enable

impl W<u32, Reg<u32, _BDCR>>

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - External Low Speed oscillator enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - External Low Speed oscillator bypass

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - LSE oscillator drive capability

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

impl W<u32, Reg<u32, _CSR>>

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - Internal low speed oscillator enable

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 24 - Remove reset flag

pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>

Bit 25 - Option byte loader reset flag

pub fn pinrstf(&mut self) -> PINRSTF_W<'_>

Bit 26 - PIN reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>

Bit 27 - POR/PDR reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>

Bit 28 - Software reset flag

pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>

Bit 29 - Independent watchdog reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>

Bit 30 - Window watchdog reset flag

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>

Bit 31 - Low-power reset flag

pub fn v18pwrrstf(&mut self) -> V18PWRRSTF_W<'_>

Bit 23 - Reset flag of the 1.8 V domain

impl W<u32, Reg<u32, _AHBRSTR>>

pub fn ioparst(&mut self) -> IOPARST_W<'_>

Bit 17 - I/O port A reset

pub fn iopbrst(&mut self) -> IOPBRST_W<'_>

Bit 18 - I/O port B reset

pub fn iopcrst(&mut self) -> IOPCRST_W<'_>

Bit 19 - I/O port C reset

pub fn iopdrst(&mut self) -> IOPDRST_W<'_>

Bit 20 - I/O port D reset

pub fn ioperst(&mut self) -> IOPERST_W<'_>

Bit 21 - I/O port E reset

pub fn iopfrst(&mut self) -> IOPFRST_W<'_>

Bit 22 - I/O port F reset

pub fn tscrst(&mut self) -> TSCRST_W<'_>

Bit 24 - Touch sensing controller reset

pub fn iophrst(&mut self) -> IOPHRST_W<'_>

Bit 16 - I/O port H reset

pub fn iopgrst(&mut self) -> IOPGRST_W<'_>

Bit 23 - I/O port G reset

pub fn adc12rst(&mut self) -> ADC12RST_W<'_>

Bit 28 - ADC1 and ADC2 reset

pub fn adc34rst(&mut self) -> ADC34RST_W<'_>

Bit 29 - ADC3 and ADC4 reset

impl W<u32, Reg<u32, _CFGR2>>

pub fn prediv(&mut self) -> PREDIV_W<'_>

Bits 0:3 - PREDIV division factor

pub fn adc12pres(&mut self) -> ADC12PRES_W<'_>

Bits 4:8 - ADC1 and ADC2 reset

pub fn adc34pres(&mut self) -> ADC34PRES_W<'_>

Bits 9:13 - ADC3 and ADC4 reset

impl W<u32, Reg<u32, _CFGR3>>

pub fn usart1sw(&mut self) -> USART1SW_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn i2c1sw(&mut self) -> I2C1SW_W<'_>

Bit 4 - I2C1 clock source selection

pub fn i2c2sw(&mut self) -> I2C2SW_W<'_>

Bit 5 - I2C2 clock source selection

pub fn usart2sw(&mut self) -> USART2SW_W<'_>

Bits 16:17 - USART2 clock source selection

pub fn usart3sw(&mut self) -> USART3SW_W<'_>

Bits 18:19 - USART3 clock source selection

pub fn tim1sw(&mut self) -> TIM1SW_W<'_>

Bit 8 - Timer1 clock source selection

pub fn tim8sw(&mut self) -> TIM8SW_W<'_>

Bit 9 - Timer8 clock source selection

pub fn uart4sw(&mut self) -> UART4SW_W<'_>

Bits 20:21 - UART4 clock source selection

pub fn uart5sw(&mut self) -> UART5SW_W<'_>

Bits 22:23 - UART5 clock source selection

pub fn i2c3sw(&mut self) -> I2C3SW_W<'_>

Bit 6 - I2C3 clock source selection

pub fn tim20sw(&mut self) -> TIM20SW_W<'_>

Bit 15 - Timer20 clock source selection

pub fn tim15sw(&mut self) -> TIM15SW_W<'_>

Bit 10 - Timer15 clock source selection

pub fn tim16sw(&mut self) -> TIM16SW_W<'_>

Bit 11 - Timer16 clock source selection

pub fn tim17sw(&mut self) -> TIM17SW_W<'_>

Bit 13 - Timer17 clock source selection

pub fn tim2sw(&mut self) -> TIM2SW_W<'_>

Bit 24 - Timer2 clock source selection

pub fn tim34sw(&mut self) -> TIM34SW_W<'_>

Bit 25 - Timer34 clock source selection

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half Transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel Priority level

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

impl W<u32, Reg<u32, _NDTR>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _PAR>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _MAR>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel 1 Global interrupt clear

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel 1 Transfer Complete clear

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel 1 Half Transfer clear

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel 1 Transfer Error clear

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel 2 Global interrupt clear

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel 2 Transfer Complete clear

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel 2 Half Transfer clear

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel 2 Transfer Error clear

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel 3 Global interrupt clear

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel 3 Transfer Complete clear

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel 3 Half Transfer clear

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel 3 Transfer Error clear

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel 4 Global interrupt clear

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel 4 Transfer Complete clear

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel 4 Half Transfer clear

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel 4 Transfer Error clear

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel 5 Global interrupt clear

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel 5 Transfer Complete clear

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel 5 Half Transfer clear

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel 5 Transfer Error clear

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel 6 Global interrupt clear

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel 6 Transfer Complete clear

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel 6 Half Transfer clear

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel 6 Transfer Error clear

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel 7 Global interrupt clear

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel 7 Transfer Complete clear

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel 7 Half Transfer clear

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel 7 Transfer Error clear

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>

Bits 10:11 - Internal trigger 1 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn it4_rmp(&mut self) -> IT4_RMP_W<'_>

Bits 6:7 - Timer Input 4 remap

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 3 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable deassertion time

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m(&mut self) -> M_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:15 - mantissa of USARTDIV

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of timeout clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn crcl(&mut self) -> CRCL_W<'_>

Bit 11 - CRC length

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>

pub fn i2smod(&mut self) -> I2SMOD_W<'_>

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>

Bit 0 - Channel length (number of bits per audio channel)

impl W<u32, Reg<u32, _I2SPR>>

pub fn mckoe(&mut self) -> MCKOE_W<'_>

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _IMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Interrupt Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Interrupt Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Interrupt Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Interrupt Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Interrupt Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Interrupt Mask on line 28

impl W<u32, Reg<u32, _EMR>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Event Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Event Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Event Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Event Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Event Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Event Mask on line 28

impl W<u32, Reg<u32, _RTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Rising trigger event configuration of line 17

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

impl W<u32, Reg<u32, _FTSR>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>

Bit 17 - Falling trigger event configuration of line 17

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

impl W<u32, Reg<u32, _SWIER>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>

Bit 17 - Software Interrupt on line 17

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

impl W<u32, Reg<u32, _PR>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>

Bit 17 - Pending bit 17

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

impl W<u32, Reg<u32, _CR>>

pub fn lpds(&mut self) -> LPDS_W<'_>

Bit 0 - Low-power deep sleep

pub fn pdds(&mut self) -> PDDS_W<'_>

Bit 1 - Power down deepsleep

pub fn cwuf(&mut self) -> CWUF_W<'_>

Bit 2 - Clear wakeup flag

pub fn csbf(&mut self) -> CSBF_W<'_>

Bit 3 - Clear standby flag

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 4 - Power voltage detector enable

pub fn pls(&mut self) -> PLS_W<'_>

Bits 5:7 - PVD level selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn ensd1(&mut self) -> ENSD1_W<'_>

Bit 9 - ENable SD1 ADC

pub fn ensd2(&mut self) -> ENSD2_W<'_>

Bit 10 - ENable SD2 ADC

pub fn ensd3(&mut self) -> ENSD3_W<'_>

Bit 11 - ENable SD3 ADC

impl W<u32, Reg<u32, _CSR>>

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 8 - Enable WKUP1 pin

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 9 - Enable WKUP2 pin

pub fn ewup3(&mut self) -> EWUP3_W<'_>

Bit 10 - Enable WKUP3 pin

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb0(&mut self) -> FB0_W<'_>

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>

Bit 31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb0(&mut self) -> FB0_W<'_>

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>

Bit 31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn can2sb(&mut self) -> CAN2SB_W<'_>

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>

Bit 27 - Filter active

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bit 0 - Device address

pub fn add1(&mut self) -> ADD1_W<'_>

Bit 1 - Device address

pub fn add2(&mut self) -> ADD2_W<'_>

Bit 2 - Device address

pub fn add3(&mut self) -> ADD3_W<'_>

Bit 3 - Device address

pub fn add4(&mut self) -> ADD4_W<'_>

Bit 4 - Device address

pub fn add5(&mut self) -> ADD5_W<'_>

Bit 5 - Device address

pub fn add6(&mut self) -> ADD6_W<'_>

Bit 6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 13 - Software reset

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit 9:8 (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

pub fn oa1(&mut self) -> OA1_W<'_>

Bits 0:9 - Interface address

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

impl W<u32, Reg<u32, _ISR>>

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>

Bit 15 - RTC_TAMP3 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAFCR>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn pc13value(&mut self) -> PC13VALUE_W<'_>

Bit 18 - PC13 value

pub fn pc13mode(&mut self) -> PC13MODE_W<'_>

Bit 19 - PC13 mode

pub fn pc14value(&mut self) -> PC14VALUE_W<'_>

Bit 20 - PC14 value

pub fn pc14mode(&mut self) -> PC14MODE_W<'_>

Bit 21 - PC 14 mode

pub fn pc15value(&mut self) -> PC15VALUE_W<'_>

Bit 22 - PC15 value

pub fn pc15mode(&mut self) -> PC15MODE_W<'_>

Bit 23 - PC15 mode

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR1>>

pub fn eocalie(&mut self) -> EOCALIE_W<'_>

Bit 0 - End of calibration interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 1 - Injected end of conversion interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 3 - Regular end of conversion interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 4 - Regular data overrun interrupt enable

pub fn refv(&mut self) -> REFV_W<'_>

Bits 8:9 - Reference voltage selection

pub fn slowck(&mut self) -> SLOWCK_W<'_>

Bit 10 - Slow clock mode enable

pub fn sbi(&mut self) -> SBI_W<'_>

Bit 11 - Enter Standby mode when idle

pub fn pdi(&mut self) -> PDI_W<'_>

Bit 12 - Enter power down mode when idle

pub fn jsync(&mut self) -> JSYNC_W<'_>

Bit 14 - Launch a injected conversion synchronously with SDADC1

pub fn rsync(&mut self) -> RSYNC_W<'_>

Bit 15 - Launch regular conversion synchronously with SDADC1

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>

Bit 16 - DMA channel enabled to read data for the injected channel group

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>

Bit 17 - DMA channel enabled to read data for the regular channel

pub fn init(&mut self) -> INIT_W<'_>

Bit 31 - Initialization mode request

impl W<u32, Reg<u32, _CR2>>

pub fn fast(&mut self) -> FAST_W<'_>

Bit 24 - Fast conversion mode selection

pub fn rswstart(&mut self) -> RSWSTART_W<'_>

Bit 23 - Software start of a conversion on the regular channel

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 22 - Continuous mode selection for regular conversions

pub fn rch(&mut self) -> RCH_W<'_>

Bits 16:19 - Regular channel selection

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 15 - Start a conversion of the injected group of channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 8:11 - Trigger signal selection for launching injected conversions

pub fn jds(&mut self) -> JDS_W<'_>

Bit 6 - Delay start of injected conversions.

pub fn jcont(&mut self) -> JCONT_W<'_>

Bit 5 - Continuous mode selection for injected conversions

pub fn startcalib(&mut self) -> STARTCALIB_W<'_>

Bit 4 - Start calibration

pub fn calibcnt(&mut self) -> CALIBCNT_W<'_>

Bits 1:2 - Number of calibration sequences to be performed (number of valid configurations)

pub fn adon(&mut self) -> ADON_W<'_>

Bit 0 - SDADC enable

impl W<u32, Reg<u32, _CLRISR>>

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>

Bit 4 - Clear the regular conversion overrun flag

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>

Bit 2 - Clear the injected conversion overrun flag

pub fn clreocalf(&mut self) -> CLREOCALF_W<'_>

Bit 0 - Clear the end of calibration flag

impl W<u32, Reg<u32, _JCHGR>>

pub fn jchg(&mut self) -> JCHG_W<'_>

Bits 0:8 - Injected channel group selection

impl W<u32, Reg<u32, _CONF0R>>

pub fn common0(&mut self) -> COMMON0_W<'_>

Bits 30:31 - Common mode for configuration 0

pub fn se0(&mut self) -> SE0_W<'_>

Bits 26:27 - Single-ended mode for configuration 0

pub fn gain0(&mut self) -> GAIN0_W<'_>

Bits 20:22 - Gain setting for configuration 0

pub fn offset0(&mut self) -> OFFSET0_W<'_>

Bits 0:11 - Twelve-bit calibration offset for configuration 0

impl W<u32, Reg<u32, _CONF1R>>

pub fn common1(&mut self) -> COMMON1_W<'_>

Bits 30:31 - Common mode for configuration 1

pub fn se1(&mut self) -> SE1_W<'_>

Bits 26:27 - Single-ended mode for configuration 1

pub fn gain1(&mut self) -> GAIN1_W<'_>

Bits 20:22 - Gain setting for configuration 1

pub fn offset1(&mut self) -> OFFSET1_W<'_>

Bits 0:11 - Twelve-bit calibration offset for configuration 1

impl W<u32, Reg<u32, _CONF2R>>

pub fn common2(&mut self) -> COMMON2_W<'_>

Bits 30:31 - Common mode for configuration 2

pub fn se2(&mut self) -> SE2_W<'_>

Bits 26:27 - Single-ended mode for configuration 2

pub fn gain2(&mut self) -> GAIN2_W<'_>

Bits 20:22 - Gain setting for configuration 2

pub fn offset2(&mut self) -> OFFSET2_W<'_>

Bits 0:11 - Twelve-bit calibration offset for configuration 2

impl W<u32, Reg<u32, _CONFCHR1>>

pub fn confch7(&mut self) -> CONFCH7_W<'_>

Bits 28:29 - CONFCH7

pub fn confch6(&mut self) -> CONFCH6_W<'_>

Bits 24:25 - CONFCH6

pub fn confch5(&mut self) -> CONFCH5_W<'_>

Bits 20:21 - CONFCH5

pub fn confch4(&mut self) -> CONFCH4_W<'_>

Bits 16:17 - CONFCH4

pub fn confch3(&mut self) -> CONFCH3_W<'_>

Bits 12:13 - CONFCH3

pub fn confch2(&mut self) -> CONFCH2_W<'_>

Bits 8:9 - CONFCH2

pub fn confch1(&mut self) -> CONFCH1_W<'_>

Bits 4:5 - CONFCH1

pub fn confch0(&mut self) -> CONFCH0_W<'_>

Bits 0:1 - CONFCH0

impl W<u32, Reg<u32, _CONFCHR2>>

pub fn confch8(&mut self) -> CONFCH8_W<'_>

Bits 0:1 - Channel 8 configuration

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp13(&mut self) -> MAMP13_W<'_>

Bit 11 - DAC channel1 mask/amplitude selector

pub fn mamp12(&mut self) -> MAMP12_W<'_>

Bit 10 - MAMP12

pub fn mamp11(&mut self) -> MAMP11_W<'_>

Bit 9 - MAMP11

pub fn mamp10(&mut self) -> MAMP10_W<'_>

Bit 8 - MAMP10

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bit 7 - DAC channel1 noise/triangle wave generation enable

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bit 6 - WAVE2

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _SMCR>>

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR>>

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - Debug Sleep mode

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - Trace pin assignment control

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - Trace pin assignment control

impl W<u32, Reg<u32, _APB1_FZ>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - Debug Timer 3 stopped when Core is halted

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - Debug Timer 4 stopped when Core is halted

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - Debug Timer 5 stopped when Core is halted

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - Debug Timer 7 stopped when Core is halted

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>

Bit 6 - Debug Timer 12 stopped when Core is halted

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>

Bit 7 - Debug Timer 13 stopped when Core is halted

pub fn dbg_timer14_stop(&mut self) -> DBG_TIMER14_STOP_W<'_>

Bit 8 - Debug Timer 14 stopped when Core is halted

pub fn dbg_tim18_stop(&mut self) -> DBG_TIM18_STOP_W<'_>

Bit 9 - Debug Timer 18 stopped when Core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn i2c1_smbus_timeout(&mut self) -> I2C1_SMBUS_TIMEOUT_W<'_>

Bit 21 - SMBUS timeout mode stopped when Core is halted

pub fn i2c2_smbus_timeout(&mut self) -> I2C2_SMBUS_TIMEOUT_W<'_>

Bit 22 - SMBUS timeout mode stopped when Core is halted

pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>

Bit 25 - Debug CAN stopped when core is halted

impl W<u32, Reg<u32, _APB2FZ>>

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 2 - Debug Timer 15 stopped when Core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 3 - Debug Timer 16 stopped when Core is halted

pub fn dbg_tim17_sto(&mut self) -> DBG_TIM17_STO_W<'_>

Bit 4 - Debug Timer 17 stopped when Core is halted

pub fn dbg_tim19_stop(&mut self) -> DBG_TIM19_STOP_W<'_>

Bit 5 - Debug Timer 19 stopped when Core is halted

impl W<u32, Reg<u32, _BCR1>>

pub fn cclken(&mut self) -> CCLKEN_W<'_>

Bit 20 - CCLKEN

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR1>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR2>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR2>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR3>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR3>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR4>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

impl W<u32, Reg<u32, _BTR4>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _PCR2>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR2>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM2>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT2>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PCR3>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR3>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM3>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT3>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PCR4>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR4>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM4>>

pub fn memhizx(&mut self) -> MEMHIZX_W<'_>

Bits 24:31 - MEMHIZx

pub fn memholdx(&mut self) -> MEMHOLDX_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwaitx(&mut self) -> MEMWAITX_W<'_>

Bits 8:15 - MEMWAITx

pub fn memsetx(&mut self) -> MEMSETX_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT4>>

pub fn atthizx(&mut self) -> ATTHIZX_W<'_>

Bits 24:31 - ATTHIZx

pub fn attholdx(&mut self) -> ATTHOLDX_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwaitx(&mut self) -> ATTWAITX_W<'_>

Bits 8:15 - ATTWAITx

pub fn attsetx(&mut self) -> ATTSETX_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _PIO4>>

pub fn iohizx(&mut self) -> IOHIZX_W<'_>

Bits 24:31 - IOHIZx

pub fn ioholdx(&mut self) -> IOHOLDX_W<'_>

Bits 16:23 - IOHOLDx

pub fn iowaitx(&mut self) -> IOWAITX_W<'_>

Bits 8:15 - IOWAITx

pub fn iosetx(&mut self) -> IOSETX_W<'_>

Bits 0:7 - IOSETx

impl W<u32, Reg<u32, _BWTR1>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR2>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR3>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BWTR4>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms3(&mut self) -> SMS3_W<'_>

Bit 16 - Slave mode selection bit 3

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn c5if(&mut self) -> C5IF_W<'_>

Bit 16 - Capture/Compare 5 interrupt flag

pub fn c6if(&mut self) -> C6IF_W<'_>

Bit 17 - Capture/Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output Polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output Polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc5m_3(&mut self) -> OC5M_3_W<'_>

Bit 16 - Outout Compare 5 mode bit 3

pub fn oc6m_3(&mut self) -> OC6M_3_W<'_>

Bit 24 - Outout Compare 6 mode bit 3

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 5 value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 6 value

impl W<u32, Reg<u32, _OR>>

pub fn tim1_etr_adc1_rmp(&mut self) -> TIM1_ETR_ADC1_RMP_W<'_>

Bits 0:1 - TIM1_ETR_ADC1 remapping capability

pub fn tim1_etr_adc4_rmp(&mut self) -> TIM1_ETR_ADC4_RMP_W<'_>

Bits 2:3 - TIM1_ETR_ADC4 remapping capability

impl W<u32, Reg<u32, _CFGR1>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:2 - Memory mapping selection bits

pub fn usb_it_rmp(&mut self) -> USB_IT_RMP_W<'_>

Bit 5 - USB interrupt remap

pub fn tim1_itr3_rmp(&mut self) -> TIM1_ITR3_RMP_W<'_>

Bit 6 - Timer 1 ITR3 selection

pub fn dac1_trig_rmp(&mut self) -> DAC1_TRIG_RMP_W<'_>

Bit 7 - DAC trigger remap (when TSEL = 001)

pub fn adc2_dma_rmp(&mut self) -> ADC2_DMA_RMP_W<'_>

Bit 8 - ADC24 DMA remapping bit

pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<'_>

Bit 11 - TIM16 DMA request remapping bit

pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<'_>

Bit 12 - TIM17 DMA request remapping bit

pub fn tim6_dac1_ch1_dma_rmp(&mut self) -> TIM6_DAC1_CH1_DMA_RMP_W<'_>

Bit 13 - TIM6 and DAC1 DMA request remapping bit

pub fn tim7_dac1_ch2_dma_rmp(&mut self) -> TIM7_DAC1_CH2_DMA_RMP_W<'_>

Bit 14 - TIM7 and DAC2 DMA request remapping bit

pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>

Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>

Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>

Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>

Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - I2C1 Fast Mode Plus

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - I2C2 Fast Mode Plus

pub fn encoder_mode(&mut self) -> ENCODER_MODE_W<'_>

Bits 22:23 - Encoder mode

pub fn fpu_ie5(&mut self) -> FPU_IE5_W<'_>

Bit 31 - Inexact interrupt enable

pub fn fpu_ie4(&mut self) -> FPU_IE4_W<'_>

Bit 30 - Input denormal interrupt enable

pub fn fpu_ie3(&mut self) -> FPU_IE3_W<'_>

Bit 29 - Overflow interrupt enable

pub fn fpu_ie2(&mut self) -> FPU_IE2_W<'_>

Bit 28 - Underflow interrupt enable

pub fn fpu_ie1(&mut self) -> FPU_IE1_W<'_>

Bit 27 - Devide-by-zero interrupt enable

pub fn fpu_ie0(&mut self) -> FPU_IE0_W<'_>

Bit 26 - Invalid operation interrupt enable

pub fn dac2_ch1_dma_rmp(&mut self) -> DAC2_CH1_DMA_RMP_W<'_>

Bit 15 - DAC2 channel1 DMA remap

pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<'_>

Bit 24 - I2C3 Fast Mode Plus

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:15 - EXTI 3 configuration bits

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:11 - EXTI 2 configuration bits

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:7 - EXTI 1 configuration bits

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:3 - EXTI 0 configuration bits

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:15 - EXTI 7 configuration bits

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:11 - EXTI 6 configuration bits

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:7 - EXTI 5 configuration bits

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:3 - EXTI 4 configuration bits

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:15 - EXTI 11 configuration bits

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:11 - EXTI 10 configuration bits

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:7 - EXTI 9 configuration bits

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:3 - EXTI 8 configuration bits

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:15 - EXTI 15 configuration bits

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:11 - EXTI 14 configuration bits

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:7 - EXTI 13 configuration bits

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:3 - EXTI 12 configuration bits

impl W<u32, Reg<u32, _CFGR2>>

pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>

Bit 0 - Cortex-M0 LOCKUP bit enable bit

pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>

Bit 1 - SRAM parity lock bit

pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>

Bit 2 - PVD lock enable bit

pub fn byp_addr_par(&mut self) -> BYP_ADDR_PAR_W<'_>

Bit 4 - Bypass address bit 29 in parity calculation

pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>

Bit 8 - SRAM parity flag

impl W<u32, Reg<u32, _RCR>>

pub fn page0_wp(&mut self) -> PAGE0_WP_W<'_>

Bit 0 - CCM SRAM page write protection bit

pub fn page1_wp(&mut self) -> PAGE1_WP_W<'_>

Bit 1 - CCM SRAM page write protection bit

pub fn page2_wp(&mut self) -> PAGE2_WP_W<'_>

Bit 2 - CCM SRAM page write protection bit

pub fn page3_wp(&mut self) -> PAGE3_WP_W<'_>

Bit 3 - CCM SRAM page write protection bit

pub fn page4_wp(&mut self) -> PAGE4_WP_W<'_>

Bit 4 - CCM SRAM page write protection bit

pub fn page5_wp(&mut self) -> PAGE5_WP_W<'_>

Bit 5 - CCM SRAM page write protection bit

pub fn page6_wp(&mut self) -> PAGE6_WP_W<'_>

Bit 6 - CCM SRAM page write protection bit

pub fn page7_wp(&mut self) -> PAGE7_WP_W<'_>

Bit 7 - CCM SRAM page write protection bit

pub fn page8_wp(&mut self) -> PAGE8_WP_W<'_>

Bit 8 - CCM SRAM page write protection bit

pub fn page9_wp(&mut self) -> PAGE9_WP_W<'_>

Bit 9 - CCM SRAM page write protection bit

pub fn page10_wp(&mut self) -> PAGE10_WP_W<'_>

Bit 10 - CCM SRAM page write protection bit

pub fn page11_wp(&mut self) -> PAGE11_WP_W<'_>

Bit 11 - CCM SRAM page write protection bit

pub fn page12_wp(&mut self) -> PAGE12_WP_W<'_>

Bit 12 - CCM SRAM page write protection bit

pub fn page13_wp(&mut self) -> PAGE13_WP_W<'_>

Bit 13 - CCM SRAM page write protection bit

pub fn page14_wp(&mut self) -> PAGE14_WP_W<'_>

Bit 14 - CCM SRAM page write protection bit

pub fn page15_wp(&mut self) -> PAGE15_WP_W<'_>

Bit 15 - CCM SRAM page write protection bit

impl W<u32, Reg<u32, _CFGR3>>

pub fn i2c1_rx_dma_rmp(&mut self) -> I2C1_RX_DMA_RMP_W<'_>

Bits 4:5 - I2C1_RX DMA remapping bit

pub fn spi1_tx_dma_rmp(&mut self) -> SPI1_TX_DMA_RMP_W<'_>

Bits 2:3 - SPI1_TX DMA remapping bit

pub fn spi1_rx_dma_rmp(&mut self) -> SPI1_RX_DMA_RMP_W<'_>

Bits 0:1 - SPI1_RX DMA remapping bit

pub fn i2c1_tx_dma_rmp(&mut self) -> I2C1_TX_DMA_RMP_W<'_>

Bits 6:7 - I2C1_TX DMA remapping bit

pub fn adc2_dma_rmp(&mut self) -> ADC2_DMA_RMP_W<'_>

Bits 8:9 - ADC2 DMA remapping bit

impl W<u32, Reg<u32, _CFGR4>>

pub fn adc12_ext2_rmp(&mut self) -> ADC12_EXT2_RMP_W<'_>

Bit 0 - Controls the Input trigger of ADC12 regular channel EXT2

pub fn adc12_ext3_rmp(&mut self) -> ADC12_EXT3_RMP_W<'_>

Bit 1 - Controls the Input trigger of ADC12 regular channel EXT3

pub fn adc12_ext5_rmp(&mut self) -> ADC12_EXT5_RMP_W<'_>

Bit 2 - Controls the Input trigger of ADC12 regular channel EXT5

pub fn adc12_ext13_rmp(&mut self) -> ADC12_EXT13_RMP_W<'_>

Bit 3 - Controls the Input trigger of ADC12 regular channel EXT13

pub fn adc12_ext15_rmp(&mut self) -> ADC12_EXT15_RMP_W<'_>

Bit 4 - Controls the Input trigger of ADC12 regular channel EXT15

pub fn adc12_jext3_rmp(&mut self) -> ADC12_JEXT3_RMP_W<'_>

Bit 5 - Controls the Input trigger of ADC12 injected channel JEXT3

pub fn adc12_jext6_rmp(&mut self) -> ADC12_JEXT6_RMP_W<'_>

Bit 6 - Controls the Input trigger of ADC12 injected channel JEXT6

pub fn adc12_jext13_rmp(&mut self) -> ADC12_JEXT13_RMP_W<'_>

Bit 7 - Controls the Input trigger of ADC12 injected channel JEXT13

pub fn adc34_ext5_rmp(&mut self) -> ADC34_EXT5_RMP_W<'_>

Bit 8 - Controls the Input trigger of ADC34 regular channel EXT5

pub fn adc34_ext6_rmp(&mut self) -> ADC34_EXT6_RMP_W<'_>

Bit 9 - Controls the Input trigger of ADC34 regular channel EXT6

pub fn adc34_ext15_rmp(&mut self) -> ADC34_EXT15_RMP_W<'_>

Bit 10 - Controls the Input trigger of ADC34 regular channel EXT15

pub fn adc34_jext5_rmp(&mut self) -> ADC34_JEXT5_RMP_W<'_>

Bit 11 - Controls the Input trigger of ADC34 injected channel JEXT5

pub fn adc34_jext11_rmp(&mut self) -> ADC34_JEXT11_RMP_W<'_>

Bit 12 - Controls the Input trigger of ADC34 injected channel JEXT11

pub fn adc34_jext14_rmp(&mut self) -> ADC34_JEXT14_RMP_W<'_>

Bit 13 - Controls the Input trigger of ADC34 injected channel JEXT14

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _ISR>>

pub fn jqovf(&mut self) -> JQOVF_W<'_>

Bit 10 - JQOVF

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - AWD3

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - AWD2

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - AWD1

pub fn jeos(&mut self) -> JEOS_W<'_>

Bit 6 - JEOS

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 5 - JEOC

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - OVR

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - EOS

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - EOC

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - EOSMP

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADRDY

impl W<u32, Reg<u32, _IER>>

pub fn jqovfie(&mut self) -> JQOVFIE_W<'_>

Bit 10 - JQOVFIE

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - AWD3IE

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - AWD2IE

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - AWD1IE

pub fn jeosie(&mut self) -> JEOSIE_W<'_>

Bit 6 - JEOSIE

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 5 - JEOCIE

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - OVRIE

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - EOSIE

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - EOCIE

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - EOSMPIE

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADRDYIE

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADCAL

pub fn adcaldif(&mut self) -> ADCALDIF_W<'_>

Bit 30 - ADCALDIF

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bits 28:29 - ADVREGEN

pub fn jadstp(&mut self) -> JADSTP_W<'_>

Bit 5 - JADSTP

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADSTP

pub fn jadstart(&mut self) -> JADSTART_W<'_>

Bit 3 - JADSTART

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADSTART

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADDIS

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADEN

impl W<u32, Reg<u32, _CFGR>>

pub fn awd1ch(&mut self) -> AWD1CH_W<'_>

Bits 26:30 - AWDCH1CH

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 25 - JAUTO

pub fn jawd1en(&mut self) -> JAWD1EN_W<'_>

Bit 24 - JAWD1EN

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - AWD1EN

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - AWD1SGL

pub fn jqm(&mut self) -> JQM_W<'_>

Bit 21 - JQM

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 20 - JDISCEN

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 17:19 - DISCNUM

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - DISCEN

pub fn autdly(&mut self) -> AUTDLY_W<'_>

Bit 14 - AUTDLY

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - CONT

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - OVRMOD

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - EXTEN

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:9 - EXTSEL

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ALIGN

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - RES

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - DMACFG

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMAEN

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - SMP9

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - SMP8

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - SMP7

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - SMP6

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - SMP5

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - SMP4

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - SMP3

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - SMP2

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - SMP1

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - SMP18

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - SMP17

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - SMP16

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - SMP15

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - SMP14

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - SMP13

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - SMP12

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - SMP11

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - SMP10

impl W<u32, Reg<u32, _TR1>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - HT1

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - LT1

impl W<u32, Reg<u32, _TR2>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:23 - HT2

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:7 - LT2

impl W<u32, Reg<u32, _TR3>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:23 - HT3

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:7 - LT3

impl W<u32, Reg<u32, _SQR1>>

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 24:28 - SQ4

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 18:22 - SQ3

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 12:16 - SQ2

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 6:10 - SQ1

pub fn l(&mut self) -> L_W<'_>

Bits 0:3 - L3

impl W<u32, Reg<u32, _SQR2>>

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 24:28 - SQ9

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 18:22 - SQ8

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 12:16 - SQ7

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 6:10 - SQ6

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 0:4 - SQ5

impl W<u32, Reg<u32, _SQR3>>

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 24:28 - SQ14

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 18:22 - SQ13

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 12:16 - SQ12

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 6:10 - SQ11

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 0:4 - SQ10

impl W<u32, Reg<u32, _SQR4>>

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 6:10 - SQ16

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 0:4 - SQ15

impl W<u32, Reg<u32, _JSQR>>

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 26:30 - JSQ4

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 20:24 - JSQ3

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 14:18 - JSQ2

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 8:12 - JSQ1

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 6:7 - JEXTEN

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 2:5 - JEXTSEL

pub fn jl(&mut self) -> JL_W<'_>

Bits 0:1 - JL

impl W<u32, Reg<u32, _OFR1>>

pub fn offset1_en(&mut self) -> OFFSET1_EN_W<'_>

Bit 31 - OFFSET1_EN

pub fn offset1_ch(&mut self) -> OFFSET1_CH_W<'_>

Bits 26:30 - OFFSET1_CH

pub fn offset1(&mut self) -> OFFSET1_W<'_>

Bits 0:11 - OFFSET1

impl W<u32, Reg<u32, _OFR2>>

pub fn offset2_en(&mut self) -> OFFSET2_EN_W<'_>

Bit 31 - OFFSET2_EN

pub fn offset2_ch(&mut self) -> OFFSET2_CH_W<'_>

Bits 26:30 - OFFSET2_CH

pub fn offset2(&mut self) -> OFFSET2_W<'_>

Bits 0:11 - OFFSET2

impl W<u32, Reg<u32, _OFR3>>

pub fn offset3_en(&mut self) -> OFFSET3_EN_W<'_>

Bit 31 - OFFSET3_EN

pub fn offset3_ch(&mut self) -> OFFSET3_CH_W<'_>

Bits 26:30 - OFFSET3_CH

pub fn offset3(&mut self) -> OFFSET3_W<'_>

Bits 0:11 - OFFSET3

impl W<u32, Reg<u32, _OFR4>>

pub fn offset4_en(&mut self) -> OFFSET4_EN_W<'_>

Bit 31 - OFFSET4_EN

pub fn offset4_ch(&mut self) -> OFFSET4_CH_W<'_>

Bits 26:30 - OFFSET4_CH

pub fn offset4(&mut self) -> OFFSET4_W<'_>

Bits 0:11 - OFFSET4

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch0(&mut self) -> AWD2CH0_W<'_>

Bit 0 - AWD2CH

pub fn awd2ch1(&mut self) -> AWD2CH1_W<'_>

Bit 1 - AWD2CH

pub fn awd2ch2(&mut self) -> AWD2CH2_W<'_>

Bit 2 - AWD2CH

pub fn awd2ch3(&mut self) -> AWD2CH3_W<'_>

Bit 3 - AWD2CH

pub fn awd2ch4(&mut self) -> AWD2CH4_W<'_>

Bit 4 - AWD2CH

pub fn awd2ch5(&mut self) -> AWD2CH5_W<'_>

Bit 5 - AWD2CH

pub fn awd2ch6(&mut self) -> AWD2CH6_W<'_>

Bit 6 - AWD2CH

pub fn awd2ch7(&mut self) -> AWD2CH7_W<'_>

Bit 7 - AWD2CH

pub fn awd2ch8(&mut self) -> AWD2CH8_W<'_>

Bit 8 - AWD2CH

pub fn awd2ch9(&mut self) -> AWD2CH9_W<'_>

Bit 9 - AWD2CH

pub fn awd2ch10(&mut self) -> AWD2CH10_W<'_>

Bit 10 - AWD2CH

pub fn awd2ch11(&mut self) -> AWD2CH11_W<'_>

Bit 11 - AWD2CH

pub fn awd2ch12(&mut self) -> AWD2CH12_W<'_>

Bit 12 - AWD2CH

pub fn awd2ch13(&mut self) -> AWD2CH13_W<'_>

Bit 13 - AWD2CH

pub fn awd2ch14(&mut self) -> AWD2CH14_W<'_>

Bit 14 - AWD2CH

pub fn awd2ch15(&mut self) -> AWD2CH15_W<'_>

Bit 15 - AWD2CH

pub fn awd2ch16(&mut self) -> AWD2CH16_W<'_>

Bit 16 - AWD2CH

pub fn awd2ch17(&mut self) -> AWD2CH17_W<'_>

Bit 17 - AWD2CH

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch0(&mut self) -> AWD3CH0_W<'_>

Bit 0 - AWD3CH

pub fn awd3ch1(&mut self) -> AWD3CH1_W<'_>

Bit 1 - AWD3CH

pub fn awd3ch2(&mut self) -> AWD3CH2_W<'_>

Bit 2 - AWD3CH

pub fn awd3ch3(&mut self) -> AWD3CH3_W<'_>

Bit 3 - AWD3CH

pub fn awd3ch4(&mut self) -> AWD3CH4_W<'_>

Bit 4 - AWD3CH

pub fn awd3ch5(&mut self) -> AWD3CH5_W<'_>

Bit 5 - AWD3CH

pub fn awd3ch6(&mut self) -> AWD3CH6_W<'_>

Bit 6 - AWD3CH

pub fn awd3ch7(&mut self) -> AWD3CH7_W<'_>

Bit 7 - AWD3CH

pub fn awd3ch8(&mut self) -> AWD3CH8_W<'_>

Bit 8 - AWD3CH

pub fn awd3ch9(&mut self) -> AWD3CH9_W<'_>

Bit 9 - AWD3CH

pub fn awd3ch10(&mut self) -> AWD3CH10_W<'_>

Bit 10 - AWD3CH

pub fn awd3ch11(&mut self) -> AWD3CH11_W<'_>

Bit 11 - AWD3CH

pub fn awd3ch12(&mut self) -> AWD3CH12_W<'_>

Bit 12 - AWD3CH

pub fn awd3ch13(&mut self) -> AWD3CH13_W<'_>

Bit 13 - AWD3CH

pub fn awd3ch14(&mut self) -> AWD3CH14_W<'_>

Bit 14 - AWD3CH

pub fn awd3ch15(&mut self) -> AWD3CH15_W<'_>

Bit 15 - AWD3CH

pub fn awd3ch16(&mut self) -> AWD3CH16_W<'_>

Bit 16 - AWD3CH

pub fn awd3ch17(&mut self) -> AWD3CH17_W<'_>

Bit 17 - AWD3CH

impl W<u32, Reg<u32, _DIFSEL>>

pub fn difsel_10(&mut self) -> DIFSEL_10_W<'_>

Bit 0 - Differential mode for channels 15 to 1

pub fn difsel_11(&mut self) -> DIFSEL_11_W<'_>

Bit 1 - Differential mode for channels 15 to 1

pub fn difsel_12(&mut self) -> DIFSEL_12_W<'_>

Bit 2 - Differential mode for channels 15 to 1

pub fn difsel_13(&mut self) -> DIFSEL_13_W<'_>

Bit 3 - Differential mode for channels 15 to 1

pub fn difsel_14(&mut self) -> DIFSEL_14_W<'_>

Bit 4 - Differential mode for channels 15 to 1

pub fn difsel_15(&mut self) -> DIFSEL_15_W<'_>

Bit 5 - Differential mode for channels 15 to 1

pub fn difsel_16(&mut self) -> DIFSEL_16_W<'_>

Bit 6 - Differential mode for channels 15 to 1

pub fn difsel_17(&mut self) -> DIFSEL_17_W<'_>

Bit 7 - Differential mode for channels 15 to 1

pub fn difsel_18(&mut self) -> DIFSEL_18_W<'_>

Bit 8 - Differential mode for channels 15 to 1

pub fn difsel_19(&mut self) -> DIFSEL_19_W<'_>

Bit 9 - Differential mode for channels 15 to 1

pub fn difsel_110(&mut self) -> DIFSEL_110_W<'_>

Bit 10 - Differential mode for channels 15 to 1

pub fn difsel_111(&mut self) -> DIFSEL_111_W<'_>

Bit 11 - Differential mode for channels 15 to 1

pub fn difsel_112(&mut self) -> DIFSEL_112_W<'_>

Bit 12 - Differential mode for channels 15 to 1

pub fn difsel_113(&mut self) -> DIFSEL_113_W<'_>

Bit 13 - Differential mode for channels 15 to 1

pub fn difsel_114(&mut self) -> DIFSEL_114_W<'_>

Bit 14 - Differential mode for channels 15 to 1

pub fn difsel_115(&mut self) -> DIFSEL_115_W<'_>

Bit 15 - Differential mode for channels 15 to 1

pub fn difsel_116(&mut self) -> DIFSEL_116_W<'_>

Bit 16 - Differential mode for channels 15 to 1

pub fn difsel_117(&mut self) -> DIFSEL_117_W<'_>

Bit 17 - Differential mode for channels 15 to 1

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact_d(&mut self) -> CALFACT_D_W<'_>

Bits 16:22 - CALFACT_D

pub fn calfact_s(&mut self) -> CALFACT_S_W<'_>

Bits 0:6 - CALFACT_S

impl W<u32, Reg<u32, _CCR>>

pub fn dual(&mut self) -> DUAL_W<'_>

Bits 0:4 - Dual ADC mode selection

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 8:11 - Delay between 2 sampling phases

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 13 - DMA configuration (for multi-ADC mode)

pub fn mdma(&mut self) -> MDMA_W<'_>

Bits 14:15 - Direct memory access mode for multi ADC mode

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 16:17 - ADC clock mode

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Lok Key

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port x Reset bit y

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port x Reset bit y

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port x Reset bit y

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port x Reset bit y

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port x Reset bit y

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port x Reset bit y

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port x Reset bit y

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port x Reset bit y

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port x Reset bit y

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port x Reset bit y

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port x Reset bit y

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port x Reset bit y

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port x Reset bit y

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port x Reset bit y

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port x Reset bit y

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port x Reset bit y

impl W<u32, Reg<u32, _OPAMP2_CSR>>

pub fn opamp2en(&mut self) -> OPAMP2EN_W<'_>

Bit 0 - OPAMP2 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _OPAMP3_CSR>>

pub fn opamp3en(&mut self) -> OPAMP3EN_W<'_>

Bit 0 - OPAMP3 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _OPAMP4_CSR>>

pub fn opamp4en(&mut self) -> OPAMP4EN_W<'_>

Bit 0 - OPAMP4 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _OPAMP1_CSR>>

pub fn opamp1en(&mut self) -> OPAMP1EN_W<'_>

Bit 0 - OPAMP1 enable

pub fn force_vp(&mut self) -> FORCE_VP_W<'_>

Bit 1 - FORCE_VP

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bits 2:3 - OPAMP Non inverting input selection

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 5:6 - OPAMP inverting input selection

pub fn tcm_en(&mut self) -> TCM_EN_W<'_>

Bit 7 - Timer controlled Mux mode enable

pub fn vms_sel(&mut self) -> VMS_SEL_W<'_>

Bit 8 - OPAMP inverting input secondary selection

pub fn vps_sel(&mut self) -> VPS_SEL_W<'_>

Bits 9:10 - OPAMP Non inverting input secondary selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 11 - Calibration mode enable

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bits 12:13 - Calibration selection

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 14:17 - Gain in PGA mode

pub fn user_trim(&mut self) -> USER_TRIM_W<'_>

Bit 18 - User trimming enable

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 19:23 - Offset trimming value (PMOS)

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 24:28 - Offset trimming value (NMOS)

pub fn tstref(&mut self) -> TSTREF_W<'_>

Bit 29 - TSTREF

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - OPAMP lock

impl W<u32, Reg<u32, _COMP2_CSR>>

pub fn comp2en(&mut self) -> COMP2EN_W<'_>

Bit 0 - Comparator 2 enable

pub fn comp2inmsel(&mut self) -> COMP2INMSEL_W<'_>

Bits 4:6 - Comparator 2 inverting input selection

pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<'_>

Bits 10:13 - Comparator 2 output selection

pub fn comp2pol(&mut self) -> COMP2POL_W<'_>

Bit 15 - Comparator 2 output polarity

pub fn comp2_blanking(&mut self) -> COMP2_BLANKING_W<'_>

Bits 18:20 - Comparator 2 blanking source

pub fn comp2lock(&mut self) -> COMP2LOCK_W<'_>

Bit 31 - Comparator 2 lock

pub fn comp2mode(&mut self) -> COMP2MODE_W<'_>

Bits 2:3 - Comparator 2 mode

pub fn comp2inpsel(&mut self) -> COMP2INPSEL_W<'_>

Bit 7 - Comparator 2 non inverted input

pub fn comp2winmode(&mut self) -> COMP2WINMODE_W<'_>

Bit 9 - Comparator 2 window mode

pub fn comp2hyst(&mut self) -> COMP2HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis

pub fn comp2inmsel3(&mut self) -> COMP2INMSEL3_W<'_>

Bit 22 - Comparator 2 inverting input selection

impl W<u32, Reg<u32, _COMP4_CSR>>

pub fn comp4en(&mut self) -> COMP4EN_W<'_>

Bit 0 - Comparator 4 enable

pub fn comp4inmsel(&mut self) -> COMP4INMSEL_W<'_>

Bits 4:6 - Comparator 4 inverting input selection

pub fn comp4outsel(&mut self) -> COMP4OUTSEL_W<'_>

Bits 10:13 - Comparator 4 output selection

pub fn comp4pol(&mut self) -> COMP4POL_W<'_>

Bit 15 - Comparator 4 output polarity

pub fn comp4_blanking(&mut self) -> COMP4_BLANKING_W<'_>

Bits 18:20 - Comparator 4 blanking source

pub fn comp4lock(&mut self) -> COMP4LOCK_W<'_>

Bit 31 - Comparator 4 lock

pub fn comp4winmode(&mut self) -> COMP4WINMODE_W<'_>

Bit 9 - Comparator 4 window mode

pub fn comp4mode(&mut self) -> COMP4MODE_W<'_>

Bits 2:3 - Comparator 4 mode

pub fn comp4inpsel(&mut self) -> COMP4INPSEL_W<'_>

Bit 7 - Comparator 4 non inverted input

pub fn comp4hyst(&mut self) -> COMP4HYST_W<'_>

Bits 16:17 - Comparator 4 hysteresis

pub fn comp4inmsel3(&mut self) -> COMP4INMSEL3_W<'_>

Bit 22 - Comparator 4 inverting input selection

impl W<u32, Reg<u32, _COMP6_CSR>>

pub fn comp6en(&mut self) -> COMP6EN_W<'_>

Bit 0 - Comparator 6 enable

pub fn comp6inmsel(&mut self) -> COMP6INMSEL_W<'_>

Bits 4:6 - Comparator 6 inverting input selection

pub fn comp6outsel(&mut self) -> COMP6OUTSEL_W<'_>

Bits 10:13 - Comparator 6 output selection

pub fn comp6pol(&mut self) -> COMP6POL_W<'_>

Bit 15 - Comparator 6 output polarity

pub fn comp6_blanking(&mut self) -> COMP6_BLANKING_W<'_>

Bits 18:20 - Comparator 6 blanking source

pub fn comp6lock(&mut self) -> COMP6LOCK_W<'_>

Bit 31 - Comparator 6 lock

pub fn comp6winmode(&mut self) -> COMP6WINMODE_W<'_>

Bit 9 - Comparator 6 window mode

pub fn comp6mode(&mut self) -> COMP6MODE_W<'_>

Bits 2:3 - Comparator 6 mode

pub fn comp6inpsel(&mut self) -> COMP6INPSEL_W<'_>

Bit 7 - Comparator 6 non inverted input

pub fn comp6hyst(&mut self) -> COMP6HYST_W<'_>

Bits 16:17 - Comparator 6 hysteresis

pub fn comp6inmsel3(&mut self) -> COMP6INMSEL3_W<'_>

Bit 22 - Comparator 6 inverting input selection

impl W<u32, Reg<u32, _COMP3_CSR>>

pub fn comp3en(&mut self) -> COMP3EN_W<'_>

Bit 0 - Comparator 3 enable

pub fn comp3mode(&mut self) -> COMP3MODE_W<'_>

Bits 2:3 - Comparator 3 mode

pub fn comp3inmsel(&mut self) -> COMP3INMSEL_W<'_>

Bits 4:6 - Comparator 3 inverting input selection

pub fn comp3inpsel(&mut self) -> COMP3INPSEL_W<'_>

Bit 7 - Comparator 3 non inverted input

pub fn comp3outsel(&mut self) -> COMP3OUTSEL_W<'_>

Bits 10:13 - Comparator 3 output selection

pub fn comp3pol(&mut self) -> COMP3POL_W<'_>

Bit 15 - Comparator 3 output polarity

pub fn comp3hyst(&mut self) -> COMP3HYST_W<'_>

Bits 16:17 - Comparator 3 hysteresis

pub fn comp3_blanking(&mut self) -> COMP3_BLANKING_W<'_>

Bits 18:20 - Comparator 3 blanking source

pub fn comp3lock(&mut self) -> COMP3LOCK_W<'_>

Bit 31 - Comparator 3 lock

impl W<u32, Reg<u32, _COMP5_CSR>>

pub fn comp5en(&mut self) -> COMP5EN_W<'_>

Bit 0 - Comparator 5 enable

pub fn comp5mode(&mut self) -> COMP5MODE_W<'_>

Bits 2:3 - Comparator 5 mode

pub fn comp5inmsel(&mut self) -> COMP5INMSEL_W<'_>

Bits 4:6 - Comparator 5 inverting input selection

pub fn comp5inpsel(&mut self) -> COMP5INPSEL_W<'_>

Bit 7 - Comparator 5 non inverted input

pub fn comp5outsel(&mut self) -> COMP5OUTSEL_W<'_>

Bits 10:13 - Comparator 5 output selection

pub fn comp5pol(&mut self) -> COMP5POL_W<'_>

Bit 15 - Comparator 5 output polarity

pub fn comp5hyst(&mut self) -> COMP5HYST_W<'_>

Bits 16:17 - Comparator 5 hysteresis

pub fn comp5_blanking(&mut self) -> COMP5_BLANKING_W<'_>

Bits 18:20 - Comparator 5 blanking source

pub fn comp5lock(&mut self) -> COMP5LOCK_W<'_>

Bit 31 - Comparator 5 lock

impl W<u32, Reg<u32, _COMP7_CSR>>

pub fn comp7en(&mut self) -> COMP7EN_W<'_>

Bit 0 - Comparator 7 enable

pub fn comp7mode(&mut self) -> COMP7MODE_W<'_>

Bits 2:3 - Comparator 7 mode

pub fn comp7inmsel(&mut self) -> COMP7INMSEL_W<'_>

Bits 4:6 - Comparator 7 inverting input selection

pub fn comp7inpsel(&mut self) -> COMP7INPSEL_W<'_>

Bit 7 - Comparator 7 non inverted input

pub fn comp7outsel(&mut self) -> COMP7OUTSEL_W<'_>

Bits 10:13 - Comparator 7 output selection

pub fn comp7pol(&mut self) -> COMP7POL_W<'_>

Bit 15 - Comparator 7 output polarity

pub fn comp7hyst(&mut self) -> COMP7HYST_W<'_>

Bits 16:17 - Comparator 7 hysteresis

pub fn comp7_blanking(&mut self) -> COMP7_BLANKING_W<'_>

Bits 18:20 - Comparator 7 blanking source

pub fn comp7lock(&mut self) -> COMP7LOCK_W<'_>

Bit 31 - Comparator 7 lock

impl W<u32, Reg<u32, _COMP1_CSR>>

pub fn comp1en(&mut self) -> COMP1EN_W<'_>

Bit 0 - Comparator 1 enable

pub fn comp1_inp_dac(&mut self) -> COMP1_INP_DAC_W<'_>

Bit 1 - Comparator 1 non inverting input connection to DAC output

pub fn comp1mode(&mut self) -> COMP1MODE_W<'_>

Bits 2:3 - Comparator 1 mode

pub fn comp1inmsel(&mut self) -> COMP1INMSEL_W<'_>

Bits 4:6 - Comparator 1 inverting input selection

pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<'_>

Bits 10:13 - Comparator 1 output selection

pub fn comp1pol(&mut self) -> COMP1POL_W<'_>

Bit 15 - Comparator 1 output polarity

pub fn comp1hyst(&mut self) -> COMP1HYST_W<'_>

Bits 16:17 - Comparator 1 hysteresis

pub fn comp1_blanking(&mut self) -> COMP1_BLANKING_W<'_>

Bits 18:20 - Comparator 1 blanking source

pub fn comp1lock(&mut self) -> COMP1LOCK_W<'_>

Bit 31 - Comparator 1 lock