Module stm32_hal2::timer

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Expand description

Provides support for basic timer functionality. Includes initialization, interrupts, and PWM features. Also supports capture compare, output compare, burst DMA, and getting the current uptime using an overflowing wrapper. (In seconds, milliseconds, or microseconds)

Low-power timers (LPTIM) and high-presolution timers (HRTIM) are not yet supported.

Structs§

  • BasicTimer
    Represents a Basic timer, used primarily to trigger the onboard DAC. Eg Tim6 or Tim7.
  • Timer
    Represents a General Purpose or Advanced Control timer.
  • TimerConfig
    Initial configuration data for Timer peripherals.
  • ValueError
    Used for when attempting to set a timer period that is out of range.

Enums§

  • Alignment
    Output alignment. Sets TIMx_CR1 register, CMS field.
  • CaptureCompare
    Capture/Compare selection. This field defines the direction of the channel (input/output) as well as the used input. It affects the TIMx_CCMR1 register, CCxS fields. Note that the signifiders of the input sources varies depending on the channel. For example, the one labeled InputTi1 here is always the associated channel, while InputTi2 is 2 for ch1, 1 for ch2, 4 for ch3, and 3 for ch4.
  • CaptureCompareDma
    Capture/Compaer DMA selection. Sets TIMx_CR2 register, CCDS field.
  • CountDir
    Timer count direction. Defaults to Up.
  • InputSlaveMode
    When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Sets SMCR register, SMS field.
  • InputTrigger
    This bit-field selects the trigger input to be used to synchronize the counter. Sets SMCR register, TS field.
  • MasterModeSelection
    These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). Sets CR2 register, MMS field.
  • OutputCompare
    See F303 ref man, section 21.4.7. H745 RM, section 41.4.8. Sets TIMx_CCMR1 register, OC1M field. These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
  • Polarity
    Capture/Compare output polarity. Defaults to ActiveHigh in hardware. Sets TIMx_CCER register, CCxP and CCXNP fields.
  • TimChannel
    Timer channel
  • TimerInterrupt
    Timer interrupt
  • UpdateReqSrc
    Update Request source. This bit is set and cleared by software to select the UEV event sources. Sets TIMx_CR1 register, URS field.

Statics§