Enum MasterModeSelection

#[repr(u8)]
pub enum MasterModeSelection {
    Reset = 0,
    Enable = 1,
    Update = 2,
    ComparePulse = 3,
    Compare1 = 4,
    Compare2 = 5,
    Compare3 = 6,
    Compare4 = 7,
}

These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). Sets CR2 register, MMS field.

Variants

Reset = 0

Tthe UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

Enable = 1

the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

Update = 2

The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

ComparePulse = 3

Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).

Compare1 = 4

OC1REF signal is used as trigger output (TRGO)

Compare2 = 5

OC2REF signal is used as trigger output (TRGO)

Compare3 = 6

OC3REF signal is used as trigger output (TRGO)

Compare4 = 7

OC4REF signal is used as trigger output (TRGO)

Trait Implementations

impl Clone for MasterModeSelection

fn clone(&self) -> MasterModeSelection

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for MasterModeSelection