Enum ClockMode

#[repr(u8)]
pub enum ClockMode {
    Async = 0,
    SyncDiv1 = 1,
    SyncDiv2 = 2,
    SyncDiv4 = 3,
}

ADC Clock mode (L44 RM, Section 16.4.3) The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 40: ADC clock scheme):

1. The ADC clock can be a specific clock source. It can be derived from the following clock sources: – The system clock – PLLSAI1 (single ADC implementation) Refer to RCC Section for more information on how to generate ADC dedicated clock. To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.
2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]). To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different from “00”.

Variants

Async = 0

Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock

SyncDiv1 = 1

Use AHB clock rcc_hclk3 (or just hclk depending on variant). “For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).”

SyncDiv2 = 2

Use AHB clock rcc_hclk3 (or just hclk depending on variant) divided by 2

SyncDiv4 = 3

Use AHB clock rcc_hclk3 (or just hclk depending on variant) divided by 4

Trait Implementations

impl Clone for ClockMode

fn clone(&self) -> ClockMode

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for ClockMode

fn eq(&self, other: &ClockMode) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for ClockMode

impl StructuralPartialEq for ClockMode