Crate rustdv_methodology 

rustdv-methodology

The verification methodology layer — rustdv’s analog of the UVM’s component methodology (design-doc §5, as revised by review-memo R1–R6).

Read this first: R3, R4 and R5 are being reversed. They are what made rustdv a closed-world framework — one that cannot configure or override anything you did not write yourself — and the branch this crate is on exists to undo them. output/.design-decisions.md is authoritative; the list below marks each item’s real status so nobody mistakes the current code for the intended design.

• Transactions are plain structs with std derives (R1) — no base trait. Stands.
• The component tree is the ownership tree (R2): children are struct fields; ComponentNode provides traversal, hand-implementable or generated by #[derive(Component)]. Stands — the tree is still ownership; what returns is the phase structure over it.
• build/connect are constructor conventions (R3); the runtime lifecycle is the Component trait. Reversed — build/connect are real phase methods again (D5/D6/D51), and the runner drives all nine phases over the tree (run_component_test). The first half of ch24 (the phase-logging test) runs on this. Still pending: two-stage construction, where a parent creates children as Option<T>/Vec<T> in its own build — the second half of ch24.
• Configuration is typed config structs passed to constructors (R4). Reversed by D11–D16, not yet implemented. A path-addressed ConfigDb returns, with three-tier resolution and loud failure.
• Variation points are constructor injection (R5) — no factory. Reversed, not yet implemented. The factory returns in ch29 (D26 keeps it out of ch23 only because the book does).
• Communication is channels + AnalysisBus + the sequencer handshake, preserved event-for-event from pyuvm (R6, §5.6). Stands, and is being extended: TLM ports, exports and FIFOs arrive per D17–D24, with ports in components and exports on FIFOs.

What has landed on this branch is step 4: RustdvCtx, the one context (D47), and Component’s async fn run (D46, D48).

Re-exports

pub use analysis::AnalysisBus;

pub use analysis::PublishExport;

pub use analysis::SubscribeExport;

pub use shared::RustdvShared;

pub use channel::channel;

pub use channel::Receiver;

pub use channel::Sender;

pub use channel::TlmEmpty;

pub use channel::TlmError;

pub use channel::TlmFull;

pub use component::build_all;

pub use component::check_all;

pub use component::connect_all;

pub use component::end_of_elaboration_all;

pub use component::extract_all;

pub use component::final_all;

pub use component::check_connections;

pub use component::print_hierarchy;

pub use component::report_all;

pub use component::run_all;

pub use component::run_component_test;

pub use component::run_extract_check_report;

pub use component::unconnected_ports;

pub use component::start_all;

pub use component::start_of_simulation_all;

pub use component::Active;

pub use component::CheckSink;

pub use component::Component;

pub use component::ComponentNode;

pub use component::DynPhases;

pub use component::RustdvCtx;

pub use config::ConfigDb;

pub use config::ConfigError;

pub use error::TestError;

pub use factory::RustdvComp;

pub use factory::ComponentReg;

pub use factory::Factory;

pub use factory::Maker;

pub use fifo::GetExport;

pub use fifo::PeekExport;

pub use fifo::PutExport;

pub use fifo::TapExport;

pub use fifo::TlmFifo;

pub use port::bind;

pub use port::ConnectError;

pub use port::GetIf;

pub use port::GetPort;

pub use port::PeekIf;

pub use port::PeekPort;

pub use port::Port;

pub use port::PortField;

pub use port::PortInfo;

pub use port::PortName;

pub use port::PortOwner;

pub use port::PublishIf;

pub use port::PublishPort;

pub use port::PutIf;

pub use port::PutPort;

pub use port::SinkHandle;

pub use port::SubscribePort;

pub use port::Subscriber;

pub use objection::ObjectionGuard;

pub use objection::ObjectionRegistry;

pub use sequence::clear_seq_overrides;

pub use sequence::create_seq;

pub use sequence::set_seq_override;

pub use sequence::set_sequence_seed;

pub use sequence::DynSequence;

pub use sequence::ResponseQueue;

pub use sequence::RustdvSeq;

pub use sequence::SeqCtx;

pub use sequence::SeqError;

pub use sequence::SeqItem;

pub use sequence::SeqItemExport;

pub use sequence::SeqItemIf;

pub use sequence::SeqItemPort;

pub use sequence::Sequence;

pub use sequence::Sequencer;

pub use sequence::TxnId;

Modules

analysis

Analysis: one write, every subscriber hears it (D86–D88; pyuvm uvm_analysis_port, uvm_subscriber, uvm_tlm_analysis_fifo).

channel

Channels: the TLM-1 replacement (design-doc §5.6, review-memo R6). Twelve pyuvm port classes become six methods on two types; direction lives in the type name; a mismatch is a compile error.

component

Component lifecycle and hierarchy traversal (design-doc §5.2/§5.3).

config

The ConfigDb — path-addressed configuration (D11–D16, D65–D68).

error

Test failure value.

factory

The factory (design-doc §15, D69–D75).

fifo

TlmFifo<T>: the UVM uvm_tlm_fifo — a component that encapsulates a queue (pyuvm’s Queue/Mailbox) so two components connect to the same FIFO and neither learns the other exists (D17/D23/D24; pyuvm uvm_tlm_fifo, default depth 1).

objection

Objections: distributed end-of-test consensus with RAII guards (design-doc §5.3; pyuvm: ObjectionHandler, uvm_component.objection()). Forgetting to drop is impossible; diagnostics (description, raise site) are captured in the guard.

port

TLM ports, exports, and how they connect (D83–D85).

sequence

Sequences: stimulus as a program, separate from the testbench structure.

shared

RustdvShared<T>: state two components can both see (D88).