Module component 

Component lifecycle and hierarchy traversal (design-doc §5.2/§5.3).

Superseded, being replaced — do not build on it. What this file still implements is review-memo R3: build/connect as constructor conventions rather than phases, a component’s new(config, ...) constructing its children (// build:) and taking channel endpoints as arguments (// connect:), with only the runtime lifecycle left as a trait.

D5 and D6 reverse that, and the reversal has begun. build (top-down) and connect (bottom-up) are real phase methods again (D51), because the gap between “a component exists” and “its children exist” is where all late binding lives — path-addressed configuration, factory overrides, TLM connection. The Component trait below now carries all nine phases and run_component_test drives them. new(config, ...)-style construction survives only in not-yet- converted testbenches (tinyalu_tb), not as the design.

What has landed. Step 4 (D46–D49): a test is a component with an async fn run, receiving the one universal RustdvCtx. Ch24 first half (D51/D52): the nine phases, the phaser, path-aware phase logging. Ch24 second half: two-stage construction (a parent creates children as Option<T>/Vec<T> in its own build) and the bottom-up run_all traversal firing every component’s run.

Structs

CheckSink

Collector for check-phase failures (design-doc §5.3 signature).

RustdvCtx

Everything a running testbench is handed: the DUT, randomization, the objection registry, and the component’s path.

Enums

Active

Agent activity (pyuvm’s ConfigDB is_active int becomes an enum — mapping row 42; illegal values are unrepresentable).

Traits

Component

The UVM phase lifecycle (design-doc §5.3, D51), restored in full. Nine phases, each a method with a default no-op body — override only what you use, exactly as pyuvm’s uvm_component does. build and connect are real phases again, not the “constructor conventions” R3 collapsed them into; restoring them is the point of this chapter.

ComponentNode

Structural traversal over the ownership tree (design-doc D5.2). Generated by #[derive(Component)] for structs whose children are fields marked #[component]; hand-implementable by design (OQ-15: the derive is convenience, not requirement).

DynPhases

Dyn-safe mirror of Component’s non-async phases (D48).

Functions

build_all

Top-down: build a node, then build the children it just created (D6). Reading children_mut after build is what lets a parent construct them in its own build phase and have the walk descend into them.

check_all

Top-down.

check_connections

Run the connection sweep and turn any misses into one error listing them all. Called by the runner between connect and end_of_elaboration.

connect_all

Bottom-up: children connect before parents.

end_of_elaboration_all

Top-down.

extract_all

Top-down.

final_all

Top-down.

print_hierarchy

Debug printer: the child walker serving pyuvm’s hierarchy print (design-doc §5.2).

report_all

Top-down.

run_all

Bottom-up: every component’s run fires, children first (D48). The walk is boxed-recursive because dyn_run yields a boxed future we await, and the children’s borrows are held across those awaits.

run_component_test

The full phaser: drive every UVM phase over a component tree, in order (D51) — the analog of pyuvm handing the test class to its phaser. The runner calls this for a #[rustdv::test] struct, so the test body is just the phase methods; no hand-rolled start_all.

run_extract_check_report

The standard post-run tail: extract → check → report → final, returning Err if any check failed (an Err fails the test, design-doc §0.6).

start_all

Bottom-up: children start before parents (transitional spawn hook).

start_of_simulation_all

Top-down.

unconnected_ports

Every required port in the tree that nobody connected, as path.name (kind).