Struct rust_hdl::widgets::test_helpers::LazyFIFOReader

pub struct LazyFIFOReader<T: Synth, const N: usize> {
    pub clock: Signal<In, Clock>,
    pub bus: FIFOReadController<T>,
    pub done: Signal<Out, Bit>,
    pub start: Signal<In, Bit>,
    pub error: Signal<Out, Bit>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

bus: FIFOReadController<T>

done: Signal<Out, Bit>

start: Signal<In, Bit>

error: Signal<Out, Bit>

Implementations

impl<T: Synth, const N: usize> LazyFIFOReader<T, N>

pub fn new(data: &[T], sleeps: &[Bits<32>]) -> LazyFIFOReader<T, N>

Trait Implementations

impl<T: Synth, const N: usize> Block for LazyFIFOReader<T, N>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Synth, const N: usize> Logic for LazyFIFOReader<T, N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>