Struct rust_hdl::widgets::synchronizer::VectorSynchronizer

pub struct VectorSynchronizer<T: Synth> {
    pub clock_in: Signal<In, Clock>,
    pub sig_in: Signal<In, T>,
    pub busy: Signal<Out, Bit>,
    pub send: Signal<In, Bit>,
    pub clock_out: Signal<In, Clock>,
    pub sig_out: Signal<Out, T>,
    pub update: Signal<Out, Bit>,
    /* private fields */
}

A VectorSynchronizer uses a SyncSender and SyncReceiver in a matched pair to transmit a vector of bits (or any Synth type from one clock domain to a second clock domain without metastability or data corruption. You can think of a VectorSynchronizer as a single-element asynchronous FIFO, and indeed [AsynchronousFIFO] uses the VectorSynchronizer internally.

Note that the VectorSynchronizer can be used to reflect a value/register into a second clock domain by tying self.send.next = !self.busy.val(). In that case, the output signal will be always attempting to follow the [sig_in] input as quickly as possible.

Fields

clock_in: Signal<In, Clock>

The input clock interface. Input data is clocked in using this clock.

sig_in: Signal<In, T>

The input data interface. Any synthesizable type can be used here. This is the data to send.

busy: Signal<Out, Bit>

The busy signal is asserted as long as the synchronizer is, well, synchronizing. You must wait until this flag goes low before attempting to send more data. The [send] signal is only valid when [busy] is low.

send: Signal<In, Bit>

Raise the [send] signal for a single clock cycle to indicate that the current data on [sig_in] should be sent across the synchronizer.

clock_out: Signal<In, Clock>

The clock to use on the output side of the VectorSynchronizer. This is the output clock.

sig_out: Signal<Out, T>

Data synchronized to the output clock [clock_out].

update: Signal<Out, Bit>

The update flag is strobed whenever a new valid output is available on [sig_out].

Trait Implementations

impl<T: Synth> Block for VectorSynchronizer<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Default + Synth> Default for VectorSynchronizer<T>

fn default() -> VectorSynchronizer<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for VectorSynchronizer<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>