Struct rust_hdl::hls::spi::HLSSPIMasterDynamicMode

pub struct HLSSPIMasterDynamicMode<const D: usize, const A: usize, const W: usize> {
    pub spi: SPIWiresMaster,
    pub upstream: SoCBusResponder<D, A>,
    /* private fields */
}

Fields

spi: SPIWiresMaster

upstream: SoCBusResponder<D, A>

Implementations

impl<const D: usize, const A: usize, const W: usize> HLSSPIMasterDynamicMode<D, A, W>

pub fn new(config: SPIConfigDynamicMode) -> Self

Trait Implementations

impl<const D: usize, const A: usize, const W: usize> Block for HLSSPIMasterDynamicMode<D, A, W>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const D: usize, const A: usize, const W: usize> HLSNamedPorts for HLSSPIMasterDynamicMode<D, A, W>

fn ports(&self) -> Vec<String>

impl<const D: usize, const A: usize, const W: usize> Logic for HLSSPIMasterDynamicMode<D, A, W>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>