Struct rust_hdl::hls::sdram_controller::SDRAMController

pub struct SDRAMController<const R: usize, const C: usize> {
    pub dram: SDRAMDriver<16>,
    pub upstream: SoCBusResponder<16, 8>,
    /* private fields */
}

Fields

dram: SDRAMDriver<16>

upstream: SoCBusResponder<16, 8>

Implementations

impl<const R: usize, const C: usize> SDRAMController<R, C>

pub fn new(
    cas_delay: u32,
    timings: MemoryTimings,
    buffer: OutputBuffer
) -> SDRAMController<R, C>

Trait Implementations

impl<const R: usize, const C: usize> Block for SDRAMController<R, C>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const R: usize, const C: usize> HLSNamedPorts for SDRAMController<R, C>

fn ports(&self) -> Vec<String>

impl<const R: usize, const C: usize> Logic for SDRAMController<R, C>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>