Struct rust_hdl::hls::controller::BaseController

pub struct BaseController<const A: usize> {
    pub from_cpu: FIFOReadController<Bits<16>>,
    pub to_cpu: FIFOWriteController<Bits<16>>,
    pub clock: Signal<In, Clock>,
    pub bus: SoCBusController<16, { A }>,
    /* private fields */
}

Fields

from_cpu: FIFOReadController<Bits<16>>

to_cpu: FIFOWriteController<Bits<16>>

clock: Signal<In, Clock>

bus: SoCBusController<16, { A }>

Trait Implementations

impl<const A: usize> Block for BaseController<A>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const A: usize> Default for BaseController<A>

fn default() -> BaseController<A>

Returns the “default value” for a type.

impl<const A: usize> Logic for BaseController<A>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>