Struct rust_hdl::widgets::synchronizer::SyncReceiver

pub struct SyncReceiver<T: Synth> {
    pub sig_out: Signal<Out, T>,
    pub clock: Signal<In, Clock>,
    pub sig_cross: Signal<In, T>,
    pub flag_in: Signal<In, Bit>,
    pub ack_out: Signal<Out, Bit>,
    pub update: Signal<Out, Bit>,
    /* private fields */
}

A SyncReceiver works together with a SyncSender to transmit data from one clock domain to another (in one direction). To use a SyncReceiver wire up the [sig_cross], [flag_in] and [ack_out] signals between the two.

Fields

sig_out: Signal<Out, T>

The data output synchronized to the receiver’s clock

clock: Signal<In, Clock>

The receivers clock signal. Data is synchronized to this clock.

sig_cross: Signal<In, T>

The wires used to send data from the SyncSender to the SyncReceiver.

flag_in: Signal<In, Bit>

This is wired up to the SyncSender::flag_out, and carries the new-data flag.

ack_out: Signal<Out, Bit>

This is wired up to the SyncSender::ack_in, and carries the acknowledge flag.

update: Signal<Out, Bit>

This signal will strobe high for one clock when the output is valid and synchronized.

Trait Implementations

impl<T: Synth> Block for SyncReceiver<T>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<T: Default + Synth> Default for SyncReceiver<T>

fn default() -> SyncReceiver<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for SyncReceiver<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>