Struct rust_hdl::core::clock::Clock

#[repr(transparent)]
pub struct Clock {
    pub clk: bool,
}

Fundamentally a Clock signal in RustHDL is simply a transparent wrapper around a boolean valued signal. So it could be thought of as a simple 1-bit wide signal. However, semantically, clocks are rarely treated like other signals, and typically connect only to dedicated clock ports on synchronous logic (like [DFF] or [RAM]).

Fields

clk: bool

The clock signal itself. Available using this field of the struct.

Trait Implementations

impl Clone for Clock

fn clone(&self) -> Clock

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Clock

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Clock

fn default() -> Clock

Returns the “default value” for a type.

impl From<bool> for Clock

fn from(x: bool) -> Clock

Converts to this type from the input type.

impl Hash for Clock

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H) where
    H: Hasher, 

Feeds a slice of this type into the given Hasher.

impl Not for Clock

type Output = Clock

The resulting type after applying the ! operator.

fn not(self) -> Self::Output

Performs the unary ! operation.

impl PartialEq<Clock> for Clock

fn eq(&self, other: &Clock) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Synth for Clock

const BITS: usize = 1usize

fn descriptor() -> TypeDescriptor

fn vcd(self) -> VCDValue

fn verilog(self) -> VerilogLiteral

impl Copy for Clock

impl Eq for Clock

impl StructuralEq for Clock

impl StructuralPartialEq for Clock