Struct rust_hdl_widgets::spi::mux::MuxSlaves

pub struct MuxSlaves<const N: usize, const A: usize> {
    pub from_master: SPIWiresSlave,
    pub to_slaves: [SPIWiresMaster; N],
    pub sel: Signal<In, Bits<A>>,
}

Fields

from_master: SPIWiresSlave

to_slaves: [SPIWiresMaster; N]

sel: Signal<In, Bits<A>>

Trait Implementations

impl<const N: usize, const A: usize> Block for MuxSlaves<N, A>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const N: usize, const A: usize> Default for MuxSlaves<N, A>

fn default() -> Self

Returns the “default value” for a type.

impl<const N: usize, const A: usize> Logic for MuxSlaves<N, A>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>