Struct rust_hdl_core::signal::Signal

pub struct Signal<D: Direction, T: Synth> {
    pub next: T,
    pub changed: bool,
    /* private fields */
}

Fields

next: T

changed: bool

Implementations

impl<T: Synth> Signal<In, T>

pub fn join(&mut self, other: &mut Signal<Out, T>)

pub fn join_hdl( my_name: &str, owner_name: &str, other_name: &str ) -> Vec<VerilogLink>

impl<T: Synth> Signal<Out, T>

pub fn join(&mut self, other: &mut Signal<In, T>)

pub fn join_hdl( my_name: &str, owner_name: &str, other_name: &str ) -> Vec<VerilogLink>

impl<D: Direction, T: Synth> Signal<D, T>

pub fn add_constraint(&mut self, constraint: PinConstraint)

pub fn add_location(&mut self, index: usize, location: &str)

pub fn add_signal_type(&mut self, index: usize, signal: SignalType)

impl Signal<In, Clock>

pub fn pos_edge(&self) -> bool

pub fn neg_edge(&self) -> bool

impl<T: Synth> Signal<Out, T>

pub fn new_with_default(init: T) -> Signal<Out, T>

impl<D: Direction> Signal<D, Bit>

pub fn pin_signal(location: &str, kind: SignalType) -> Signal<D, Bit>

impl<T: Synth> Signal<InOut, T>

pub fn set_tristate_is_output(&mut self, flag: bool)

pub fn is_driving_tristate(&self) -> bool

pub fn simulate_connected_tristate(&mut self, other: &mut Self)

impl<T: Synth> Signal<InOut, T>

pub fn join(&mut self, other: &mut Signal<InOut, T>)

pub fn join_hdl( my_name: &str, owner_name: &str, other_name: &str ) -> Vec<VerilogLink>

impl<T: Synth> Signal<Local, T>

pub fn val(&self) -> T

impl<T: Synth> Signal<In, T>

pub fn val(&self) -> T

impl<T: Synth> Signal<Out, T>

pub fn val(&self) -> T

impl<T: Synth> Signal<InOut, T>

pub fn val(&self) -> T

Trait Implementations

impl<D: Direction, T: Synth> Block for Signal<D, T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<D: Clone + Direction, T: Clone + Synth> Clone for Signal<D, T>

fn clone(&self) -> Signal<D, T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<D: Debug + Direction, T: Debug + Synth> Debug for Signal<D, T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<D: Direction, T: Synth> Default for Signal<D, T>

fn default() -> Self

Returns the “default value” for a type.

impl<D: Direction, T: Synth> Logic for Signal<D, T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>

impl<T: Synth> LogicJoin for Signal<In, T>

fn join_connect(&mut self)

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>

impl<T: Synth> LogicJoin for Signal<InOut, T>

fn join_connect(&mut self)

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>

impl<T: Synth> LogicJoin for Signal<Out, T>

fn join_connect(&mut self)

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>

impl<T: Synth> LogicLink for Signal<In, T>

fn link(&mut self, other: &mut Self)

fn link_hdl( my_name: &str, owner_name: &str, other_name: &str ) -> Vec<VerilogLink>

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

impl<T: Synth> LogicLink for Signal<InOut, T>

fn link(&mut self, other: &mut Self)

fn link_hdl( my_name: &str, owner_name: &str, other_name: &str ) -> Vec<VerilogLink>

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

impl<T: Synth> LogicLink for Signal<Out, T>

fn link(&mut self, other: &mut Self)

fn link_hdl( my_name: &str, owner_name: &str, other_name: &str ) -> Vec<VerilogLink>

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)