Struct rust_hdl_widgets::ramrom::sync_rom::SyncROM

pub struct SyncROM<D: Synth, const N: usize> {
    pub address: Signal<In, Bits<N>>,
    pub clock: Signal<In, Clock>,
    pub data: Signal<Out, D>,
    /* private fields */
}

Fields

address: Signal<In, Bits<N>>

clock: Signal<In, Clock>

data: Signal<Out, D>

Implementations

impl<D: Synth, const N: usize> SyncROM<D, N>

pub fn new(values: BTreeMap<Bits<N>, D>) -> Self

Trait Implementations

impl<D: Synth, const N: usize> Block for SyncROM<D, N>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<I: Iterator<Item = D>, D: Synth, const N: usize> From<I> for SyncROM<D, N>

fn from(v: I) -> Self

Converts to this type from the input type.

impl<D: Synth, const N: usize> Logic for SyncROM<D, N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>