Struct rust_hdl_widgets::ramrom::ram::RAMWrite

pub struct RAMWrite<D: Synth, const N: usize> {
    pub address: Signal<In, Bits<N>>,
    pub clock: Signal<In, Clock>,
    pub data: Signal<In, D>,
    pub enable: Signal<In, bool>,
}

Fields

address: Signal<In, Bits<N>>

clock: Signal<In, Clock>

data: Signal<In, D>

enable: Signal<In, bool>

Trait Implementations

impl<D: Synth, const N: usize> Block for RAMWrite<D, N>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<D: Default + Synth, const N: usize> Default for RAMWrite<D, N>

fn default() -> RAMWrite<D, N>

Returns the “default value” for a type.

impl<D: Synth, const N: usize> Logic for RAMWrite<D, N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>

impl<D: Synth, const N: usize> LogicJoin for RAMWrite<D, N>

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>

impl<D: Synth, const N: usize> LogicLink for RAMWrite<D, N>

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>