Struct rust_hdl_widgets::i2c::i2c_test_target::I2CTestBus

pub struct I2CTestBus<const N: usize> {
    pub endpoints: [I2CBusReceiver; N],
    pub sda_state: Signal<Local, Bit>,
    pub scl_state: Signal<Local, Bit>,
}

Fields

endpoints: [I2CBusReceiver; N]

sda_state: Signal<Local, Bit>

scl_state: Signal<Local, Bit>

Trait Implementations

impl<const N: usize> Block for I2CTestBus<N>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const N: usize> Default for I2CTestBus<N>

fn default() -> Self

Returns the “default value” for a type.

impl<const N: usize> Logic for I2CTestBus<N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>