Struct rust_hdl_widgets::i2c::i2c_target::I2CTarget

pub struct I2CTarget {
    pub i2c: I2CBusDriver,
    pub clock: Signal<In, Clock>,
    pub from_bus: Signal<Out, Bits<8>>,
    pub bus_write: Signal<Out, Bit>,
    pub active: Signal<In, Bit>,
    pub stop: Signal<Out, Bit>,
    pub to_bus: Signal<In, Bits<8>>,
    pub write_enable: Signal<In, Bit>,
    pub ack: Signal<Out, Bit>,
    pub nack: Signal<Out, Bit>,
    pub write_ok: Signal<Out, Bit>,
    /* private fields */
}

Fields

i2c: I2CBusDriver

clock: Signal<In, Clock>

from_bus: Signal<Out, Bits<8>>

bus_write: Signal<Out, Bit>

active: Signal<In, Bit>

stop: Signal<Out, Bit>

to_bus: Signal<In, Bits<8>>

write_enable: Signal<In, Bit>

ack: Signal<Out, Bit>

nack: Signal<Out, Bit>

write_ok: Signal<Out, Bit>

Trait Implementations

impl Block for I2CTarget

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Default for I2CTarget

fn default() -> I2CTarget

Returns the “default value” for a type.

impl Logic for I2CTarget

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>