Struct rust_hdl_widgets::fifo::fifo_reducer::FIFOReducer

pub struct FIFOReducer<const DW: usize, const DN: usize, const REVERSE: bool> {
    pub data_in: Signal<In, Bits<DW>>,
    pub read: Signal<Out, Bit>,
    pub empty: Signal<In, Bit>,
    pub data_out: Signal<Out, Bits<DN>>,
    pub write: Signal<Out, Bit>,
    pub full: Signal<In, Bit>,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

data_in: Signal<In, Bits<DW>>

read: Signal<Out, Bit>

empty: Signal<In, Bit>

data_out: Signal<Out, Bits<DN>>

write: Signal<Out, Bit>

full: Signal<In, Bit>

clock: Signal<In, Clock>

Trait Implementations

impl<const DW: usize, const DN: usize, const REVERSE: bool> Block for FIFOReducer<DW, DN, REVERSE>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const DW: usize, const DN: usize, const REVERSE: bool> Default for FIFOReducer<DW, DN, REVERSE>

fn default() -> Self

Returns the “default value” for a type.

impl<const DW: usize, const DN: usize, const REVERSE: bool> Logic for FIFOReducer<DW, DN, REVERSE>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>