Struct rust_hdl_widgets::edge_ff::EdgeDFF

pub struct EdgeDFF<T: Synth> {
    pub d: Signal<In, T>,
    pub q: Signal<Out, T>,
    pub clk: Signal<In, Clock>,
}

Fields

d: Signal<In, T>

q: Signal<Out, T>

clk: Signal<In, Clock>

Implementations

impl<T: Synth> EdgeDFF<T>

pub fn new(init: T) -> EdgeDFF<T>

Trait Implementations

impl<T: Synth> Block for EdgeDFF<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Clone + Synth> Clone for EdgeDFF<T>

fn clone(&self) -> EdgeDFF<T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Debug + Synth> Debug for EdgeDFF<T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<T: Default + Synth> Default for EdgeDFF<T>

fn default() -> EdgeDFF<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for EdgeDFF<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>