Struct rust_hdl_widgets::edge_detector::EdgeDetector

pub struct EdgeDetector {
    pub input_signal: Signal<In, Bit>,
    pub edge_signal: Signal<Out, Bit>,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

input_signal: Signal<In, Bit>

edge_signal: Signal<Out, Bit>

clock: Signal<In, Clock>

Implementations

impl EdgeDetector

pub fn new(is_rising: bool) -> Self

Trait Implementations

impl Block for EdgeDetector

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Logic for EdgeDetector

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>