Struct rust_hdl_widgets::delay_line::DelayLine

pub struct DelayLine<D: Synth, const N: usize, const W: usize> {
    pub clock: Signal<In, Clock>,
    pub data_in: Signal<In, D>,
    pub data_out: Signal<Out, D>,
    pub delay: Signal<In, Bits<W>>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

data_in: Signal<In, D>

data_out: Signal<Out, D>

delay: Signal<In, Bits<W>>

Trait Implementations

impl<D: Synth, const N: usize, const W: usize> Block for DelayLine<D, N, W>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<D: Synth, const N: usize, const W: usize> Default for DelayLine<D, N, W>

fn default() -> Self

Returns the “default value” for a type.

impl<D: Synth, const N: usize, const W: usize> Logic for DelayLine<D, N, W>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>