Struct rust_hdl_sim::ad7193_sim::AD7193Simulator

pub struct AD7193Simulator {
    pub wires: SPIWiresSlave,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

wires: SPIWiresSlave

clock: Signal<In, Clock>

Implementations

impl AD7193Simulator

pub fn new(config: AD7193Config) -> Self

Trait Implementations

impl Block for AD7193Simulator

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Logic for AD7193Simulator

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>