Struct rust_hdl_hls::fifo_linker::FIFOLink

pub struct FIFOLink<T: Synth> {
    pub read: FIFOReadController<T>,
    pub write: FIFOWriteController<T>,
    /* private fields */
}

Fields

read: FIFOReadController<T>

write: FIFOWriteController<T>

Trait Implementations

impl<T: Synth> Block for FIFOLink<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Default + Synth> Default for FIFOLink<T>

fn default() -> FIFOLink<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for FIFOLink<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>