Struct rust_hdl_hls::bus::FIFOReadController

pub struct FIFOReadController<T: Synth> {
    pub data: Signal<In, T>,
    pub read: Signal<Out, Bit>,
    pub empty: Signal<In, Bit>,
    pub almost_empty: Signal<In, Bit>,
}

Fields

data: Signal<In, T>

read: Signal<Out, Bit>

empty: Signal<In, Bit>

almost_empty: Signal<In, Bit>

Implementations

impl<T: Synth> FIFOReadController<T>

pub fn join(&mut self, other: &mut FIFOReadResponder<T>)

Trait Implementations

impl<T: Synth> Block for FIFOReadController<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Clone + Synth> Clone for FIFOReadController<T>

fn clone(&self) -> FIFOReadController<T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Debug + Synth> Debug for FIFOReadController<T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<T: Default + Synth> Default for FIFOReadController<T>

fn default() -> FIFOReadController<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for FIFOReadController<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>

impl<T: Synth> LogicJoin for FIFOReadController<T>

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>

impl<T: Synth> LogicLink for FIFOReadController<T>

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>