Struct rust_hdl_hls::fifo::SyncFIFO

pub struct SyncFIFO<T: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> {
    pub bus_write: FIFOWriteResponder<T>,
    pub bus_read: FIFOReadResponder<T>,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

bus_write: FIFOWriteResponder<T>

bus_read: FIFOReadResponder<T>

clock: Signal<In, Clock>

Trait Implementations

impl<T: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for SyncFIFO<T, N, NP1, BLOCK_SIZE>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Default + Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Default for SyncFIFO<T, N, NP1, BLOCK_SIZE>

fn default() -> SyncFIFO<T, N, NP1, BLOCK_SIZE>

Returns the “default value” for a type.

impl<T: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for SyncFIFO<T, N, NP1, BLOCK_SIZE>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>