Struct HalfGuard 

pub struct HalfGuard<'a, DIR, T: Copy, const N: usize> { /* private fields */ }

RAII guard for half-buffer access in a circular DMA transfer.

Holds an &'b mut reborrow of the parent CircRead / CircWrite, so a second half_guard call is rejected by the borrow checker until this guard is dropped.

The DIR parameter is one of Read / Write and selects which cache op is emitted at construction (DCB-00 §5 transition row for DeviceActiveCirc<DIR> HalfGuard).

Implementations

impl<'a, DIR, T: Copy, const N: usize> HalfGuard<'a, DIR, T, N>

pub fn as_slice(&self) -> &[T]

Read-only view of the guarded half.

pub fn as_mut_slice(&mut self) -> &mut [T]

Mutable view of the guarded half.

pub fn half(&self) -> Half

Which half this guard exposes.

impl<'a, T: Copy, const N: usize> HalfGuard<'a, Read, T, N>

Direction-specific release for HalfGuard<Read, _, _>.

Per DCB-00 §5 (DCB-01b-A 2026-05-03 amendment) the Read direction’s cache op fires at release, not at construction: the CPU is the producer; cleaning before the writes would publish stale data. The clean here publishes the just-completed CPU writes before the engine wraps to this half on its next pass.

pub fn release<C: DcaCache>( self, ctx: &mut DcaCacheCtx<'_, C>, current_half: Half, ) -> Result<(), HalfGuardOverrun>

Release the guard. Emits DcaCache::clean over the guarded half’s extent (the cache op for the Read direction; publishes CPU writes), then performs the INV-D7 stream-position checkpoint.

current_half is the half the DMA engine is currently servicing; the caller reads it from NDTR / LIVR / etc. immediately before this call. If the DMA has crossed into the half this guard exposes (i.e. current_half == self.half), the post-condition check fires per DCB-00 §6 INV-D7: panic! in debug_assertions, error return in release.

impl<'a, T: Copy, const N: usize> HalfGuard<'a, Write, T, N>

Direction-specific release for HalfGuard<Write, _, _>.

Per DCB-00 §5 the Write direction’s cache op fires at construction (invalidate over the inactive half). release performs only the INV-D7 stream-position checkpoint — the CPU has only read; no dirty lines need publishing.

pub fn release<C: DcaCache>( self, _ctx: &mut DcaCacheCtx<'_, C>, current_half: Half, ) -> Result<(), HalfGuardOverrun>

Release the guard. No cache op (the entry-side invalidate already drained stale lines). Performs the INV-D7 stream-position checkpoint.

_ctx is unused for Write direction (kept for symmetry with HalfGuard<Read>::release).