Struct CircRead 

pub struct CircRead<'a, T: Copy, const N: usize> { /* private fields */ }

Continuous DMA-read typestate handle.

The DMA engine reads the buffer in circular mode (typically double-buffer for audio TX, video stream-out, etc.). The CPU is the producer and may fill the inactive half through a HalfGuard<Read, _, _> obtained from CircRead::half_guard.

Implementations

impl<'a, T: Copy, const N: usize> CircRead<'a, T, N>

pub fn dma_addr(&self) -> DmaAddr

DMA bus address of the buffer (stable for the typestate’s lifetime; equal to the address returned during the start_circular_* transition).

pub fn half_guard<'b, C: DcaCache>( &'b mut self, _ctx: &mut DcaCacheCtx<'_, C>, half: Half, ) -> HalfGuard<'b, Read, T, N>

Acquire a guard over the inactive half.

half names which half is currently safe to access — the caller knows from the engine’s stream-position register (NDTR for STM32 DMA, LIVR for SAI, etc.) which half the DMA is currently servicing. Per DCB-00 §6 INV-D7, releasing the guard with HalfGuard::release re-checks the stream-position.

No cache op is emitted at construction. Per DCB-00 §5 (DCB-01b-A 2026-05-03 amendment), the Read direction’s cache op fires at release — the CPU is about to write new data via the guard’s slice, so cleaning now would publish stale data. The clean at release publishes the just-completed CPU writes before the engine wraps to this half on its next pass.

ctx is unused at construction for Read direction (kept in the signature for symmetry with CircWrite::half_guard, which uses it for the entry-side invalidate).

pub fn stop_circular<C: DcaCache>( self, ctx: &mut DcaCacheCtx<'_, C>, ) -> Cpu<'a, T, N>

Stop the circular transfer and transition back to Cpu.

Caller MUST stop the engine before calling. Cache op: DcaCache::clean over the full padded extent, ensuring any CPU-written data still in cache is published to RAM before the buffer leaves DCB ownership.