Module rk3399_rs::ddr_mon

DDR Monitor

Modules

• ddrmon_ch0_count_num
  Channel 0 Timer Count Number
• ddrmon_ch0_ddr_fifo0_addr
  DDR Channel 0 Controller Interface Address FIFO0
• ddrmon_ch0_ddr_fifo1_addr
  DDR Channel 0 Controller Interface Address FIFO1
• ddrmon_ch0_ddr_fifo2_addr
  DDR Channel 0 Controller Interface Address FIFO2
• ddrmon_ch0_ddr_fifo3_addr
  DDR Channel 0 Controller Interface Address FIFO3
• ddrmon_ch0_dfi_access_num
  Channel 0 DFI Read and Write Command Number
• ddrmon_ch0_dfi_act_num
  Channel 0 DFI Active Command Number
• ddrmon_ch0_dfi_rd_num
  Channel 0 DFI read Command Number
• ddrmon_ch0_dfi_wr_num
  Channel 0 DFI write Command Number
• ddrmon_ch0_rd_end_addr
  Channel 0 Read End Address
• ddrmon_ch0_rd_start_addr
  Channel 0 Read Start Address
• ddrmon_ch0_wr_end_addr
  Channel 0 Write End Address
• ddrmon_ch0_wr_start_addr
  Channel 0 Write Start Address
• ddrmon_ch1_count_num
  Channel 1 Timer Count Number
• ddrmon_ch1_ddr_fifo0_addr
  DDR Channel 1 Controller Interface Address FIFO0
• ddrmon_ch1_ddr_fifo1_addr
  DDR Channel 1 Controller Interface Address FIFO1
• ddrmon_ch1_ddr_fifo2_addr
  DDR Channel 1 Controller Interface Address FIFO2
• ddrmon_ch1_ddr_fifo3_addr
  DDR Channel 1 Controller Interface Address FIFO3
• ddrmon_ch1_dfi_access_num
  Channel 1 DFI Read and Write Command Number
• ddrmon_ch1_dfi_act_num
  Channel 1 DFI Active Command Number
• ddrmon_ch1_dfi_rd_num
  Channel 1 DFI read Command Number
• ddrmon_ch1_dfi_wr_num
  Channel 1 DFI write Command Number
• ddrmon_ch1_rd_end_addr
  Channel 1 Read End Address
• ddrmon_ch1_rd_start_addr
  Channel 1 Read Start Address
• ddrmon_ch1_wr_end_addr
  Channel 1 Write End Address
• ddrmon_ch1_wr_start_addr
  Channel 1 Write Start Address
• ddrmon_ctrl
  DDR Monitor Control Register
• ddrmon_ddr_if_ctrl
  DDR interface Control Register
• ddrmon_floor_number
  The Low Threshold in the Comparison of DDR Access
• ddrmon_int_mask
  Interrupt mask control
• ddrmon_int_status
  Interrupt Status
• ddrmon_ip_version
  DDR Monitor IP Version
• ddrmon_timer_count
  The DFI Timer Threshold
• ddrmon_top_number
  The High Threshold in the Comparison of DDR Access

Structs

• RegisterBlock
  Register block

Type Aliases

• DdrmonCh0CountNum
  DDRMON_CH0_COUNT_NUM (r) register accessor: Channel 0 Timer Count Number
• DdrmonCh0DdrFifo0Addr
  DDRMON_CH0_DDR_FIFO0_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO0
• DdrmonCh0DdrFifo1Addr
  DDRMON_CH0_DDR_FIFO1_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO1
• DdrmonCh0DdrFifo2Addr
  DDRMON_CH0_DDR_FIFO2_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO2
• DdrmonCh0DdrFifo3Addr
  DDRMON_CH0_DDR_FIFO3_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO3
• DdrmonCh0DfiAccessNum
  DDRMON_CH0_DFI_ACCESS_NUM (r) register accessor: Channel 0 DFI Read and Write Command Number
• DdrmonCh0DfiActNum
  DDRMON_CH0_DFI_ACT_NUM (r) register accessor: Channel 0 DFI Active Command Number
• DdrmonCh0DfiRdNum
  DDRMON_CH0_DFI_RD_NUM (r) register accessor: Channel 0 DFI read Command Number
• DdrmonCh0DfiWrNum
  DDRMON_CH0_DFI_WR_NUM (r) register accessor: Channel 0 DFI write Command Number
• DdrmonCh0RdEndAddr
  DDRMON_CH0_RD_END_ADDR (rw) register accessor: Channel 0 Read End Address
• DdrmonCh0RdStartAddr
  DDRMON_CH0_RD_START_ADDR (rw) register accessor: Channel 0 Read Start Address
• DdrmonCh0WrEndAddr
  DDRMON_CH0_WR_END_ADDR (rw) register accessor: Channel 0 Write End Address
• DdrmonCh0WrStartAddr
  DDRMON_CH0_WR_START_ADDR (rw) register accessor: Channel 0 Write Start Address
• DdrmonCh1CountNum
  DDRMON_CH1_COUNT_NUM (r) register accessor: Channel 1 Timer Count Number
• DdrmonCh1DdrFifo0Addr
  DDRMON_CH1_DDR_FIFO0_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO0
• DdrmonCh1DdrFifo1Addr
  DDRMON_CH1_DDR_FIFO1_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO1
• DdrmonCh1DdrFifo2Addr
  DDRMON_CH1_DDR_FIFO2_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO2
• DdrmonCh1DdrFifo3Addr
  DDRMON_CH1_DDR_FIFO3_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO3
• DdrmonCh1DfiAccessNum
  DDRMON_CH1_DFI_ACCESS_NUM (r) register accessor: Channel 1 DFI Read and Write Command Number
• DdrmonCh1DfiActNum
  DDRMON_CH1_DFI_ACT_NUM (r) register accessor: Channel 1 DFI Active Command Number
• DdrmonCh1DfiRdNum
  DDRMON_CH1_DFI_RD_NUM (r) register accessor: Channel 1 DFI read Command Number
• DdrmonCh1DfiWrNum
  DDRMON_CH1_DFI_WR_NUM (r) register accessor: Channel 1 DFI write Command Number
• DdrmonCh1RdEndAddr
  DDRMON_CH1_RD_END_ADDR (rw) register accessor: Channel 1 Read End Address
• DdrmonCh1RdStartAddr
  DDRMON_CH1_RD_START_ADDR (rw) register accessor: Channel 1 Read Start Address
• DdrmonCh1WrEndAddr
  DDRMON_CH1_WR_END_ADDR (rw) register accessor: Channel 1 Write End Address
• DdrmonCh1WrStartAddr
  DDRMON_CH1_WR_START_ADDR (rw) register accessor: Channel 1 Write Start Address
• DdrmonCtrl
  DDRMON_CTRL (rw) register accessor: DDR Monitor Control Register
• DdrmonDdrIfCtrl
  DDRMON_DDR_IF_CTRL (rw) register accessor: DDR interface Control Register
• DdrmonFloorNumber
  DDRMON_FLOOR_NUMBER (r) register accessor: The Low Threshold in the Comparison of DDR Access
• DdrmonIntMask
  DDRMON_INT_MASK (rw) register accessor: Interrupt mask control
• DdrmonIntStatus
  DDRMON_INT_STATUS (r) register accessor: Interrupt Status
• DdrmonIpVersion
  DDRMON_IP_VERSION (r) register accessor: DDR Monitor IP Version
• DdrmonTimerCount
  DDRMON_TIMER_COUNT (r) register accessor: The DFI Timer Threshold
• DdrmonTopNumber
  DDRMON_TOP_NUMBER (r) register accessor: The High Threshold in the Comparison of DDR Access