Module rk3399_rs::ddr_mon::ddrmon_ctrl

DDR Monitor Control Register

Structs

• DdrmonCtrlSpec
  DDR Monitor Control Register

Enums

• HardwareEn
  Hardware Mode Enable
• Lpddr3En
  LPDDR3 Mode Monitor Enable
• Lpddr4En
  LPDDR4 Mode Enable
• SoftwareEn
  Software Mode Enable
• TimerCntEn
  DFI Timer Count Enable

Type Aliases

• HardwareEnR
  Field HARDWARE_EN reader - Hardware Mode Enable
• HardwareEnW
  Field HARDWARE_EN writer - Hardware Mode Enable
• Lpddr3EnR
  Field LPDDR3_EN reader - LPDDR3 Mode Monitor Enable
• Lpddr3EnW
  Field LPDDR3_EN writer - LPDDR3 Mode Monitor Enable
• Lpddr4EnR
  Field LPDDR4_EN reader - LPDDR4 Mode Enable
• Lpddr4EnW
  Field LPDDR4_EN writer - LPDDR4 Mode Enable
• R
  Register DDRMON_CTRL reader
• SoftwareEnR
  Field SOFTWARE_EN reader - Software Mode Enable
• SoftwareEnW
  Field SOFTWARE_EN writer - Software Mode Enable
• TimerCntEnR
  Field TIMER_CNT_EN reader - DFI Timer Count Enable
• TimerCntEnW
  Field TIMER_CNT_EN writer - DFI Timer Count Enable
• W
  Register DDRMON_CTRL writer
• WriteEnableR
  Field WRITE_ENABLE reader - bit0~15 write enable When bit 16=1, bit 0 can be written by softwar . When bit 16=0, bit 0 cannot be written by software; When bit 17=1, bit 1 can be written by software. When bit 17=0, bit 1 cannot be written by software; …… When bit 31=1, bit 15 can be written by software. When bit 31=0, bit 15 cannot be written by software;
• WriteEnableW
  Field WRITE_ENABLE writer - bit0~15 write enable When bit 16=1, bit 0 can be written by softwar . When bit 16=0, bit 0 cannot be written by software; When bit 17=1, bit 1 can be written by software. When bit 17=0, bit 1 cannot be written by software; …… When bit 31=1, bit 15 can be written by software. When bit 31=0, bit 15 cannot be written by software;